diff --git a/.gitlab/ci/docs.yml b/.gitlab/ci/docs.yml
index 139ac5b32e..3ea791048a 100644
--- a/.gitlab/ci/docs.yml
+++ b/.gitlab/ci/docs.yml
@@ -118,7 +118,7 @@ build_docs_html_full:
     paths:
       - docs/_build/*/*/*.txt
       - docs/_build/*/*/html/*
-    expire_in: 12 hrs
+    expire_in: 4 days
   variables:
     DOC_BUILDERS: "html"
 
@@ -131,7 +131,7 @@ build_docs_html_partial:
     paths:
       - docs/_build/*/*/*.txt
       - docs/_build/*/*/html/*
-    expire_in: 12 hrs
+    expire_in: 4 days
   variables:
     DOC_BUILDERS: "html"
   parallel:
diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml
index b6b906cee0..2141eb025f 100644
--- a/.pre-commit-config.yaml
+++ b/.pre-commit-config.yaml
@@ -137,7 +137,7 @@ repos:
         name: Check tools dir files patterns
         entry: tools/ci/check_tools_files_patterns.py
         language: python
-        files: '^tools/.+'
+        files: '^(tools/.+|.gitlab/ci/rules\.yml)'
         additional_dependencies:
           - PyYAML == 5.3.1
         pass_filenames: false
diff --git a/components/bootloader/subproject/main/bootloader_start.c b/components/bootloader/subproject/main/bootloader_start.c
index 64d80c77c9..147c382565 100644
--- a/components/bootloader/subproject/main/bootloader_start.c
+++ b/components/bootloader/subproject/main/bootloader_start.c
@@ -4,8 +4,10 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <stdbool.h>
+#include "sdkconfig.h"
 #include "esp_log.h"
 #include "esp_rom_sys.h"
+#include "esp_rom_caps.h"
 #include "bootloader_init.h"
 #include "bootloader_utility.h"
 #include "bootloader_common.h"
diff --git a/components/bootloader_support/src/bootloader_common_loader.c b/components/bootloader_support/src/bootloader_common_loader.c
index b46e43f4bd..058037df54 100644
--- a/components/bootloader_support/src/bootloader_common_loader.c
+++ b/components/bootloader_support/src/bootloader_common_loader.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,6 +12,9 @@
 #include "esp_rom_crc.h"
 #include "esp_rom_gpio.h"
 #include "esp_flash_partitions.h"
+#if CONFIG_SECURE_BOOT
+#include "esp_secure_boot.h"
+#endif
 #include "bootloader_flash.h"
 #include "bootloader_common.h"
 #include "soc/gpio_periph.h"
@@ -274,7 +277,12 @@ rtc_retain_mem_t* bootloader_common_get_rtc_retain_mem(void)
     #define RETAIN_MEM_SIZE     ALIGN_UP(sizeof(rtc_retain_mem_t), 8)
     #define RTC_RETAIN_MEM_ADDR (SOC_RTC_DRAM_HIGH - RETAIN_MEM_SIZE)
 #endif //ESP_ROM_HAS_LP_ROM
+
+#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
+    static rtc_retain_mem_t *const s_bootloader_retain_mem = (rtc_retain_mem_t *)RTC_RETAIN_MEM_ADDR - ESP_SECURE_BOOT_DIGEST_LEN;
+#else
     static rtc_retain_mem_t *const s_bootloader_retain_mem = (rtc_retain_mem_t *)RTC_RETAIN_MEM_ADDR;
+#endif
     return s_bootloader_retain_mem;
 #else
     static __attribute__((section(".bootloader_data_rtc_mem"))) rtc_retain_mem_t s_bootloader_retain_mem;
diff --git a/components/bootloader_support/src/bootloader_random_esp32c5.c b/components/bootloader_support/src/bootloader_random_esp32c5.c
index 15c2314413..826aa785ee 100644
--- a/components/bootloader_support/src/bootloader_random_esp32c5.c
+++ b/components/bootloader_support/src/bootloader_random_esp32c5.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,6 +8,7 @@
 #include "hal/regi2c_ctrl_ll.h"
 #include "hal/adc_ll.h"
 #include "hal/adc_types.h"
+#include "hal/rng_ll.h"
 #include "esp_private/regi2c_ctrl.h"
 #include "soc/lpperi_reg.h"
 
@@ -51,9 +52,9 @@ void bootloader_random_enable(void)
     adc_ll_digi_set_trigger_interval(200);
     adc_ll_digi_trigger_enable();
 
-    SET_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_SAMPLE_ENABLE);
-    REG_SET_FIELD(LPPERI_RNG_CFG_REG, LPPERI_RTC_TIMER_EN, 0x3);
-    SET_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_TIMER_EN);
+    rng_ll_enable_sample(true);
+    rng_ll_enable_rtc_timer(true);
+    rng_ll_enable_rng_timer(true);
 }
 
 void bootloader_random_disable(void)
diff --git a/components/bootloader_support/src/flash_encrypt.c b/components/bootloader_support/src/flash_encrypt.c
index 362eea9a3c..9e311b156d 100644
--- a/components/bootloader_support/src/flash_encrypt.c
+++ b/components/bootloader_support/src/flash_encrypt.c
@@ -210,6 +210,7 @@ void esp_flash_encryption_set_release_mode(void)
 #endif // CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED
 #endif // !CONFIG_IDF_TARGET_ESP32
 
+#if !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_REV_MIN_FULL < 300)
 #ifdef SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND
     if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) {
         uint8_t xts_pseudo_level = 0;
@@ -221,7 +222,7 @@ void esp_flash_encryption_set_release_mode(void)
         }
     }
 #endif
-
+#endif
 #ifdef CONFIG_IDF_TARGET_ESP32
     esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_DIS_CACHE);
 #else
@@ -483,6 +484,7 @@ bool esp_flash_encryption_cfg_verify_release_mode(void)
     }
     result &= secure;
 
+#if !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_REV_MIN_FULL < 300)
 #if SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND
     if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) {
         uint8_t xts_pseudo_level = 0;
@@ -493,7 +495,7 @@ bool esp_flash_encryption_cfg_verify_release_mode(void)
         }
     }
 #endif
-
+#endif
     return result;
 }
 #endif // not CONFIG_IDF_TARGET_ESP32
diff --git a/components/bt/common/ble_log/Kconfig.in b/components/bt/common/ble_log/Kconfig.in
index 35405367e2..a707f82d3a 100644
--- a/components/bt/common/ble_log/Kconfig.in
+++ b/components/bt/common/ble_log/Kconfig.in
@@ -70,15 +70,39 @@ if BLE_LOG_ENABLED
         help
             Enable BLE Log for Link Layer
 
-    config BLE_LOG_LBM_LL_TRANS_SIZE
-        int "Buffer size for each peripheral transport of Link Layer LBM"
-        depends on BLE_LOG_LL_ENABLED
-        default 1024
+    if BLE_LOG_LL_ENABLED
+        config BLE_LOG_LBM_LL_TRANS_SIZE
+            int "Buffer size for each peripheral transport of Link Layer LBM"
+            default 1024
+            help
+                There're 2 Link Layer dedicated log buffer managers (LBMs) with
+                compare-and-swap (CAS) protection. Each LBM is managing 2 ping-
+                pong buffers, which means there will be additional 2 * 2 *
+                BLE_LOG_LBM_LL_TRANS_SIZE bytes buffer allocated
+
+        config BLE_LOG_LL_HCI_LOG_PAYLOAD_LEN_LIMIT_ENABLED
+            bool "Enable LL HCI Log Payload Length Limit"
+            default n
+            help
+                Enable length limit for LL HCI Log payload (addr_append).
+                When enabled, if len_append exceeds the configured limit,
+                it will be truncated to the maximum length.
+
+        config BLE_LOG_LL_HCI_LOG_PAYLOAD_LEN_LIMIT
+            int "LL HCI Log Payload Length Limit (bytes)"
+            depends on BLE_LOG_LL_HCI_LOG_PAYLOAD_LEN_LIMIT_ENABLED
+            default 32
+            help
+                Maximum length for LL HCI Log payload (len_append).
+                When the feature is enabled and len_append exceeds this value,
+                it will be truncated.
+    endif
+
+    config BLE_LOG_HOST_SIDE_HCI_LOG_ENABLED
+        bool "Enable BLE Host side HCI Logging"
+        default y
         help
-            There're 2 Link Layer dedicated log buffer managers (LBMs) with
-            compare-and-swap (CAS) protection. Each LBM is managing 2 ping-
-            pong buffers, which means there will be additional 2 * 2 *
-            BLE_LOG_LBM_LL_TRANS_SIZE bytes buffer allocated
+            Enable BLE Host side HCI Logging
 
     config BLE_LOG_PAYLOAD_CHECKSUM_ENABLED
         bool "Enable payload checksum for BLE Log data integrity check"
diff --git a/components/bt/common/ble_log/src/ble_log_lbm.c b/components/bt/common/ble_log/src/ble_log_lbm.c
index 4504663c5f..8c95a815d5 100644
--- a/components/bt/common/ble_log/src/ble_log_lbm.c
+++ b/components/bt/common/ble_log/src/ble_log_lbm.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -107,8 +107,7 @@ void ble_log_lbm_write_trans(ble_log_prph_trans_t **trans, ble_log_src_t src_cod
     }
     if (len_append) {
 #if CONFIG_SOC_ESP_NIMBLE_CONTROLLER
-        if (omdata && !BLE_LOG_IN_ISR()) {
-            /* os_mbuf_copydata is in flash and not safe to call from ISR */
+        if (omdata) {
             os_mbuf_copydata((struct os_mbuf *)addr_append, 0,
                              len_append, buf + BLE_LOG_FRAME_HEAD_LEN + len);
         }
@@ -427,17 +426,17 @@ BLE_LOG_IRAM_ATTR
 bool ble_log_write_hex(ble_log_src_t src_code, const uint8_t *addr, size_t len)
 {
     BLE_LOG_REF_COUNT_ACQUIRE(&lbm_ref_count);
-    size_t payload_len = len + sizeof(uint32_t);
     if (!lbm_enabled) {
         goto exit;
     }
 
     /* Get transport */
+    size_t payload_len = len + sizeof(uint32_t);
     ble_log_lbm_t *lbm = ble_log_lbm_acquire();
     ble_log_prph_trans_t **trans = ble_log_lbm_get_trans(lbm, payload_len);
     if (!trans) {
         ble_log_lbm_release(lbm);
-        goto exit;
+        goto failed;
     }
 
     /* Write transport */
@@ -452,12 +451,13 @@ bool ble_log_write_hex(ble_log_src_t src_code, const uint8_t *addr, size_t len)
     BLE_LOG_REF_COUNT_RELEASE(&lbm_ref_count);
     return true;
 
-exit:
+failed:
 #if CONFIG_BLE_LOG_ENH_STAT_ENABLED
     if (lbm_inited) {
         ble_log_stat_mgr_update(src_code, payload_len, true);
     }
 #endif /* CONFIG_BLE_LOG_ENH_STAT_ENABLED */
+exit:
     BLE_LOG_REF_COUNT_RELEASE(&lbm_ref_count);
     return false;
 }
@@ -468,10 +468,12 @@ void ble_log_write_hex_ll(uint32_t len, const uint8_t *addr,
                           uint32_t len_append, const uint8_t *addr_append, uint32_t flag)
 {
     BLE_LOG_REF_COUNT_ACQUIRE(&lbm_ref_count);
-    size_t payload_len = len + len_append;
+    if (!lbm_enabled) {
+        goto exit;
+    }
 
-    /* Source code shall be determined before LBM enable status check */
-    ble_log_src_t src_code;
+    /* Source code shall be determined before LBM determination */
+    ble_log_src_t src_code = BLE_LOG_SRC_MAX;
     bool use_ll_task = false;
     if (flag & BIT(BLE_LOG_LL_FLAG_ISR)) {
         src_code = BLE_LOG_SRC_LL_ISR;
@@ -485,24 +487,33 @@ void ble_log_write_hex_ll(uint32_t len, const uint8_t *addr,
     }
     bool omdata = flag & BIT(BLE_LOG_LL_FLAG_OMDATA);
 
-    if (!lbm_enabled) {
-        goto exit;
-    }
-
     /* Determine LBM by flag */
     ble_log_lbm_t *lbm;
     if (BLE_LOG_IN_ISR()) {
         /* Reuse common LBM acquire logic */
         lbm = ble_log_lbm_acquire();
+
+        /* os_mbuf_copydata is in flash and not safe to call from ISR */
+        omdata = false;
     } else {
-        lbm = (use_ll_task)? &(lbm_ctx->lbm_ll_task): &(lbm_ctx->lbm_ll_hci);
+        if (use_ll_task) {
+            lbm = &(lbm_ctx->lbm_ll_task);
+        } else {
+            lbm = &(lbm_ctx->lbm_ll_hci);
+#if CONFIG_BLE_LOG_LL_HCI_LOG_PAYLOAD_LEN_LIMIT_ENABLED
+            if (len_append > CONFIG_BLE_LOG_LL_HCI_LOG_PAYLOAD_LEN_LIMIT) {
+                len_append = CONFIG_BLE_LOG_LL_HCI_LOG_PAYLOAD_LEN_LIMIT;
+            }
+#endif /* CONFIG_BLE_LOG_LL_HCI_LOG_PAYLOAD_LEN_LIMIT_ENABLED */
+        }
     }
 
     /* Get transport */
+    size_t payload_len = len + len_append;
     ble_log_prph_trans_t **trans = ble_log_lbm_get_trans(lbm, payload_len);
     if (!trans) {
         ble_log_lbm_release(lbm);
-        goto exit;
+        goto failed;
     }
 
     /* Write transport */
@@ -512,12 +523,13 @@ void ble_log_write_hex_ll(uint32_t len, const uint8_t *addr,
     BLE_LOG_REF_COUNT_RELEASE(&lbm_ref_count);
     return;
 
-exit:
+failed:
 #if CONFIG_BLE_LOG_ENH_STAT_ENABLED
     if (lbm_inited) {
         ble_log_stat_mgr_update(src_code, payload_len, true);
     }
 #endif /* CONFIG_BLE_LOG_ENH_STAT_ENABLED */
+exit:
     BLE_LOG_REF_COUNT_RELEASE(&lbm_ref_count);
     return;
 }
diff --git a/components/bt/host/bluedroid/api/esp_bluedroid_hci.c b/components/bt/host/bluedroid/api/esp_bluedroid_hci.c
index ac64d17d04..82f0246e3e 100644
--- a/components/bt/host/bluedroid/api/esp_bluedroid_hci.c
+++ b/components/bt/host/bluedroid/api/esp_bluedroid_hci.c
@@ -19,6 +19,9 @@
 #if CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
 #include "ble_log/ble_log_spi_out.h"
 #endif // CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
+#if CONFIG_BLE_LOG_ENABLED
+#include "ble_log.h"
+#endif /* CONFIG_BLE_LOG_ENABLED */
 
 static esp_bluedroid_hci_driver_operations_t s_hci_driver_ops = { 0 };
 
@@ -70,6 +73,9 @@ void hci_host_send_packet(uint8_t *data, uint16_t len)
 #if CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
     ble_log_spi_out_hci_write(BLE_LOG_SPI_OUT_SOURCE_HCI_DOWNSTREAM, data, len);
 #endif // CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
+#if CONFIG_BLE_LOG_HOST_SIDE_HCI_LOG_ENABLED
+    ble_log_write_hex(BLE_LOG_SRC_HCI, data, len);
+#endif /* CONFIG_BLE_LOG_HOST_SIDE_HCI_LOG_ENABLED */
 #if (BT_CONTROLLER_INCLUDED == TRUE)
     esp_vhci_host_send_packet(data, len);
 #else /* BT_CONTROLLER_INCLUDED == TRUE */
diff --git a/components/bt/host/bluedroid/hci/hci_hal_h4.c b/components/bt/host/bluedroid/hci/hci_hal_h4.c
index 90cb2a1177..cadf70005f 100644
--- a/components/bt/host/bluedroid/hci/hci_hal_h4.c
+++ b/components/bt/host/bluedroid/hci/hci_hal_h4.c
@@ -45,6 +45,9 @@
 #if CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
 #include "ble_log/ble_log_spi_out.h"
 #endif // CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
+#if CONFIG_BLE_LOG_ENABLED
+#include "ble_log.h"
+#endif /* CONFIG_BLE_LOG_ENABLED */
 
 #define HCI_BLE_EVENT 0x3e
 #define PACKET_TYPE_TO_INBOUND_INDEX(type) ((type) - 2)
@@ -605,6 +608,9 @@ static int host_recv_pkt_cb(uint8_t *data, uint16_t len)
 #if CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
     ble_log_spi_out_hci_write(BLE_LOG_SPI_OUT_SOURCE_HCI_UPSTREAM, data, len);
 #endif // CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
+#if CONFIG_BLE_LOG_HOST_SIDE_HCI_LOG_ENABLED
+    ble_log_write_hex(BLE_LOG_SRC_HCI, data, len);
+#endif /* CONFIG_BLE_LOG_HOST_SIDE_HCI_LOG_ENABLED */
     //Target has packet to host, malloc new buffer for packet
     BT_HDR *pkt = NULL;
 #if (BLE_42_SCAN_EN == TRUE)
diff --git a/components/bt/host/bluedroid/stack/gatt/att_protocol.c b/components/bt/host/bluedroid/stack/gatt/att_protocol.c
index c16967c6ef..f2654f1a15 100644
--- a/components/bt/host/bluedroid/stack/gatt/att_protocol.c
+++ b/components/bt/host/bluedroid/stack/gatt/att_protocol.c
@@ -395,8 +395,7 @@ tGATT_STATUS attp_send_msg_to_l2cap(tGATT_TCB *p_tcb, BT_HDR *p_toL2CAP)
     }
 
     if (l2cap_ret == L2CAP_DW_FAILED) {
-        GATT_TRACE_DEBUG("ATT   failed to pass msg:0x%0x to L2CAP",
-                         *((UINT8 *)(p_toL2CAP + 1) + p_toL2CAP->offset));
+        GATT_TRACE_DEBUG("ATT failed to pass msg to L2CAP");
         return GATT_INTERNAL_ERROR;
     } else if (l2cap_ret == L2CAP_DW_CONGESTED) {
         GATT_TRACE_DEBUG("ATT congested, message accepted");
diff --git a/components/bt/host/nimble/esp-hci/src/esp_nimble_hci.c b/components/bt/host/nimble/esp-hci/src/esp_nimble_hci.c
index 6dded0363b..fe99401d7e 100644
--- a/components/bt/host/nimble/esp-hci/src/esp_nimble_hci.c
+++ b/components/bt/host/nimble/esp-hci/src/esp_nimble_hci.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -27,6 +27,9 @@
 #if CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
 #include "ble_log/ble_log_spi_out.h"
 #endif // CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
+#if CONFIG_BLE_LOG_ENABLED
+#include "ble_log.h"
+#endif /* CONFIG_BLE_LOG_ENABLED */
 
 #define NIMBLE_VHCI_TIMEOUT_MS  2000
 #define BLE_HCI_EVENT_HDR_LEN               (2)
@@ -80,6 +83,9 @@ void esp_vhci_host_send_packet_wrapper(uint8_t *data, uint16_t len)
 #if CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
     ble_log_spi_out_hci_write(BLE_LOG_SPI_OUT_SOURCE_HCI_DOWNSTREAM, data, len);
 #endif // CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
+#if CONFIG_BLE_LOG_HOST_SIDE_HCI_LOG_ENABLED
+    ble_log_write_hex(BLE_LOG_SRC_HCI, data, len);
+#endif /* CONFIG_BLE_LOG_HOST_SIDE_HCI_LOG_ENABLED */
     esp_vhci_host_send_packet(data, len);
 }
 
@@ -260,6 +266,9 @@ static int host_rcv_pkt(uint8_t *data, uint16_t len)
 #if CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
     ble_log_spi_out_hci_write(BLE_LOG_SPI_OUT_SOURCE_HCI_UPSTREAM, data, len);
 #endif // CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
+#if CONFIG_BLE_LOG_HOST_SIDE_HCI_LOG_ENABLED
+    ble_log_write_hex(BLE_LOG_SRC_HCI, data, len);
+#endif /* CONFIG_BLE_LOG_HOST_SIDE_HCI_LOG_ENABLED */
 
     bt_record_hci_data(data, len);
 
diff --git a/components/bt/host/nimble/nimble b/components/bt/host/nimble/nimble
index 112925dfe7..d9a6fa8630 160000
--- a/components/bt/host/nimble/nimble
+++ b/components/bt/host/nimble/nimble
@@ -1 +1 @@
-Subproject commit 112925dfe7712ecfe9ccfe37510c7fdcb1fd962a
+Subproject commit d9a6fa863017fd6d8486c50d244acfbbb898a590
diff --git a/components/esp_adc/esp32/adc_dma.c b/components/esp_adc/esp32/adc_dma.c
index 0aceacd769..32e481b586 100644
--- a/components/esp_adc/esp32/adc_dma.c
+++ b/components/esp_adc/esp32/adc_dma.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -43,7 +43,12 @@ static IRAM_ATTR void adc_dma_intr_handler(void *arg)
 
 esp_err_t adc_dma_intr_event_init(adc_continuous_ctx_t *adc_ctx)
 {
-    return (esp_intr_alloc(i2s_periph_signal[ADC_DMA_I2S_HOST].irq, ESP_INTR_FLAG_IRAM, adc_dma_intr_handler,
+    int intr_flags = ESP_INTR_FLAG_LOWMED | ESP_INTR_FLAG_SHARED;
+#if CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE
+    intr_flags |= ESP_INTR_FLAG_IRAM;
+#endif
+
+    return (esp_intr_alloc(i2s_periph_signal[ADC_DMA_I2S_HOST].irq, intr_flags, adc_dma_intr_handler,
                            (void *)adc_ctx, &adc_ctx->adc_dma.dma_intr_hdl));
 }
 
diff --git a/components/esp_adc/esp32s2/adc_dma.c b/components/esp_adc/esp32s2/adc_dma.c
index 1b6be919f5..07afab8946 100644
--- a/components/esp_adc/esp32s2/adc_dma.c
+++ b/components/esp_adc/esp32s2/adc_dma.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -40,7 +40,12 @@ static IRAM_ATTR void adc_dma_intr_handler(void *arg)
 
 esp_err_t adc_dma_intr_event_init(adc_continuous_ctx_t *adc_ctx)
 {
-    return (esp_intr_alloc(spicommon_irqdma_source_for_host(ADC_DMA_SPI_HOST), ESP_INTR_FLAG_IRAM, adc_dma_intr_handler,
+    int intr_flags = ESP_INTR_FLAG_LOWMED | ESP_INTR_FLAG_SHARED;
+#if CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE
+    intr_flags |= ESP_INTR_FLAG_IRAM;
+#endif
+
+    return (esp_intr_alloc(spicommon_irqdma_source_for_host(ADC_DMA_SPI_HOST), intr_flags, adc_dma_intr_handler,
                            (void *)adc_ctx, &adc_ctx->adc_dma.dma_intr_hdl));
 }
 
diff --git a/components/esp_driver_isp/include/driver/isp_ccm.h b/components/esp_driver_isp/include/driver/isp_ccm.h
index f779ff3cb7..c9e39868fb 100644
--- a/components/esp_driver_isp/include/driver/isp_ccm.h
+++ b/components/esp_driver_isp/include/driver/isp_ccm.h
@@ -20,7 +20,7 @@ extern "C" {
  *
  */
 typedef struct {
-    float matrix[ISP_CCM_DIMENSION][ISP_CCM_DIMENSION];     /*!< The color correction matrix in float, range (-4.0, 4.0) */
+    float matrix[ISP_CCM_DIMENSION][ISP_CCM_DIMENSION];     /*!< The color correction matrix in float*/
     bool saturation;                                        /*!< Whether to use saturation when the float data in the matrix is out of the range,
                                                              *   For example, if one of the matrix data is 5.0,
                                                              *   When saturation is true, and final value will be limited to 4.0, and won't rise error
diff --git a/components/esp_driver_isp/src/isp_ccm.c b/components/esp_driver_isp/src/isp_ccm.c
index cb688dc7f3..4a194fc44e 100644
--- a/components/esp_driver_isp/src/isp_ccm.c
+++ b/components/esp_driver_isp/src/isp_ccm.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -21,6 +21,17 @@ esp_err_t esp_isp_ccm_configure(isp_proc_handle_t proc, const esp_isp_ccm_config
 {
     ESP_RETURN_ON_FALSE(proc && ccm_cfg, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
 
+    // Check matrix values are within valid range
+    float max_range = (1 << ISP_LL_CCM_MATRIX_INT_BITS);
+    float min_range = -(1 << ISP_LL_CCM_MATRIX_INT_BITS);
+    for (int i = 0; i < ISP_CCM_DIMENSION; i++) {
+        for (int j = 0; j < ISP_CCM_DIMENSION; j++) {
+            float value = ccm_cfg->matrix[i][j];
+            ESP_RETURN_ON_FALSE(value >= min_range && value <= max_range, ESP_ERR_INVALID_ARG, TAG,
+                                "Matrix[%d][%d] value %f is out of range [%f, %f]", i, j, value, min_range, max_range);
+        }
+    }
+
     bool ret = true;
     bool valid = false;
     portENTER_CRITICAL(&proc->spinlock);
diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c
index 138637e62f..a8d4737ebe 100644
--- a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c
+++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c
@@ -391,7 +391,7 @@ TEST_CASE("parallel_rx_unit_pulse_delimiter_test_via_i2s", "[parlio_rx]")
 {
     parlio_rx_pulse_delimiter_config_t pls_deli_cfg = {
         .valid_sig_line_id = TEST_VALID_SIG,
-        .sample_edge = PARLIO_SAMPLE_EDGE_NEG,
+        .sample_edge = PARLIO_SAMPLE_EDGE_POS,
         .bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB,
         .eof_data_len = TEST_EOF_DATA_LEN,
         .timeout_ticks = 0,
diff --git a/components/esp_eth/include/esp_eth_mac_esp.h b/components/esp_eth/include/esp_eth_mac_esp.h
index d75e3fc387..a756b01e93 100644
--- a/components/esp_eth/include/esp_eth_mac_esp.h
+++ b/components/esp_eth/include/esp_eth_mac_esp.h
@@ -182,6 +182,7 @@ typedef struct {
 #if !SOC_EMAC_RMII_CLK_OUT_INTERNAL_LOOPBACK
     eth_mac_clock_config_t clock_config_out_in;     /*!< EMAC input clock configuration for internally generated output clock (when output clock is looped back externally) */
 #endif //SOC_EMAC_RMII_CLK_OUT_INTERNAL_LOOPBACK
+    int32_t mdc_freq_hz;                            /*!< EMAC MDC frequency range limit, if set to 0 or a negative value, the driver will set the CSR clock range up to 2.5 MHz */
 } eth_esp32_emac_config_t;
 
 /**
@@ -257,6 +258,7 @@ typedef bool (*ts_target_exceed_cb_from_isr_t)(esp_eth_mediator_t *eth, void *us
         },                                                                    \
         .dma_burst_len = ETH_DMA_BURST_LEN_32,                                \
         .intr_priority = 0,                                                   \
+        .mdc_freq_hz = 0,                                                     \
     }
 #elif CONFIG_IDF_TARGET_ESP32P4
 #define ETH_ESP32_EMAC_DEFAULT_CONFIG()                                       \
@@ -277,6 +279,7 @@ typedef bool (*ts_target_exceed_cb_from_isr_t)(esp_eth_mediator_t *eth, void *us
         },                                                                    \
         .dma_burst_len = ETH_DMA_BURST_LEN_32,                                \
         .intr_priority = 0,                                                   \
+        .mdc_freq_hz = 0,                                                     \
         .emac_dataif_gpio =                                                   \
         {                                                                     \
             .rmii =                                                           \
diff --git a/components/esp_eth/src/mac/esp_eth_mac_esp.c b/components/esp_eth/src/mac/esp_eth_mac_esp.c
index c9f9084b8e..8f87de5532 100644
--- a/components/esp_eth/src/mac/esp_eth_mac_esp.c
+++ b/components/esp_eth/src/mac/esp_eth_mac_esp.c
@@ -73,6 +73,7 @@ typedef struct {
     bool do_flow_ctrl;  // indicates whether we need to do software flow control
     bool use_pll;  // Only use (A/M)PLL in EMAC_DATA_INTERFACE_RMII && EMAC_CLK_OUT
     SemaphoreHandle_t multi_reg_mutex; // lock for multiple register access
+    int32_t mdc_freq_hz;
 #ifdef CONFIG_PM_ENABLE
     esp_pm_lock_handle_t pm_lock;
 #endif
@@ -547,7 +548,14 @@ static esp_err_t emac_esp32_init(esp_eth_mac_t *mac)
     }
     ESP_GOTO_ON_FALSE(to < emac->sw_reset_timeout_ms / 10, ESP_ERR_TIMEOUT, err, TAG, "reset timeout");
     /* set smi clock */
-    emac_hal_set_csr_clock_range(&emac->hal, esp_clk_apb_freq());
+    uint32_t csr_freq_hz;
+    soc_module_clk_t csr_clk_src = emac_ll_get_csr_clk_src();
+    ESP_GOTO_ON_ERROR(esp_clk_tree_src_get_freq_hz(csr_clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &csr_freq_hz), err, TAG, "get CSR frequency failed");
+    if (emac->mdc_freq_hz <= 0) {
+        emac_hal_set_csr_clock_range(&emac->hal, csr_freq_hz);
+    } else {
+        emac_hal_find_set_closest_csr_clock_range(&emac->hal, emac->mdc_freq_hz, csr_freq_hz);
+    }
     /* init mac registers by default */
     emac_hal_init_mac_default(&emac->hal);
     /* init dma registers with selected EMAC-DMA configuration */
@@ -843,6 +851,8 @@ esp_eth_mac_t *esp_eth_mac_new_esp32(const eth_esp32_emac_config_t *esp32_config
     emac->dma_burst_len = esp32_config->dma_burst_len;
     emac->sw_reset_timeout_ms = config->sw_reset_timeout_ms;
 
+    emac->mdc_freq_hz = esp32_config->mdc_freq_hz;
+
     emac->flow_control_high_water_mark = FLOW_CONTROL_HIGH_WATER_MARK;
     emac->flow_control_low_water_mark = FLOW_CONTROL_LOW_WATER_MARK;
     emac->parent.set_mediator = emac_esp32_set_mediator;
diff --git a/components/esp_eth/test_apps/.build-test-rules.yml b/components/esp_eth/test_apps/.build-test-rules.yml
index 3d07cc18a3..dc4d00c17b 100644
--- a/components/esp_eth/test_apps/.build-test-rules.yml
+++ b/components/esp_eth/test_apps/.build-test-rules.yml
@@ -2,7 +2,7 @@
 
 components/esp_eth/test_apps:
   enable:
-    - if: IDF_TARGET in ["esp32"] # TODO: IDF-14365
+    - if: IDF_TARGET in ["esp32", "esp32p4"]
       reason: ESP32 and ESP32P4 have internal EMAC. SPI Ethernet runners are based on ESP32.
   depends_components:
     - esp_eth
diff --git a/components/esp_eth/test_apps/README.md b/components/esp_eth/test_apps/README.md
index 0e2cf8cb13..9747c000db 100644
--- a/components/esp_eth/test_apps/README.md
+++ b/components/esp_eth/test_apps/README.md
@@ -1,6 +1,6 @@
 # EMAC Test
-| Supported Targets | ESP32 |
-| ----------------- | ----- |
+| Supported Targets | ESP32 | ESP32-P4 |
+| ----------------- | ----- | -------- |
 
 This test app is used to test Ethernet MAC behavior with different chips.
 
diff --git a/components/esp_eth/test_apps/pytest_esp_eth.py b/components/esp_eth/test_apps/pytest_esp_eth.py
index f32e5cf7ae..cd29d3cfd6 100644
--- a/components/esp_eth/test_apps/pytest_esp_eth.py
+++ b/components/esp_eth/test_apps/pytest_esp_eth.py
@@ -288,48 +288,42 @@ def test_esp_eth_ip101(dut: IdfDut) -> None:
 
 
 # ----------- IP101 ESP32P4 -----------
-@pytest.mark.eth_ip101
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14365')
 @pytest.mark.parametrize(
-    'config',
+    'config, target',
     [
-        'default_ip101_esp32p4',
+        pytest.param('default_ip101_esp32p4', 'esp32p4', marks=[pytest.mark.eth_ip101]),
+        pytest.param('default_ip101_esp32p4v1', 'esp32p4', marks=[pytest.mark.eth_ip101, pytest.mark.esp32p4_eco4]),
     ],
-    indirect=True,
+    indirect=['target'],
 )
-@idf_parametrize('target', ['esp32p4'], indirect=['target'])
 def test_esp32p4_ethernet(dut: IdfDut) -> None:
     ethernet_test(dut)
     dut.serial.hard_reset()
     ethernet_l2_test(dut)
 
 
-@pytest.mark.eth_ip101
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14365')
 @pytest.mark.parametrize(
-    'config',
+    'config, target',
     [
-        'default_ip101_esp32p4',
+        pytest.param('default_ip101_esp32p4', 'esp32p4', marks=[pytest.mark.eth_ip101]),
+        pytest.param('default_ip101_esp32p4v1', 'esp32p4', marks=[pytest.mark.eth_ip101, pytest.mark.esp32p4_eco4]),
     ],
-    indirect=True,
+    indirect=['target'],
 )
-@idf_parametrize('target', ['esp32p4'], indirect=['target'])
 def test_esp32p4_emac(dut: IdfDut) -> None:
     ethernet_int_emac_test(dut)
     dut.serial.hard_reset()
     ethernet_heap_alloc_test(dut)
 
 
-@pytest.mark.eth_ip101
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14365')
 @pytest.mark.parametrize(
-    'config',
+    'config, target',
     [
-        'rmii_clko_esp32p4',
+        pytest.param('rmii_clko_esp32p4', 'esp32p4', marks=[pytest.mark.eth_ip101]),
+        pytest.param('rmii_clko_esp32p4v1', 'esp32p4', marks=[pytest.mark.eth_ip101, pytest.mark.esp32p4_eco4]),
     ],
-    indirect=True,
+    indirect=['target'],
 )
-@idf_parametrize('target', ['esp32p4'], indirect=['target'])
 def test_esp32p4_emac_clko(dut: IdfDut) -> None:
     dut.run_all_single_board_cases(group='esp_emac_clk_out')
 
diff --git a/components/esp_eth/test_apps/sdkconfig.ci.default_ip101_esp32p4v1 b/components/esp_eth/test_apps/sdkconfig.ci.default_ip101_esp32p4v1
new file mode 100644
index 0000000000..73e634ed33
--- /dev/null
+++ b/components/esp_eth/test_apps/sdkconfig.ci.default_ip101_esp32p4v1
@@ -0,0 +1,12 @@
+CONFIG_IDF_TARGET="esp32p4"
+CONFIG_ESP32P4_SELECTS_REV_LESS_V3=y
+
+CONFIG_UNITY_ENABLE_FIXTURE=y
+CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y
+CONFIG_ETH_USE_ESP32_EMAC=y
+CONFIG_ESP_TASK_WDT_EN=n
+
+CONFIG_TARGET_USE_INTERNAL_ETHERNET=y
+CONFIG_TARGET_ETH_PHY_DEVICE_IP101=y
+
+CONFIG_TARGET_USE_DEFAULT_EMAC_CONFIG=y
diff --git a/components/esp_eth/test_apps/sdkconfig.ci.rmii_clko_esp32p4v1 b/components/esp_eth/test_apps/sdkconfig.ci.rmii_clko_esp32p4v1
new file mode 100644
index 0000000000..f5b3550e85
--- /dev/null
+++ b/components/esp_eth/test_apps/sdkconfig.ci.rmii_clko_esp32p4v1
@@ -0,0 +1,18 @@
+CONFIG_IDF_TARGET="esp32p4"
+CONFIG_ESP32P4_SELECTS_REV_LESS_V3=y
+
+CONFIG_UNITY_ENABLE_FIXTURE=y
+CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y
+CONFIG_ETH_USE_ESP32_EMAC=y
+CONFIG_ESP_TASK_WDT_EN=n
+
+CONFIG_TARGET_USE_INTERNAL_ETHERNET=y
+CONFIG_TARGET_ETH_PHY_DEVICE_IP101=y
+
+CONFIG_TARGET_USE_DEFAULT_EMAC_CONFIG=y
+
+CONFIG_TARGET_RMII_CLK_OUT=y
+# Test board needs to be modified!
+# Connect GPIO23 to GPIO32 via wire.
+CONFIG_TARGET_RMII_CLK_OUT_GPIO=23
+CONFIG_TARGET_RMII_CLK_IN_GPIO=32
diff --git a/components/esp_event/test_apps/pytest_esp_event.py b/components/esp_event/test_apps/pytest_esp_event.py
index a8b47ca347..20d59bb2b9 100644
--- a/components/esp_event/test_apps/pytest_esp_event.py
+++ b/components/esp_event/test_apps/pytest_esp_event.py
@@ -7,6 +7,14 @@ from pytest_embedded_idf.utils import idf_parametrize
 
 @pytest.mark.generic
 @idf_parametrize('target', ['esp32', 'esp32s2', 'esp32c3'], indirect=['target'])
+@pytest.mark.parametrize(
+    'config',
+    [
+        'defaults',
+        'no_isr_post',
+    ],
+    indirect=True,
+)
 def test_esp_event(dut: Dut) -> None:
     dut.run_all_single_board_cases()
 
@@ -14,6 +22,13 @@ def test_esp_event(dut: Dut) -> None:
 @pytest.mark.host_test
 @pytest.mark.qemu
 @pytest.mark.xfail('config.getvalue("target") == "esp32c3"', reason='Unstable on QEMU, needs investigation')
+@pytest.mark.parametrize(
+    'config',
+    [
+        'defaults',
+    ],
+    indirect=True,
+)
 @idf_parametrize('target', ['esp32', 'esp32c3'], indirect=['target'])
 def test_esp_event_qemu(dut: Dut) -> None:
     for case in dut.test_menu:
@@ -23,6 +38,13 @@ def test_esp_event_qemu(dut: Dut) -> None:
 
 @pytest.mark.host_test
 @idf_parametrize('target', ['linux'], indirect=['target'])
+@pytest.mark.parametrize(
+    'config',
+    [
+        'defaults',
+    ],
+    indirect=True,
+)
 def test_esp_event_posix_simulator(dut: Dut) -> None:
     dut.expect_exact('Press ENTER to see the list of tests.')
     dut.write('*')
@@ -31,6 +53,13 @@ def test_esp_event_posix_simulator(dut: Dut) -> None:
 
 @pytest.mark.generic
 @idf_parametrize('target', ['esp32'], indirect=['target'])
+@pytest.mark.parametrize(
+    'config',
+    [
+        'defaults',
+    ],
+    indirect=True,
+)
 def test_esp_event_profiling(dut: Dut) -> None:
     dut.expect_exact('Press ENTER to see the list of tests.')
     dut.write('"profiling reports valid values"')
diff --git a/components/esp_event/test_apps/sdkconfig.ci.defaults b/components/esp_event/test_apps/sdkconfig.ci.defaults
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/components/esp_event/test_apps/sdkconfig.ci.no_isr_post b/components/esp_event/test_apps/sdkconfig.ci.no_isr_post
index 1b0464b258..74478bc74b 100644
--- a/components/esp_event/test_apps/sdkconfig.ci.no_isr_post
+++ b/components/esp_event/test_apps/sdkconfig.ci.no_isr_post
@@ -1,3 +1,2 @@
 # This configuration checks the event loop if posting from ISR is disabled
-CONFIG_ESP_TASK_WDT_INIT=n
-CONFIG_POST_EVENTS_FROM_ISR=n
+CONFIG_ESP_EVENT_POST_FROM_ISR=n
diff --git a/components/esp_hw_support/Kconfig b/components/esp_hw_support/Kconfig
index efaf9a418a..0965331144 100644
--- a/components/esp_hw_support/Kconfig
+++ b/components/esp_hw_support/Kconfig
@@ -319,6 +319,7 @@ menu "Hardware Settings"
     config ESP_ENABLE_PVT
         bool "Auto adjust hp & lp voltage using pvt function (MUST ENABLE FOR MP)"
         depends on SOC_PMU_PVT_SUPPORTED
+        default n if IDF_TARGET_ESP32C6
         default y
         help
             If enabled, hp & lp voltage can be auto adjust by PVT characteristic.
diff --git a/components/esp_hw_support/dma/esp_dma_utils.c b/components/esp_hw_support/dma/esp_dma_utils.c
index a820291bcd..14e2a56648 100644
--- a/components/esp_hw_support/dma/esp_dma_utils.c
+++ b/components/esp_hw_support/dma/esp_dma_utils.c
@@ -20,6 +20,9 @@
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
 #include "esp_cache.h"
+#if CONFIG_SPIRAM
+#include "esp_private/esp_psram_mspi.h"
+#endif
 
 static const char *TAG = "dma_utils";
 
@@ -52,7 +55,7 @@ esp_err_t esp_dma_split_rx_buffer_to_cache_aligned(void *rx_buffer, size_t buffe
     } else {
         // If the stash buffer is offered by the caller, check if it is aligned
         ESP_RETURN_ON_FALSE_ISR(split_line_size == 0 || (uintptr_t)(*ret_stash_buffer) % split_line_size == 0,
-                            ESP_ERR_INVALID_ARG, TAG, "the offered stash buffer is not aligned");
+                                ESP_ERR_INVALID_ARG, TAG, "the offered stash buffer is not aligned");
         // If the stash buffer is offered by the caller, use it
         stash_buffer = *ret_stash_buffer;
     }
@@ -127,6 +130,15 @@ esp_err_t esp_dma_merge_aligned_rx_buffers(dma_buffer_split_array_t *align_array
 {
     ESP_RETURN_ON_FALSE_ISR(align_array, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
 
+#if CONFIG_SPIRAM
+    // check if the original buffer is in external RAM, if so, add memory barrier
+    if (esp_ptr_external_ram(align_array->buf.head.recovery_address) ||
+            esp_ptr_external_ram(align_array->buf.body.recovery_address) ||
+            esp_ptr_external_ram(align_array->buf.tail.recovery_address)) {
+        esp_psram_mspi_mb();
+    }
+#endif
+
     // only need to copy the head and tail buffer
     if (align_array->buf.head.length) {
         memcpy(align_array->buf.head.recovery_address, align_array->buf.head.aligned_buffer, align_array->buf.head.length);
diff --git a/components/esp_hw_support/dma/gdma.c b/components/esp_hw_support/dma/gdma.c
index a1348db51c..23c6f12b47 100644
--- a/components/esp_hw_support/dma/gdma.c
+++ b/components/esp_hw_support/dma/gdma.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -28,7 +28,6 @@
 
 #include "gdma_priv.h"
 #include "esp_memory_utils.h"
-#include "esp_flash_encrypt.h"
 
 #if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
 #include "esp_private/gdma_sleep_retention.h"
@@ -383,6 +382,21 @@ esp_err_t gdma_config_transfer(gdma_channel_handle_t dma_chan, const gdma_transf
     // always enable descriptor burst as the descriptor is always word aligned and is in the internal SRAM
     bool en_desc_burst = true;
     bool en_data_burst = max_data_burst_size > 0;
+
+#if SOC_PSRAM_DMA_CAPABLE || SOC_DMA_CAN_ACCESS_FLASH
+    // if MSPI encryption is enabled, and DMA wants to read/write external memory
+    if (efuse_hal_flash_encryption_enabled() && config->access_ext_mem) {
+        uint32_t enc_mem_alignment = GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT;
+        // when DMA access the encrypted external memory, extra alignment is needed for external memory
+        ext_mem_alignment = MAX(ext_mem_alignment, enc_mem_alignment);
+        if (max_data_burst_size < enc_mem_alignment) {
+            ESP_LOGW(TAG, "GDMA channel access encrypted external memory, adjust burst size to %d", enc_mem_alignment);
+            en_data_burst = true;
+            max_data_burst_size = enc_mem_alignment;
+        }
+    }
+#endif // SOC_PSRAM_DMA_CAPABLE || SOC_DMA_CAN_ACCESS_FLASH
+
     gdma_hal_enable_burst(hal, pair->pair_id, dma_chan->direction, en_data_burst, en_desc_burst);
     if (en_data_burst) {
         gdma_hal_set_burst_size(hal, pair->pair_id, dma_chan->direction, max_data_burst_size);
@@ -395,17 +409,6 @@ esp_err_t gdma_config_transfer(gdma_channel_handle_t dma_chan, const gdma_transf
     }
 #endif
 
-    // if MSPI encryption is enabled, and DMA wants to read/write external memory
-    if (esp_flash_encryption_enabled()) {
-        gdma_hal_enable_access_encrypt_mem(hal, pair->pair_id, dma_chan->direction, config->access_ext_mem);
-        // when DMA access the encrypted memory, extra alignment is needed for external memory
-        if (config->access_ext_mem) {
-            ext_mem_alignment = MAX(ext_mem_alignment, GDMA_ACCESS_ENCRYPTION_MEM_ALIGNMENT);
-        }
-    } else {
-        gdma_hal_enable_access_encrypt_mem(hal, pair->pair_id, dma_chan->direction, false);
-    }
-
     // if the channel is not allowed to access external memory, set a super big (meaningless) alignment value
     // so when the upper layer checks the alignment with an external buffer, the check should fail
     if (!config->access_ext_mem) {
diff --git a/components/esp_hw_support/dma/gdma_link.c b/components/esp_hw_support/dma/gdma_link.c
index 8994399d0e..dc8b057c29 100644
--- a/components/esp_hw_support/dma/gdma_link.c
+++ b/components/esp_hw_support/dma/gdma_link.c
@@ -16,6 +16,7 @@
 #include "esp_heap_caps.h"
 #include "esp_private/gdma_link.h"
 #include "hal/cache_hal.h"
+#include "hal/efuse_hal.h"
 #include "hal/cache_ll.h"
 #include "esp_cache.h"
 
@@ -79,9 +80,16 @@ esp_err_t gdma_new_link_list(const gdma_link_list_config_t *config, gdma_link_li
     // guard against overflow when calculating total bytes for descriptors
     ESP_GOTO_ON_FALSE(num_items <= SIZE_MAX / item_size, ESP_ERR_INVALID_SIZE, err, TAG, "list too big");
 
+    bool items_in_ext_mem = config->flags.items_in_ext_mem;
     uint32_t list_items_mem_caps = MALLOC_CAP_8BIT | MALLOC_CAP_DMA;
-    if (config->flags.items_in_ext_mem) {
-        list_items_mem_caps |= MALLOC_CAP_SPIRAM;
+    if (items_in_ext_mem) {
+        if (efuse_hal_flash_encryption_enabled()) {
+            items_in_ext_mem = false;
+            list_items_mem_caps |= MALLOC_CAP_INTERNAL;
+            ESP_LOGW(TAG, "DMA linked list items cannot be placed in PSRAM when external memory encryption is enabled, using internal memory instead");
+        } else {
+            list_items_mem_caps |= MALLOC_CAP_SPIRAM;
+        }
     } else {
         list_items_mem_caps |= MALLOC_CAP_INTERNAL;
     }
@@ -90,7 +98,7 @@ esp_err_t gdma_new_link_list(const gdma_link_list_config_t *config, gdma_link_li
 
     // do memory sync if the list items are in the cache
     uint32_t data_cache_line_size = 0;
-    if (config->flags.items_in_ext_mem) {
+    if (items_in_ext_mem) {
         data_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA);
     } else {
         data_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
@@ -178,6 +186,10 @@ esp_err_t gdma_link_mount_buffers(gdma_link_list_handle_t list, int start_item_i
         size_t max_buffer_mount_length = ALIGN_DOWN(GDMA_MAX_BUFFER_SIZE_PER_LINK_ITEM, buffer_alignment);
         if (!config->flags.bypass_buffer_align_check) {
             ESP_RETURN_ON_FALSE_ISR(((uintptr_t)buf & (buffer_alignment - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "buf misalign idx=%"PRIu32" align=%"PRIu32, bi, buffer_alignment);
+            if (efuse_hal_flash_encryption_enabled()) {
+                // buffer size must be aligned to the encryption alignment which should be provided by the upper buffer_alignment
+                ESP_RETURN_ON_FALSE_ISR((len & (buffer_alignment - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "buf len misalign idx=%"PRIu32" len=%"PRIu32" align=%"PRIu32"", bi, len, buffer_alignment);
+            }
         }
         size_t num_items_need = (len + max_buffer_mount_length - 1) / max_buffer_mount_length;
         ESP_RETURN_ON_FALSE_ISR(num_items_need <= remaining, ESP_ERR_INVALID_ARG, TAG,
diff --git a/components/esp_hw_support/dma/gdma_priv.h b/components/esp_hw_support/dma/gdma_priv.h
index 4c0d921a59..977bd05db0 100644
--- a/components/esp_hw_support/dma/gdma_priv.h
+++ b/components/esp_hw_support/dma/gdma_priv.h
@@ -30,6 +30,7 @@
 #include "hal/gdma_hal_ahb.h"
 #include "hal/gdma_hal_axi.h"
 #include "soc/gdma_periph.h"
+#include "hal/efuse_hal.h"
 #include "soc/periph_defs.h"
 #include "esp_private/gdma.h"
 #include "esp_private/periph_ctrl.h"
@@ -40,8 +41,6 @@
 #define GDMA_MEM_ALLOC_CAPS    MALLOC_CAP_DEFAULT
 #endif
 
-#define GDMA_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 /*!< The alignment of the memory and size when DMA accesses the encryption memory */
-
 ///!< Logging settings
 #define TAG "gdma"
 
diff --git a/components/esp_hw_support/hw_random.c b/components/esp_hw_support/hw_random.c
index f451189ff0..49992019c9 100644
--- a/components/esp_hw_support/hw_random.c
+++ b/components/esp_hw_support/hw_random.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2016-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2016-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -25,6 +25,9 @@
 
 #if SOC_RNG_CLOCK_IS_INDEPENDENT
 #include "hal/lp_clkrst_ll.h"
+#if SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE || SOC_RNG_RTC_TIMER_ENTROPY_SOURCE
+#include "hal/rng_ll.h"
+#endif
 #endif
 
 #if defined CONFIG_IDF_TARGET_ESP32S3
@@ -106,15 +109,10 @@ void esp_fill_random(void *buf, size_t len)
 #if SOC_RNG_CLOCK_IS_INDEPENDENT && !ESP_TEE_BUILD
 ESP_SYSTEM_INIT_FN(init_rng, SECONDARY, BIT(0), 102)
 {
+#if SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE || SOC_RNG_RTC_TIMER_ENTROPY_SOURCE
+    rng_ll_enable();
+#else
     _lp_clkrst_ll_enable_rng_clock(true);
-#if SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE
-    SET_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_SAMPLE_ENABLE);
-#endif
-
-#if SOC_RNG_RTC_TIMER_ENTROPY_SOURCE
-    // This would only be effective if the RTC clock is enabled
-    REG_SET_FIELD(LPPERI_RNG_CFG_REG, LPPERI_RTC_TIMER_EN, 0x3);
-    SET_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_TIMER_EN);
 #endif
     return ESP_OK;
 }
diff --git a/components/esp_hw_support/linker.lf b/components/esp_hw_support/linker.lf
index c5c80bdff1..d839f8bf8b 100644
--- a/components/esp_hw_support/linker.lf
+++ b/components/esp_hw_support/linker.lf
@@ -43,7 +43,7 @@ entries:
         elif PM_SLP_IRAM_OPT = y && IDF_TARGET_ESP32P4 != y:
             pmu_param:get_act_hp_dbias (noflash)
             pmu_param:get_act_lp_dbias (noflash)
-    if SOC_PMU_PVT_SUPPORTED = y:
+    if SOC_PMU_PVT_SUPPORTED = y && ESP_ENABLE_PVT = y:
         pmu_pvt (noflash)
     if PM_SLP_IRAM_OPT = y && SOC_USB_SERIAL_JTAG_SUPPORTED = y:
         sleep_console (noflash)
diff --git a/components/esp_hw_support/port/esp32c6/CMakeLists.txt b/components/esp_hw_support/port/esp32c6/CMakeLists.txt
index ed1586db48..bf7b225913 100644
--- a/components/esp_hw_support/port/esp32c6/CMakeLists.txt
+++ b/components/esp_hw_support/port/esp32c6/CMakeLists.txt
@@ -15,6 +15,10 @@ if(NOT non_os_build)
 
 endif()
 
+if(NOT BOOTLOADER_BUILD AND CONFIG_ESP_ENABLE_PVT)
+    list(APPEND srcs "pmu_pvt.c")
+endif()
+
 add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
 
 target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
diff --git a/components/esp_hw_support/port/esp32c6/include/soc/rtc.h b/components/esp_hw_support/port/esp32c6/include/soc/rtc.h
index 307702a3c1..241541ff20 100644
--- a/components/esp_hw_support/port/esp32c6/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32c6/include/soc/rtc.h
@@ -96,6 +96,54 @@ set sleep_init default param
 #define RTC_CNTL_PD_CUR_SLEEP_DEFAULT  1
 #define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
 
+#if CONFIG_ESP_ENABLE_PVT
+/*
+set pvt default param
+*/
+#define PVT_CHANNEL0_SEL        34
+#define PVT_CHANNEL1_SEL        38
+#define PVT_CHANNEL0_CFG        0x1033e
+#define PVT_CHANNEL1_CFG        0x1033e
+#define PVT_CHANNEL2_CFG        0x10000
+#define PVT_CMD0                0x24
+#define PVT_CMD1                0x5
+#define PVT_CMD2                0x427
+#define PVT_TARGET              0xffff
+#define PVT_CLK_DIV             1
+#define PVT_EDG_MODE            1
+#define PVT_DELAY_NUM_HIGH      108
+#define PVT_DELAY_NUM_LOW       98
+#define PVT_PUMP_CHANNEL_CODE   1
+#define PVT_PUMP_BITMAP         21
+#define PVT_PUMP_DRV            0
+#define PVT_DELAY_NUM_PUMP      95
+
+/**
+ * @brief Initialize PVT related parameters
+ */
+void pvt_auto_dbias_init(void);
+
+/**
+ * @brief Enable or disable PVT functions
+ *
+ * @param enable  true to enable, false to disable
+ */
+void pvt_func_enable(bool enable);
+
+/**
+ * @brief Initialize charge pump related parameters
+ */
+void charge_pump_init(void);
+
+/**
+ * @brief Enable or disable charge pump functions
+ *
+ * @param enable  true to enable, false to disable
+ */
+void charge_pump_enable(bool enable);
+
+#endif //#if CONFIG_ESP_ENABLE_PVT
+
 /*
 The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
 storing in efuse (based on ATE 5k ECO3 chips)
diff --git a/components/esp_hw_support/port/esp32c6/pmu_init.c b/components/esp_hw_support/port/esp32c6/pmu_init.c
index 93d5b1645a..93e0d64a6e 100644
--- a/components/esp_hw_support/port/esp32c6/pmu_init.c
+++ b/components/esp_hw_support/port/esp32c6/pmu_init.c
@@ -19,6 +19,10 @@
 #include "regi2c_ctrl.h"
 #include "esp_private/ocode_init.h"
 #include "esp_rom_sys.h"
+#include "soc/rtc.h"
+#include "hal/efuse_ll.h"
+#include "hal/efuse_hal.h"
+#include "esp_hw_log.h"
 
 static __attribute__((unused)) const char *TAG = "pmu_init";
 
@@ -226,4 +230,20 @@ void pmu_init(void)
         esp_ocode_calib_init();
     }
 #endif
+
+#if CONFIG_ESP_ENABLE_PVT
+    /*setup pvt function*/
+    uint32_t blk_version = efuse_hal_blk_version();
+    if (blk_version >= 3) {
+        pvt_auto_dbias_init();
+        charge_pump_init();
+
+        pvt_func_enable(true);
+        charge_pump_enable(true);
+        esp_rom_delay_us(1000);
+    }
+    else {
+        ESP_HW_LOGW(TAG, "blk_version is less than 3, pvt function not supported in efuse.");
+    }
+#endif
 }
diff --git a/components/esp_hw_support/port/esp32c6/pmu_param.c b/components/esp_hw_support/port/esp32c6/pmu_param.c
index 15184c698c..40f24b5943 100644
--- a/components/esp_hw_support/port/esp32c6/pmu_param.c
+++ b/components/esp_hw_support/port/esp32c6/pmu_param.c
@@ -351,7 +351,7 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
 
 #define PMU_LP_SLEEP_POWER_CONFIG_DEFAULT() { \
     .dig_power = {              \
-        .mem_dslp       = 1,    \
+        .mem_dslp       = 0,    \
         .peri_pd_en     = 0,    \
     }, \
     .clk_power = {              \
diff --git a/components/esp_hw_support/port/esp32c6/pmu_pvt.c b/components/esp_hw_support/port/esp32c6/pmu_pvt.c
new file mode 100644
index 0000000000..c8a28616f7
--- /dev/null
+++ b/components/esp_hw_support/port/esp32c6/pmu_pvt.c
@@ -0,0 +1,170 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <esp_types.h>
+#include "sdkconfig.h"
+#include "esp_attr.h"
+#include "soc/soc.h"
+#include "soc/pmu_struct.h"
+#include "soc/pvt_reg.h"
+#include "soc/pmu_reg.h"
+#include "soc/pcr_reg.h"
+#include "hal/pmu_hal.h"
+#include "pmu_param.h"
+#include "esp_rom_sys.h"
+#include "esp_private/esp_pmu.h"
+#include "soc/regi2c_dig_reg.h"
+#include "regi2c_ctrl.h"
+#include "soc/rtc.h"
+#include "hal/efuse_ll.h"
+#include "hal/efuse_hal.h"
+#include "esp_hw_log.h"
+
+static __attribute__((unused)) const char *TAG = "pmu_pvt";
+
+#if CONFIG_ESP_ENABLE_PVT
+
+static uint8_t get_lp_hp_gap(void)
+{
+    int8_t pvt_offset = 0;
+    uint32_t blk_version = efuse_hal_blk_version();
+    if (blk_version >= 3) {
+        uint8_t offset_read = efuse_ll_get_dbias_vol_gap();
+        bool offset_flag = offset_read >> 4;
+        uint8_t offset_value = offset_read & 0xf;
+        int8_t pvt_offset = 0;
+        if (offset_flag) {
+            pvt_offset = -1 * offset_value;
+        } else {
+            pvt_offset = offset_value;
+        }
+        pvt_offset = pvt_offset - 2;
+        assert((pvt_offset >= -15) && (pvt_offset <= 13));
+        if (pvt_offset < 0 ) {
+            pvt_offset = 16 - pvt_offset;
+        }
+    }
+    return pvt_offset;
+}
+
+static void set_pvt_hp_lp_gap(uint8_t value)
+{
+    bool flag = value >> 4;
+    uint8_t abs_value = value & 0xf;
+
+    SET_PERI_REG_BITS(PVT_DBIAS_CMD0_REG, PVT_DBIAS_CMD0_OFFSET_FLAG, flag, PVT_DBIAS_CMD0_OFFSET_FLAG_S);
+    SET_PERI_REG_BITS(PVT_DBIAS_CMD0_REG, PVT_DBIAS_CMD0_OFFSET_VALUE, abs_value, PVT_DBIAS_CMD0_OFFSET_VALUE_S);
+    SET_PERI_REG_BITS(PVT_DBIAS_CMD1_REG, PVT_DBIAS_CMD1_OFFSET_FLAG, flag, PVT_DBIAS_CMD1_OFFSET_FLAG_S);
+    SET_PERI_REG_BITS(PVT_DBIAS_CMD1_REG, PVT_DBIAS_CMD1_OFFSET_VALUE, abs_value, PVT_DBIAS_CMD1_OFFSET_VALUE_S);
+    SET_PERI_REG_BITS(PVT_DBIAS_CMD2_REG, PVT_DBIAS_CMD2_OFFSET_FLAG, flag, PVT_DBIAS_CMD2_OFFSET_FLAG_S);
+    SET_PERI_REG_BITS(PVT_DBIAS_CMD2_REG, PVT_DBIAS_CMD2_OFFSET_VALUE, abs_value, PVT_DBIAS_CMD2_OFFSET_VALUE_S);
+}
+
+FORCE_INLINE_ATTR uint32_t get_pvt_hp_dbias(void)
+{
+    return REG_GET_FIELD(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_DBIAS_VOL);
+}
+
+FORCE_INLINE_ATTR uint32_t get_pvt_lp_dbias(void)
+{
+    return REG_GET_FIELD(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_LP_DBIAS_VOL);
+}
+
+void pvt_auto_dbias_init(void)
+{
+    uint32_t blk_version = efuse_hal_blk_version();
+    if (blk_version >= 3) {
+        SET_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
+        SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
+        /*config for dbias func*/
+        CLEAR_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN);
+        esp_rom_delay_us(1);
+        SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL_SEL0_REG, PVT_DBIAS_CHANNEL0_SEL, PVT_CHANNEL0_SEL, PVT_DBIAS_CHANNEL0_SEL_S);
+        SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL_SEL0_REG, PVT_DBIAS_CHANNEL1_SEL, PVT_CHANNEL1_SEL, PVT_DBIAS_CHANNEL1_SEL_S);  // Select monitor cell ,which  used to monitor PVT situation
+        SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL0_SEL_REG, PVT_DBIAS_CHANNEL0_CFG, PVT_CHANNEL0_CFG, PVT_DBIAS_CHANNEL0_CFG_S);
+        SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL1_SEL_REG, PVT_DBIAS_CHANNEL1_CFG, PVT_CHANNEL1_CFG, PVT_DBIAS_CHANNEL1_CFG_S);
+        SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL2_SEL_REG, PVT_DBIAS_CHANNEL2_CFG, PVT_CHANNEL2_CFG, PVT_DBIAS_CHANNEL2_CFG_S);  // Configure filter threshold  for avoiding auto-dbias overly sensitive regulation
+        SET_PERI_REG_BITS(PVT_DBIAS_CMD0_REG, PVT_DBIAS_CMD0_PVT, PVT_CMD0, PVT_DBIAS_CMD0_PVT_S);
+        SET_PERI_REG_BITS(PVT_DBIAS_CMD1_REG, PVT_DBIAS_CMD1_PVT, PVT_CMD1, PVT_DBIAS_CMD1_PVT_S);
+        SET_PERI_REG_BITS(PVT_DBIAS_CMD2_REG, PVT_DBIAS_CMD2_PVT, PVT_CMD2, PVT_DBIAS_CMD2_PVT_S); // Configure auto-dbias adjust property, such as adjusting step
+        SET_PERI_REG_BITS(PVT_DBIAS_TIMER_REG, PVT_TIMER_TARGET, PVT_TARGET, PVT_TIMER_TARGET_S);   // Configure auto-dbias  voltage regulation cycle
+
+        SET_PERI_REG_BITS(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM, PVT_CLK_DIV, PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S); //pvt function clock divider number
+
+        /*config for pvt cell: unit0; site2; vt2*/
+        SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_SEL); //pvt function clock source select
+        SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_REG, PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0, PVT_EDG_MODE, PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_S);  // Select edge_mode
+        SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0, PVT_DELAY_NUM_HIGH, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_S); // The threshold for determining whether the voltage is too high
+        SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_REG, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1, PVT_DELAY_NUM_LOW, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_S); // The threshold for determining whether the voltage is too low
+        SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_REG, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2, PVT_DELAY_NUM_PUMP, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_S); // The threshold for chargepump
+
+        /*config lp offset for pvt func*/
+        uint8_t lp_hp_gap = get_lp_hp_gap();
+        set_pvt_hp_lp_gap(lp_hp_gap);
+    } else {
+        ESP_HW_LOGD(TAG, "blk_version is less than 3, pvt auto dbias init not supported in efuse.");
+    }
+}
+
+void IRAM_ATTR pvt_func_enable(bool enable)
+{
+    uint32_t blk_version = efuse_hal_blk_version();
+    if (blk_version >= 3) {
+        if (enable) {
+            SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT);     // start calibration @HP_CALI_DBIAS_DEFAUL
+            SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
+            SET_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
+            SET_PERI_REG_MASK(PVT_CLK_CFG_REG, PVT_MONITOR_CLK_PVT_EN);
+            SET_PERI_REG_MASK(PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG, PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0);    // enable pvt clk
+            esp_rom_delay_us(10);
+            CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pvt
+            CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT);     // must clear @HP_CALI_DBIAS_DEFAULT
+            SET_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN);   // enable auto dbias
+        } else {
+            uint32_t pvt_hp_dbias = get_pvt_hp_dbias();
+            uint32_t pvt_lp_dbias = get_pvt_lp_dbias(); // update pvt_cali_dbias
+            SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, pvt_hp_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S);
+            SET_PERI_REG_BITS(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, pvt_lp_dbias, PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S);
+            CLEAR_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); //disable auto dbias
+            SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL);   // hand over control of dbias to pmu
+            CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
+            CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
+        }
+    } else {
+        ESP_HW_LOGD(TAG, "blk_version is less than 3, pvt enable not supported in efuse.");
+    }
+}
+
+void charge_pump_init(void)
+{
+    uint32_t blk_version = efuse_hal_blk_version();
+    if (blk_version >= 3) {
+        /*config for charge pump*/
+        SET_PERI_REG_BITS(PVT_PMUP_CHANNEL_CFG_REG, PVT_PUMP_CHANNEL_CODE0, PVT_PUMP_CHANNEL_CODE, PVT_PUMP_CHANNEL_CODE0_S);   //Set channel code
+        WRITE_PERI_REG(PVT_PMUP_BITMAP_LOW0_REG, (1 << PVT_PUMP_BITMAP));  // Select monitor cell for charge pump
+        SET_PERI_REG_BITS(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_DRV0, PVT_PUMP_DRV, PVT_PUMP_DRV0_S); //Configure the charging intensity
+    } else {
+        ESP_HW_LOGD(TAG, "blk_version is less than 3, pvt charge_pump init not supported in efuse.");
+    }
+}
+
+void IRAM_ATTR charge_pump_enable(bool enable)
+{
+    uint32_t blk_version = efuse_hal_blk_version();
+    if (blk_version >= 3) {
+        if (enable) {
+            SET_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN);   // enable charge pump
+        } else {
+            CLEAR_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); //disable charge pump
+        }
+    } else {
+        ESP_HW_LOGD(TAG, "blk_version is less than 3, pvt charge_pump enable not supported in efuse.");
+    }
+}
+
+#endif
diff --git a/components/esp_hw_support/port/esp32c6/pmu_sleep.c b/components/esp_hw_support/port/esp32c6/pmu_sleep.c
index 274fd9ca61..4fcbfce208 100644
--- a/components/esp_hw_support/port/esp32c6/pmu_sleep.c
+++ b/components/esp_hw_support/port/esp32c6/pmu_sleep.c
@@ -314,6 +314,10 @@ static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_con
     pmu_ll_hp_set_regulator_xpd               (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd);
     pmu_ll_hp_set_regulator_dbias             (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbias);
     pmu_ll_hp_set_regulator_driver_bar        (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.drv_b);
+#if CONFIG_ESP_ENABLE_PVT
+    uint32_t pvt_hp_dbias = GET_PERI_REG_BITS2(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_DBIAS_VOL_V, PMU_HP_DBIAS_VOL_S);
+    pmu_ll_hp_set_regulator_dbias             (ctx->hal->dev, HP(MODEM), pvt_hp_dbias);
+#endif
 
     pmu_ll_lp_set_dbg_atten            (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbg_atten);
     pmu_ll_lp_set_current_power_off    (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.pd_cur);
diff --git a/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h b/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h
index a0974f6a19..523ffb42db 100644
--- a/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h
+++ b/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h
@@ -305,7 +305,7 @@ typedef struct {
     .lp_sys[PMU_MODE_LP_SLEEP] = {                                          \
         .dig_power = {                                                      \
             .peri_pd_en    = ((sleep_flags) & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \
-            .mem_dslp      = 1                                              \
+            .mem_dslp      = 0                                              \
         },                                                                  \
         .clk_power = {                                                      \
             .xpd_xtal32k   = ((sleep_flags) & PMU_SLEEP_PD_XTAL32K) ? 0 : 1,\
diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk.c b/components/esp_hw_support/port/esp32c6/rtc_clk.c
index 07f287a9a7..95ebe55901 100644
--- a/components/esp_hw_support/port/esp32c6/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32c6/rtc_clk.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -190,6 +190,10 @@ static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
     clk_ll_cpu_set_ls_divider(div);
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
     esp_rom_set_cpu_ticks_per_us(cpu_freq);
+#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
+    charge_pump_enable(false);
+    pvt_func_enable(false);
+#endif
 }
 
 static void rtc_clk_cpu_freq_to_8m(void)
@@ -198,6 +202,10 @@ static void rtc_clk_cpu_freq_to_8m(void)
     clk_ll_cpu_set_ls_divider(1);
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
     esp_rom_set_cpu_ticks_per_us(20);
+#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
+    charge_pump_enable(false);
+    pvt_func_enable(false);
+#endif
 }
 
 /**
@@ -207,6 +215,12 @@ static void rtc_clk_cpu_freq_to_8m(void)
  */
 static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
 {
+#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
+    pvt_auto_dbias_init();
+    charge_pump_init();
+    pvt_func_enable(true);
+    charge_pump_enable(true);
+#endif
     clk_ll_cpu_set_hs_divider(CLK_LL_PLL_480M_FREQ_MHZ / cpu_freq_mhz);
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
     esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk_init.c b/components/esp_hw_support/port/esp32c6/rtc_clk_init.c
index 9ab938f02a..97e5a1638c 100644
--- a/components/esp_hw_support/port/esp32c6/rtc_clk_init.c
+++ b/components/esp_hw_support/port/esp32c6/rtc_clk_init.c
@@ -80,6 +80,8 @@ void rtc_clk_init(rtc_clk_config_t cfg)
     uint32_t hp_cali_dbias = get_act_hp_dbias();
     uint32_t lp_cali_dbias = get_act_lp_dbias();
 
+    SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // Hand over control of dbias to pmu
+
     SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, hp_cali_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S);
     SET_PERI_REG_BITS(PMU_HP_MODEM_HP_REGULATOR0_REG, PMU_HP_MODEM_HP_REGULATOR_DBIAS, hp_cali_dbias, PMU_HP_MODEM_HP_REGULATOR_DBIAS_S);
     SET_PERI_REG_BITS(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, lp_cali_dbias, PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S);
diff --git a/components/esp_hw_support/port/esp32p4/Kconfig.hw_support b/components/esp_hw_support/port/esp32p4/Kconfig.hw_support
index 7699334a4a..779fb19e95 100644
--- a/components/esp_hw_support/port/esp32p4/Kconfig.hw_support
+++ b/components/esp_hw_support/port/esp32p4/Kconfig.hw_support
@@ -34,6 +34,9 @@ choice ESP32P4_REV_MIN
     config ESP32P4_REV_MIN_300
         bool "Rev v3.0"
         depends on !ESP32P4_SELECTS_REV_LESS_V3
+    config ESP32P4_REV_MIN_301
+        bool "Rev v3.1"
+        depends on !ESP32P4_SELECTS_REV_LESS_V3
 endchoice
 
 config ESP32P4_REV_MIN_FULL
@@ -42,6 +45,7 @@ config ESP32P4_REV_MIN_FULL
     default 1 if ESP32P4_REV_MIN_1
     default 100 if ESP32P4_REV_MIN_100
     default 300 if ESP32P4_REV_MIN_300
+    default 301 if ESP32P4_REV_MIN_301
 
 config ESP_REV_MIN_FULL
     int
diff --git a/components/esp_hw_support/port/esp32p4/esp_clk_tree.c b/components/esp_hw_support/port/esp32p4/esp_clk_tree.c
index 102ea66476..02448f5e4f 100644
--- a/components/esp_hw_support/port/esp32p4/esp_clk_tree.c
+++ b/components/esp_hw_support/port/esp32p4/esp_clk_tree.c
@@ -8,6 +8,7 @@
 #include "esp_clk_tree.h"
 #include "esp_err.h"
 #include "esp_check.h"
+#include "soc/clk_tree_defs.h"
 #include "soc/rtc.h"
 #include "hal/clk_gate_ll.h"
 #include "hal/clk_tree_hal.h"
@@ -32,6 +33,12 @@ esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_sr
     case SOC_MOD_CLK_XTAL:
         clk_src_freq = clk_hal_xtal_get_freq_mhz() * MHZ;
         break;
+    case SOC_MOD_CLK_SYS:
+        clk_src_freq = clk_hal_sys_get_freq_hz();
+        break;
+    case SOC_MOD_CLK_APB:
+        clk_src_freq = clk_hal_apb_get_freq_hz();
+        break;
     case SOC_MOD_CLK_PLL_F20M:
         clk_src_freq = CLK_LL_PLL_480M_FREQ_MHZ / clk_ll_pll_f20m_get_divider() * MHZ;
         break;
diff --git a/components/esp_hw_support/port/esp32p4/pmu_sleep.c b/components/esp_hw_support/port/esp32p4/pmu_sleep.c
index a0bea8e56b..1d0330180e 100644
--- a/components/esp_hw_support/port/esp32p4/pmu_sleep.c
+++ b/components/esp_hw_support/port/esp32p4/pmu_sleep.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -221,11 +221,14 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
         config->analog = analog_default;
     }
 
+    if ((sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) || (sleep_flags & RTC_SLEEP_XTAL_AS_RTC_FAST)) {
+        config->analog.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
+        config->analog.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
+    }
+
     if (sleep_flags & RTC_SLEEP_XTAL_AS_RTC_FAST) {
         // Keep XTAL on in HP_SLEEP state if it is the clock source of RTC_FAST
         power_default.hp_sys.xtal.xpd_xtal = 1;
-        config->analog.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
-        config->analog.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
         config->analog.hp_sys.analog.dbg_atten = PMU_DBG_ATTEN_ACTIVE_DEFAULT;
         config->analog.hp_sys.analog.dbias = HP_CALI_ACTIVE_DBIAS_DEFAULT;
     }
diff --git a/components/esp_hw_support/port/esp32p4/rtc_clk_init.c b/components/esp_hw_support/port/esp32p4/rtc_clk_init.c
index 97f6eefb0b..a49598ff2f 100644
--- a/components/esp_hw_support/port/esp32p4/rtc_clk_init.c
+++ b/components/esp_hw_support/port/esp32p4/rtc_clk_init.c
@@ -68,15 +68,24 @@ void rtc_clk_init(rtc_clk_config_t cfg)
         hp_dcmvset = pvt_hp_dcmvset;
     }
     // Switch to DCDC
+#if CONFIG_ESP32P4_REV_MIN_301
+    unsigned chip_version = efuse_hal_chip_revision();
+    if (ESP_CHIP_REV_ABOVE(chip_version, 301)) {
+        SET_PERI_REG_MASK(PMU_DCM_CTRL_REG, PMU_DCDC_FB_RES_FORCE_PD);
+    }
+#endif
     pmu_ll_set_dcdc_en(&PMU, true);
     pmu_ll_set_dcdc_switch_force_power_down(&PMU, false);
     pmu_ll_hp_set_dcm_vset(&PMU, PMU_MODE_HP_ACTIVE, hp_dcmvset);
     SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // Hand over control of dbias to pmu
     esp_rom_delay_us(1000);
-    unsigned chip_version = efuse_hal_chip_revision();
+#if CONFIG_ESP32P4_REV_MIN_301
     if (ESP_CHIP_REV_ABOVE(chip_version, 301)) {
         REG_SET_FIELD(LP_SYSTEM_REG_SYS_CTRL_REG, LP_SYSTEM_REG_LP_FIB_SEL, 0xEF);// lp_fib_sel bit4 set to 0: select dig_fib_reg instead of ana_fib_reg
+        CLEAR_PERI_REG_MASK(PMU_DCM_CTRL_REG, PMU_DCDC_FB_RES_FORCE_PD);
+        esp_rom_delay_us(10);
     }
+#endif
     pmu_ll_hp_set_regulator_xpd(&PMU, PMU_MODE_HP_ACTIVE, false);
 
     soc_xtal_freq_t xtal_freq = cfg.xtal_freq;
diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c
index 5d0c46a928..913ad231da 100644
--- a/components/esp_hw_support/sleep_modes.c
+++ b/components/esp_hw_support/sleep_modes.c
@@ -40,6 +40,10 @@
 #include "hal/rtc_io_hal.h"
 #include "hal/clk_tree_hal.h"
 
+#if __has_include("hal/rng_ll.h")
+#include "hal/rng_ll.h"
+#endif
+
 #if SOC_SLEEP_SYSTIMER_STALL_WORKAROUND
 #include "hal/systimer_ll.h"
 #endif
@@ -751,7 +755,7 @@ static SLEEP_FN_ATTR void misc_modules_sleep_prepare(uint32_t sleep_flags, bool
         regi2c_tsens_reg_read();
 #endif
     }
-#if CONFIG_ESP_ENABLE_PVT
+#if CONFIG_ESP_ENABLE_PVT && SOC_PVT_EN_WITH_SLEEP
     pvt_func_enable(false);
 #endif
 
@@ -766,7 +770,7 @@ static SLEEP_FN_ATTR void misc_modules_sleep_prepare(uint32_t sleep_flags, bool
  */
 static SLEEP_FN_ATTR void misc_modules_wake_prepare(uint32_t sleep_flags)
 {
-#if CONFIG_ESP_ENABLE_PVT
+#if CONFIG_ESP_ENABLE_PVT && SOC_PVT_EN_WITH_SLEEP
     pvt_func_enable(true);
 #endif
 
@@ -810,6 +814,13 @@ static SLEEP_FN_ATTR void misc_modules_wake_prepare(uint32_t sleep_flags)
 #if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
     regi2c_tsens_reg_write();
 #endif
+#if RNG_LL_DEPENDS_ON_LP_PERIPH
+    if (sleep_flags & PMU_SLEEP_PD_LP_PERIPH) {
+        // Re-enable the RNG module.
+        rng_ll_reset();
+        rng_ll_enable();
+    }
+#endif
 }
 
 static SLEEP_FN_ATTR void sleep_low_power_clock_calibration(bool is_dslp)
@@ -2706,7 +2717,8 @@ static SLEEP_FN_ATTR uint32_t get_power_down_flags(void)
 #endif
 
 #if SOC_PM_SUPPORT_CNNT_PD
-    if (s_config.domain[ESP_PD_DOMAIN_CNNT].pd_option != ESP_PD_OPTION_ON && top_domain_pd_allowed()) {
+    // The TOP domain depends on the CNNT domain, only after the TOP power domain has been powered off is the CNNT power domain allowed to power down.
+    if (s_config.domain[ESP_PD_DOMAIN_CNNT].pd_option != ESP_PD_OPTION_ON && (pd_flags & PMU_SLEEP_PD_TOP)) {
         pd_flags |= PMU_SLEEP_PD_CNNT;
     }
 #endif
@@ -2737,9 +2749,6 @@ static SLEEP_FN_ATTR uint32_t get_power_down_flags(void)
         // TOP power domain depends on the RTC_PERIPH power domain on ESP32C6, RTC_PERIPH should only be disabled when the TOP domain is down.
         pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
     }
-#elif CONFIG_IDF_TARGET_ESP32C5
-    // TODO: [ESP32C5] PM-642 RNG module depends on LP PERIPH domain, force it on temporary.
-    pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
 #endif
     return pd_flags;
 }
diff --git a/components/esp_hw_support/sleep_system_peripheral.c b/components/esp_hw_support/sleep_system_peripheral.c
index bd8297654f..286659d00c 100644
--- a/components/esp_hw_support/sleep_system_peripheral.c
+++ b/components/esp_hw_support/sleep_system_peripheral.c
@@ -164,7 +164,7 @@ static __attribute__((unused)) esp_err_t sleep_sys_periph_retention_init(void *a
     err = sleep_pau_retention_init();
     if(err) goto error;
 #endif
-#if CONFIG_ESP_ENABLE_PVT
+#if CONFIG_ESP_ENABLE_PVT && SOC_PVT_RETENTION_BY_REGDMA
     err = sleep_pvt_retention_init();
     if(err) goto error;
 #endif
diff --git a/components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c b/components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c
index 7374d0589c..b5c9456a21 100644
--- a/components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c
+++ b/components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c
@@ -16,6 +16,8 @@
 #include "freertos/semphr.h"
 #include "ccomp_timer.h"
 #include "esp_async_memcpy.h"
+#include "hal/efuse_hal.h"
+
 #if SOC_GDMA_SUPPORTED
 #include "hal/gdma_ll.h"
 #endif
@@ -148,17 +150,19 @@ static bool test_async_memcpy_cb_v1(async_memcpy_handle_t mcp_hdl, async_memcpy_
 static void test_memory_copy_blocking(async_memcpy_handle_t driver)
 {
     SemaphoreHandle_t sem = xSemaphoreCreateBinary();
-    const uint32_t test_buffer_size[] = {256, 512, 1024, 2048, 4096, 5012};
+    const uint32_t test_buffer_size[] = {256, 512, 1024, 2048, 4096, 5008};
     memcpy_testbench_context_t test_context = {
-        .align = 4,
+        .align = 16,
     };
     for (int i = 0; i < sizeof(test_buffer_size) / sizeof(test_buffer_size[0]); i++) {
         // Test different align edge
         for (int off = 0; off < 4; off++) {
             test_context.buffer_size = test_buffer_size[i];
             test_context.seed = i;
-            test_context.src_offset = off;
-            test_context.dst_offset = off;
+            if (!efuse_hal_flash_encryption_enabled()) {
+                test_context.src_offset = off;
+                test_context.dst_offset = off;
+            }
             async_memcpy_setup_testbench(&test_context);
 
             TEST_ESP_OK(esp_async_memcpy(driver, test_context.to_addr, test_context.from_addr, test_context.copy_size, test_async_memcpy_cb_v1, sem));
@@ -235,6 +239,9 @@ TEST_CASE("memory copy with dest address unaligned", "[async mcp]")
     };
     [[maybe_unused]] async_memcpy_handle_t driver = NULL;
 
+    if (efuse_hal_flash_encryption_enabled()) {
+        TEST_PASS_MESSAGE("Flash encryption is enabled, skip this test");
+    }
 
 #if SOC_CP_DMA_SUPPORTED
     printf("Testing memcpy by CP DMA\r\n");
diff --git a/components/esp_hw_support/test_apps/dma/main/test_dw_gdma.c b/components/esp_hw_support/test_apps/dma/main/test_dw_gdma.c
index 45eeb11c32..37999612cb 100644
--- a/components/esp_hw_support/test_apps/dma/main/test_dw_gdma.c
+++ b/components/esp_hw_support/test_apps/dma/main/test_dw_gdma.c
@@ -11,6 +11,7 @@
 #include "unity.h"
 #include "esp_private/dw_gdma.h"
 #include "hal/dw_gdma_ll.h"
+#include "hal/efuse_hal.h"
 #include "esp_cache.h"
 #include "esp_private/esp_cache_private.h"
 
@@ -540,6 +541,9 @@ TEST_CASE("DW_GDMA M2M Test: memory set with fixed address", "[DW_GDMA]")
     size_t int_mem_alignment = 0;
     TEST_ESP_OK(esp_cache_get_alignment(MALLOC_CAP_SPIRAM, &ext_mem_alignment));
     TEST_ESP_OK(esp_cache_get_alignment(0, &int_mem_alignment));
+    if (efuse_hal_flash_encryption_enabled()) {
+        TEST_PASS_MESSAGE("Flash encryption is enabled, skip this test");
+    }
     uint8_t *src_buf = heap_caps_aligned_calloc(ext_mem_alignment, 1, 256, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
     uint8_t *dst_buf = heap_caps_aligned_calloc(int_mem_alignment, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
     TEST_ASSERT_NOT_NULL(src_buf);
diff --git a/components/esp_hw_support/test_apps/dma/main/test_gdma.c b/components/esp_hw_support/test_apps/dma/main/test_gdma.c
index bb487b2a2b..d9e0bc5065 100644
--- a/components/esp_hw_support/test_apps/dma/main/test_gdma.c
+++ b/components/esp_hw_support/test_apps/dma/main/test_gdma.c
@@ -20,6 +20,7 @@
 #include "hal/gdma_ll.h"
 #include "hal/cache_ll.h"
 #include "hal/cache_hal.h"
+#include "hal/efuse_hal.h"
 #include "esp_cache.h"
 #include "esp_memory_utils.h"
 #include "gdma_test_utils.h"
@@ -173,7 +174,8 @@ TEST_CASE("GDMA channel allocation", "[GDMA]")
 }
 
 static void test_gdma_config_link_list(gdma_channel_handle_t tx_chan, gdma_channel_handle_t rx_chan,
-                                       gdma_link_list_handle_t *tx_link_list, gdma_link_list_handle_t *rx_link_list, bool dma_link_in_ext_mem)
+                                       gdma_link_list_handle_t *tx_link_list, gdma_link_list_handle_t *rx_link_list,
+                                       size_t burst_size, bool dma_link_in_ext_mem)
 {
 
     gdma_strategy_config_t strategy = {
@@ -183,6 +185,15 @@ static void test_gdma_config_link_list(gdma_channel_handle_t tx_chan, gdma_chann
     TEST_ESP_OK(gdma_apply_strategy(tx_chan, &strategy));
     TEST_ESP_OK(gdma_apply_strategy(rx_chan, &strategy));
 
+    gdma_transfer_config_t transfer_cfg = {
+        .max_data_burst_size = burst_size,
+#if SOC_DMA_CAN_ACCESS_FLASH
+        .access_ext_mem = true,
+#endif
+    };
+    TEST_ESP_OK(gdma_config_transfer(tx_chan, &transfer_cfg));
+    TEST_ESP_OK(gdma_config_transfer(rx_chan, &transfer_cfg));
+
     gdma_trigger_t m2m_trigger = GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0);
     // get a free DMA trigger ID for memory copy
     uint32_t free_m2m_id_mask = 0;
@@ -231,16 +242,24 @@ static void test_gdma_m2m_transaction(gdma_channel_handle_t tx_chan, gdma_channe
     TEST_ASSERT_NOT_NULL(done_sem);
     TEST_ESP_OK(gdma_register_rx_event_callbacks(rx_chan, &rx_cbs, done_sem));
 
+    if (efuse_hal_flash_encryption_enabled()) {
+        dma_link_in_ext_mem = false;
+    }
+
     gdma_link_list_handle_t tx_link_list = NULL;
     gdma_link_list_handle_t rx_link_list = NULL;
-    test_gdma_config_link_list(tx_chan, rx_chan, &tx_link_list, &rx_link_list, dma_link_in_ext_mem);
+    test_gdma_config_link_list(tx_chan, rx_chan, &tx_link_list, &rx_link_list, 16, dma_link_in_ext_mem);
+
+    size_t int_mem_alignment = 0;
+    size_t ext_mem_alignment = 0;
+    TEST_ESP_OK(gdma_get_alignment_constraints(tx_chan, &int_mem_alignment, &ext_mem_alignment));
 
     // allocate the source buffer from SRAM
-    uint8_t *src_data = heap_caps_calloc(1, 128, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
+    uint8_t *src_data = heap_caps_aligned_calloc(int_mem_alignment, 1, 128, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
     TEST_ASSERT_NOT_NULL(src_data);
 
     // allocate the destination buffer from SRAM
-    uint8_t *dst_data = heap_caps_calloc(1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
+    uint8_t *dst_data = heap_caps_aligned_calloc(int_mem_alignment, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
     TEST_ASSERT_NOT_NULL(dst_data);
 
     // prepare the source data
@@ -253,7 +272,7 @@ static void test_gdma_m2m_transaction(gdma_channel_handle_t tx_chan, gdma_channe
     }
     // test DMA can read data from main flash
 #if SOC_DMA_CAN_ACCESS_FLASH
-    const char *src_string = "GDMA can read data from MSPI Flash";
+    static const char src_string[] __attribute__((aligned(GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT))) = "GDMA can read MSPI Flash data!!!";
     size_t src_string_len = strlen(src_string);
     TEST_ASSERT_TRUE(esp_ptr_in_drom(src_string));
 
@@ -268,12 +287,12 @@ static void test_gdma_m2m_transaction(gdma_channel_handle_t tx_chan, gdma_channe
     gdma_buffer_mount_config_t tx_buf_mount_config[] = {
         [0] = {
             .buffer = src_data,
-            .buffer_alignment = 1,
+            .buffer_alignment = int_mem_alignment,
             .length = 64,
         },
         [1] = {
             .buffer = src_data + 64,
-            .buffer_alignment = 1,
+            .buffer_alignment = int_mem_alignment,
             .length = 64,
 #if !SOC_DMA_CAN_ACCESS_FLASH
             .flags = {
@@ -285,7 +304,7 @@ static void test_gdma_m2m_transaction(gdma_channel_handle_t tx_chan, gdma_channe
 #if SOC_DMA_CAN_ACCESS_FLASH
         [2] = {
             .buffer = (void *)src_string,
-            .buffer_alignment = 1,
+            .buffer_alignment = ext_mem_alignment,
             .length = src_string_len,
             .flags = {
                 .mark_eof = true,
@@ -412,6 +431,8 @@ static void test_gdma_m2m_unaligned_buffer_test(uint8_t *dst_data, uint8_t *src_
 {
     TEST_ASSERT_NOT_NULL(src_data);
     TEST_ASSERT_NOT_NULL(dst_data);
+    memset(src_data, 0, data_length + offset_len);
+    memset(dst_data, 0, data_length + offset_len);
     gdma_channel_handle_t tx_chan = NULL;
     gdma_channel_handle_t rx_chan = NULL;
     gdma_channel_alloc_config_t tx_chan_alloc_config = {};
@@ -430,7 +451,10 @@ static void test_gdma_m2m_unaligned_buffer_test(uint8_t *dst_data, uint8_t *src_
 
     gdma_link_list_handle_t tx_link_list = NULL;
     gdma_link_list_handle_t rx_link_list = NULL;
-    test_gdma_config_link_list(tx_chan, rx_chan, &tx_link_list, &rx_link_list, false);
+    test_gdma_config_link_list(tx_chan, rx_chan, &tx_link_list, &rx_link_list, 0, false);
+
+    size_t rx_mem_alignment = 0;
+    TEST_ESP_OK(gdma_get_alignment_constraints(rx_chan, &rx_mem_alignment, NULL));
 
     // prepare the source data
     for (int i = 0; i < data_length; i++) {
@@ -460,7 +484,7 @@ static void test_gdma_m2m_unaligned_buffer_test(uint8_t *dst_data, uint8_t *src_
     TEST_ESP_OK(esp_dma_split_rx_buffer_to_cache_aligned(dst_data + offset_len, data_length, &align_array, &stash_buffer));
     for (int i = 0; i < 3; i++) {
         rx_aligned_buf_mount_config[i].buffer = align_array.aligned_buffer[i].aligned_buffer;
-        rx_aligned_buf_mount_config[i].buffer_alignment = sram_alignment;
+        rx_aligned_buf_mount_config[i].buffer_alignment = MAX(sram_alignment, rx_mem_alignment);
         rx_aligned_buf_mount_config[i].length = align_array.aligned_buffer[i].length;
     }
     TEST_ESP_OK(gdma_link_mount_buffers(rx_link_list, 0, rx_aligned_buf_mount_config, 3, NULL));
@@ -496,6 +520,10 @@ static void test_gdma_m2m_unaligned_buffer_test(uint8_t *dst_data, uint8_t *src_
 
 TEST_CASE("GDMA M2M Unaligned RX Buffer Test", "[GDMA][M2M]")
 {
+    if (efuse_hal_flash_encryption_enabled()) {
+        TEST_PASS_MESSAGE("Flash encryption is enabled, skip this test");
+    }
+
     uint8_t *sbuf = heap_caps_aligned_calloc(64, 1, 10240, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
     uint8_t *dbuf = heap_caps_aligned_calloc(64, 1, 10240, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
 
diff --git a/components/esp_hw_support/test_apps/dma/main/test_gdma_crc.c b/components/esp_hw_support/test_apps/dma/main/test_gdma_crc.c
index fd0e75a5fd..b54d81a20d 100644
--- a/components/esp_hw_support/test_apps/dma/main/test_gdma_crc.c
+++ b/components/esp_hw_support/test_apps/dma/main/test_gdma_crc.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,6 +17,7 @@
 #include "soc/soc_caps.h"
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
+#include "hal/gdma_ll.h"
 #include "esp_cache.h"
 
 typedef struct {
@@ -32,37 +33,47 @@ static test_crc_case_t crc_test_cases[] = {
         .crc_bit_width = 8,
         .init_value = 0x00,
         .poly_hex = 0x07,
-        .expected_result = 0xC6,
+        .expected_result = 0xB8,
     },
     [1] = {
         .crc_bit_width = 8,
         .init_value = 0x00,
         .poly_hex = 0x07,
         .reverse_data_mask = true, // refin = true
-        .expected_result = 0xDE,
+        .expected_result = 0xF0,
     },
     // CRC16, x^16+x^12+x^5+1
     [2] = {
         .crc_bit_width = 16,
         .init_value = 0xFFFF,
         .poly_hex = 0x1021,
-        .expected_result = 0x5289,
+        .expected_result = 0xA9B2,
     },
     // CRC32, x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
     [3] = {
         .crc_bit_width = 32,
         .init_value = 0xFFFFFFFF,
         .poly_hex = 0x04C11DB7,
-        .expected_result = 0x63B3E283,
+        .expected_result = 0x692F6C7E,
     }
 };
 
 // CRC online: https://www.lddgo.net/en/encrypt/crc
 static void test_gdma_crc_calculation(gdma_channel_handle_t tx_chan, int test_num_crc_algorithm)
 {
+    // Note, burst size should be at least 16 when accessing encrypted external memory
+    gdma_transfer_config_t transfer_cfg = {
+        .max_data_burst_size = 16,
+        .access_ext_mem = true,
+    };
+    TEST_ESP_OK(gdma_config_transfer(tx_chan, &transfer_cfg));
+
     uint32_t crc_result = 0;
-    const char *test_input_string = "Share::Connect::Innovate";
+
+    static const char test_input_string[] __attribute__((aligned(GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT))) = "GDMACRC Share::Connect::Innovate";
     size_t input_data_size = strlen(test_input_string);
+
+    TEST_ASSERT_EQUAL((uintptr_t)test_input_string % GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT, 0);
     // this test case also test the GDMA can fetch data from MSPI Flash
     TEST_ASSERT_TRUE(esp_ptr_in_drom(test_input_string));
     printf("Calculate CRC value for string: \"%s\"\r\n", test_input_string);
diff --git a/components/esp_hw_support/test_apps/dma/pytest_dma.py b/components/esp_hw_support/test_apps/dma/pytest_dma.py
index e70adf3476..d9b663c51c 100644
--- a/components/esp_hw_support/test_apps/dma/pytest_dma.py
+++ b/components/esp_hw_support/test_apps/dma/pytest_dma.py
@@ -33,3 +33,29 @@ def test_dma(dut: Dut) -> None:
 @idf_parametrize('target', ['esp32s3'], indirect=['target'])
 def test_dma_psram(dut: Dut) -> None:
     dut.run_all_single_board_cases(reset=True)
+
+
+@pytest.mark.flash_encryption
+@pytest.mark.parametrize(
+    'config',
+    [
+        'ext_mem_encryption',
+    ],
+    indirect=True,
+)
+@idf_parametrize('target', ['esp32p4', 'esp32c5'], indirect=['target'])
+def test_dma_ext_mem_encryption(dut: Dut) -> None:
+    dut.run_all_single_board_cases(reset=True)
+
+
+@pytest.mark.flash_encryption_f4r8
+@pytest.mark.parametrize(
+    'config',
+    [
+        'ext_mem_encryption',
+    ],
+    indirect=True,
+)
+@idf_parametrize('target', ['esp32s3'], indirect=['target'])
+def test_dma_ext_mem_encryption_s3_f4r8(dut: Dut) -> None:
+    dut.run_all_single_board_cases(reset=True)
diff --git a/components/esp_hw_support/test_apps/dma/sdkconfig.ci.ext_mem_encryption b/components/esp_hw_support/test_apps/dma/sdkconfig.ci.ext_mem_encryption
new file mode 100644
index 0000000000..5be9651c38
--- /dev/null
+++ b/components/esp_hw_support/test_apps/dma/sdkconfig.ci.ext_mem_encryption
@@ -0,0 +1,9 @@
+CONFIG_PARTITION_TABLE_OFFSET=0x9000
+CONFIG_SECURE_FLASH_ENC_ENABLED=y
+CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT=y
+CONFIG_SECURE_BOOT_ALLOW_ROM_BASIC=y
+CONFIG_SECURE_BOOT_ALLOW_JTAG=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE=y
+CONFIG_SECURE_FLASH_REQUIRE_ALREADY_ENABLED=y
diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_random.c b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_random.c
index bd9ed24fd5..264dc4859a 100644
--- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_random.c
+++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_random.c
@@ -5,9 +5,20 @@
  */
 #include <stdio.h>
 #include <string.h>
+#include <math.h>
+#include <inttypes.h>
+#include "sdkconfig.h"
+#include "soc/soc_caps.h"
 #include "unity.h"
 #include "esp_random.h"
 
+#if SOC_LIGHT_SLEEP_SUPPORTED
+#include "esp_sleep.h"
+#include "esp_private/esp_sleep_internal.h"
+#include "esp_private/sleep_cpu.h"
+#include "esp_private/esp_pmu.h"
+#endif
+
 /* Note: these are just sanity tests, not the same as
    entropy tests
 */
@@ -69,3 +80,57 @@ TEST_CASE("call esp_fill_random()", "[random]")
         TEST_ASSERT_EQUAL_HEX8(0xFF, one_buf[x]);
     }
 }
+
+TEST_CASE("verify esp_random() bit balance 0/1 ratio", "[random]")
+{
+#if SOC_LIGHT_SLEEP_SUPPORTED
+    esp_sleep_context_t sleep_ctx;
+    esp_sleep_set_sleep_context(&sleep_ctx);
+    printf("go to light sleep for 1 seconds\r\n");
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(true));
+#endif
+    TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
+    TEST_ESP_OK(esp_light_sleep_start());
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && !SOC_PM_TOP_PD_NOT_ALLOWED
+    // check if the power domain also is powered down
+    TEST_ASSERT_EQUAL(PMU_SLEEP_PD_TOP, (sleep_ctx.sleep_flags) & PMU_SLEEP_PD_TOP);
+#endif
+    esp_sleep_set_sleep_context(NULL);
+    printf("Waked up! Let's see if esp_random can still work correctly...\r\n");
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(false));
+#endif
+#endif
+
+    const size_t NUM_RANDOM = 50000; /* Need enough samples for statistical significance */
+    const float EXPECTED_RATIO = 0.5f; /* Expected ratio of 1s */
+    const float TOLERANCE = 0.01f; /* Allow 1% deviation (49%-51%) */
+    uint32_t bit_counts[32] = {0}; /* Count of 1s for each bit position */
+    /* Collect random numbers and count 1s in each bit position */
+    for (int i = 0; i < NUM_RANDOM; i++) {
+        uint32_t r = esp_random();
+        for (int bit = 0; bit < 32; bit++) {
+            if (r & (1U << bit)) {
+                bit_counts[bit]++;
+            }
+        }
+    }
+    /* Verify each bit position has approximately 50% ones */
+    printf("\nBit balance statistics (total samples: %zu):\n", NUM_RANDOM);
+    printf("Bit | 1s count | 0s count | 1s ratio | 0s ratio | Deviation\n");
+    printf("----|----------|----------|----------|----------|----------\n");
+    for (int bit = 0; bit < 32; bit++) {
+        uint32_t ones_count = bit_counts[bit];
+        uint32_t zeros_count = NUM_RANDOM - ones_count;
+        float ratio_ones = (float)ones_count / NUM_RANDOM;
+        float ratio_zeros = (float)zeros_count / NUM_RANDOM;
+        float deviation = fabs(ratio_ones - EXPECTED_RATIO);
+
+        printf("%3d | %8" PRIu32 " | %8" PRIu32 " | %8.4f | %8.4f | %9.4f\n",
+               bit, ones_count, zeros_count, ratio_ones, ratio_zeros, deviation);
+
+        /* Check if ratio is within tolerance */
+        TEST_ASSERT_LESS_THAN_FLOAT(TOLERANCE, deviation);
+    }
+}
diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.ci.release b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.ci.release
index 8b0a31a9bc..c7a5959d40 100644
--- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.ci.release
+++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.ci.release
@@ -4,3 +4,5 @@ CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
 
 # we can silent the assertion to save the binary footprint
 CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
+
+CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y
diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.defaults b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.defaults
index cc85282c55..c8801945ed 100644
--- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.defaults
+++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.defaults
@@ -6,3 +6,6 @@ CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
 
 # we can silent the assertion to save the binary footprint
 CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
+
+# primitives for checking sleep internal state
+CONFIG_ESP_SLEEP_DEBUG=y
diff --git a/components/esp_mm/heap_align_hw.c b/components/esp_mm/heap_align_hw.c
index d31ea59bd3..344b27b882 100644
--- a/components/esp_mm/heap_align_hw.c
+++ b/components/esp_mm/heap_align_hw.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,9 +9,11 @@
 #include "sdkconfig.h"
 #include "esp_heap_caps.h"
 #include "esp_private/esp_cache_private.h"
+#include "esp_private/gdma.h"
 #include "soc/soc_caps.h"
 #if SOC_GDMA_SUPPORTED
 #include "hal/gdma_ll.h"
+#include "hal/efuse_hal.h"
 #endif
 
 #if CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH
@@ -80,6 +82,12 @@ HEAP_IRAM_ATTR void esp_heap_adjust_alignment_to_hw(size_t *p_alignment, size_t
     }
 #endif
 
+#if SOC_GDMA_SUPPORTED && (SOC_PSRAM_DMA_CAPABLE || SOC_DMA_CAN_ACCESS_FLASH)
+    if ((caps & MALLOC_CAP_DMA) && efuse_hal_flash_encryption_enabled()) {
+        alignment = (alignment > GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT) ? alignment : GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT;
+    }
+#endif
+
     // Align up `size` to resulting alignment as well.
     size = (size + alignment - 1) & (~(alignment - 1));
 
diff --git a/components/esp_netif/test_apps/.build-test-rules.yml b/components/esp_netif/test_apps/.build-test-rules.yml
index 9e37eaeb54..7baad88301 100644
--- a/components/esp_netif/test_apps/.build-test-rules.yml
+++ b/components/esp_netif/test_apps/.build-test-rules.yml
@@ -13,7 +13,7 @@ components/esp_netif/test_apps/test_app_esp_netif:
 
 components/esp_netif/test_apps/test_app_vfs_l2tap:
   disable:
-    - if: IDF_TARGET not in ["esp32"] # TODO: IDF-14365
+    - if: IDF_TARGET not in ["esp32", "esp32p4"]
       temporary: true
       reason: Not needed to test on all targets (chosen two, one for each architecture plus P4 tests time stamping)
   depends_components:
diff --git a/components/esp_netif/test_apps/test_app_vfs_l2tap/README.md b/components/esp_netif/test_apps/test_app_vfs_l2tap/README.md
index f708a1985a..4873c15b15 100644
--- a/components/esp_netif/test_apps/test_app_vfs_l2tap/README.md
+++ b/components/esp_netif/test_apps/test_app_vfs_l2tap/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 |
-| ----------------- | ----- |
+| Supported Targets | ESP32 | ESP32-P4 |
+| ----------------- | ----- | -------- |
diff --git a/components/esp_netif/test_apps/test_app_vfs_l2tap/pytest_esp_vfs_l2tap.py b/components/esp_netif/test_apps/test_app_vfs_l2tap/pytest_esp_vfs_l2tap.py
index fb14d5ce59..237510d992 100644
--- a/components/esp_netif/test_apps/test_app_vfs_l2tap/pytest_esp_vfs_l2tap.py
+++ b/components/esp_netif/test_apps/test_app_vfs_l2tap/pytest_esp_vfs_l2tap.py
@@ -2,31 +2,15 @@
 # SPDX-License-Identifier: CC0-1.0
 import pytest
 from pytest_embedded import Dut
-from pytest_embedded_idf.utils import idf_parametrize
 
 
-@pytest.mark.ethernet
 @pytest.mark.parametrize(
-    'config',
+    'config, target',
     [
-        'defaults',
+        pytest.param('default_esp32', 'esp32', marks=[pytest.mark.eth_ip101]),
+        pytest.param('default_esp32p4', 'esp32p4', marks=[pytest.mark.eth_ip101]),
     ],
-    indirect=True,
+    indirect=['target'],
 )
-@idf_parametrize('target', ['esp32'], indirect=['target'])
 def test_esp_netif_vfs_l2tp(dut: Dut) -> None:
     dut.run_all_single_board_cases()
-
-
-@pytest.mark.eth_ip101
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14365')
-@pytest.mark.parametrize(
-    'config',
-    [
-        'defaults',
-    ],
-    indirect=True,
-)
-@idf_parametrize('target', ['esp32p4'], indirect=['target'])
-def test_esp_netif_vfs_l2tp_p4(dut: Dut) -> None:
-    dut.run_all_single_board_cases()
diff --git a/components/esp_netif/test_apps/test_app_vfs_l2tap/sdkconfig.ci.default_esp32 b/components/esp_netif/test_apps/test_app_vfs_l2tap/sdkconfig.ci.default_esp32
new file mode 100644
index 0000000000..2a43df1a39
--- /dev/null
+++ b/components/esp_netif/test_apps/test_app_vfs_l2tap/sdkconfig.ci.default_esp32
@@ -0,0 +1 @@
+CONFIG_IDF_TARGET="esp32"
diff --git a/components/esp_netif/test_apps/test_app_vfs_l2tap/sdkconfig.ci.default_esp32p4 b/components/esp_netif/test_apps/test_app_vfs_l2tap/sdkconfig.ci.default_esp32p4
new file mode 100644
index 0000000000..bd81009ac8
--- /dev/null
+++ b/components/esp_netif/test_apps/test_app_vfs_l2tap/sdkconfig.ci.default_esp32p4
@@ -0,0 +1 @@
+CONFIG_IDF_TARGET="esp32p4"
diff --git a/components/esp_netif/test_apps/test_app_vfs_l2tap/sdkconfig.ci.defaults b/components/esp_netif/test_apps/test_app_vfs_l2tap/sdkconfig.defaults
similarity index 100%
rename from components/esp_netif/test_apps/test_app_vfs_l2tap/sdkconfig.ci.defaults
rename to components/esp_netif/test_apps/test_app_vfs_l2tap/sdkconfig.defaults
diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld
index 3a0dafc1e4..df398b3a6e 100644
--- a/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld
+++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld
@@ -15,7 +15,7 @@ esf_buf_recycle = 0x40001ae8;
 hal_mac_tx_set_ppdu = 0x40001af8;
 ic_mac_deinit = 0x40001b00;
 lmacAdjustTimestamp = 0x40001b10;
-lmacDiscardMSDU = 0x40001b18;
+/*lmacDiscardMSDU = 0x40001b18;*/
 lmacEndFrameExchangeSequence = 0x40001b1c;
 lmacMSDUAged = 0x40001b28;
 //lmacSetTxFrame = 0x40001b4c;
@@ -30,7 +30,7 @@ pm_sleep = 0x40001bbc;
 //pm_tbtt_process = 0x40001bc4;
 ppAssembleAMPDU = 0x40001bcc;
 ppCalTxAMPDULength = 0x40001bd8;
-ppRxFragmentProc = 0x40001c28;
+/*ppRxFragmentProc = 0x40001c28;*/
 ppRxPkt = 0x40001c2c;
 pp_coex_tx_request = 0x40001c54;
 /* rcGetSched = 0x40001c88; */
diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.ld
index bba447a7a5..ab59a9deaf 100644
--- a/components/esp_rom/esp32c2/ld/esp32c2.rom.ld
+++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.ld
@@ -711,7 +711,7 @@ wDev_Rxbuf_Deinit = 0x40001e5c;
 ppCalTkipMic = 0x40001e60;
 wDev_SnifferRxData = 0x40001e64;
 hal_crypto_enable = 0x40001e68;
-hal_crypto_disable = 0x40001e6c;
+/*hal_crypto_disable = 0x40001e6c;*/
 wDev_Insert_KeyEntry = 0x40001e70;
 wDev_remove_KeyEntry = 0x40001e74;
 rc_enable_trc = 0x40001e78;
diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld
index d10b0524de..e49badf07e 100644
--- a/components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld
+++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld
@@ -8,7 +8,7 @@ esf_buf_alloc_dynamic = 0x400015c0;
 esf_buf_recycle = 0x400015c4;
 /*hal_mac_tx_set_ppdu = 0x400015d4;*/
 ic_mac_deinit = 0x400015dc;
-lmacDiscardMSDU = 0x400015f4;
+/*lmacDiscardMSDU = 0x400015f4;*/
 /*lmacSetTxFrame = 0x40001628;*/
 lmacTxDone = 0x4000162c;
 /*lmacTxFrame = 0x40001630;*/
diff --git a/components/esp_rom/esp32c5/Kconfig.soc_caps.in b/components/esp_rom/esp32c5/Kconfig.soc_caps.in
index 0092c8f37e..f475909a2a 100644
--- a/components/esp_rom/esp32c5/Kconfig.soc_caps.in
+++ b/components/esp_rom/esp32c5/Kconfig.soc_caps.in
@@ -122,3 +122,7 @@ config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
 config ESP_ROM_DELAY_US_PATCH
     bool
     default y
+
+config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
+    bool
+    default y
diff --git a/components/esp_rom/esp32c5/esp_rom_caps.h b/components/esp_rom/esp32c5/esp_rom_caps.h
index 2d0fd6829e..1812656eb2 100644
--- a/components/esp_rom/esp32c5/esp_rom_caps.h
+++ b/components/esp_rom/esp32c5/esp_rom_caps.h
@@ -36,3 +36,4 @@
 #define ESP_ROM_CLIC_INT_THRESH_PATCH       (1) // ROM version of esprv_intc_int_set_threshold incorrectly assumes lowest MINTTHRESH is 0x1F, should be 0xF
 #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY  (1) // ROM mem/str functions are not optimized well for misaligned memory access.
 #define ESP_ROM_DELAY_US_PATCH              (1) // ROM ets_delay_us needs patch for U-mode operation
+#define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP (1) // ROM supports the secure boot fast wakeup feature
diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld
index 64e04af8d7..7e498f0847 100644
--- a/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld
+++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld
@@ -59,7 +59,7 @@ is_lmac_idle = 0x40000c84;
 ic_get_he_rts_threshold_bytes = 0x40000c88;
 lmacAdjustTimestamp = 0x40000c8c;
 lmacDiscardAgedMSDU = 0x40000c90;
-lmacDiscardMSDU = 0x40000c94;
+/*lmacDiscardMSDU = 0x40000c94;*/
 lmacEndFrameExchangeSequence = 0x40000c98;
 lmacIsIdle = 0x40000c9c;
 lmacIsLongFrame = 0x40000ca0;
@@ -184,7 +184,7 @@ ppRecycleAmpdu = 0x40000e78;
 ppRecycleRxPkt = 0x40000e7c;
 ppResortTxAMPDU = 0x40000e80;
 ppResumeTxAMPDU = 0x40000e84;
-ppRxFragmentProc = 0x40000e88;
+/*ppRxFragmentProc = 0x40000e88;*/
 /* ppRxPkt = 0x40000e8c; */
 /* ppRxProtoProc = 0x40000e90; */
 ppSearchTxQueue = 0x40000e94;
diff --git a/components/esp_rom/esp32c6/Kconfig.soc_caps.in b/components/esp_rom/esp32c6/Kconfig.soc_caps.in
index 45540e3414..2f6dba3eca 100644
--- a/components/esp_rom/esp32c6/Kconfig.soc_caps.in
+++ b/components/esp_rom/esp32c6/Kconfig.soc_caps.in
@@ -126,3 +126,7 @@ config ESP_ROM_NO_USB_SERIAL_OUTPUT_API
 config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
     bool
     default y
+
+config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
+    bool
+    default y
diff --git a/components/esp_rom/esp32c6/esp_rom_caps.h b/components/esp_rom/esp32c6/esp_rom_caps.h
index 1edcc24b96..1bd42f0899 100644
--- a/components/esp_rom/esp32c6/esp_rom_caps.h
+++ b/components/esp_rom/esp32c6/esp_rom_caps.h
@@ -37,3 +37,4 @@
 #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC        (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
 #define ESP_ROM_NO_USB_SERIAL_OUTPUT_API    (1) // ROM does not export the usb-serial-jtag write char function
 #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY  (1) // ROM mem/str functions are not optimized well for misaligned memory access.
+#define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP (1) // ROM supports the secure boot fast wakeup feature
diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.eco4.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.eco4.ld
index 18937e41a7..5cc25c45cb 100644
--- a/components/esp_rom/esp32c61/ld/esp32c61.rom.eco4.ld
+++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.eco4.ld
@@ -36,7 +36,7 @@ pm_clear_wakeup_signal = 0x40000d78;
 pm_mac_disable_tsf_tbtt_soc_wakeup = 0x40000d7c;
 pm_mac_disable_tsf_tbtt_modem_wakeup = 0x40000d80;
 pm_mac_enable_tsf_tbtt_soc_wakeup = 0x40000d84;
-pm_mac_enable_tsf_tbtt_modem_wakeup = 0x40000d88;
+//pm_mac_enable_tsf_tbtt_modem_wakeup = 0x40000d88;
 //pm_mac_modem_params_rt_update = 0x40000d8c;
 pm_coex_pwr_update = 0x40000d9c;
 ppMapTxQueue = 0x40000ddc;
diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld
index b648e2a8e1..f11f406e68 100644
--- a/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld
+++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld
@@ -57,7 +57,7 @@ is_lmac_idle = 0x40000bf4;
 ic_get_he_rts_threshold_bytes = 0x40000bf8;
 lmacAdjustTimestamp = 0x40000bfc;
 lmacDiscardAgedMSDU = 0x40000c00;
-lmacDiscardMSDU = 0x40000c04;
+/*lmacDiscardMSDU = 0x40000c04;*/
 lmacEndFrameExchangeSequence = 0x40000c08;
 lmacIsIdle = 0x40000c0c;
 lmacIsLongFrame = 0x40000c10;
@@ -184,7 +184,7 @@ ppRecycleAmpdu = 0x40000df0;
 ppRecycleRxPkt = 0x40000df4;
 ppResortTxAMPDU = 0x40000df8;
 ppResumeTxAMPDU = 0x40000dfc;
-ppRxFragmentProc = 0x40000e00;
+/*ppRxFragmentProc = 0x40000e00;*/
 /*ppRxPkt = 0x40000e04;*/
 /*ppRxProtoProc = 0x40000e08;*/
 ppSearchTxQueue = 0x40000e0c;
diff --git a/components/esp_rom/esp32h2/Kconfig.soc_caps.in b/components/esp_rom/esp32h2/Kconfig.soc_caps.in
index c1166324a1..57dae80a53 100644
--- a/components/esp_rom/esp32h2/Kconfig.soc_caps.in
+++ b/components/esp_rom/esp32h2/Kconfig.soc_caps.in
@@ -118,3 +118,7 @@ config ESP_ROM_NO_USB_SERIAL_OUTPUT_API
 config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
     bool
     default y
+
+config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
+    bool
+    default y
diff --git a/components/esp_rom/esp32h2/esp_rom_caps.h b/components/esp_rom/esp32h2/esp_rom_caps.h
index 38e0777b98..cb9475c9ea 100644
--- a/components/esp_rom/esp32h2/esp_rom_caps.h
+++ b/components/esp_rom/esp32h2/esp_rom_caps.h
@@ -35,3 +35,4 @@
 #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC        (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
 #define ESP_ROM_NO_USB_SERIAL_OUTPUT_API    (1) // ROM does not export the usb-serial-jtag write char function
 #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY  (1) // ROM mem/str functions are not optimized well for misaligned memory access.
+#define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP     (1) // ROM supports the secure boot fast wakeup feature
diff --git a/components/esp_rom/esp32h21/Kconfig.soc_caps.in b/components/esp_rom/esp32h21/Kconfig.soc_caps.in
index e455d4e363..d7f1e52541 100644
--- a/components/esp_rom/esp32h21/Kconfig.soc_caps.in
+++ b/components/esp_rom/esp32h21/Kconfig.soc_caps.in
@@ -98,3 +98,7 @@ config ESP_ROM_HAS_OUTPUT_PUTC_FUNC
 config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
     bool
     default y
+
+config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
+    bool
+    default y
diff --git a/components/esp_rom/esp32h21/esp_rom_caps.h b/components/esp_rom/esp32h21/esp_rom_caps.h
index 6dc77b3576..95e5fefff2 100644
--- a/components/esp_rom/esp32h21/esp_rom_caps.h
+++ b/components/esp_rom/esp32h21/esp_rom_caps.h
@@ -31,3 +31,4 @@
 // #define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB  (1) // ROM supports the HP core to jump to the RTC memory to execute stub code after waking up from deepsleep. //TODO: [ESP32H21] IDF-11515
 #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC        (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
 #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY  (1) // ROM mem/str functions are not optimized well for misaligned memory access.
+#define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP (1) // ROM supports the secure boot fast wakeup feature
diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld
index 4e9df1c155..63b0f8464a 100644
--- a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld
+++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld
@@ -955,7 +955,7 @@ lmacReachShortLimit = 0x40005394;
 lmacRecycleMPDU = 0x400053a0;
 lmacRxDone = 0x400053ac;
 /*lmacSetTxFrame = 0x400053b8;*/
-lmacTxDone = 0x400053c4;
+/*lmacTxDone = 0x400053c4;*/
 /*lmacTxFrame = 0x400053d0;*/
 mac_tx_set_duration = 0x400053dc;
 /* mac_tx_set_htsig = 0x400053e8;*/
diff --git a/components/esp_system/ld/ld.common b/components/esp_system/ld/ld.common
index dfe698e4df..2af596f33e 100644
--- a/components/esp_system/ld/ld.common
+++ b/components/esp_system/ld/ld.common
@@ -11,6 +11,13 @@
 /* CPU instruction prefetch padding size for flash mmap scenario */
 #define _esp_flash_mmap_prefetch_pad_size 16
 
+/* Copy from esp_secure_boot.h */
+#ifdef CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS
+#define ESP_SECURE_BOOT_DIGEST_LEN 48
+#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
+#define ESP_SECURE_BOOT_DIGEST_LEN 32
+#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
+
 /*
  * PMP region granularity size
  * Software may determine the PMP granularity by writing zero to pmp0cfg, then writing all ones
@@ -70,6 +77,8 @@
 	   has the required alignment */
 	    #define ULP_ALIGNMENT_REQ_BYTES 256
         #define RESERVE_RTC_MEM ALIGN_UP(ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC, ULP_ALIGNMENT_REQ_BYTES)
+    #elif CONFIG_SECURE_BOOT && CONFIG_ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
+        #define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC + ESP_SECURE_BOOT_DIGEST_LEN)
     #else
         #define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC)
     #endif
diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c
index cbd5dafa3c..a993c472ce 100644
--- a/components/esp_system/port/cpu_start.c
+++ b/components/esp_system/port/cpu_start.c
@@ -547,7 +547,8 @@ MSPI_INIT_ATTR void sys_rtc_init(const soc_reset_reason_t *rst_reas)
     esp_rtc_init();
 }
 
-NOINLINE_ATTR IRAM_ATTR void flash_init_state(void)
+#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
+static NOINLINE_ATTR IRAM_ATTR void flash_init_state(void)
 {
     /**
      * This function initialise the Flash chip to the user-defined settings.
@@ -564,7 +565,6 @@ NOINLINE_ATTR IRAM_ATTR void flash_init_state(void)
 #endif
 }
 
-#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
 MSPI_INIT_ATTR void mspi_init(void)
 {
 #if CONFIG_ESPTOOLPY_OCT_FLASH && !CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT
@@ -612,6 +612,20 @@ MSPI_INIT_ATTR void mspi_init(void)
 }
 #endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
 
+#if CONFIG_IDF_TARGET_ESP32 && !CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_SPIRAM_BOOT_HW_INIT
+/*
+ * Adjust flash configuration. This must be placed in IRAM because running from flash,
+ * while it is being reconfigured, will result in corrupt data being read.
+ */
+NOINLINE_ATTR IRAM_ATTR static void configure_flash(esp_image_header_t *fhdr)
+{
+    bootloader_flash_gpio_config(fhdr);
+    bootloader_flash_dummy_config(fhdr);
+    bootloader_flash_clock_config(fhdr);
+    bootloader_flash_cs_timing_config();
+}
+#endif // CONFIG_IDF_TARGET_ESP32 && !CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_SPIRAM_BOOT_HW_INIT
+
 /*
  * Initialize other parts of the system, including other CPUs.
  * As CPU0 needs to disable the cache in system_early_init function, the other cores are not allowed to run with the
@@ -643,6 +657,10 @@ NOINLINE_ATTR static void system_early_init(const soc_reset_reason_t *rst_reas)
 
 #if SOC_CPU_CORES_NUM > 1 // there is no 'single-core mode' for natively single-core processors
 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
+#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_REV_MIN_FULL >= 300
+    // Ensure autoclock gating mode for core1 is enabled, it gets disabled in single-core mode.
+    REG_SET_BIT(HP_SYS_CLKRST_CPU_WAITI_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN);
+#endif
     start_other_core();
 #else
     ESP_EARLY_LOGI(TAG, "Single core mode");
@@ -851,10 +869,7 @@ NOINLINE_ATTR static void system_early_init(const soc_reset_reason_t *rst_reas)
 #if CONFIG_IDF_TARGET_ESP32
 #if !CONFIG_SPIRAM_BOOT_HW_INIT
     // If psram is uninitialized, we need to improve some flash configuration.
-    bootloader_flash_clock_config(&fhdr);
-    bootloader_flash_gpio_config(&fhdr);
-    bootloader_flash_dummy_config(&fhdr);
-    bootloader_flash_cs_timing_config();
+    configure_flash(&fhdr);
 #endif //!CONFIG_SPIRAM_BOOT_HW_INIT
 #endif //CONFIG_IDF_TARGET_ESP32
 
diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c
index 711f6ab8c5..e0e31d38dc 100644
--- a/components/esp_system/port/soc/esp32c6/clk.c
+++ b/components/esp_system/port/soc/esp32c6/clk.c
@@ -316,8 +316,10 @@ __attribute__((weak)) void esp_perip_clk_init(void)
         REG_CLR_BIT(PCR_TRACE_CONF_REG, PCR_TRACE_CLK_EN);
         REG_CLR_BIT(PCR_RETENTION_CONF_REG, PCR_RETENTION_CLK_EN);
         REG_CLR_BIT(PCR_MEM_MONITOR_CONF_REG, PCR_MEM_MONITOR_CLK_EN);
+#if !CONFIG_ESP_ENABLE_PVT
         REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
         REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
+#endif
         WRITE_PERI_REG(PCR_CTRL_CLK_OUT_EN_REG, 0);
 
 #if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
diff --git a/components/esp_wifi/include/esp_wifi.h b/components/esp_wifi/include/esp_wifi.h
index abd4f5b053..31fb849b58 100644
--- a/components/esp_wifi/include/esp_wifi.h
+++ b/components/esp_wifi/include/esp_wifi.h
@@ -1092,6 +1092,9 @@ typedef void (*esp_vendor_ie_cb_t)(void *ctx, wifi_vendor_ie_type_t type, const
   * @param     vnd_ie Pointer to vendor specific element data. First 6 bytes should be a header with fields matching vendor_ie_data_t.
   *            If enable is false, this argument is ignored and can be NULL. Data does not need to remain valid after the function returns.
   *
+  * @attention If user set the same vendor ie twice, the second set will fail and return ESP_ERR_INVALID_ARG.
+  *            Please clear the vendor ie before setting again.
+  *
   * @return
   *    - ESP_OK: succeed
   *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init()
diff --git a/components/esp_wifi/include/esp_wifi_types_generic.h b/components/esp_wifi/include/esp_wifi_types_generic.h
index 399c0afb59..cc98293dc9 100644
--- a/components/esp_wifi/include/esp_wifi_types_generic.h
+++ b/components/esp_wifi/include/esp_wifi_types_generic.h
@@ -536,7 +536,7 @@ typedef struct {
     wifi_cipher_type_t pairwise_cipher;       /**< Pairwise cipher of SoftAP, group cipher will be derived using this. Cipher values are valid starting from WIFI_CIPHER_TYPE_TKIP, enum values before that will be considered as invalid and default cipher suites(TKIP+CCMP) will be used. Valid cipher suites in softAP mode are WIFI_CIPHER_TYPE_TKIP, WIFI_CIPHER_TYPE_CCMP, WIFI_CIPHER_TYPE_TKIP_CCMP, WIFI_CIPHER_TYPE_GCMP and WIFI_CIPHER_TYPE_GCMP256. */
     bool ftm_responder;                       /**< Enable FTM Responder mode */
     wifi_pmf_config_t pmf_cfg;                /**< Configuration for Protected Management Frame */
-    wifi_sae_pwe_method_t sae_pwe_h2e;        /**< Configuration for SAE PWE derivation method */
+    wifi_sae_pwe_method_t sae_pwe_h2e;        /**< Configuration for SAE PWE derivation method. Default value :2 (WPA3_SAE_PWE_BOTH) */
     uint8_t transition_disable;               /**< Whether to enable transition disable feature */
     uint8_t sae_ext;                          /**< Enable SAE EXT feature. SOC_GCMP_SUPPORT is required for this feature. */
     wifi_bss_max_idle_config_t bss_max_idle_cfg;  /**< Configuration for bss max idle, effective if CONFIG_WIFI_BSS_MAX_IDLE_SUPPORT is enabled */
@@ -566,7 +566,7 @@ typedef struct {
     uint32_t owe_enabled: 1;                  /**< Whether OWE is enabled for the connection */
     uint32_t transition_disable: 1;           /**< Whether to enable transition disable feature */
     uint32_t reserved1: 26;                   /**< Reserved for future feature set */
-    wifi_sae_pwe_method_t sae_pwe_h2e;        /**< Configuration for SAE PWE derivation method */
+    wifi_sae_pwe_method_t sae_pwe_h2e;        /**< Configuration for SAE PWE derivation method. Default value :2 (WPA3_SAE_PWE_BOTH) */
     wifi_sae_pk_mode_t sae_pk_mode;           /**< Configuration for SAE-PK (Public Key) Authentication method */
     uint8_t failure_retry_cnt;                /**< Number of connection retries station will do before moving to next AP. scan_method should be set as WIFI_ALL_CHANNEL_SCAN to use this config.
                                                    Note: Enabling this may cause connection time to increase in case best AP doesn't behave properly. */
diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib
index 156aed2cb6..8f933de0fd 160000
--- a/components/esp_wifi/lib
+++ b/components/esp_wifi/lib
@@ -1 +1 @@
-Subproject commit 156aed2cb6e6c9987dc2e7402fee907158cdf885
+Subproject commit 8f933de0fdd1a6577f862db2810eafc61463d4d8
diff --git a/components/hal/emac_hal.c b/components/hal/emac_hal.c
index 5fa476dce8..3f377ecc3c 100644
--- a/components/hal/emac_hal.c
+++ b/components/hal/emac_hal.c
@@ -5,6 +5,8 @@
  */
 #include <string.h>
 #include "sdkconfig.h"
+#include <stdlib.h>
+#include "soc/soc_caps.h"
 #include "esp_attr.h"
 #include "hal/emac_hal.h"
 #include "hal/emac_ll.h"
@@ -13,6 +15,15 @@
 #define EMAC_PTP_INIT_TIMEOUT_US (10)
 #endif // SOC_EMAC_IEEE1588V2_SUPPORTED
 
+static uint8_t emac_crs_div_table[] = {
+    42,
+    62,
+    16,
+    26,
+    102,
+    124,
+};
+
 static esp_err_t emac_hal_flush_trans_fifo(emac_hal_context_t *hal)
 {
     emac_ll_flush_trans_fifo_enable(hal->dma_regs, true);
@@ -39,6 +50,21 @@ void emac_hal_init(emac_hal_context_t *hal)
 #endif
 }
 
+void emac_hal_find_set_closest_csr_clock_range(emac_hal_context_t *hal, int mdc_freq_hz, int freq_hz)
+{
+    int min_diff = abs(freq_hz / emac_crs_div_table[0] - mdc_freq_hz);
+    uint32_t best_div = 0;
+
+    for (int i = 1; i < sizeof(emac_crs_div_table) / sizeof(emac_crs_div_table[0]); i++) {
+        int cur_diff = abs(freq_hz / emac_crs_div_table[i] - mdc_freq_hz);
+        if (cur_diff < min_diff) {
+            min_diff = cur_diff;
+            best_div = i;
+        }
+    }
+    emac_ll_set_csr_clock_division(hal->mac_regs, best_div);
+}
+
 void emac_hal_set_csr_clock_range(emac_hal_context_t *hal, int freq)
 {
     /* Tell MAC system clock Frequency in MHz, which will determine the frequency range of MDC(1MHz~2.5MHz) */
diff --git a/components/hal/esp32/include/hal/emac_ll.h b/components/hal/esp32/include/hal/emac_ll.h
index 76ff9b0404..3dc6ee2f5a 100644
--- a/components/hal/esp32/include/hal/emac_ll.h
+++ b/components/hal/esp32/include/hal/emac_ll.h
@@ -22,6 +22,7 @@
 #include "soc/emac_mac_struct.h"
 #include "soc/emac_ext_struct.h"
 #include "soc/dport_reg.h"
+#include "soc/clk_tree_defs.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -694,6 +695,12 @@ static inline void emac_ll_pause_frame_enable(emac_ext_dev_t *ext_regs, bool ena
 }
 /*************** End of ext regs operation *********************/
 
+static inline soc_module_clk_t emac_ll_get_csr_clk_src(void)
+{
+    // Source of the ESP32 EMAC CRS clock is APB clock.
+    return SOC_MOD_CLK_APB;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32c5/include/hal/gdma_ll.h b/components/hal/esp32c5/include/hal/gdma_ll.h
index f4a17e88f4..8176ed1c40 100644
--- a/components/hal/esp32c5/include/hal/gdma_ll.h
+++ b/components/hal/esp32c5/include/hal/gdma_ll.h
@@ -9,6 +9,7 @@
 #include "hal/ahb_dma_ll.h"
 #define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
 #define GDMA_LL_MAX_BURST_SIZE_PSRAM      32 // PSRAM controller doesn't support burst access with size > 32 bytes
+#define GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 // The alignment of the memory and size when DMA accesses encrypted memory
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/hal/esp32c5/include/hal/parlio_ll.h b/components/hal/esp32c5/include/hal/parlio_ll.h
index 26f714c693..1e3cb294ef 100644
--- a/components/hal/esp32c5/include/hal/parlio_ll.h
+++ b/components/hal/esp32c5/include/hal/parlio_ll.h
@@ -255,8 +255,9 @@ static inline void parlio_ll_rx_start_soft_recv(parl_io_dev_t *dev, bool en)
 __attribute__((always_inline))
 static inline void parlio_ll_rx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
 {
-    dev->rx_clk_cfg.rx_clk_i_inv = edge;
-    dev->rx_clk_cfg.rx_clk_o_inv = edge;
+    bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
+    dev->rx_clk_cfg.rx_clk_i_inv = invert;
+    dev->rx_clk_cfg.rx_clk_o_inv = invert;
 }
 
 /**
@@ -559,8 +560,9 @@ static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t sta
  */
 static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
 {
-    dev->tx_clk_cfg.tx_clk_i_inv = edge;
-    dev->tx_clk_cfg.tx_clk_o_inv = edge;
+    bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
+    dev->tx_clk_cfg.tx_clk_i_inv = invert;
+    dev->tx_clk_cfg.tx_clk_o_inv = invert;
 }
 
 /**
diff --git a/components/hal/esp32c5/include/hal/rng_ll.h b/components/hal/esp32c5/include/hal/rng_ll.h
new file mode 100644
index 0000000000..f930c7c8d0
--- /dev/null
+++ b/components/hal/esp32c5/include/hal/rng_ll.h
@@ -0,0 +1,88 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "soc/lpperi_struct.h"
+#include "hal/lp_clkrst_ll.h"
+
+#define RNG_LL_DEPENDS_ON_LP_PERIPH 1
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Enable or disable RNG sampling.
+ *
+ * @param enable True to enable, False to disable
+ */
+static inline void rng_ll_enable_sample(bool enable)
+{
+    LPPERI.rng_cfg.rng_sample_enable = enable;
+}
+
+/**
+ * @brief Enable or disable rng xor rtc timer.
+ *
+ * @param enable True to enable, False to disable
+ */
+static inline void rng_ll_enable_rtc_timer(bool enable)
+{
+    LPPERI.rng_cfg.rtc_timer_en = enable ? 0x3 : 0x0;
+}
+
+/**
+ * @brief Enable or disable rng xor async rng timer.
+ *
+ * @param enable True to enable, False to disable
+ */
+static inline void rng_ll_enable_rng_timer(bool enable)
+{
+    LPPERI.rng_cfg.rng_timer_en = enable;
+}
+
+/**
+ * @brief Reset RNG.
+ */
+static inline void rng_ll_reset(void)
+{
+    LPPERI.reset_en.lp_rng_reset_en = 1;
+    LPPERI.reset_en.lp_rng_reset_en = 0;
+}
+
+/**
+ * @brief Enable RNG module
+ *
+ * TODO: unify in rng_hal.c
+ */
+static inline void rng_ll_enable(void)
+{
+    _lp_clkrst_ll_enable_rng_clock(true);
+    rng_ll_enable_sample(true);
+    rng_ll_enable_rtc_timer(true);
+    rng_ll_enable_rng_timer(true);
+}
+
+/**
+ * @brief Disable RNG module
+ *
+ * TODO: unify in rng_hal.c
+ */
+static inline void rng_ll_disable(void)
+{
+    rng_ll_enable_sample(false);
+    rng_ll_enable_rtc_timer(false);
+    rng_ll_enable_rng_timer(false);
+    _lp_clkrst_ll_enable_rng_clock(false);
+}
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32c61/include/hal/gdma_ll.h b/components/hal/esp32c61/include/hal/gdma_ll.h
index f4a17e88f4..8176ed1c40 100644
--- a/components/hal/esp32c61/include/hal/gdma_ll.h
+++ b/components/hal/esp32c61/include/hal/gdma_ll.h
@@ -9,6 +9,7 @@
 #include "hal/ahb_dma_ll.h"
 #define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
 #define GDMA_LL_MAX_BURST_SIZE_PSRAM      32 // PSRAM controller doesn't support burst access with size > 32 bytes
+#define GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 // The alignment of the memory and size when DMA accesses encrypted memory
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/hal/esp32h2/include/hal/parlio_ll.h b/components/hal/esp32h2/include/hal/parlio_ll.h
index e8964cc00c..4f00a41f36 100644
--- a/components/hal/esp32h2/include/hal/parlio_ll.h
+++ b/components/hal/esp32h2/include/hal/parlio_ll.h
@@ -258,8 +258,9 @@ static inline void parlio_ll_rx_start_soft_recv(parl_io_dev_t *dev, bool en)
 __attribute__((always_inline))
 static inline void parlio_ll_rx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
 {
-    dev->rx_clk_cfg.rx_clk_i_inv = edge;
-    dev->rx_clk_cfg.rx_clk_o_inv = edge;
+    bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
+    dev->rx_clk_cfg.rx_clk_i_inv = invert;
+    dev->rx_clk_cfg.rx_clk_o_inv = invert;
 }
 
 /**
@@ -567,8 +568,9 @@ static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t sta
  */
 static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
 {
-    dev->tx_clk_cfg.tx_clk_i_inv = edge;
-    dev->tx_clk_cfg.tx_clk_o_inv = edge;
+    bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
+    dev->tx_clk_cfg.tx_clk_i_inv = invert;
+    dev->tx_clk_cfg.tx_clk_o_inv = invert;
 }
 
 /**
diff --git a/components/hal/esp32h21/include/hal/gdma_ll.h b/components/hal/esp32h21/include/hal/gdma_ll.h
index 4d0f42c613..3e56d0d621 100644
--- a/components/hal/esp32h21/include/hal/gdma_ll.h
+++ b/components/hal/esp32h21/include/hal/gdma_ll.h
@@ -49,6 +49,7 @@ extern "C" {
 
 #define GDMA_LL_AHB_DESC_ALIGNMENT    4
 #define GDMA_LL_AHB_RX_BURST_NEEDS_ALIGNMENT  1
+#define GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 // The alignment of the memory and size when DMA accesses encrypted memory
 
 #define GDMA_LL_AHB_M2M_CAPABLE_PAIR_MASK   0x07  // pair 0,1,2 are M2M capable
 
diff --git a/components/hal/esp32h4/include/hal/gdma_ll.h b/components/hal/esp32h4/include/hal/gdma_ll.h
index 0e04e3b495..83db6730c6 100644
--- a/components/hal/esp32h4/include/hal/gdma_ll.h
+++ b/components/hal/esp32h4/include/hal/gdma_ll.h
@@ -9,6 +9,7 @@
 #include "hal/ahb_dma_ll.h"
 #define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
 #define GDMA_LL_MAX_BURST_SIZE_PSRAM      64 // PSRAM support INCR16
+#define GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 // The alignment of the memory and size when DMA accesses encrypted memory
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/hal/esp32p4/clk_tree_hal.c b/components/hal/esp32p4/clk_tree_hal.c
index b8f809dc79..fa1b544d62 100644
--- a/components/hal/esp32p4/clk_tree_hal.c
+++ b/components/hal/esp32p4/clk_tree_hal.c
@@ -45,7 +45,7 @@ static uint32_t clk_hal_mem_get_freq_hz(void)
     return clk_hal_cpu_get_freq_hz() / clk_ll_mem_get_divider();
 }
 
-static uint32_t clk_hal_sys_get_freq_hz(void)
+uint32_t clk_hal_sys_get_freq_hz(void)
 {
     return clk_hal_mem_get_freq_hz() / clk_ll_sys_get_divider();
 }
diff --git a/components/hal/esp32p4/include/hal/aes_ll.h b/components/hal/esp32p4/include/hal/aes_ll.h
index 8d73c7eec2..ac032f1cee 100644
--- a/components/hal/esp32p4/include/hal/aes_ll.h
+++ b/components/hal/esp32p4/include/hal/aes_ll.h
@@ -11,6 +11,7 @@
 #include "hal/aes_types.h"
 #include "soc/hp_sys_clkrst_struct.h"
 #include "soc/hwcrypto_reg.h"
+#include "hal/config.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -250,6 +251,31 @@ static inline void aes_ll_interrupt_clear(void)
     REG_WRITE(AES_INT_CLEAR_REG, 1);
 }
 
+/**
+ * @brief Enable the pseudo-round function during AES operations
+ *
+ * @param enable true to enable, false to disable
+ * @param base basic number of pseudo rounds, zero if disable
+ * @param increment increment number of pseudo rounds, zero if disable
+ * @param key_rng_cnt update frequency of the pseudo-key, zero if disable
+ */
+static inline void aes_ll_enable_pseudo_rounds(bool enable, uint8_t base, uint8_t increment, uint8_t key_rng_cnt)
+{
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_EN, enable);
+
+    if (enable) {
+        REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_BASE, base);
+        REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_INC, increment);
+        REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_RNG_CNT, key_rng_cnt);
+    } else {
+        REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_BASE, 0);
+        REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_INC, 0);
+        REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_RNG_CNT, 0);
+    }
+#endif
+}
+
 /**
  * @brief Continue a previous started transform
  *
@@ -337,6 +363,18 @@ static inline void aes_ll_gcm_read_tag(uint8_t *tag)
     }
 }
 
+/**
+ * @brief Check if the pseudo round function is supported
+ */
+static inline bool aes_ll_is_pseudo_rounds_function_supported(void)
+{
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    return true;
+#else
+    return false;
+#endif
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32p4/include/hal/axi_dma_ll.h b/components/hal/esp32p4/include/hal/axi_dma_ll.h
index a6c5a2dae1..5bd6eb601a 100644
--- a/components/hal/esp32p4/include/hal/axi_dma_ll.h
+++ b/components/hal/esp32p4/include/hal/axi_dma_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -294,6 +294,9 @@ static inline void axi_dma_ll_rx_enable_etm_task(axi_dma_dev_t *dev, uint32_t ch
 
 /**
  * @brief Whether to enable access to ecc or aes memory
+ *
+ * @note This function is not used for AXI-GDMA because it will affect the alignment requirement for internal memory.
+ *       We have ensured that the AXI-GDMA can access the encrypted memory by 16-bytes alignment in software.
  */
 static inline void axi_dma_ll_rx_enable_ext_mem_ecc_aes_access(axi_dma_dev_t *dev, uint32_t channel, bool enable)
 {
@@ -528,6 +531,9 @@ static inline void axi_dma_ll_tx_enable_etm_task(axi_dma_dev_t *dev, uint32_t ch
 
 /**
  * @brief Whether to enable access to ecc or aes memory
+ *
+ * @note This function is not used for AXI-GDMA because it will affect the alignment requirement for internal memory.
+ *       We have ensured that the AXI-GDMA can access the encrypted memory by 16-bytes alignment in software.
  */
 static inline void axi_dma_ll_tx_enable_ext_mem_ecc_aes_access(axi_dma_dev_t *dev, uint32_t channel, bool enable)
 {
diff --git a/components/hal/esp32p4/include/hal/emac_ll.h b/components/hal/esp32p4/include/hal/emac_ll.h
index f2b313ca85..c1846c2ac2 100644
--- a/components/hal/esp32p4/include/hal/emac_ll.h
+++ b/components/hal/esp32p4/include/hal/emac_ll.h
@@ -816,6 +816,12 @@ static inline void emac_ll_ts_target_int_trig_enable(emac_ptp_dev_t *ptp_regs)
 
 /************** End of ptp regs operation ********************/
 
+static inline soc_module_clk_t emac_ll_get_csr_clk_src(void)
+{
+    // Source of the ESP32P4 EMAC CRS clock is SYS clock.
+    return SOC_MOD_CLK_SYS;
+}
+
 /**
  * @brief Enable the bus clock for the EMAC module
  *
diff --git a/components/hal/esp32p4/include/hal/gdma_ll.h b/components/hal/esp32p4/include/hal/gdma_ll.h
index 6316a33f94..f987c56503 100644
--- a/components/hal/esp32p4/include/hal/gdma_ll.h
+++ b/components/hal/esp32p4/include/hal/gdma_ll.h
@@ -49,6 +49,7 @@
 #define GDMA_LL_AHB_DESC_ALIGNMENT      4
 #define GDMA_LL_AXI_DESC_ALIGNMENT      8
 #define GDMA_LL_MAX_BURST_SIZE_PSRAM    128 // PSRAM controller doesn't support burst access with size > 128 bytes
+#define GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 // The alignment of the memory and size when DMA accesses encrypted memory
 
 #if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
 #define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
diff --git a/components/hal/esp32p4/include/hal/isp_ll.h b/components/hal/esp32p4/include/hal/isp_ll.h
index aa21ed0ebc..2dc04840af 100644
--- a/components/hal/esp32p4/include/hal/isp_ll.h
+++ b/components/hal/esp32p4/include/hal/isp_ll.h
@@ -11,6 +11,7 @@
 #include "hal/misc.h"
 #include "hal/assert.h"
 #include "hal/hal_utils.h"
+#include "hal/config.h"
 #include "hal/isp_types.h"
 #include "hal/color_types.h"
 #include "hal/config.h"
@@ -130,8 +131,13 @@ extern "C" {
 /*---------------------------------------------------------------
                       CCM
 ---------------------------------------------------------------*/
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+#define ISP_LL_CCM_MATRIX_INT_BITS      (4)
+#define ISP_LL_CCM_MATRIX_FRAC_BITS     (8)
+#else
 #define ISP_LL_CCM_MATRIX_INT_BITS      (2)
 #define ISP_LL_CCM_MATRIX_FRAC_BITS     (10)
+#endif
 #define ISP_LL_CCM_MATRIX_TOT_BITS      (ISP_LL_CCM_MATRIX_INT_BITS + ISP_LL_CCM_MATRIX_FRAC_BITS + 1)  // including one sign bit
 
 typedef union {
diff --git a/components/hal/esp32p4/include/hal/parlio_ll.h b/components/hal/esp32p4/include/hal/parlio_ll.h
index a9bce617b4..21cb27c632 100644
--- a/components/hal/esp32p4/include/hal/parlio_ll.h
+++ b/components/hal/esp32p4/include/hal/parlio_ll.h
@@ -295,8 +295,9 @@ static inline void parlio_ll_rx_start_soft_recv(parl_io_dev_t *dev, bool en)
 __attribute__((always_inline))
 static inline void parlio_ll_rx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
 {
-    dev->rx_clk_cfg.rx_clk_i_inv = edge;
-    dev->rx_clk_cfg.rx_clk_o_inv = edge;
+    bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
+    dev->rx_clk_cfg.rx_clk_i_inv = invert;
+    dev->rx_clk_cfg.rx_clk_o_inv = invert;
 }
 
 /**
@@ -592,8 +593,9 @@ static inline void parlio_ll_tx_start(parl_io_dev_t *dev, bool en)
  */
 static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
 {
-    dev->tx_clk_cfg.tx_clk_i_inv = edge;
-    dev->tx_clk_cfg.tx_clk_o_inv = edge;
+    bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
+    dev->tx_clk_cfg.tx_clk_i_inv = invert;
+    dev->tx_clk_cfg.tx_clk_o_inv = invert;
 }
 
 /**
diff --git a/components/hal/esp32p4/include/hal/spi_flash_encrypted_ll.h b/components/hal/esp32p4/include/hal/spi_flash_encrypted_ll.h
index 948e964db3..66100fc93b 100644
--- a/components/hal/esp32p4/include/hal/spi_flash_encrypted_ll.h
+++ b/components/hal/esp32p4/include/hal/spi_flash_encrypted_ll.h
@@ -20,6 +20,8 @@
 #include "soc/soc.h"
 #include "soc/soc_caps.h"
 #include "hal/assert.h"
+#include "hal/config.h"
+#include "hal/spi_flash_encrypt_types.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -147,6 +149,43 @@ static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length)
     return ((address % length) == 0) ? true : false;
 }
 
+/**
+ * @brief Enable the pseudo-round function during XTS-AES operations
+ *
+ * @param mode set the mode for pseudo rounds, zero to disable, with increasing security upto three.
+ * @param base basic number of pseudo rounds, zero if disable
+ * @param increment increment number of pseudo rounds, zero if disable
+ * @param key_rng_cnt update frequency of the pseudo-key, zero if disable
+ */
+static inline void spi_flash_encrypt_ll_enable_pseudo_rounds(esp_xts_aes_psuedo_rounds_state_t mode, uint8_t base, uint8_t increment, uint8_t key_rng_cnt)
+{
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    REG_SET_FIELD(SPI_MEM_C_XTS_PSEUDO_ROUND_CONF_REG, SPI_MEM_C_MODE_PSEUDO, mode);
+
+    if (mode != ESP_XTS_AES_PSEUDO_ROUNDS_DISABLE) {
+        REG_SET_FIELD(SPI_MEM_C_XTS_PSEUDO_ROUND_CONF_REG, SPI_MEM_C_PSEUDO_BASE, base);
+        REG_SET_FIELD(SPI_MEM_C_XTS_PSEUDO_ROUND_CONF_REG, SPI_MEM_C_PSEUDO_INC, increment);
+        REG_SET_FIELD(SPI_MEM_C_XTS_PSEUDO_ROUND_CONF_REG, SPI_MEM_C_PSEUDO_RNG_CNT, key_rng_cnt);
+    } else {
+        REG_SET_FIELD(SPI_MEM_C_XTS_PSEUDO_ROUND_CONF_REG, SPI_MEM_C_PSEUDO_BASE, 0);
+        REG_SET_FIELD(SPI_MEM_C_XTS_PSEUDO_ROUND_CONF_REG, SPI_MEM_C_PSEUDO_INC, 0);
+        REG_SET_FIELD(SPI_MEM_C_XTS_PSEUDO_ROUND_CONF_REG, SPI_MEM_C_PSEUDO_RNG_CNT, 0);
+    }
+#endif
+}
+
+/**
+ * @brief Check if the pseudo round function is supported
+ */
+static inline bool spi_flash_encrypt_ll_is_pseudo_rounds_function_supported(void)
+{
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    return true;
+#else
+    return false;
+#endif
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32p4/include/hal/uart_ll.h b/components/hal/esp32p4/include/hal/uart_ll.h
index ca6529303c..e0a0eca09b 100644
--- a/components/hal/esp32p4/include/hal/uart_ll.h
+++ b/components/hal/esp32p4/include/hal/uart_ll.h
@@ -102,7 +102,7 @@ FORCE_INLINE_ATTR void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *sou
     switch (LPPERI.core_clk_sel.lp_uart_clk_sel) {
     default:
     case 0:
-        *source_clk = (soc_module_clk_t)LP_UART_SCLK_LP_FAST;
+        *source_clk = (soc_module_clk_t)LP_UART_SCLK_RC_FAST;
         break;
     case 1:
         *source_clk = (soc_module_clk_t)LP_UART_SCLK_XTAL_D2;
@@ -123,7 +123,7 @@ static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_
 {
     (void)hw;
     switch (src_clk) {
-    case LP_UART_SCLK_LP_FAST:
+    case LP_UART_SCLK_RC_FAST:
         LPPERI.core_clk_sel.lp_uart_clk_sel = 0;
         break;
     case LP_UART_SCLK_XTAL_D2:
diff --git a/components/hal/esp32s3/include/hal/gdma_ll.h b/components/hal/esp32s3/include/hal/gdma_ll.h
index 58cc22253c..8cfba49a12 100644
--- a/components/hal/esp32s3/include/hal/gdma_ll.h
+++ b/components/hal/esp32s3/include/hal/gdma_ll.h
@@ -65,6 +65,7 @@ extern "C" {
 #define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
 #define GDMA_LL_AHB_RX_BURST_NEEDS_ALIGNMENT  1
 #define GDMA_LL_MAX_BURST_SIZE_PSRAM          64 // PSRAM controller doesn't support burst access with size > 64 bytes
+#define GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 // The alignment of the memory and size when DMA accesses encrypted memory
 
 #define GDMA_LL_AHB_M2M_CAPABLE_PAIR_MASK   0x1F  // pair 0,1,2,3,4 are M2M capable
 
diff --git a/components/hal/gdma_hal_axi.c b/components/hal/gdma_hal_axi.c
index e01e87d647..9e2da3ac9f 100644
--- a/components/hal/gdma_hal_axi.c
+++ b/components/hal/gdma_hal_axi.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -163,15 +163,6 @@ uint32_t gdma_axi_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gd
     }
 }
 
-void gdma_axi_hal_enable_access_encrypt_mem(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_or_dis)
-{
-    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
-        axi_dma_ll_rx_enable_ext_mem_ecc_aes_access(hal->axi_dma_dev, chan_id, en_or_dis);
-    } else {
-        axi_dma_ll_tx_enable_ext_mem_ecc_aes_access(hal->axi_dma_dev, chan_id, en_or_dis);
-    }
-}
-
 #if SOC_GDMA_SUPPORT_CRC
 void gdma_axi_hal_clear_crc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
 {
@@ -258,7 +249,6 @@ void gdma_axi_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
     hal->get_intr_status_reg = gdma_axi_hal_get_intr_status_reg;
     hal->get_eof_desc_addr = gdma_axi_hal_get_eof_desc_addr;
     hal->set_burst_size = gdma_axi_hal_set_burst_size;
-    hal->enable_access_encrypt_mem = gdma_axi_hal_enable_access_encrypt_mem;
 #if SOC_GDMA_SUPPORT_CRC
     hal->clear_crc = gdma_axi_hal_clear_crc;
     hal->set_crc_poly = gdma_axi_hal_set_crc_poly;
diff --git a/components/hal/gdma_hal_top.c b/components/hal/gdma_hal_top.c
index d41eb342cb..fce58d443c 100644
--- a/components/hal/gdma_hal_top.c
+++ b/components/hal/gdma_hal_top.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -90,13 +90,6 @@ uint32_t gdma_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gdma_c
     return hal->get_eof_desc_addr(hal, chan_id, dir, is_success);
 }
 
-void gdma_hal_enable_access_encrypt_mem(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_or_dis)
-{
-    if (hal->enable_access_encrypt_mem) {
-        hal->enable_access_encrypt_mem(hal, chan_id, dir, en_or_dis);
-    }
-}
-
 #if SOC_GDMA_SUPPORT_CRC
 void gdma_hal_clear_crc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
 {
diff --git a/components/hal/include/hal/clk_tree_hal.h b/components/hal/include/hal/clk_tree_hal.h
index 60d083f490..629d9a4ce1 100644
--- a/components/hal/include/hal/clk_tree_hal.h
+++ b/components/hal/include/hal/clk_tree_hal.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -35,7 +35,14 @@ uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src);
 uint32_t clk_hal_cpu_get_freq_hz(void);
 
 /**
- * @brief Get APB_CLK frequency
+ * @brief Get SYS_CLK frequency, derived from MEM_CLK
+ *
+ * @return SYS clock frequency, in Hz. Returns 0 if internal clock configuration is invalid.
+ */
+uint32_t clk_hal_sys_get_freq_hz(void);
+
+/**
+ * @brief Get APB_CLK frequency, derived from SYS_CLK
  *
  * @return APB clock frequency, in Hz. Returns 0 if internal clock configuration is invalid.
  */
diff --git a/components/hal/include/hal/emac_hal.h b/components/hal/include/hal/emac_hal.h
index f911c62759..85a5593af8 100644
--- a/components/hal/include/hal/emac_hal.h
+++ b/components/hal/include/hal/emac_hal.h
@@ -246,6 +246,8 @@ void emac_hal_init(emac_hal_context_t *hal);
 
 #define emac_hal_is_reset_done(hal) emac_ll_is_reset_done((hal)->dma_regs)
 
+void emac_hal_find_set_closest_csr_clock_range(emac_hal_context_t *hal, int mdc_freq_hz, int freq_hz);
+
 void emac_hal_set_csr_clock_range(emac_hal_context_t *hal, int freq);
 
 void emac_hal_init_mac_default(emac_hal_context_t *hal);
diff --git a/components/hal/include/hal/gdma_hal.h b/components/hal/include/hal/gdma_hal.h
index 3231cc583e..a9af957a12 100644
--- a/components/hal/include/hal/gdma_hal.h
+++ b/components/hal/include/hal/gdma_hal.h
@@ -87,7 +87,6 @@ struct gdma_hal_context_t {
     void (*clear_intr)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask); /// Clear the channel interrupt
     uint32_t (*read_intr_status)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw); /// Read the channel interrupt status
     uint32_t (*get_eof_desc_addr)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool is_success); /// Get the address of the descriptor with success/error EOF flag set
-    void (*enable_access_encrypt_mem)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_or_dis); /// Enable the access to the encrypted memory
 #if SOC_GDMA_SUPPORT_CRC
     void (*clear_crc)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); /// Clear the CRC interim results
     void (*set_crc_poly)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, const gdma_hal_crc_config_t *config); /// Set the CRC polynomial
@@ -130,8 +129,6 @@ uint32_t gdma_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_ch
 
 uint32_t gdma_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool is_success);
 
-void gdma_hal_enable_access_encrypt_mem(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_or_dis);
-
 #if SOC_GDMA_SUPPORT_CRC
 void gdma_hal_build_parallel_crc_matrix(int crc_width, uint32_t crc_poly_hex, int data_width,
                                         uint32_t *lfsr_transform_matrix, uint32_t *data_transform_matrix);
diff --git a/components/heap/heap_task_info.c b/components/heap/heap_task_info.c
index 880bf358fd..8844e4fea8 100644
--- a/components/heap/heap_task_info.c
+++ b/components/heap/heap_task_info.c
@@ -57,12 +57,16 @@ FORCE_INLINE_ATTR heap_t* find_biggest_heap(void)
     heap_t *heap = NULL;
     heap_t *biggest_heap = NULL;
     SLIST_FOREACH(heap, &registered_heaps, next) {
-        if (biggest_heap == NULL) {
+        /* In the case where we are currently looking for the biggest heap during startup,
+         * before the scheduler stated, all the memory regions marked as startup stacks will
+         * be NULL here. As such, they must be ignored. After boot up, this statement will
+         * never be true. */
+        if (heap->heap == NULL) {
+            /* Continue the loop */
+        } else if (biggest_heap == NULL) {
             biggest_heap = heap;
         } else if ((biggest_heap->end - biggest_heap->start) < (heap->end - heap->start)) {
             biggest_heap = heap;
-        } else {
-            // nothing to do here
         }
     }
     return biggest_heap;
diff --git a/components/heap/port/esp32c5/memory_layout.c b/components/heap/port/esp32c5/memory_layout.c
index 577ac688d0..09a92a0c23 100644
--- a/components/heap/port/esp32c5/memory_layout.c
+++ b/components/heap/port/esp32c5/memory_layout.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,6 +11,7 @@
 #include "soc/soc.h"
 #include "heap_memory_layout.h"
 #include "esp_heap_caps.h"
+#include "esp_rom_caps.h"
 
 #if CONFIG_SECURE_ENABLE_TEE
 #define SRAM_DIRAM_TEE_ORG               (SOC_DIRAM_IRAM_LOW)
@@ -73,6 +74,18 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
  */
 #define APP_USABLE_DRAM_END                 (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
 
+#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
+#if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS
+#define ESP_SECURE_BOOT_DIGEST_LEN 48
+#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
+#define ESP_SECURE_BOOT_DIGEST_LEN 32
+#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
+
+#define APP_USABLE_RTC_MEM_END              (SOC_RTC_DATA_HIGH - ESP_SECURE_BOOT_DIGEST_LEN)
+#else
+#define APP_USABLE_RTC_MEM_END              (SOC_RTC_DATA_HIGH)
+#endif
+
 const soc_memory_region_t soc_memory_regions[] = {
 #if CONFIG_SPIRAM
     { SOC_EXTRAM_DATA_LOW,  (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW),   SOC_MEMORY_TYPE_SPIRAM, 0,                      false}, //SPI SRAM, if available
@@ -80,7 +93,7 @@ const soc_memory_region_t soc_memory_regions[] = {
     { SOC_DIRAM_DRAM_LOW,   (APP_USABLE_DRAM_END - SOC_DIRAM_DRAM_LOW),     SOC_MEMORY_TYPE_RAM,    SOC_DIRAM_IRAM_LOW,     false}, //D/IRAM, can be used as trace memory
     { APP_USABLE_DRAM_END,  (SOC_DIRAM_DRAM_HIGH - APP_USABLE_DRAM_END),    SOC_MEMORY_TYPE_RAM,    APP_USABLE_DRAM_END,    true},  //D/IRAM, can be used as trace memory (ROM reserved area)
 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
-    { SOC_RTC_DATA_LOW,     (SOC_RTC_DATA_HIGH - SOC_RTC_DATA_LOW),         SOC_MEMORY_TYPE_RTCRAM, 0,                      false}, //LPRAM
+    { SOC_RTC_DATA_LOW,     (APP_USABLE_RTC_MEM_END - SOC_RTC_DATA_LOW),    SOC_MEMORY_TYPE_RTCRAM, 0,                      false}, //LPRAM
 #endif
 };
 
diff --git a/components/heap/port/esp32c6/memory_layout.c b/components/heap/port/esp32c6/memory_layout.c
index 05dadf5714..1610aa8245 100644
--- a/components/heap/port/esp32c6/memory_layout.c
+++ b/components/heap/port/esp32c6/memory_layout.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,6 +11,7 @@
 #include "soc/soc.h"
 #include "heap_memory_layout.h"
 #include "esp_heap_caps.h"
+#include "esp_rom_caps.h"
 
 #if CONFIG_SECURE_ENABLE_TEE
 #define SRAM_DIRAM_TEE_ORG               (SOC_DIRAM_IRAM_LOW)
@@ -71,6 +72,17 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
  */
 #define APP_USABLE_DRAM_END           (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
 
+#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
+#if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS
+#define ESP_SECURE_BOOT_DIGEST_LEN 48
+#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
+#define ESP_SECURE_BOOT_DIGEST_LEN 32
+#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
+#define APP_USABLE_RTC_MEM_END              (SOC_RTC_DATA_HIGH - ESP_SECURE_BOOT_DIGEST_LEN)
+#else
+#define APP_USABLE_RTC_MEM_END              (SOC_RTC_DATA_HIGH)
+#endif
+
 const soc_memory_region_t soc_memory_regions[] = {
     { 0x40800000,           0x20000,                                   SOC_MEMORY_TYPE_RAM, 0x40800000,             false}, //D/IRAM level0, can be used as trace memory
     { 0x40820000,           0x20000,                                   SOC_MEMORY_TYPE_RAM, 0x40820000,             false}, //D/IRAM level1, can be used as trace memory
@@ -78,7 +90,7 @@ const soc_memory_region_t soc_memory_regions[] = {
     { 0x40860000,           (APP_USABLE_DRAM_END-0x40860000),          SOC_MEMORY_TYPE_RAM, 0x40860000,             false}, //D/IRAM level3, can be used as trace memory
     { APP_USABLE_DRAM_END,  (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END,    true},  //D/IRAM level3, can be used as trace memory (ROM reserved area)
 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
-    { 0x50000000,           0x4000,                                    SOC_MEMORY_TYPE_RTCRAM,  0,                      false}, //LPRAM
+    { 0x50000000,           (APP_USABLE_RTC_MEM_END - SOC_RTC_DATA_LOW), SOC_MEMORY_TYPE_RTCRAM,  0,                      false}, //LPRAM
 #endif
 };
 
diff --git a/components/heap/port/esp32h2/memory_layout.c b/components/heap/port/esp32h2/memory_layout.c
index 05071759e9..7e5710ef96 100644
--- a/components/heap/port/esp32h2/memory_layout.c
+++ b/components/heap/port/esp32h2/memory_layout.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,6 +11,7 @@
 #include "soc/soc.h"
 #include "heap_memory_layout.h"
 #include "esp_heap_caps.h"
+#include "esp_rom_caps.h"
 
 #if CONFIG_SECURE_ENABLE_TEE
 #define SRAM_DIRAM_TEE_ORG               (SOC_DIRAM_IRAM_LOW)
@@ -69,6 +70,17 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
  */
 #define APP_USABLE_DRAM_END           (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
 
+#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
+#if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS
+#define ESP_SECURE_BOOT_DIGEST_LEN 48
+#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
+#define ESP_SECURE_BOOT_DIGEST_LEN 32
+#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
+#define APP_USABLE_RTC_MEM_END              (SOC_RTC_DATA_HIGH - ESP_SECURE_BOOT_DIGEST_LEN)
+#else
+#define APP_USABLE_RTC_MEM_END              (SOC_RTC_DATA_HIGH)
+#endif
+
 const soc_memory_region_t soc_memory_regions[] = {
     { 0x40800000,           0x10000,                                    SOC_MEMORY_TYPE_RAM,    0x40800000,             false}, //D/IRAM level 0
     { 0x40810000,           0x10000,                                    SOC_MEMORY_TYPE_RAM,    0x40810000,             false}, //D/IRAM level 1
@@ -77,7 +89,7 @@ const soc_memory_region_t soc_memory_regions[] = {
     { 0x40840000,           APP_USABLE_DRAM_END-0x40840000,             SOC_MEMORY_TYPE_RAM,    0x40840000,             false}, //D/IRAM level 4
     { APP_USABLE_DRAM_END,  (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END),  SOC_MEMORY_TYPE_RAM,    APP_USABLE_DRAM_END,    true},  //D/IRAM level 4
 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
-    { 0x50000000,           0x1000,                                     SOC_MEMORY_TYPE_RTCRAM, 0,                      false}, //Fast RTC memory
+    { 0x50000000,           (APP_USABLE_RTC_MEM_END - SOC_RTC_DATA_LOW),SOC_MEMORY_TYPE_RTCRAM, 0,                      false}, //Fast RTC memory
 #endif
 };
 
diff --git a/components/heap/port/esp32h21/memory_layout.c b/components/heap/port/esp32h21/memory_layout.c
index 9f4cdc0642..1263fdeec5 100644
--- a/components/heap/port/esp32h21/memory_layout.c
+++ b/components/heap/port/esp32h21/memory_layout.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,7 +11,7 @@
 #include "soc/soc.h"
 #include "heap_memory_layout.h"
 #include "esp_heap_caps.h"
-
+#include "esp_rom_caps.h"
 
 /**
  * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
@@ -65,6 +65,17 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
  */
 #define APP_USABLE_DRAM_END           (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
 
+#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
+#if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS
+#define ESP_SECURE_BOOT_DIGEST_LEN 48
+#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
+#define ESP_SECURE_BOOT_DIGEST_LEN 32
+#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
+#define APP_USABLE_RTC_MEM_END              (SOC_RTC_DATA_HIGH - ESP_SECURE_BOOT_DIGEST_LEN)
+#else
+#define APP_USABLE_RTC_MEM_END              (SOC_RTC_DATA_HIGH)
+#endif
+
 const soc_memory_region_t soc_memory_regions[] = {
     { 0x40800000,           0x10000,                                    SOC_MEMORY_TYPE_RAM,    0x40800000,             false}, //D/IRAM level 0
     { 0x40810000,           0x10000,                                    SOC_MEMORY_TYPE_RAM,    0x40810000,             false}, //D/IRAM level 1
@@ -73,7 +84,7 @@ const soc_memory_region_t soc_memory_regions[] = {
     { 0x40840000,           APP_USABLE_DRAM_END-0x40840000,             SOC_MEMORY_TYPE_RAM,    0x40840000,             false}, //D/IRAM level 4
     { APP_USABLE_DRAM_END,  (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END),  SOC_MEMORY_TYPE_RAM,    APP_USABLE_DRAM_END,    true},  //D/IRAM level 4
 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
-    { 0x50000000,           0x1000,                                     SOC_MEMORY_TYPE_RTCRAM, 0,                      false}, //Fast RTC memory
+    { 0x50000000,           (APP_USABLE_RTC_MEM_END - SOC_RTC_DATA_LOW),SOC_MEMORY_TYPE_RTCRAM, 0,                      false}, //Fast RTC memory
 #endif
 };
 
diff --git a/components/mbedtls/port/aes/dma/esp_aes_dma_core.c b/components/mbedtls/port/aes/dma/esp_aes_dma_core.c
index a066122d95..c5e2fc8be5 100644
--- a/components/mbedtls/port/aes/dma/esp_aes_dma_core.c
+++ b/components/mbedtls/port/aes/dma/esp_aes_dma_core.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -1040,6 +1040,7 @@ int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsign
                 return -1;
             }
         }
+
         if (esp_ptr_external_ram(output)) {
             size_t dcache_line_size;
             ret = esp_cache_get_alignment(MALLOC_CAP_SPIRAM, &dcache_line_size);
@@ -1066,6 +1067,19 @@ int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsign
             return esp_aes_process_dma_ext_ram(ctx, input, output, len, stream_out, input_needs_realloc, output_needs_realloc);
         }
 
+#if (CONFIG_SPIRAM && SOC_PSRAM_DMA_CAPABLE)
+        // When a DMA engine (AES-DMA operations) writes into a PSRAM destination buffer that previously contained dirty D-cache lines,
+        // later cache eviction can write back stale data and corrupt the DMA result.
+        // Fix this by cleaning the destination buffers before starting DMA transfers.
+        if (esp_ptr_external_ram(output)) {
+            if (esp_cache_msync((void *)output, block_bytes, ESP_CACHE_MSYNC_FLAG_DIR_M2C) != ESP_OK) {
+                mbedtls_platform_zeroize(output, len);
+                ESP_LOGE(TAG, "Cache sync failed for the output in external RAM");
+                return -1;
+            }
+        }
+#endif
+
         /* Set up dma descriptors for input and output considering the 16 byte alignment requirement for EDMA */
         crypto_dma_desc_num = dma_desc_get_required_num(block_bytes, DMA_DESCRIPTOR_BUFFER_MAX_SIZE_16B_ALIGNED);
 
@@ -1155,17 +1169,6 @@ int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsign
         goto cleanup;
     }
 
-#if (CONFIG_SPIRAM && SOC_PSRAM_DMA_CAPABLE)
-    if (block_bytes > 0) {
-        if (esp_ptr_external_ram(output)) {
-            if(esp_cache_msync((void*)output, block_bytes, ESP_CACHE_MSYNC_FLAG_DIR_M2C) != ESP_OK) {
-                mbedtls_platform_zeroize(output, len);
-                ESP_LOGE(TAG, "Cache sync failed for the output in external RAM");
-                return -1;
-            }
-        }
-    }
-#endif
     aes_hal_transform_dma_finish();
 
     if (stream_bytes > 0) {
diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
index 36c2bf2e26..0dc59a0df1 100644
--- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
@@ -187,6 +187,10 @@ config SOC_PMU_SUPPORTED
     bool
     default y
 
+config SOC_PMU_PVT_SUPPORTED
+    bool
+    default y
+
 config SOC_PAU_SUPPORTED
     bool
     default y
diff --git a/components/soc/esp32c6/include/soc/pvt_reg.h b/components/soc/esp32c6/include/soc/pvt_reg.h
new file mode 100644
index 0000000000..cbc2b92a76
--- /dev/null
+++ b/components/soc/esp32c6/include/soc/pvt_reg.h
@@ -0,0 +1,2834 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PVT_PMUP_BITMAP_HIGH0_REG register
+ *  select valid pvt channel
+ */
+#define PVT_PMUP_BITMAP_HIGH0_REG (DR_REG_PVT_MONITOR_BASE + 0x0)
+/** PVT_PUMP_BITMAP_HIGH0 : R/W; bitpos: [31:0]; default: 0;
+ *  select valid high channel0
+ */
+#define PVT_PUMP_BITMAP_HIGH0    0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_HIGH0_M  (PVT_PUMP_BITMAP_HIGH0_V << PVT_PUMP_BITMAP_HIGH0_S)
+#define PVT_PUMP_BITMAP_HIGH0_V  0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_HIGH0_S  0
+
+/** PVT_PMUP_BITMAP_HIGH1_REG register
+ *  select valid pvt channel
+ */
+#define PVT_PMUP_BITMAP_HIGH1_REG (DR_REG_PVT_MONITOR_BASE + 0x4)
+/** PVT_PUMP_BITMAP_HIGH1 : R/W; bitpos: [31:0]; default: 0;
+ *  select valid high channel1
+ */
+#define PVT_PUMP_BITMAP_HIGH1    0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_HIGH1_M  (PVT_PUMP_BITMAP_HIGH1_V << PVT_PUMP_BITMAP_HIGH1_S)
+#define PVT_PUMP_BITMAP_HIGH1_V  0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_HIGH1_S  0
+
+/** PVT_PMUP_BITMAP_HIGH2_REG register
+ *  select valid pvt channel
+ */
+#define PVT_PMUP_BITMAP_HIGH2_REG (DR_REG_PVT_MONITOR_BASE + 0x8)
+/** PVT_PUMP_BITMAP_HIGH2 : R/W; bitpos: [31:0]; default: 0;
+ *  select valid high channel2
+ */
+#define PVT_PUMP_BITMAP_HIGH2    0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_HIGH2_M  (PVT_PUMP_BITMAP_HIGH2_V << PVT_PUMP_BITMAP_HIGH2_S)
+#define PVT_PUMP_BITMAP_HIGH2_V  0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_HIGH2_S  0
+
+/** PVT_PMUP_BITMAP_HIGH3_REG register
+ *  select valid pvt channel
+ */
+#define PVT_PMUP_BITMAP_HIGH3_REG (DR_REG_PVT_MONITOR_BASE + 0xc)
+/** PVT_PUMP_BITMAP_HIGH3 : R/W; bitpos: [31:0]; default: 0;
+ *  select valid high channel3
+ */
+#define PVT_PUMP_BITMAP_HIGH3    0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_HIGH3_M  (PVT_PUMP_BITMAP_HIGH3_V << PVT_PUMP_BITMAP_HIGH3_S)
+#define PVT_PUMP_BITMAP_HIGH3_V  0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_HIGH3_S  0
+
+/** PVT_PMUP_BITMAP_HIGH4_REG register
+ *  select valid pvt channel
+ */
+#define PVT_PMUP_BITMAP_HIGH4_REG (DR_REG_PVT_MONITOR_BASE + 0x10)
+/** PVT_PUMP_BITMAP_HIGH4 : R/W; bitpos: [31:0]; default: 0;
+ *  select valid high channel4
+ */
+#define PVT_PUMP_BITMAP_HIGH4    0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_HIGH4_M  (PVT_PUMP_BITMAP_HIGH4_V << PVT_PUMP_BITMAP_HIGH4_S)
+#define PVT_PUMP_BITMAP_HIGH4_V  0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_HIGH4_S  0
+
+/** PVT_PMUP_BITMAP_LOW0_REG register
+ *  select valid pvt channel
+ */
+#define PVT_PMUP_BITMAP_LOW0_REG (DR_REG_PVT_MONITOR_BASE + 0x14)
+/** PVT_PUMP_BITMAP_LOW0 : R/W; bitpos: [31:0]; default: 0;
+ *  select valid low channel0
+ */
+#define PVT_PUMP_BITMAP_LOW0    0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_LOW0_M  (PVT_PUMP_BITMAP_LOW0_V << PVT_PUMP_BITMAP_LOW0_S)
+#define PVT_PUMP_BITMAP_LOW0_V  0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_LOW0_S  0
+
+/** PVT_PMUP_BITMAP_LOW1_REG register
+ *  select valid pvt channel
+ */
+#define PVT_PMUP_BITMAP_LOW1_REG (DR_REG_PVT_MONITOR_BASE + 0x18)
+/** PVT_PUMP_BITMAP_LOW1 : R/W; bitpos: [31:0]; default: 0;
+ *  select valid low channel1
+ */
+#define PVT_PUMP_BITMAP_LOW1    0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_LOW1_M  (PVT_PUMP_BITMAP_LOW1_V << PVT_PUMP_BITMAP_LOW1_S)
+#define PVT_PUMP_BITMAP_LOW1_V  0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_LOW1_S  0
+
+/** PVT_PMUP_BITMAP_LOW2_REG register
+ *  select valid pvt channel
+ */
+#define PVT_PMUP_BITMAP_LOW2_REG (DR_REG_PVT_MONITOR_BASE + 0x1c)
+/** PVT_PUMP_BITMAP_LOW2 : R/W; bitpos: [31:0]; default: 0;
+ *  select valid low channel2
+ */
+#define PVT_PUMP_BITMAP_LOW2    0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_LOW2_M  (PVT_PUMP_BITMAP_LOW2_V << PVT_PUMP_BITMAP_LOW2_S)
+#define PVT_PUMP_BITMAP_LOW2_V  0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_LOW2_S  0
+
+/** PVT_PMUP_BITMAP_LOW3_REG register
+ *  select valid pvt channel
+ */
+#define PVT_PMUP_BITMAP_LOW3_REG (DR_REG_PVT_MONITOR_BASE + 0x20)
+/** PVT_PUMP_BITMAP_LOW3 : R/W; bitpos: [31:0]; default: 0;
+ *  select valid low channel3
+ */
+#define PVT_PUMP_BITMAP_LOW3    0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_LOW3_M  (PVT_PUMP_BITMAP_LOW3_V << PVT_PUMP_BITMAP_LOW3_S)
+#define PVT_PUMP_BITMAP_LOW3_V  0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_LOW3_S  0
+
+/** PVT_PMUP_BITMAP_LOW4_REG register
+ *  select valid pvt channel
+ */
+#define PVT_PMUP_BITMAP_LOW4_REG (DR_REG_PVT_MONITOR_BASE + 0x24)
+/** PVT_PUMP_BITMAP_LOW4 : R/W; bitpos: [31:0]; default: 0;
+ *  select valid low channel4
+ */
+#define PVT_PUMP_BITMAP_LOW4    0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_LOW4_M  (PVT_PUMP_BITMAP_LOW4_V << PVT_PUMP_BITMAP_LOW4_S)
+#define PVT_PUMP_BITMAP_LOW4_V  0xFFFFFFFFU
+#define PVT_PUMP_BITMAP_LOW4_S  0
+
+/** PVT_PMUP_DRV_CFG_REG register
+ *  configure pump drv
+ */
+#define PVT_PMUP_DRV_CFG_REG (DR_REG_PVT_MONITOR_BASE + 0x28)
+/** PVT_PUMP_EN : R/W; bitpos: [9]; default: 0;
+ *  configure pvt charge xpd
+ */
+#define PVT_PUMP_EN    (BIT(9))
+#define PVT_PUMP_EN_M  (PVT_PUMP_EN_V << PVT_PUMP_EN_S)
+#define PVT_PUMP_EN_V  0x00000001U
+#define PVT_PUMP_EN_S  9
+/** PVT_CLK_EN : R/W; bitpos: [10]; default: 0;
+ *  force register clken
+ */
+#define PVT_CLK_EN    (BIT(10))
+#define PVT_CLK_EN_M  (PVT_CLK_EN_V << PVT_CLK_EN_S)
+#define PVT_CLK_EN_V  0x00000001U
+#define PVT_CLK_EN_S  10
+/** PVT_PUMP_DRV4 : R/W; bitpos: [14:11]; default: 0;
+ *  configure cmd4 drv
+ */
+#define PVT_PUMP_DRV4    0x0000000FU
+#define PVT_PUMP_DRV4_M  (PVT_PUMP_DRV4_V << PVT_PUMP_DRV4_S)
+#define PVT_PUMP_DRV4_V  0x0000000FU
+#define PVT_PUMP_DRV4_S  11
+/** PVT_PUMP_DRV3 : R/W; bitpos: [18:15]; default: 0;
+ *  configure cmd3 drv
+ */
+#define PVT_PUMP_DRV3    0x0000000FU
+#define PVT_PUMP_DRV3_M  (PVT_PUMP_DRV3_V << PVT_PUMP_DRV3_S)
+#define PVT_PUMP_DRV3_V  0x0000000FU
+#define PVT_PUMP_DRV3_S  15
+/** PVT_PUMP_DRV2 : R/W; bitpos: [22:19]; default: 0;
+ *  configure cmd2 drv
+ */
+#define PVT_PUMP_DRV2    0x0000000FU
+#define PVT_PUMP_DRV2_M  (PVT_PUMP_DRV2_V << PVT_PUMP_DRV2_S)
+#define PVT_PUMP_DRV2_V  0x0000000FU
+#define PVT_PUMP_DRV2_S  19
+/** PVT_PUMP_DRV1 : R/W; bitpos: [26:23]; default: 0;
+ *  configure cmd1 drv
+ */
+#define PVT_PUMP_DRV1    0x0000000FU
+#define PVT_PUMP_DRV1_M  (PVT_PUMP_DRV1_V << PVT_PUMP_DRV1_S)
+#define PVT_PUMP_DRV1_V  0x0000000FU
+#define PVT_PUMP_DRV1_S  23
+/** PVT_PUMP_DRV0 : R/W; bitpos: [30:27]; default: 0;
+ *  configure cmd0 drv
+ */
+#define PVT_PUMP_DRV0    0x0000000FU
+#define PVT_PUMP_DRV0_M  (PVT_PUMP_DRV0_V << PVT_PUMP_DRV0_S)
+#define PVT_PUMP_DRV0_V  0x0000000FU
+#define PVT_PUMP_DRV0_S  27
+
+/** PVT_PMUP_CHANNEL_CFG_REG register
+ *  configure the code of valid pump channel code
+ */
+#define PVT_PMUP_CHANNEL_CFG_REG (DR_REG_PVT_MONITOR_BASE + 0x2c)
+/** PVT_PUMP_CHANNEL_CODE4 : R/W; bitpos: [11:7]; default: 0;
+ *  configure cmd4 code
+ */
+#define PVT_PUMP_CHANNEL_CODE4    0x0000001FU
+#define PVT_PUMP_CHANNEL_CODE4_M  (PVT_PUMP_CHANNEL_CODE4_V << PVT_PUMP_CHANNEL_CODE4_S)
+#define PVT_PUMP_CHANNEL_CODE4_V  0x0000001FU
+#define PVT_PUMP_CHANNEL_CODE4_S  7
+/** PVT_PUMP_CHANNEL_CODE3 : R/W; bitpos: [16:12]; default: 0;
+ *  configure cmd3 code
+ */
+#define PVT_PUMP_CHANNEL_CODE3    0x0000001FU
+#define PVT_PUMP_CHANNEL_CODE3_M  (PVT_PUMP_CHANNEL_CODE3_V << PVT_PUMP_CHANNEL_CODE3_S)
+#define PVT_PUMP_CHANNEL_CODE3_V  0x0000001FU
+#define PVT_PUMP_CHANNEL_CODE3_S  12
+/** PVT_PUMP_CHANNEL_CODE2 : R/W; bitpos: [21:17]; default: 0;
+ *  configure cmd2 code
+ */
+#define PVT_PUMP_CHANNEL_CODE2    0x0000001FU
+#define PVT_PUMP_CHANNEL_CODE2_M  (PVT_PUMP_CHANNEL_CODE2_V << PVT_PUMP_CHANNEL_CODE2_S)
+#define PVT_PUMP_CHANNEL_CODE2_V  0x0000001FU
+#define PVT_PUMP_CHANNEL_CODE2_S  17
+/** PVT_PUMP_CHANNEL_CODE1 : R/W; bitpos: [26:22]; default: 0;
+ *  configure cmd1 code
+ */
+#define PVT_PUMP_CHANNEL_CODE1    0x0000001FU
+#define PVT_PUMP_CHANNEL_CODE1_M  (PVT_PUMP_CHANNEL_CODE1_V << PVT_PUMP_CHANNEL_CODE1_S)
+#define PVT_PUMP_CHANNEL_CODE1_V  0x0000001FU
+#define PVT_PUMP_CHANNEL_CODE1_S  22
+/** PVT_PUMP_CHANNEL_CODE0 : R/W; bitpos: [31:27]; default: 0;
+ *  configure cmd0 code
+ */
+#define PVT_PUMP_CHANNEL_CODE0    0x0000001FU
+#define PVT_PUMP_CHANNEL_CODE0_M  (PVT_PUMP_CHANNEL_CODE0_V << PVT_PUMP_CHANNEL_CODE0_S)
+#define PVT_PUMP_CHANNEL_CODE0_V  0x0000001FU
+#define PVT_PUMP_CHANNEL_CODE0_S  27
+
+/** PVT_CLK_CFG_REG register
+ *  configure pvt clk
+ */
+#define PVT_CLK_CFG_REG (DR_REG_PVT_MONITOR_BASE + 0x30)
+/** PVT_PUMP_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_PUMP_CLK_DIV_NUM    0x000000FFU
+#define PVT_PUMP_CLK_DIV_NUM_M  (PVT_PUMP_CLK_DIV_NUM_V << PVT_PUMP_CLK_DIV_NUM_S)
+#define PVT_PUMP_CLK_DIV_NUM_V  0x000000FFU
+#define PVT_PUMP_CLK_DIV_NUM_S  0
+/** PVT_MONITOR_CLK_PVT_EN : R/W; bitpos: [8]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_CLK_PVT_EN    (BIT(8))
+#define PVT_MONITOR_CLK_PVT_EN_M  (PVT_MONITOR_CLK_PVT_EN_V << PVT_MONITOR_CLK_PVT_EN_S)
+#define PVT_MONITOR_CLK_PVT_EN_V  0x00000001U
+#define PVT_MONITOR_CLK_PVT_EN_S  8
+/** PVT_CLK_SEL : R/W; bitpos: [31]; default: 0;
+ *  select pvt clk
+ */
+#define PVT_CLK_SEL    (BIT(31))
+#define PVT_CLK_SEL_M  (PVT_CLK_SEL_V << PVT_CLK_SEL_S)
+#define PVT_CLK_SEL_V  0x00000001U
+#define PVT_CLK_SEL_S  31
+
+/** PVT_DBIAS_CHANNEL_SEL0_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CHANNEL_SEL0_REG (DR_REG_PVT_MONITOR_BASE + 0x34)
+/** PVT_DBIAS_CHANNEL3_SEL : R/W; bitpos: [10:4]; default: 64;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CHANNEL3_SEL    0x0000007FU
+#define PVT_DBIAS_CHANNEL3_SEL_M  (PVT_DBIAS_CHANNEL3_SEL_V << PVT_DBIAS_CHANNEL3_SEL_S)
+#define PVT_DBIAS_CHANNEL3_SEL_V  0x0000007FU
+#define PVT_DBIAS_CHANNEL3_SEL_S  4
+/** PVT_DBIAS_CHANNEL2_SEL : R/W; bitpos: [17:11]; default: 64;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CHANNEL2_SEL    0x0000007FU
+#define PVT_DBIAS_CHANNEL2_SEL_M  (PVT_DBIAS_CHANNEL2_SEL_V << PVT_DBIAS_CHANNEL2_SEL_S)
+#define PVT_DBIAS_CHANNEL2_SEL_V  0x0000007FU
+#define PVT_DBIAS_CHANNEL2_SEL_S  11
+/** PVT_DBIAS_CHANNEL1_SEL : R/W; bitpos: [24:18]; default: 64;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CHANNEL1_SEL    0x0000007FU
+#define PVT_DBIAS_CHANNEL1_SEL_M  (PVT_DBIAS_CHANNEL1_SEL_V << PVT_DBIAS_CHANNEL1_SEL_S)
+#define PVT_DBIAS_CHANNEL1_SEL_V  0x0000007FU
+#define PVT_DBIAS_CHANNEL1_SEL_S  18
+/** PVT_DBIAS_CHANNEL0_SEL : R/W; bitpos: [31:25]; default: 64;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CHANNEL0_SEL    0x0000007FU
+#define PVT_DBIAS_CHANNEL0_SEL_M  (PVT_DBIAS_CHANNEL0_SEL_V << PVT_DBIAS_CHANNEL0_SEL_S)
+#define PVT_DBIAS_CHANNEL0_SEL_V  0x0000007FU
+#define PVT_DBIAS_CHANNEL0_SEL_S  25
+
+/** PVT_DBIAS_CHANNEL_SEL1_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CHANNEL_SEL1_REG (DR_REG_PVT_MONITOR_BASE + 0x38)
+/** PVT_DBIAS_CHANNEL4_SEL : R/W; bitpos: [31:25]; default: 64;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CHANNEL4_SEL    0x0000007FU
+#define PVT_DBIAS_CHANNEL4_SEL_M  (PVT_DBIAS_CHANNEL4_SEL_V << PVT_DBIAS_CHANNEL4_SEL_S)
+#define PVT_DBIAS_CHANNEL4_SEL_V  0x0000007FU
+#define PVT_DBIAS_CHANNEL4_SEL_S  25
+
+/** PVT_DBIAS_CHANNEL0_SEL_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CHANNEL0_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x3c)
+/** PVT_DBIAS_CHANNEL0_CFG : R/W; bitpos: [16:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CHANNEL0_CFG    0x0001FFFFU
+#define PVT_DBIAS_CHANNEL0_CFG_M  (PVT_DBIAS_CHANNEL0_CFG_V << PVT_DBIAS_CHANNEL0_CFG_S)
+#define PVT_DBIAS_CHANNEL0_CFG_V  0x0001FFFFU
+#define PVT_DBIAS_CHANNEL0_CFG_S  0
+
+/** PVT_DBIAS_CHANNEL1_SEL_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CHANNEL1_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x40)
+/** PVT_DBIAS_CHANNEL1_CFG : R/W; bitpos: [16:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CHANNEL1_CFG    0x0001FFFFU
+#define PVT_DBIAS_CHANNEL1_CFG_M  (PVT_DBIAS_CHANNEL1_CFG_V << PVT_DBIAS_CHANNEL1_CFG_S)
+#define PVT_DBIAS_CHANNEL1_CFG_V  0x0001FFFFU
+#define PVT_DBIAS_CHANNEL1_CFG_S  0
+
+/** PVT_DBIAS_CHANNEL2_SEL_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CHANNEL2_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x44)
+/** PVT_DBIAS_CHANNEL2_CFG : R/W; bitpos: [16:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CHANNEL2_CFG    0x0001FFFFU
+#define PVT_DBIAS_CHANNEL2_CFG_M  (PVT_DBIAS_CHANNEL2_CFG_V << PVT_DBIAS_CHANNEL2_CFG_S)
+#define PVT_DBIAS_CHANNEL2_CFG_V  0x0001FFFFU
+#define PVT_DBIAS_CHANNEL2_CFG_S  0
+
+/** PVT_DBIAS_CHANNEL3_SEL_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CHANNEL3_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x48)
+/** PVT_DBIAS_CHANNEL3_CFG : R/W; bitpos: [16:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CHANNEL3_CFG    0x0001FFFFU
+#define PVT_DBIAS_CHANNEL3_CFG_M  (PVT_DBIAS_CHANNEL3_CFG_V << PVT_DBIAS_CHANNEL3_CFG_S)
+#define PVT_DBIAS_CHANNEL3_CFG_V  0x0001FFFFU
+#define PVT_DBIAS_CHANNEL3_CFG_S  0
+
+/** PVT_DBIAS_CHANNEL4_SEL_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CHANNEL4_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x4c)
+/** PVT_DBIAS_CHANNEL4_CFG : R/W; bitpos: [16:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CHANNEL4_CFG    0x0001FFFFU
+#define PVT_DBIAS_CHANNEL4_CFG_M  (PVT_DBIAS_CHANNEL4_CFG_V << PVT_DBIAS_CHANNEL4_CFG_S)
+#define PVT_DBIAS_CHANNEL4_CFG_V  0x0001FFFFU
+#define PVT_DBIAS_CHANNEL4_CFG_S  0
+
+/** PVT_DBIAS_CMD0_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CMD0_REG (DR_REG_PVT_MONITOR_BASE + 0x50)
+/** PVT_DBIAS_CMD0 : R/W; bitpos: [16:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CMD0_OFFSET_FLAG 1
+#define PVT_DBIAS_CMD0_OFFSET_FLAG_S 16
+#define PVT_DBIAS_CMD0_OFFSET_VALUE 0x1F
+#define PVT_DBIAS_CMD0_OFFSET_VALUE_S 11
+#define PVT_DBIAS_CMD0_PVT 0x7FF
+#define PVT_DBIAS_CMD0_PVT_S 0
+
+/** PVT_DBIAS_CMD1_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CMD1_REG (DR_REG_PVT_MONITOR_BASE + 0x54)
+/** PVT_DBIAS_CMD1 : R/W; bitpos: [16:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CMD1_OFFSET_FLAG 1
+#define PVT_DBIAS_CMD1_OFFSET_FLAG_S 16
+#define PVT_DBIAS_CMD1_OFFSET_VALUE 0x1F
+#define PVT_DBIAS_CMD1_OFFSET_VALUE_S 11
+#define PVT_DBIAS_CMD1_PVT 0x7FF
+#define PVT_DBIAS_CMD1_PVT_S 0
+
+/** PVT_DBIAS_CMD2_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CMD2_REG (DR_REG_PVT_MONITOR_BASE + 0x58)
+/** PVT_DBIAS_CMD2 : R/W; bitpos: [16:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CMD2_OFFSET_FLAG 1
+#define PVT_DBIAS_CMD2_OFFSET_FLAG_S 16
+#define PVT_DBIAS_CMD2_OFFSET_VALUE 0x1F
+#define PVT_DBIAS_CMD2_OFFSET_VALUE_S 11
+#define PVT_DBIAS_CMD2_PVT 0x7FF
+#define PVT_DBIAS_CMD2_PVT_S 0
+
+/** PVT_DBIAS_CMD3_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CMD3_REG (DR_REG_PVT_MONITOR_BASE + 0x5c)
+/** PVT_DBIAS_CMD3 : R/W; bitpos: [16:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CMD3    0x0001FFFFU
+#define PVT_DBIAS_CMD3_M  (PVT_DBIAS_CMD3_V << PVT_DBIAS_CMD3_S)
+#define PVT_DBIAS_CMD3_V  0x0001FFFFU
+#define PVT_DBIAS_CMD3_S  0
+
+/** PVT_DBIAS_CMD4_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_CMD4_REG (DR_REG_PVT_MONITOR_BASE + 0x60)
+/** PVT_DBIAS_CMD4 : R/W; bitpos: [16:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DBIAS_CMD4    0x0001FFFFU
+#define PVT_DBIAS_CMD4_M  (PVT_DBIAS_CMD4_V << PVT_DBIAS_CMD4_S)
+#define PVT_DBIAS_CMD4_V  0x0001FFFFU
+#define PVT_DBIAS_CMD4_S  0
+
+/** PVT_DBIAS_TIMER_REG register
+ *  needs desc
+ */
+#define PVT_DBIAS_TIMER_REG (DR_REG_PVT_MONITOR_BASE + 0x64)
+/** PVT_TIMER_TARGET : R/W; bitpos: [30:15]; default: 65535;
+ *  needs field desc
+ */
+#define PVT_TIMER_TARGET    0x0000FFFFU
+#define PVT_TIMER_TARGET_M  (PVT_TIMER_TARGET_V << PVT_TIMER_TARGET_S)
+#define PVT_TIMER_TARGET_V  0x0000FFFFU
+#define PVT_TIMER_TARGET_S  15
+/** PVT_TIMER_EN : R/W; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMER_EN    (BIT(31))
+#define PVT_TIMER_EN_M  (PVT_TIMER_EN_V << PVT_TIMER_EN_S)
+#define PVT_TIMER_EN_V  0x00000001U
+#define PVT_TIMER_EN_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x68)
+/** PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_M  (PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_V << PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_M  (PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_V << PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_M  (PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_V << PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_M  (PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x6c)
+/** PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_M  (PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_V << PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_M  (PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_V << PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_M  (PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_V << PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_M  (PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x70)
+/** PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_M  (PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_V << PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_M  (PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_V << PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_M  (PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_V << PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_M  (PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x74)
+/** PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_M  (PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_V << PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_M  (PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_V << PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_M  (PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_V << PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_M  (PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x78)
+/** PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_M  (PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_V << PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_M  (PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_V << PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_M  (PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_V << PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_M  (PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x7c)
+/** PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_M  (PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_V << PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_M  (PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_V << PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_M  (PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_V << PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_M  (PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x80)
+/** PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_M  (PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_V << PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_M  (PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_V << PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_M  (PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_V << PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_M  (PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x84)
+/** PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_M  (PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_V << PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_M  (PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_V << PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_M  (PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_V << PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_M  (PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x88)
+/** PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_M  (PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_V << PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_M  (PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_V << PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_M  (PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_V << PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_M  (PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x8c)
+/** PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_M  (PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_V << PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_M  (PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_V << PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_M  (PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_V << PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_M  (PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x90)
+/** PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_M  (PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_V << PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_M  (PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_V << PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_M  (PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_V << PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_M  (PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x94)
+/** PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_M  (PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_V << PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_M  (PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_V << PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_M  (PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_V << PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_M  (PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x98)
+/** PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_M  (PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_V << PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_M  (PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_V << PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_M  (PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_V << PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_M  (PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x9c)
+/** PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_M  (PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_V << PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_M  (PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_V << PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_M  (PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_V << PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_M  (PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xa0)
+/** PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_M  (PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_V << PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_M  (PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_V << PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_M  (PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_V << PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_M  (PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xa4)
+/** PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_M  (PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_V << PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_M  (PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_V << PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_M  (PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_V << PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_M  (PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xa8)
+/** PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_M  (PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_V << PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_M  (PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_V << PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_M  (PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_V << PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_M  (PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xac)
+/** PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_M  (PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_V << PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_M  (PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_V << PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_M  (PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_V << PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_M  (PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xb0)
+/** PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_M  (PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_V << PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_M  (PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_V << PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_M  (PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_V << PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_M  (PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xb4)
+/** PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_M  (PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_V << PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_M  (PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_V << PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_M  (PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_V << PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_M  (PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xb8)
+/** PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_M  (PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_V << PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_M  (PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_V << PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_M  (PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_V << PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_M  (PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xbc)
+/** PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_M  (PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_V << PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_M  (PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_V << PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_M  (PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_V << PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_M  (PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xc0)
+/** PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_M  (PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_V << PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_M  (PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_V << PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_M  (PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_V << PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_M  (PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xc4)
+/** PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_M  (PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_V << PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_M  (PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_V << PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_M  (PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_V << PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_M  (PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xc8)
+/** PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_M  (PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_V << PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_M  (PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_V << PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_M  (PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_V << PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_M  (PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xcc)
+/** PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_M  (PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_V << PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_M  (PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_V << PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_M  (PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_V << PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_M  (PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xd0)
+/** PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_M  (PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_V << PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_M  (PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_V << PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_M  (PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_V << PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_M  (PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xd4)
+/** PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_M  (PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_V << PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_S)
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_M  (PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_V << PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_M  (PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_V << PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_S  23
+/** PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_M  (PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_S)
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xd8)
+/** PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_M  (PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_V << PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_M  (PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_V << PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_M  (PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_V << PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_M  (PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xdc)
+/** PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_M  (PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_V << PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_M  (PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_V << PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_M  (PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_V << PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_M  (PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xe0)
+/** PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_M  (PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_V << PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_M  (PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_V << PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_M  (PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_V << PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_M  (PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xe4)
+/** PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_M  (PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_V << PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_S)
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_M  (PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_V << PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_M  (PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_V << PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_S  23
+/** PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_M  (PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_S)
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xe8)
+/** PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_M  (PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_V << PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_M  (PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_V << PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_M  (PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_V << PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_M  (PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xec)
+/** PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_M  (PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_V << PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_M  (PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_V << PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_M  (PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_V << PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_M  (PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xf0)
+/** PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_M  (PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_V << PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_M  (PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_V << PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_M  (PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_V << PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_M  (PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_S  31
+
+/** PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0xf4)
+/** PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3 : R/W; bitpos: [0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3    (BIT(0))
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_M  (PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_V << PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_S)
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_S  0
+/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3 : WT; bitpos: [1]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3    (BIT(1))
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_M  (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_S  1
+/** PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3 : R/W; bitpos: [9:2]; default: 20;
+ *  needs field desc
+ */
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3    0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_M  (PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_V << PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_S)
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_V  0x000000FFU
+#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_S  2
+/** PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3 : RO; bitpos: [30:23]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3    0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_M  (PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_V << PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_S)
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_V  0x000000FFU
+#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_S  23
+/** PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3 : RO; bitpos: [31]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3    (BIT(31))
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_M  (PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_S)
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_S  31
+
+/** PVT_COMB_PD_SITE0_UNIT0_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT0_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0xf8)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_M  (PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_V << PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT1_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT1_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0xfc)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_M  (PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_V << PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT2_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT2_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x100)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_M  (PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_V << PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT3_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT3_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x104)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_M  (PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_V << PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT0_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT0_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x108)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_M  (PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_V << PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT1_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT1_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x10c)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_M  (PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_V << PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT2_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT2_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x110)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_M  (PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_V << PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT3_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT3_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x114)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_M  (PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_V << PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT0_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT0_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x118)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_M  (PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_V << PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT1_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT1_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x11c)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_M  (PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_V << PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT2_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT2_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x120)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_M  (PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_V << PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE0_UNIT3_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE0_UNIT3_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x124)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_M  (PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_V << PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT0_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT0_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x128)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_M  (PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_V << PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT1_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT1_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x12c)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_M  (PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_V << PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT2_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT2_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x130)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_M  (PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_V << PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT3_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT3_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x134)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_M  (PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_V << PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT0_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT0_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x138)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_M  (PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_V << PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT1_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT1_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x13c)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_M  (PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_V << PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT2_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT2_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x140)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_M  (PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_V << PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT3_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT3_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x144)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_M  (PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_V << PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT0_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT0_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x148)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_M  (PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_V << PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT1_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT1_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x14c)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_M  (PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_V << PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT2_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT2_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x150)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_M  (PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_V << PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE1_UNIT3_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE1_UNIT3_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x154)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_M  (PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_V << PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x158)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_M  (PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_V << PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT1_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT1_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x15c)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_M  (PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_V << PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT2_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT2_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x160)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_M  (PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_V << PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT3_VT0_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT3_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x164)
+/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_S  0
+/** PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_M  (PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_V << PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_S)
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT0_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT0_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x168)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_M  (PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_V << PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT1_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT1_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x16c)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_M  (PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_V << PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT2_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT2_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x170)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_M  (PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_V << PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT3_VT1_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT3_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x174)
+/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_S  0
+/** PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_M  (PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_V << PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_S)
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x178)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_M  (PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_V << PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT1_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT1_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x17c)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_M  (PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_V << PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x180)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_M  (PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_V << PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_S  16
+
+/** PVT_COMB_PD_SITE2_UNIT3_VT2_CONF2_REG register
+ *  needs desc
+ */
+#define PVT_COMB_PD_SITE2_UNIT3_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x184)
+/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3 : R/W; bitpos: [1:0]; default: 0;
+ *  needs field desc
+ */
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3    0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_M  (PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_S)
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_V  0x00000003U
+#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_S  0
+/** PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3 : RO; bitpos: [15]; default: 0;
+ *  needs field desc
+ */
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3    (BIT(15))
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_M  (PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_V << PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_S)
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_V  0x00000001U
+#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_S  15
+/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3 : RO; bitpos: [31:16]; default: 0;
+ *  needs field desc
+ */
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3    0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_M  (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_S)
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_V  0x0000FFFFU
+#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_S  16
+
+/** PVT_DATE_REG register
+ *  version register
+ */
+#define PVT_DATE_REG (DR_REG_PVT_MONITOR_BASE + 0xffc)
+/** PVT_DATE : R/W; bitpos: [31:0]; default: 34677040;
+ *  version register
+ */
+#define PVT_DATE    0xFFFFFFFFU
+#define PVT_DATE_M  (PVT_DATE_V << PVT_DATE_S)
+#define PVT_DATE_V  0xFFFFFFFFU
+#define PVT_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h
index f0179b93a1..6ebae4676a 100644
--- a/components/soc/esp32c6/include/soc/soc_caps.h
+++ b/components/soc/esp32c6/include/soc/soc_caps.h
@@ -63,6 +63,7 @@
 #define SOC_BOD_SUPPORTED               1
 #define SOC_APM_SUPPORTED               1 /*!< Support for APM peripheral */
 #define SOC_PMU_SUPPORTED               1
+#define SOC_PMU_PVT_SUPPORTED           1
 #define SOC_PAU_SUPPORTED               1
 #define SOC_LP_TIMER_SUPPORTED          1
 #define SOC_LP_AON_SUPPORTED            1
diff --git a/components/soc/esp32c6/include/soc/system_periph_retention.h b/components/soc/esp32c6/include/soc/system_periph_retention.h
index fa93faf4e0..6709d36a69 100644
--- a/components/soc/esp32c6/include/soc/system_periph_retention.h
+++ b/components/soc/esp32c6/include/soc/system_periph_retention.h
@@ -77,6 +77,16 @@ extern const regdma_entries_config_t flash_spimem_regs_retention[SPIMEM_RETENTIO
 #define SYSTIMER_RETENTION_LINK_LEN   19
 extern const regdma_entries_config_t systimer_regs_retention[SYSTIMER_RETENTION_LINK_LEN];
 
+/**
+ * @brief Provide access to pvt configuration registers retention
+ * context definition.
+ *
+ * This is an internal function of the sleep retention driver, and is not
+ * useful for external use.
+ */
+#define PVT_RETENTION_LINK_LEN        1
+extern const regdma_entries_config_t pvt_regs_retention[PVT_RETENTION_LINK_LEN];
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32c6/system_retention_periph.c b/components/soc/esp32c6/system_retention_periph.c
index 25f1b093d3..652f0df374 100644
--- a/components/soc/esp32c6/system_retention_periph.c
+++ b/components/soc/esp32c6/system_retention_periph.c
@@ -17,6 +17,7 @@
 #include "soc/gpio_reg.h"
 #include "soc/io_mux_reg.h"
 #include "soc/interrupt_matrix_reg.h"
+#include "soc/pvt_reg.h"
 
 /* Interrupt Matrix Registers Context */
 #define N_REGS_INTR_MATRIX()    (((INTMTX_CORE0_CLOCK_GATE_REG - DR_REG_INTMTX_BASE) / 4) + 1)
@@ -113,3 +114,10 @@ const regdma_entries_config_t systimer_regs_retention[] = {
     [18] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x12), SYSTIMER_INT_ENA_REG,        SYSTIMER_INT_ENA_REG,             1,                                0, 0), .owner = ENTRY(0) | ENTRY(2) }  /* Systimer intr enable */
 };
 _Static_assert(ARRAY_SIZE(systimer_regs_retention) == SYSTIMER_RETENTION_LINK_LEN, "Inconsistent Systimer retention link length definitions");
+
+/* PVT Registers Context */
+#define N_REGS_PVT    (((PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_REG - DR_REG_PVT_MONITOR_BASE) / 4) + 1)
+const regdma_entries_config_t pvt_regs_retention[] = {
+    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PVT_LINK(0x00), DR_REG_PVT_MONITOR_BASE, DR_REG_PVT_MONITOR_BASE, N_REGS_PVT, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+};
+_Static_assert(ARRAY_SIZE(pvt_regs_retention) == PVT_RETENTION_LINK_LEN, "Inconsistent PVT retention link length definitions");
diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
index a4f2fe8530..563dd879da 100644
--- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
@@ -239,6 +239,14 @@ config SOC_PMU_PVT_SUPPORTED
     bool
     default y
 
+config SOC_PVT_EN_WITH_SLEEP
+    bool
+    default y
+
+config SOC_PVT_RETENTION_BY_REGDMA
+    bool
+    default y
+
 config SOC_DCDC_SUPPORTED
     bool
     default y
@@ -379,6 +387,10 @@ config SOC_AES_SUPPORT_AES_256
     bool
     default y
 
+config SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION
+    bool
+    default y
+
 config SOC_ADC_RTC_CTRL_SUPPORTED
     bool
     default y
@@ -1939,6 +1951,10 @@ config SOC_FLASH_ENCRYPTION_XTS_AES_256
     bool
     default y
 
+config SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND
+    bool
+    default y
+
 config SOC_UART_NUM
     int
     default 6
diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h
index 456b67b8b9..51f6612d9a 100644
--- a/components/soc/esp32p4/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -146,6 +146,8 @@ typedef enum {
     SOC_MOD_CLK_RTC_FAST,                      /*!< RTC_FAST_CLK can be sourced from XTAL, RC_FAST, or LP_PLL by configuring soc_rtc_fast_clk_src_t */
     SOC_MOD_CLK_RTC_SLOW,                      /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC32K by configuring soc_rtc_slow_clk_src_t */
     // For digital domain: peripherals
+    SOC_MOD_CLK_SYS,                           /*!< SYS_CLK is the system clock, derived from HP_ROOT clock source */
+    SOC_MOD_CLK_APB,                           /*!< APB_CLK is highly dependent on the CPU_CLK source */
     SOC_MOD_CLK_PLL_F20M,                      /*!< PLL_F20M_CLK is derived from SPLL (clock gating + default divider 24), its default frequency is 20MHz */
     SOC_MOD_CLK_PLL_F25M,                      /*!< PLL_F25M_CLK is derived from MPLL (clock gating + configurable divider), it will have a frequency of 25MHz */
     SOC_MOD_CLK_PLL_F50M,                      /*!< PLL_F50M_CLK is derived from MPLL (clock gating + configurable divider 10), it will have a frequency of 50MHz */
@@ -274,16 +276,16 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of LP_UART
  */
-#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2}
+#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL_D2}
 
 /**
  * @brief Type of LP_UART clock source
  */
 typedef enum {
-    LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST,        /*!< LP_UART source clock is LP(RTC)_FAST */
+    LP_UART_SCLK_RC_FAST = SOC_MOD_CLK_RC_FAST,         /*!< LP_UART source clock is FOSC */
     LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2,         /*!< LP_UART source clock is XTAL_D2 */
     // LP_UART_SCLK_LP_PLL  = SOC_MOD_CLK_LP_PLL,          /*!< LP_UART source clock is LP_PLL (8M PLL) */ TODO: LP_PLL clock requires extra support
-    LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST,        /*!< LP_UART source clock default choice is LP(RTC)_FAST */
+    LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RC_FAST,        /*!< LP_UART source clock default choice is FOSC */
 } soc_periph_lp_uart_clk_src_t;
 
 //////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h
index e2b4c6c008..7b8d9f0eb3 100644
--- a/components/soc/esp32p4/include/soc/soc_caps.h
+++ b/components/soc/esp32p4/include/soc/soc_caps.h
@@ -76,6 +76,8 @@
 #define SOC_APM_SUPPORTED               1
 #define SOC_PMU_SUPPORTED               1
 #define SOC_PMU_PVT_SUPPORTED           1
+#define SOC_PVT_EN_WITH_SLEEP           1
+#define SOC_PVT_RETENTION_BY_REGDMA     1
 #define SOC_DCDC_SUPPORTED              1
 #define SOC_PAU_SUPPORTED               1     //TODO: IDF-7531
 #define SOC_LP_TIMER_SUPPORTED          1
@@ -119,6 +121,8 @@
 #define SOC_AES_SUPPORT_AES_128 (1)
 #define SOC_AES_SUPPORT_AES_256 (1)
 
+#define SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION (1)
+
 /*-------------------------- ADC CAPS -------------------------------*/
 /*!< SAR ADC Module*/
 #define SOC_ADC_RTC_CTRL_SUPPORTED              1
@@ -703,8 +707,9 @@
 #define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX   (64)
 #define SOC_FLASH_ENCRYPTION_XTS_AES        1
 #define SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS 1
-#define SOC_FLASH_ENCRYPTION_XTS_AES_128    1
-#define SOC_FLASH_ENCRYPTION_XTS_AES_256    1
+#define SOC_FLASH_ENCRYPTION_XTS_AES_128    1  /* SOC_EFUSE_XTS_AES_KEY_128 (1) || SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128 (1) */
+#define SOC_FLASH_ENCRYPTION_XTS_AES_256    1  /* SOC_EFUSE_XTS_AES_KEY_256 (1) || SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256 (1) */
+#define SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND  1 /*!< Only available in chip version above 3.0 */
 /*-------------------------- MEMPROT CAPS ------------------------------------*/
 
 /*-------------------------- UART CAPS ---------------------------------------*/
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/aes_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/aes_reg.h
index 741786dbf1..7bcb4bba9e 100644
--- a/components/soc/esp32p4/register/hw_ver3/soc/aes_reg.h
+++ b/components/soc/esp32p4/register/hw_ver3/soc/aes_reg.h
@@ -12,7 +12,7 @@ extern "C" {
 #endif
 
 /** AES_KEY_0_REG register
- *  Key material key_0 configure register
+ *  AES key data register 0
  */
 #define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
 /** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
@@ -24,7 +24,7 @@ extern "C" {
 #define AES_KEY_0_S  0
 
 /** AES_KEY_1_REG register
- *  Key material key_1 configure register
+ *  AES key data register 1
  */
 #define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
 /** AES_KEY_1 : R/W; bitpos: [31:0]; default: 0;
@@ -36,7 +36,7 @@ extern "C" {
 #define AES_KEY_1_S  0
 
 /** AES_KEY_2_REG register
- *  Key material key_2 configure register
+ *  AES key data register 2
  */
 #define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
 /** AES_KEY_2 : R/W; bitpos: [31:0]; default: 0;
@@ -48,7 +48,7 @@ extern "C" {
 #define AES_KEY_2_S  0
 
 /** AES_KEY_3_REG register
- *  Key material key_3 configure register
+ *  AES key data register 3
  */
 #define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
 /** AES_KEY_3 : R/W; bitpos: [31:0]; default: 0;
@@ -60,7 +60,7 @@ extern "C" {
 #define AES_KEY_3_S  0
 
 /** AES_KEY_4_REG register
- *  Key material key_4 configure register
+ *  AES key data register 4
  */
 #define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
 /** AES_KEY_4 : R/W; bitpos: [31:0]; default: 0;
@@ -72,7 +72,7 @@ extern "C" {
 #define AES_KEY_4_S  0
 
 /** AES_KEY_5_REG register
- *  Key material key_5 configure register
+ *  AES key data register 5
  */
 #define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
 /** AES_KEY_5 : R/W; bitpos: [31:0]; default: 0;
@@ -84,7 +84,7 @@ extern "C" {
 #define AES_KEY_5_S  0
 
 /** AES_KEY_6_REG register
- *  Key material key_6 configure register
+ *  AES key data register 6
  */
 #define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
 /** AES_KEY_6 : R/W; bitpos: [31:0]; default: 0;
@@ -96,7 +96,7 @@ extern "C" {
 #define AES_KEY_6_S  0
 
 /** AES_KEY_7_REG register
- *  Key material key_7 configure register
+ *  AES key data register 7
  */
 #define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
 /** AES_KEY_7 : R/W; bitpos: [31:0]; default: 0;
@@ -108,7 +108,7 @@ extern "C" {
 #define AES_KEY_7_S  0
 
 /** AES_TEXT_IN_0_REG register
- *  source text material text_in_0 configure register
+ *  Source text data register 0
  */
 #define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
 /** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
@@ -120,7 +120,7 @@ extern "C" {
 #define AES_TEXT_IN_0_S  0
 
 /** AES_TEXT_IN_1_REG register
- *  source text material text_in_1 configure register
+ *  Source text data register 1
  */
 #define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
 /** AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0;
@@ -132,7 +132,7 @@ extern "C" {
 #define AES_TEXT_IN_1_S  0
 
 /** AES_TEXT_IN_2_REG register
- *  source text material text_in_2 configure register
+ *  Source text data register 2
  */
 #define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
 /** AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0;
@@ -144,7 +144,7 @@ extern "C" {
 #define AES_TEXT_IN_2_S  0
 
 /** AES_TEXT_IN_3_REG register
- *  source text material text_in_3 configure register
+ *  Source text data register 3
  */
 #define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
 /** AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0;
@@ -156,7 +156,7 @@ extern "C" {
 #define AES_TEXT_IN_3_S  0
 
 /** AES_TEXT_OUT_0_REG register
- *  result text material text_out_0 configure register
+ *  Result text data register 0
  */
 #define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
 /** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
@@ -168,7 +168,7 @@ extern "C" {
 #define AES_TEXT_OUT_0_S  0
 
 /** AES_TEXT_OUT_1_REG register
- *  result text material text_out_1 configure register
+ *  Result text data register 1
  */
 #define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
 /** AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0;
@@ -180,7 +180,7 @@ extern "C" {
 #define AES_TEXT_OUT_1_S  0
 
 /** AES_TEXT_OUT_2_REG register
- *  result text material text_out_2 configure register
+ *  Result text data register 2
  */
 #define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
 /** AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0;
@@ -192,7 +192,7 @@ extern "C" {
 #define AES_TEXT_OUT_2_S  0
 
 /** AES_TEXT_OUT_3_REG register
- *  result text material text_out_3 configure register
+ *  Result text data register 3
  */
 #define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
 /** AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0;
@@ -204,12 +204,19 @@ extern "C" {
 #define AES_TEXT_OUT_3_S  0
 
 /** AES_MODE_REG register
- *  AES Mode register
+ *  Defines key length and encryption / decryption
  */
 #define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
 /** AES_MODE : R/W; bitpos: [2:0]; default: 0;
- *  This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
- *  Reserved, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: Reserved, 3'd6: AES-DE-256.
+ *  Configures the key length and encryption / decryption of the AES accelerator.
+ *  0: AES-128 encryption
+ *  1: AES-192 encryption
+ *  2: AES-256 encryption
+ *  3: Reserved
+ *  4: AES-128 decryption
+ *  5: AES-192 decryption
+ *  6: AES-256 decryption
+ *  7: Reserved
  */
 #define AES_MODE    0x00000007U
 #define AES_MODE_M  (AES_MODE_V << AES_MODE_S)
@@ -230,11 +237,13 @@ extern "C" {
 #define AES_ENDIAN_S  0
 
 /** AES_TRIGGER_REG register
- *  AES trigger register
+ *  Operation start controlling register
  */
 #define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
 /** AES_TRIGGER : WT; bitpos: [0]; default: 0;
- *  Set this bit to start AES calculation.
+ *  Configures whether or not to start AES operation.
+ *  0: No effect
+ *  1: Start
  */
 #define AES_TRIGGER    (BIT(0))
 #define AES_TRIGGER_M  (AES_TRIGGER_V << AES_TRIGGER_S)
@@ -242,12 +251,21 @@ extern "C" {
 #define AES_TRIGGER_S  0
 
 /** AES_STATE_REG register
- *  AES state register
+ *  Operation status register
  */
 #define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
 /** AES_STATE : RO; bitpos: [1:0]; default: 0;
- *  Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0:
- *  idle, 1: busy, 2: calculation_done.
+ *  Represents the working status of the AES accelerator.
+ *  In Typical AES working mode:
+ *  0: IDLE
+ *  1: WORK
+ *  2: No effect
+ *  3: No effect
+ *  In DMA-AES working mode:
+ *  0: IDLE
+ *  1: WORK
+ *  2: DONE
+ *  3: No effect
  */
 #define AES_STATE    0x00000003U
 #define AES_STATE_M  (AES_STATE_V << AES_STATE_S)
@@ -279,11 +297,13 @@ extern "C" {
 #define AES_T0_MEM_SIZE_BYTES 16
 
 /** AES_DMA_ENABLE_REG register
- *  DMA-AES working mode register
+ *  Selects the working mode of the AES accelerator
  */
 #define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
 /** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
- *  1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
+ *  Configures the working mode of the AES accelerator.
+ *  0: Typical AES
+ *  1: DMA-AES
  */
 #define AES_DMA_ENABLE    (BIT(0))
 #define AES_DMA_ENABLE_M  (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
@@ -291,12 +311,20 @@ extern "C" {
 #define AES_DMA_ENABLE_S  0
 
 /** AES_BLOCK_MODE_REG register
- *  AES cipher block mode register
+ *  Defines the block cipher mode
  */
 #define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
 /** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
- *  Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB,
- *  0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
+ *  Configures the block cipher mode of the AES accelerator operating under the DMA-AES
+ *  working mode.
+ *  0: ECB (Electronic Code Block)
+ *  1: CBC (Cipher Block Chaining)
+ *  2: OFB (Output FeedBack)
+ *  3: CTR (Counter)
+ *  4: CFB8 (8-bit Cipher FeedBack)
+ *  5: CFB128 (128-bit Cipher FeedBack)
+ *  6: GCM
+ *  7: Reserved
  */
 #define AES_BLOCK_MODE    0x00000007U
 #define AES_BLOCK_MODE_M  (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
@@ -304,11 +332,12 @@ extern "C" {
 #define AES_BLOCK_MODE_S  0
 
 /** AES_BLOCK_NUM_REG register
- *  AES block number register
+ *  Block number configuration register
  */
 #define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
 /** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
- *  Those bits stores the number of Plaintext/ciphertext block.
+ *  Represents the Block Number of plaintext or ciphertext when the AES accelerator
+ *  operates under the DMA-AES working mode. For details, see Section . "
  */
 #define AES_BLOCK_NUM    0xFFFFFFFFU
 #define AES_BLOCK_NUM_M  (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
@@ -316,11 +345,13 @@ extern "C" {
 #define AES_BLOCK_NUM_S  0
 
 /** AES_INC_SEL_REG register
- *  Standard incrementing function configure register
+ *  Standard incrementing function register
  */
 #define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
 /** AES_INC_SEL : R/W; bitpos: [0]; default: 0;
- *  This bit decides the standard incrementing function. 0: INC32. 1: INC128.
+ *  Configures the Standard Incrementing Function for CTR block operation.
+ *  0: INC_32
+ *  1: INC_128
  */
 #define AES_INC_SEL    (BIT(0))
 #define AES_INC_SEL_M  (AES_INC_SEL_V << AES_INC_SEL_S)
@@ -364,11 +395,13 @@ extern "C" {
 #define AES_CONTINUE_S  0
 
 /** AES_INT_CLEAR_REG register
- *  AES Interrupt clear register
+ *  DMA-AES interrupt clear register
  */
 #define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac)
 /** AES_INT_CLEAR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the AES interrupt.
+ *  Configures whether or not to clear AES interrupt.
+ *  0: No effect
+ *  1: Clear
  */
 #define AES_INT_CLEAR    (BIT(0))
 #define AES_INT_CLEAR_M  (AES_INT_CLEAR_V << AES_INT_CLEAR_S)
@@ -376,11 +409,13 @@ extern "C" {
 #define AES_INT_CLEAR_S  0
 
 /** AES_INT_ENA_REG register
- *  AES Interrupt enable register
+ *  DMA-AES interrupt enable register
  */
 #define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
 /** AES_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
+ *  Configures whether or not to enable AES interrupt.
+ *  0: Disable
+ *  1: Enable
  */
 #define AES_INT_ENA    (BIT(0))
 #define AES_INT_ENA_M  (AES_INT_ENA_V << AES_INT_ENA_S)
@@ -391,27 +426,86 @@ extern "C" {
  *  AES version control register
  */
 #define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
-/** AES_DATE : R/W; bitpos: [29:0]; default: 538513936;
+/** AES_DATE : R/W; bitpos: [27:0]; default: 36774000;
  *  This bits stores the version information of AES.
  */
-#define AES_DATE    0x3FFFFFFFU
+#define AES_DATE    0x0FFFFFFFU
 #define AES_DATE_M  (AES_DATE_V << AES_DATE_S)
-#define AES_DATE_V  0x3FFFFFFFU
+#define AES_DATE_V  0x0FFFFFFFU
 #define AES_DATE_S  0
 
 /** AES_DMA_EXIT_REG register
- *  AES-DMA exit config
+ *  Operation exit controlling register
  */
 #define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
 /** AES_DMA_EXIT : WT; bitpos: [0]; default: 0;
- *  Set this register to leave calculation done stage. Recommend to use it after
- *  software finishes reading DMA's output buffer.
+ *  Configures whether or not to exit AES operation.
+ *  0: No effect
+ *  1: Exit
+ *  Only valid for DMA-AES operation.
  */
 #define AES_DMA_EXIT    (BIT(0))
 #define AES_DMA_EXIT_M  (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
 #define AES_DMA_EXIT_V  0x00000001U
 #define AES_DMA_EXIT_S  0
 
+/** AES_RX_RESET_REG register
+ *  AES-DMA reset rx-fifo register
+ */
+#define AES_RX_RESET_REG (DR_REG_AES_BASE + 0xc0)
+/** AES_RX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset rx_fifo under dma_aes working mode.
+ */
+#define AES_RX_RESET    (BIT(0))
+#define AES_RX_RESET_M  (AES_RX_RESET_V << AES_RX_RESET_S)
+#define AES_RX_RESET_V  0x00000001U
+#define AES_RX_RESET_S  0
+
+/** AES_TX_RESET_REG register
+ *  AES-DMA reset tx-fifo register
+ */
+#define AES_TX_RESET_REG (DR_REG_AES_BASE + 0xc4)
+/** AES_TX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset tx_fifo under dma_aes working mode.
+ */
+#define AES_TX_RESET    (BIT(0))
+#define AES_TX_RESET_M  (AES_TX_RESET_V << AES_TX_RESET_S)
+#define AES_TX_RESET_V  0x00000001U
+#define AES_TX_RESET_S  0
+
+/** AES_PSEUDO_REG register
+ *  AES PSEUDO function configure register
+ */
+#define AES_PSEUDO_REG (DR_REG_AES_BASE + 0xd0)
+/** AES_PSEUDO_EN : R/W; bitpos: [0]; default: 0;
+ *  This bit decides whether the pseudo round function is enable or not.
+ */
+#define AES_PSEUDO_EN    (BIT(0))
+#define AES_PSEUDO_EN_M  (AES_PSEUDO_EN_V << AES_PSEUDO_EN_S)
+#define AES_PSEUDO_EN_V  0x00000001U
+#define AES_PSEUDO_EN_S  0
+/** AES_PSEUDO_BASE : R/W; bitpos: [4:1]; default: 2;
+ *  Those bits decides the basic number of pseudo round number.
+ */
+#define AES_PSEUDO_BASE    0x0000000FU
+#define AES_PSEUDO_BASE_M  (AES_PSEUDO_BASE_V << AES_PSEUDO_BASE_S)
+#define AES_PSEUDO_BASE_V  0x0000000FU
+#define AES_PSEUDO_BASE_S  1
+/** AES_PSEUDO_INC : R/W; bitpos: [6:5]; default: 2;
+ *  Those bits decides the increment number of pseudo round number
+ */
+#define AES_PSEUDO_INC    0x00000003U
+#define AES_PSEUDO_INC_M  (AES_PSEUDO_INC_V << AES_PSEUDO_INC_S)
+#define AES_PSEUDO_INC_V  0x00000003U
+#define AES_PSEUDO_INC_S  5
+/** AES_PSEUDO_RNG_CNT : R/W; bitpos: [9:7]; default: 7;
+ *  Those bits decides the update frequency of the pseudo-key.
+ */
+#define AES_PSEUDO_RNG_CNT    0x00000007U
+#define AES_PSEUDO_RNG_CNT_M  (AES_PSEUDO_RNG_CNT_V << AES_PSEUDO_RNG_CNT_S)
+#define AES_PSEUDO_RNG_CNT_V  0x00000007U
+#define AES_PSEUDO_RNG_CNT_S  7
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/wpa_supplicant/esp_supplicant/src/esp_wifi_driver.h b/components/wpa_supplicant/esp_supplicant/src/esp_wifi_driver.h
index e99fd88dab..a76ff994e7 100644
--- a/components/wpa_supplicant/esp_supplicant/src/esp_wifi_driver.h
+++ b/components/wpa_supplicant/esp_supplicant/src/esp_wifi_driver.h
@@ -131,7 +131,7 @@ struct wpa_funcs {
     bool (*wpa_ap_deinit)(void *data);
     bool (*wpa_ap_join)(void **sm, u8 *bssid, u8 *wpa_ie, u8 wpa_ie_len, u8* rsnxe, u16 rsnxe_len, bool *pmf_enable, int subtype, uint8_t *pairwise_cipher);
     bool (*wpa_ap_remove)(u8 *bssid);
-    uint8_t *(*wpa_ap_get_wpa_ie)(uint8_t *len);
+    uint8_t *(*wpa_ap_get_wpa_ie)(size_t *len);
     bool (*wpa_ap_rx_eapol)(void *hapd_data, void *sm, u8 *data, size_t data_len);
     void (*wpa_ap_get_peer_spp_msg)(void *sm, bool *spp_cap, bool *spp_req);
     char *(*wpa_config_parse_string)(const char *value, size_t *len);
diff --git a/components/wpa_supplicant/esp_supplicant/src/esp_wpa_main.c b/components/wpa_supplicant/esp_supplicant/src/esp_wpa_main.c
index b0333289ad..c08cbe2925 100644
--- a/components/wpa_supplicant/esp_supplicant/src/esp_wpa_main.c
+++ b/components/wpa_supplicant/esp_supplicant/src/esp_wpa_main.c
@@ -147,7 +147,7 @@ bool  wpa_attach(void)
     return ret;
 }
 
-uint8_t  *wpa_ap_get_wpa_ie(uint8_t *ie_len)
+uint8_t  *wpa_ap_get_wpa_ie(size_t *ie_len)
 {
     struct hostapd_data *hapd = (struct hostapd_data *)esp_wifi_get_hostap_private_internal();
 
diff --git a/docs/en/get-started/establish-serial-connection.rst b/docs/en/get-started/establish-serial-connection.rst
index 235ebd863f..b171b18bf7 100644
--- a/docs/en/get-started/establish-serial-connection.rst
+++ b/docs/en/get-started/establish-serial-connection.rst
@@ -264,7 +264,9 @@ on Arch Linux this is done by adding the user to ``uucp`` group with the followi
 
     sudo usermod -a -G uucp $USER
 
-Make sure you re-login to enable read and write permissions for the serial port.
+.. note::
+
+    Make sure you re-login to enable read and write permissions for the serial port.
 
 Verify Serial Connection
 ------------------------
diff --git a/docs/zh_CN/get-started/establish-serial-connection.rst b/docs/zh_CN/get-started/establish-serial-connection.rst
index 95da7209af..5d364c9394 100644
--- a/docs/zh_CN/get-started/establish-serial-connection.rst
+++ b/docs/zh_CN/get-started/establish-serial-connection.rst
@@ -264,7 +264,9 @@ macOS::
 
     sudo usermod -a -G uucp $USER
 
-请重新登录，确保串口读写权限生效。
+.. note::
+
+    请重新登录，确保串口读写权限生效。
 
 确认串口连接
 ------------------------
diff --git a/examples/ethernet/.build-test-rules.yml b/examples/ethernet/.build-test-rules.yml
index c73718e096..db876fc715 100644
--- a/examples/ethernet/.build-test-rules.yml
+++ b/examples/ethernet/.build-test-rules.yml
@@ -4,11 +4,11 @@ examples/ethernet/basic:
   enable:
     - if: INCLUDE_DEFAULT == 1
   disable:
-    - if: IDF_TARGET in ["esp32h21", "esp32h4", "esp32p4"]
+    - if: IDF_TARGET in ["esp32h21", "esp32h4"]
       temporary: true
-      reason: not supported yet # TODO: [ESP32H21] IDF-11581 [ESP32H4] IDF-12360, IDF-14365
+      reason: not supported yet # TODO: [ESP32H21] IDF-11581 [ESP32H4] IDF-12360
   disable_test:
-    - if: IDF_TARGET not in ["esp32"]
+    - if: IDF_TARGET not in ["esp32", "esp32p4"]
       temporary: true
       reason: lack of runners
   depends_components:
@@ -21,9 +21,9 @@ examples/ethernet/basic:
 
 examples/ethernet/iperf:
   disable:
-    - if: IDF_TARGET in ["esp32h21", "esp32h4", "esp32p4"]
+    - if: IDF_TARGET in ["esp32h21", "esp32h4"]
       temporary: true
-      reason: not supported yet # TODO: [ESP32H21] IDF-11581 [ESP32H4] IDF-12360, IDF-14365
+      reason: not supported yet # TODO: [ESP32H21] IDF-11581 [ESP32H4] IDF-12360
   disable_test:
     - if: IDF_TARGET not in ["esp32", "esp32p4"]
       temporary: true
diff --git a/examples/ethernet/basic/README.md b/examples/ethernet/basic/README.md
index 2a25d912c2..76ef20af00 100644
--- a/examples/ethernet/basic/README.md
+++ b/examples/ethernet/basic/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
 
 # Ethernet Example
 (See the README.md file in the upper level 'examples' directory for more information about examples.)
diff --git a/examples/ethernet/basic/pytest_eth_basic.py b/examples/ethernet/basic/pytest_eth_basic.py
index d9109007ac..50cd18a296 100644
--- a/examples/ethernet/basic/pytest_eth_basic.py
+++ b/examples/ethernet/basic/pytest_eth_basic.py
@@ -5,19 +5,19 @@ import subprocess
 
 import pytest
 from pytest_embedded import Dut
-from pytest_embedded_idf.utils import idf_parametrize
 
 
 @pytest.mark.parametrize(
-    'config',
+    'config, target',
     [
-        pytest.param('default_ip101', marks=[pytest.mark.ethernet_router]),
-        pytest.param('default_generic', marks=[pytest.mark.ethernet_router]),
-        pytest.param('default_dm9051', marks=[pytest.mark.eth_dm9051]),
+        pytest.param('default_ip101', 'esp32', marks=[pytest.mark.ethernet_router]),
+        pytest.param('default_generic', 'esp32', marks=[pytest.mark.ethernet_router]),
+        pytest.param('default_dm9051', 'esp32', marks=[pytest.mark.eth_dm9051]),
+        pytest.param('defaults_esp32p4', 'esp32p4', marks=[pytest.mark.eth_ip101]),
+        pytest.param('defaults_esp32p4v1', 'esp32p4', marks=[pytest.mark.eth_ip101, pytest.mark.esp32p4_eco4]),
     ],
-    indirect=True,
+    indirect=['target'],
 )
-@idf_parametrize('target', ['esp32'], indirect=['target'])
 def test_esp_eth_basic(dut: Dut) -> None:
     # wait for ip received
     dut_ip = dut.expect(r'esp_netif_handlers: .+ ip: (\d+\.\d+\.\d+\.\d+),').group(1)
diff --git a/examples/ethernet/basic/sdkconfig.ci.defaults_esp32p4 b/examples/ethernet/basic/sdkconfig.ci.defaults_esp32p4
new file mode 100644
index 0000000000..3cf3a371a1
--- /dev/null
+++ b/examples/ethernet/basic/sdkconfig.ci.defaults_esp32p4
@@ -0,0 +1,4 @@
+CONFIG_IDF_TARGET="esp32p4"
+
+CONFIG_ETH_ENABLED=y
+CONFIG_ETH_USE_ESP32_EMAC=y
diff --git a/examples/ethernet/basic/sdkconfig.ci.defaults_esp32p4v1 b/examples/ethernet/basic/sdkconfig.ci.defaults_esp32p4v1
new file mode 100644
index 0000000000..5548711301
--- /dev/null
+++ b/examples/ethernet/basic/sdkconfig.ci.defaults_esp32p4v1
@@ -0,0 +1,5 @@
+CONFIG_IDF_TARGET="esp32p4"
+CONFIG_ESP32P4_SELECTS_REV_LESS_V3=y
+
+CONFIG_ETH_ENABLED=y
+CONFIG_ETH_USE_ESP32_EMAC=y
diff --git a/examples/ethernet/iperf/README.md b/examples/ethernet/iperf/README.md
index 806c86337d..4f609030b2 100644
--- a/examples/ethernet/iperf/README.md
+++ b/examples/ethernet/iperf/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
 
 # Ethernet iperf Example
 
diff --git a/examples/ethernet/iperf/pytest_eth_iperf.py b/examples/ethernet/iperf/pytest_eth_iperf.py
index 0d5b758be6..36fcc53b35 100644
--- a/examples/ethernet/iperf/pytest_eth_iperf.py
+++ b/examples/ethernet/iperf/pytest_eth_iperf.py
@@ -134,16 +134,14 @@ def test_esp_eth_iperf_ip101(
     test_esp_eth_iperf(dut, log_performance, check_performance, udp_tx_bw_lim=90)
 
 
-@pytest.mark.eth_ip101
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14365')
 @pytest.mark.parametrize(
-    'config',
+    'config, target',
     [
-        'default_ip101_esp32p4',
+        pytest.param('default_ip101_esp32p4', 'esp32p4', marks=[pytest.mark.eth_ip101]),
+        pytest.param('default_ip101_esp32p4v1', 'esp32p4', marks=[pytest.mark.eth_ip101, pytest.mark.esp32p4_eco4]),
     ],
-    indirect=True,
+    indirect=['target'],
 )
-@idf_parametrize('target', ['esp32p4'], indirect=['target'])
 def test_esp_eth_iperf_ip101_esp32p4(
     dut: Dut,
     log_performance: Callable[[str, object], None],
diff --git a/examples/ethernet/iperf/sdkconfig.ci.default_ip101_esp32p4v1 b/examples/ethernet/iperf/sdkconfig.ci.default_ip101_esp32p4v1
new file mode 100644
index 0000000000..d41a943f92
--- /dev/null
+++ b/examples/ethernet/iperf/sdkconfig.ci.default_ip101_esp32p4v1
@@ -0,0 +1,50 @@
+CONFIG_IDF_TARGET="esp32p4"
+CONFIG_ESP32P4_SELECTS_REV_LESS_V3=y
+
+# Increase main task stack size
+CONFIG_ESP_MAIN_TASK_STACK_SIZE=7168
+
+# Enable filesystem for console commands history storage
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_PARTITION_TABLE_CUSTOM=y
+CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions_example.csv"
+CONFIG_PARTITION_TABLE_FILENAME="partitions_example.csv"
+
+# Enable FreeRTOS stats formatting functions, needed for 'tasks' command
+CONFIG_FREERTOS_USE_TRACE_FACILITY=y
+CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS=y
+
+# --------------------------------
+# Performance optimization options
+# --------------------------------
+# The lwIP and iperf tasks have a serial dependency (i.e., iperf must wait for lwIP to process packets),
+# meaning that running in multi-core mode does not significantly improve performance. Additionally,
+# IRAM optimizations have a more noticeable effect in single-core mode.
+# However, while a single-core configuration can enhance iperf performance in controlled or isolated
+# testing scenarios, it may not be optimal for real-world applications where the system also needs to
+# handle additional, non-network-related tasks. In such cases, multi-core configurations might be better
+# suited for balancing workloads and ensuring overall system responsiveness.
+
+# Run FreeRTOS only on the first core
+CONFIG_FREERTOS_UNICORE=y
+
+# Disable watch dog
+CONFIG_ESP_INT_WDT=n
+CONFIG_ESP_TASK_WDT_EN=n
+
+# Enable lwIP IRAM optimization
+CONFIG_LWIP_IRAM_OPTIMIZATION=y
+
+# Enable Ethernet IRAM optimization
+CONFIG_ETH_IRAM_OPTIMIZATION=y
+
+CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET=y
+CONFIG_EXAMPLE_ETH_PHY_IP101=y
+CONFIG_EXAMPLE_ETH_MDC_GPIO=31
+CONFIG_EXAMPLE_ETH_MDIO_GPIO=52
+CONFIG_EXAMPLE_ETH_PHY_RST_GPIO=51
+CONFIG_EXAMPLE_ETH_PHY_ADDR=1
+
+CONFIG_ETH_ENABLED=y
+CONFIG_ETH_USE_ESP32_EMAC=y
+CONFIG_ETH_PHY_INTERFACE_RMII=y
diff --git a/examples/peripherals/isp/multi_pipelines/main/isp_dsi_main.c b/examples/peripherals/isp/multi_pipelines/main/isp_dsi_main.c
index b84532617d..6a3df077fa 100644
--- a/examples/peripherals/isp/multi_pipelines/main/isp_dsi_main.c
+++ b/examples/peripherals/isp/multi_pipelines/main/isp_dsi_main.c
@@ -441,7 +441,9 @@ void app_main(void)
     }
 
     ESP_ERROR_CHECK(esp_cam_ctlr_enable(handle));
-    //---------------ISP Init------------------//
+    /*---------------------------------------------------------------
+                          ISP Init
+    ---------------------------------------------------------------*/
     isp_proc_handle_t isp_proc = NULL;
     esp_isp_processor_cfg_t isp_config = {
         .clk_hz = 80 * 1000 * 1000,
@@ -456,6 +458,9 @@ void app_main(void)
     ESP_ERROR_CHECK(esp_isp_new_processor(&isp_config, &isp_proc));
     ESP_ERROR_CHECK(esp_isp_enable(isp_proc));
 
+    /*---------------------------------------------------------------
+                          BF
+    ---------------------------------------------------------------*/
     esp_isp_bf_config_t bf_config = {
         .denoising_level = 5,
         .padding_mode = ISP_BF_EDGE_PADDING_MODE_SRND_DATA,
@@ -470,6 +475,9 @@ void app_main(void)
     ESP_ERROR_CHECK(esp_isp_bf_configure(isp_proc, &bf_config));
     ESP_ERROR_CHECK(esp_isp_bf_enable(isp_proc));
 
+    /*---------------------------------------------------------------
+                          BLC
+    ---------------------------------------------------------------*/
 #if CONFIG_ESP32P4_REV_MIN_FULL >= 300
     /**
      * This piece of BLC code is to show how to use the BLC related APIs.
@@ -513,6 +521,9 @@ void app_main(void)
     ESP_ERROR_CHECK(esp_isp_blc_set_correction_offset(isp_proc, &blc_offset));
 #endif
 
+    /*---------------------------------------------------------------
+                          DEMOSAIC
+    ---------------------------------------------------------------*/
     esp_isp_demosaic_config_t demosaic_config = {
         .grad_ratio = {
             .integer = 2,
@@ -522,6 +533,38 @@ void app_main(void)
     ESP_ERROR_CHECK(esp_isp_demosaic_configure(isp_proc, &demosaic_config));
     ESP_ERROR_CHECK(esp_isp_demosaic_enable(isp_proc));
 
+    /*---------------------------------------------------------------
+                          CCM
+    ---------------------------------------------------------------*/
+    /**
+     * CCM is used for color correction and white balance adjustment.
+     * It should be configured after demosaic and before gamma correction.
+     *
+     * The matrix format is:
+     * [R_out]   [RR RG RB] [R_in]
+     * [G_out] = [GR GG GB] [G_in]
+     * [B_out]   [BR BG BB] [B_in]
+     *
+     * For ESP32P4 ECO5:
+     * - Matrix coefficients range: ±15.996 (4-bit integer + 8-bit fraction)
+     * - For earlier versions: ±3.999 (2-bit integer + 10-bit fraction)
+     */
+    esp_isp_ccm_config_t ccm_config = {
+        .matrix = {
+            // Default identity matrix (no color correction)
+            {1.0, 0.0, 0.0},   // R channel: R = 1.0*R + 0.0*G + 0.0*B
+            {0.0, 1.0, 0.0},   // G channel: G = 0.0*R + 1.0*G + 0.0*B
+            {0.0, 0.0, 1.0}    // B channel: B = 0.0*R + 0.0*G + 1.0*B
+        },
+        .saturation = false        // Don't use saturation for out-of-range values
+    };
+
+    ESP_ERROR_CHECK(esp_isp_ccm_configure(isp_proc, &ccm_config));
+    ESP_ERROR_CHECK(esp_isp_ccm_enable(isp_proc));
+
+    /*---------------------------------------------------------------
+                          GAMMA
+    ---------------------------------------------------------------*/
     isp_gamma_curve_points_t pts = {};
     ESP_ERROR_CHECK(esp_isp_gamma_fill_curve_points(s_gamma_correction_curve, &pts));
     ESP_ERROR_CHECK(esp_isp_gamma_configure(isp_proc, COLOR_COMPONENT_R, &pts));
@@ -529,6 +572,9 @@ void app_main(void)
     ESP_ERROR_CHECK(esp_isp_gamma_configure(isp_proc, COLOR_COMPONENT_B, &pts));
     ESP_ERROR_CHECK(esp_isp_gamma_enable(isp_proc));
 
+    /*---------------------------------------------------------------
+                          SHARPEN
+    ---------------------------------------------------------------*/
     esp_isp_sharpen_config_t sharpen_config = {
         .h_freq_coeff = {
             .integer = 2,
@@ -552,6 +598,9 @@ void app_main(void)
     ESP_ERROR_CHECK(esp_isp_sharpen_configure(isp_proc, &sharpen_config));
     ESP_ERROR_CHECK(esp_isp_sharpen_enable(isp_proc));
 
+    /*---------------------------------------------------------------
+                          COLOR
+    ---------------------------------------------------------------*/
     esp_isp_color_config_t color_config = {
         .color_contrast = {
             .integer = 1,
@@ -568,6 +617,9 @@ void app_main(void)
     ESP_ERROR_CHECK(esp_isp_color_enable(isp_proc));
 
 #if CONFIG_ESP32P4_REV_MIN_FULL >= 100
+    /*---------------------------------------------------------------
+                          LSC
+    ---------------------------------------------------------------*/
     esp_isp_lsc_gain_array_t gain_array = {};
     esp_isp_lsc_config_t lsc_config = {
         .gain_array = &gain_array,
diff --git a/examples/protocols/sockets/udp_multicast/pytest_udp_multicast.py b/examples/protocols/sockets/udp_multicast/pytest_udp_multicast.py
index 2f7a14bdf1..cc7fe4f53e 100644
--- a/examples/protocols/sockets/udp_multicast/pytest_udp_multicast.py
+++ b/examples/protocols/sockets/udp_multicast/pytest_udp_multicast.py
@@ -11,7 +11,6 @@ import netifaces
 import pytest
 from common_test_methods import get_host_ip4_by_dest_ip
 from pytest_embedded import Dut
-from pytest_embedded_idf.utils import idf_parametrize
 
 PORT = 3333
 IPV6_REGEX = (
@@ -156,10 +155,12 @@ def test_examples_udp_multicast_proto(dut: Dut, ip_version: str = 'ipv4', nic: s
     sock.close()
 
 
-@pytest.mark.eth_ip101
-@idf_parametrize(
-    'target',
-    ['esp32', 'esp32p4'],
+@pytest.mark.parametrize(
+    'config, target',
+    [
+        pytest.param('default_ip101', 'esp32', marks=[pytest.mark.eth_ip101]),
+        pytest.param('default_ip101_esp32p4', 'esp32p4', marks=[pytest.mark.eth_ip101]),
+    ],
     indirect=['target'],
 )
 def test_examples_udp_multicast(dut: Dut) -> None:
diff --git a/examples/system/heap_task_tracking/advanced/README.md b/examples/system/heap_task_tracking/advanced/README.md
index ca8fe744d4..60184556e5 100644
--- a/examples/system/heap_task_tracking/advanced/README.md
+++ b/examples/system/heap_task_tracking/advanced/README.md
@@ -1,7 +1,7 @@
 | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
 | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
 
-# Heap Task Tracking Basic Example
+# Heap Task Tracking Advanced Example
 
 ## Overview
 
@@ -10,7 +10,7 @@ The main then goes into a loop calling functions retrieving statistics for the "
 For each tasks, the following information is retrieved and printed:
     - the task name
     - the task status (running or deleted)
-    - the overall peak memory usage of the task 
+    - the overall peak memory usage of the task
     - the overall current memory usage of the task
 For each heap used by a given task, the following information is printed:
     - the heap name
diff --git a/examples/wifi/espnow/main/espnow_example_main.c b/examples/wifi/espnow/main/espnow_example_main.c
index 61dfb55e14..b43a381496 100644
--- a/examples/wifi/espnow/main/espnow_example_main.c
+++ b/examples/wifi/espnow/main/espnow_example_main.c
@@ -363,7 +363,7 @@ static esp_err_t example_espnow_init(void)
     memcpy(send_param->dest_mac, s_example_broadcast_mac, ESP_NOW_ETH_ALEN);
     example_espnow_data_prepare(send_param);
 
-    xTaskCreate(example_espnow_task, "example_espnow_task", 2048, send_param, 4, NULL);
+    xTaskCreate(example_espnow_task, "example_espnow_task", 2560, send_param, 4, NULL);
 
     return ESP_OK;
 }
diff --git a/tools/cmake/project.cmake b/tools/cmake/project.cmake
index 72504c061c..1194687d0b 100644
--- a/tools/cmake/project.cmake
+++ b/tools/cmake/project.cmake
@@ -503,6 +503,7 @@ function(__project_init components_var test_components_var)
         if(DEFINED COMPONENTS)
             message(WARNING "The MINIMAL_BUILD property is disregarded because the COMPONENTS variable is defined.")
             set(minimal_build OFF)
+            idf_build_set_property(MINIMAL_BUILD OFF)
         else()
             set(COMPONENTS main ${TEST_COMPONENTS})
             set(minimal_build ON)
diff --git a/tools/ldgen/ldgen/generation.py b/tools/ldgen/ldgen/generation.py
index 945884981f..794149aec8 100644
--- a/tools/ldgen/ldgen/generation.py
+++ b/tools/ldgen/ldgen/generation.py
@@ -1,5 +1,5 @@
 #
-# SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Apache-2.0
 #
 import collections
@@ -83,11 +83,13 @@ class Placement:
         #
         # Placement can also be a basis if it has flags
         # (self.flags) or its basis has flags (self.basis.flags)
-        significant = (not self.basis or
-                       self.target != self.basis.target or
-                       (self.flags and not self.basis.flags) or
-                       (not self.flags and self.basis.flags) or
-                       self.force)
+        significant = (
+            not self.basis
+            or self.target != self.basis.target
+            or (self.flags and not self.basis.flags)
+            or (not self.flags and self.basis.flags)
+            or self.force
+        )
 
         if significant and not self.explicit and not self.sections:
             # The placement is significant, but it is an intermediate placement
@@ -155,7 +157,7 @@ class EntityNode:
         assert name and name != Entity.ALL
 
         child = [c for c in self.children if c.name == name]
-        assert (len(child) <= 1)
+        assert len(child) <= 1
 
         if not child:
             child = self.child_t(self, name)
@@ -169,7 +171,7 @@ class EntityNode:
         commands = collections.defaultdict(list)
 
         def process_commands(cmds):
-            for (target, commands_list) in cmds.items():
+            for target, commands_list in cmds.items():
                 commands[target].extend(commands_list)
 
         # Process the commands generated from this node
@@ -221,16 +223,28 @@ class EntityNode:
                 placement_sections = frozenset(placement.sections)
                 command_sections = sections if sections == placement_sections else placement_sections
 
-                command = InputSectionDesc(placement.node.entity, command_sections,
-                                           [e.node.entity for e in placement.exclusions], keep, sort, tied)
+                command = InputSectionDesc(
+                    placement.node.entity,
+                    command_sections,
+                    [e.node.entity for e in placement.exclusions],
+                    keep,
+                    sort,
+                    tied,
+                )
                 commands[placement.target].append(command)
 
                 # Generate commands for intermediate, non-explicit exclusion placements here,
                 # so that they can be enclosed by flags that affect the parent placement.
                 for subplacement in placement.subplacements:
                     if not subplacement.flags and not subplacement.explicit:
-                        command = InputSectionDesc(subplacement.node.entity, subplacement.sections,
-                                                   [e.node.entity for e in subplacement.exclusions], keep, sort, tied)
+                        command = InputSectionDesc(
+                            subplacement.node.entity,
+                            subplacement.sections,
+                            [e.node.entity for e in subplacement.exclusions],
+                            keep,
+                            sort,
+                            tied,
+                        )
                         commands[placement.target].append(command)
 
                 for flag in surround_type:
@@ -319,7 +333,20 @@ class ObjectNode(EntityNode):
 
             if obj_sections:
                 symbol = entity.symbol
-                remove_sections = [s.replace('.*', '.%s' % symbol) for s in sections if '.*' in s]
+                remove_sections = [s.replace('.*', f'.{symbol}') for s in sections if '.*' in s]
+                # As part of IPA optimization, the compiler may perform
+                # constant propagation and generate specialized versions of a
+                # function. For example, for the function spiflash_start_core,
+                # the compiler might also generate a
+                # spiflash_start_core.constprop.0 symbol, which will be placed
+                # in a separate input section named
+                # .text.spiflash_start_core.constprop.0. Ensure that such
+                # generated functions are placed into the appropriate marker as
+                # well.
+                remove_sections_patterns = [s.replace('.*', f'.{symbol}.*') for s in sections if '.*' in s]
+                for pattern in remove_sections_patterns:
+                    remove_sections.extend(fnmatch.filter(obj_sections, pattern))
+
                 filtered_sections = [s for s in obj_sections if s not in remove_sections]
 
                 if set(filtered_sections) != set(obj_sections):
@@ -404,7 +431,7 @@ class Generation:
         for scheme in self.schemes.values():
             sections_bucket = collections.defaultdict(list)
 
-            for (sections_name, target_name) in scheme.entries:
+            for sections_name, target_name in scheme.entries:
                 # Get the sections under the bucket 'target_name'. If this bucket does not exist
                 # is created automatically
                 sections_in_bucket = sections_bucket[target_name]
@@ -420,7 +447,7 @@ class Generation:
             scheme_dictionary[scheme.name] = sections_bucket
 
         # Search for and raise exception on first instance of sections mapped to multiple targets
-        for (scheme_name, sections_bucket) in scheme_dictionary.items():
+        for scheme_name, sections_bucket in scheme_dictionary.items():
             for sections_a, sections_b in itertools.combinations(sections_bucket.values(), 2):
                 set_a = set()
                 set_b = set()
@@ -453,15 +480,17 @@ class Generation:
         for mapping in self.mappings.values():
             archive = mapping.archive
 
-            for (obj, symbol, scheme_name) in mapping.entries:
+            for obj, symbol, scheme_name in mapping.entries:
                 entity = Entity(archive, obj, symbol)
 
                 # Check the entity exists
-                if (self.check_mappings
-                        and entity.specificity.value > Entity.Specificity.ARCHIVE.value
-                        and mapping.name not in self.check_mapping_exceptions):
+                if (
+                    self.check_mappings
+                    and entity.specificity.value > Entity.Specificity.ARCHIVE.value
+                    and mapping.name not in self.check_mapping_exceptions
+                ):
                     if not entities.check_exists(entity):
-                        message = "'%s' not found" % str(entity)
+                        message = f"'{entity}' not found"
                         raise GenerationException(message, mapping)
 
                 if (obj, symbol, scheme_name) in mapping.flags.keys():
@@ -469,16 +498,16 @@ class Generation:
                     # Check if all section->target defined in the current
                     # scheme.
                     for flag in flags:
-                        if (flag.target not in scheme_dictionary[scheme_name].keys()
-                                or flag.section not in
-                                [_s.name for _s in scheme_dictionary[scheme_name][flag.target]]):
-                            message = "%s->%s not defined in scheme '%s'" % (flag.section, flag.target, scheme_name)
+                        if flag.target not in scheme_dictionary[scheme_name].keys() or flag.section not in [
+                            _s.name for _s in scheme_dictionary[scheme_name][flag.target]
+                        ]:
+                            message = f"{flag.section}->{flag.target} not defined in scheme '{scheme_name}'"
                             raise GenerationException(message, mapping)
                 else:
                     flags = None
 
                 # Create placement for each 'section -> target' in the scheme.
-                for (target, sections) in scheme_dictionary[scheme_name].items():
+                for target, sections in scheme_dictionary[scheme_name].items():
                     for section in sections:
                         # Find the applicable flags
                         _flags = []
@@ -509,9 +538,9 @@ class Generation:
                             if _flags or existing.flags:
                                 if (_flags and not existing.flags) or (not _flags and existing.flags):
                                     _flags.extend(existing.flags)
-                                    entity_mappings[key] = Generation.EntityMapping(entity,
-                                                                                    sections_str,
-                                                                                    target, _flags)
+                                    entity_mappings[key] = Generation.EntityMapping(
+                                        entity, sections_str, target, _flags
+                                    )
                                 elif _flags == existing.flags:
                                     pass
                                 else:
@@ -552,8 +581,7 @@ class Generation:
             if fragment.name in dict_to_append_to:
                 stored = dict_to_append_to[fragment.name].path
                 new = fragment.path
-                message = "Duplicate definition of fragment '%s' found in %s and %s." % (
-                    fragment.name, stored, new)
+                message = f"Duplicate definition of fragment '{fragment.name}' found in {stored} and {new}."
                 raise GenerationException(message)
 
             dict_to_append_to[fragment.name] = fragment
@@ -573,6 +601,6 @@ class GenerationException(LdGenFailure):
 
     def __str__(self):
         if self.fragment:
-            return "%s\nIn fragment '%s' defined in '%s'." % (self.message, self.fragment.name, self.fragment.path)
+            return f"{self.message}\nIn fragment '{self.fragment.name}' defined in '{self.fragment.path}'."
         else:
             return self.message
diff --git a/tools/ldgen/test/data/libspi_flash.a.txt b/tools/ldgen/test/data/libspi_flash.a.txt
new file mode 100644
index 0000000000..3b626cfcb9
--- /dev/null
+++ b/tools/ldgen/test/data/libspi_flash.a.txt
@@ -0,0 +1,1242 @@
+In archive ./build/esp-idf/spi_flash/libspi_flash.a:
+
+flash_brownout_hook.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .text.spi_flash_needs_reset_check 00000020  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  4 .text.spi_flash_set_erasing_flag 0000000a  00000000  00000000  00000054  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  5 .text.spi_flash_brownout_need_reset 00000014  00000000  00000000  0000005e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  6 .sbss.flash_erasing 00000001  00000000  00000000  00000072  2**0
+                  ALLOC
+  7 .sbss.flash_brownout_needs_reset 00000001  00000000  00000000  00000072  2**0
+                  ALLOC
+  8 .debug_info   000001eb  00000000  00000000  00000072  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+  9 .debug_abbrev 0000012a  00000000  00000000  0000025d  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 10 .debug_aranges 00000030  00000000  00000000  00000387  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 11 .debug_ranges 00000020  00000000  00000000  000003b7  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 12 .debug_line   0000024b  00000000  00000000  000003d7  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 13 .debug_str    00000406  00000000  00000000  00000622  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 14 .comment      00000030  00000000  00000000  00000a28  2**0
+                  CONTENTS, READONLY
+ 15 .note.GNU-stack 00000000  00000000  00000000  00000a58  2**0
+                  CONTENTS, READONLY
+ 16 .debug_frame  00000040  00000000  00000000  00000a58  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 17 .riscv.attributes 00000065  00000000  00000000  00000a98  2**0
+                  CONTENTS, READONLY
+
+spi_flash_chip_drivers.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .rodata.spi_flash_chip_list_check.str1.4 000000c5  00000000  00000000  00000034  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  4 .text.spi_flash_chip_list_check 00000144  00000000  00000000  000000fa  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  5 .sdata.esp_flash_registered_chips 00000004  00000000  00000000  00000240  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, DATA
+  6 .data.default_registered_chips 00000010  00000000  00000000  00000244  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, DATA
+  7 .debug_info   00000f1b  00000000  00000000  00000254  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+  8 .debug_abbrev 00000258  00000000  00000000  0000116f  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+  9 .debug_loc    00000113  00000000  00000000  000013c7  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 10 .debug_aranges 00000020  00000000  00000000  000014da  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 11 .debug_ranges 00000010  00000000  00000000  000014fa  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 12 .debug_line   00000784  00000000  00000000  0000150a  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 13 .debug_str    00000b95  00000000  00000000  00001c8e  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 14 .comment      00000030  00000000  00000000  00002823  2**0
+                  CONTENTS, READONLY
+ 15 .note.GNU-stack 00000000  00000000  00000000  00002853  2**0
+                  CONTENTS, READONLY
+ 16 .debug_frame  00000038  00000000  00000000  00002854  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 17 .riscv.attributes 00000065  00000000  00000000  0000288c  2**0
+                  CONTENTS, READONLY
+
+spi_flash_chip_generic.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .text.spi_flash_chip_generic_detect_size 00000032  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  4 .text.spi_flash_chip_generic_probe 00000004  00000000  00000000  00000066  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  5 .text.spi_flash_chip_generic_reset 00000060  00000000  00000000  0000006a  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  6 .text.spi_flash_chip_generic_erase_chip 00000088  00000000  00000000  000000ca  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  7 .text.spi_flash_chip_generic_set_write_protect 0000004c  00000000  00000000  00000152  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  8 .text.spi_flash_chip_generic_read_reg 0000000a  00000000  00000000  0000019e  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  9 .text.spi_flash_chip_generic_wait_idle 000000a4  00000000  00000000  000001a8  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 10 .text.spi_flash_chip_generic_config_host_io_mode 0000013e  00000000  00000000  0000024c  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 11 .text.spi_flash_chip_generic_get_caps 00000086  00000000  00000000  0000038a  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 12 .text.spi_flash_chip_generic_suspend_cmd_conf 00000024  00000000  00000000  00000410  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+ 13 .rodata.spi_flash_chip_generic_read.str1.4 00000039  00000000  00000000  00000434  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 14 .text.spi_flash_chip_generic_read 000000ec  00000000  00000000  0000046e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 15 .text.spi_flash_chip_generic_write 000000b6  00000000  00000000  0000055a  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 16 .text.spi_flash_chip_generic_yield 0000004a  00000000  00000000  00000610  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 17 .rodata.spi_flash_chip_generic_read_unique_id.str1.4 00000048  00000000  00000000  0000065c  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 18 .text.spi_flash_chip_generic_read_unique_id 000000b0  00000000  00000000  000006a4  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 19 .text.spi_flash_chip_generic_get_write_protect 0000003a  00000000  00000000  00000754  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 20 .text.spi_flash_chip_generic_write_encrypted 000000f4  00000000  00000000  0000078e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 21 .text.spi_flash_common_read_qe_sr.constprop.0.isra.0 00000048  00000000  00000000  00000882  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 22 .text.spi_flash_common_read_status_16b_rdsr_rdsr2 00000048  00000000  00000000  000008ca  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 23 .text.spi_flash_common_write_qe_sr.isra.0 00000046  00000000  00000000  00000912  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 24 .text.spi_flash_common_write_status_16b_wrsr 00000010  00000000  00000000  00000958  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 25 .text.spi_flash_chip_generic_erase_block 000000cc  00000000  00000000  00000968  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 26 .text.spi_flash_chip_generic_erase_sector 000000cc  00000000  00000000  00000a34  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 27 .text.spi_flash_chip_generic_page_program 000000ba  00000000  00000000  00000b00  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 28 .text.spi_flash_chip_generic_read_unique_id_none 00000006  00000000  00000000  00000bba  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+ 29 .text.spi_flash_common_read_status_8b_rdsr2 00000010  00000000  00000000  00000bc0  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 30 .text.spi_flash_chip_generic_get_io_mode 00000024  00000000  00000000  00000bd0  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 31 .text.spi_flash_common_read_status_8b_rdsr 0000000e  00000000  00000000  00000bf4  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 32 .text.spi_flash_common_write_status_8b_wrsr 00000010  00000000  00000000  00000c02  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 33 .text.spi_flash_common_write_status_8b_wrsr2 00000012  00000000  00000000  00000c12  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 34 .text.spi_flash_common_set_io_mode 000000a2  00000000  00000000  00000c24  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 35 .text.spi_flash_chip_generic_set_io_mode 0000001c  00000000  00000000  00000cc6  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 36 .rodata.esp_flash_chip_generic 0000007c  00000000  00000000  00000ce4  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+ 37 .srodata.chip_name 00000008  00000000  00000000  00000d60  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 38 .rodata.TAG   0000000d  00000000  00000000  00000d68  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 39 .dram1.5      00000014  00000000  00000000  00000d78  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 40 .dram1.4      00000018  00000000  00000000  00000d8c  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, DATA
+ 41 .dram1.3      00000004  00000000  00000000  00000da4  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, DATA
+ 42 .dram1.2      00000004  00000000  00000000  00000da8  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, DATA
+ 43 .dram1.1      00000006  00000000  00000000  00000dac  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 44 .dram1.0      00000006  00000000  00000000  00000db4  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 45 .debug_info   00003096  00000000  00000000  00000dba  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 46 .debug_abbrev 00000616  00000000  00000000  00003e50  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 47 .debug_loc    00002153  00000000  00000000  00004466  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 48 .debug_aranges 00000110  00000000  00000000  000065b9  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 49 .debug_ranges 000001f0  00000000  00000000  000066c9  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 50 .debug_line   000024e8  00000000  00000000  000068b9  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 51 .debug_str    0000240c  00000000  00000000  00008da1  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 52 .comment      00000030  00000000  00000000  0000b1ad  2**0
+                  CONTENTS, READONLY
+ 53 .note.GNU-stack 00000000  00000000  00000000  0000b1dd  2**0
+                  CONTENTS, READONLY
+ 54 .debug_frame  00000484  00000000  00000000  0000b1e0  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 55 .riscv.attributes 00000065  00000000  00000000  0000b664  2**0
+                  CONTENTS, READONLY
+
+spi_flash_chip_issi.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .text.spi_flash_chip_issi_probe 00000018  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  4 .text.spi_flash_chip_issi_get_caps 00000004  00000000  00000000  0000004c  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  5 .text.spi_flash_chip_issi_set_io_mode 0000001c  00000000  00000000  00000050  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  6 .text.spi_flash_chip_issi_get_io_mode 00000024  00000000  00000000  0000006c  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  7 .rodata.esp_flash_chip_issi 0000007c  00000000  00000000  00000090  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+  8 .srodata.chip_name 00000005  00000000  00000000  0000010c  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  9 .debug_info   0000103d  00000000  00000000  00000111  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 10 .debug_abbrev 00000260  00000000  00000000  0000114e  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 11 .debug_loc    00000124  00000000  00000000  000013ae  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 12 .debug_aranges 00000038  00000000  00000000  000014d2  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 13 .debug_ranges 00000028  00000000  00000000  0000150a  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 14 .debug_line   0000043f  00000000  00000000  00001532  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 15 .debug_str    00000d47  00000000  00000000  00001971  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 16 .comment      00000030  00000000  00000000  000026b8  2**0
+                  CONTENTS, READONLY
+ 17 .note.GNU-stack 00000000  00000000  00000000  000026e8  2**0
+                  CONTENTS, READONLY
+ 18 .debug_frame  00000060  00000000  00000000  000026e8  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 19 .riscv.attributes 00000065  00000000  00000000  00002748  2**0
+                  CONTENTS, READONLY
+
+spi_flash_chip_mxic.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .text.spi_flash_chip_mxic_probe 00000022  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  4 .text.spi_flash_chip_mxic_detect_size 00000034  00000000  00000000  00000056  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  5 .text.spi_flash_chip_mxic_get_caps 00000004  00000000  00000000  0000008a  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  6 .rodata.esp_flash_chip_mxic 0000007c  00000000  00000000  00000090  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+  7 .srodata.chip_name 00000005  00000000  00000000  0000010c  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  8 .debug_info   0000137d  00000000  00000000  00000111  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+  9 .debug_abbrev 00000229  00000000  00000000  0000148e  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 10 .debug_loc    00000165  00000000  00000000  000016b7  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 11 .debug_aranges 00000030  00000000  00000000  0000181c  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 12 .debug_ranges 00000020  00000000  00000000  0000184c  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 13 .debug_line   0000053d  00000000  00000000  0000186c  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 14 .debug_str    00001acb  00000000  00000000  00001da9  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 15 .comment      00000030  00000000  00000000  00003874  2**0
+                  CONTENTS, READONLY
+ 16 .note.GNU-stack 00000000  00000000  00000000  000038a4  2**0
+                  CONTENTS, READONLY
+ 17 .debug_frame  00000040  00000000  00000000  000038a4  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 18 .riscv.attributes 00000065  00000000  00000000  000038e4  2**0
+                  CONTENTS, READONLY
+
+spi_flash_chip_gd.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .text.spi_flash_chip_gd_get_caps 00000014  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  4 .text.spi_flash_chip_gd_detect_size 00000026  00000000  00000000  00000048  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  5 .text.spi_flash_chip_gd_suspend_cmd_conf 00000024  00000000  00000000  0000006e  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  6 .text.spi_flash_chip_gd_get_io_mode 00000024  00000000  00000000  00000092  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  7 .text.spi_flash_chip_gd_probe 0000003c  00000000  00000000  000000b6  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  8 .text.spi_flash_chip_gd_set_io_mode 00000050  00000000  00000000  000000f2  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  9 .rodata.esp_flash_chip_gd 0000007c  00000000  00000000  00000144  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+ 10 .srodata.chip_name 00000003  00000000  00000000  000001c0  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 11 .debug_info   000011c7  00000000  00000000  000001c3  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 12 .debug_abbrev 00000333  00000000  00000000  0000138a  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 13 .debug_loc    00000300  00000000  00000000  000016bd  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 14 .debug_aranges 00000048  00000000  00000000  000019bd  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 15 .debug_ranges 00000068  00000000  00000000  00001a05  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 16 .debug_line   0000060a  00000000  00000000  00001a6d  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 17 .debug_str    00000ddc  00000000  00000000  00002077  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 18 .comment      00000030  00000000  00000000  00002e53  2**0
+                  CONTENTS, READONLY
+ 19 .note.GNU-stack 00000000  00000000  00000000  00002e83  2**0
+                  CONTENTS, READONLY
+ 20 .debug_frame  0000008c  00000000  00000000  00002e84  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 21 .riscv.attributes 00000065  00000000  00000000  00002f10  2**0
+                  CONTENTS, READONLY
+
+spi_flash_chip_winbond.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .text.spi_flash_chip_winbond_probe 00000012  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  4 .text.spi_flash_chip_winbond_get_caps 00000014  00000000  00000000  00000046  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  5 .text.spi_flash_chip_winbond_suspend_cmd_conf 00000024  00000000  00000000  0000005a  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  6 .rodata.spi_flash_chip_winbond_read.str1.4 00000039  00000000  00000000  00000080  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  7 .text.spi_flash_chip_winbond_read 000000ec  00000000  00000000  000000ba  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  8 .text.spi_flash_chip_winbond_erase_block 000000e6  00000000  00000000  000001a6  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  9 .text.spi_flash_chip_winbond_erase_sector 000000e2  00000000  00000000  0000028c  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 10 .text.spi_flash_chip_winbond_page_program 000000b4  00000000  00000000  0000036e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 11 .rodata.esp_flash_chip_winbond 0000007c  00000000  00000000  00000424  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+ 12 .srodata.chip_name 00000008  00000000  00000000  000004a0  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 13 .srodata.TAG  00000008  00000000  00000000  000004a8  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 14 .debug_info   00001764  00000000  00000000  000004b0  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 15 .debug_abbrev 000003c5  00000000  00000000  00001c14  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 16 .debug_loc    000009ea  00000000  00000000  00001fd9  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 17 .debug_aranges 00000050  00000000  00000000  000029c3  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 18 .debug_ranges 00000078  00000000  00000000  00002a13  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 19 .debug_line   00000d8c  00000000  00000000  00002a8b  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 20 .debug_str    00000eb0  00000000  00000000  00003817  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 21 .comment      00000030  00000000  00000000  000046c7  2**0
+                  CONTENTS, READONLY
+ 22 .note.GNU-stack 00000000  00000000  00000000  000046f7  2**0
+                  CONTENTS, READONLY
+ 23 .debug_frame  00000150  00000000  00000000  000046f8  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 24 .riscv.attributes 00000065  00000000  00000000  00004848  2**0
+                  CONTENTS, READONLY
+
+spi_flash_chip_boya.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .text.spi_flash_chip_boya_probe 00000014  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  4 .text.spi_flash_chip_boya_get_caps 00000004  00000000  00000000  00000048  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  5 .rodata.esp_flash_chip_boya 0000007c  00000000  00000000  0000004c  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+  6 .srodata.chip_name 00000005  00000000  00000000  000000c8  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  7 .debug_info   00000f04  00000000  00000000  000000cd  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+  8 .debug_abbrev 000001f8  00000000  00000000  00000fd1  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+  9 .debug_loc    00000081  00000000  00000000  000011c9  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 10 .debug_aranges 00000028  00000000  00000000  0000124a  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 11 .debug_ranges 00000018  00000000  00000000  00001272  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 12 .debug_line   00000384  00000000  00000000  0000128a  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 13 .debug_str    00000ca6  00000000  00000000  0000160e  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 14 .comment      00000030  00000000  00000000  000022b4  2**0
+                  CONTENTS, READONLY
+ 15 .note.GNU-stack 00000000  00000000  00000000  000022e4  2**0
+                  CONTENTS, READONLY
+ 16 .debug_frame  00000030  00000000  00000000  000022e4  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 17 .riscv.attributes 00000065  00000000  00000000  00002314  2**0
+                  CONTENTS, READONLY
+
+spi_flash_chip_mxic_opi.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .text.spi_flash_chip_mxic_opi_probe 00000020  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  4 .text.spi_flash_chip_mxic_opi_detect_size 0000002c  00000000  00000000  00000054  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  5 .text.spi_flash_chip_mxic_opi_get_caps 00000004  00000000  00000000  00000080  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  6 .text.spi_flash_chip_mxic_opi_set_write_protect 00000074  00000000  00000000  00000084  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  7 .text.spi_flash_chip_mxic_opi_erase_chip 00000086  00000000  00000000  000000f8  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  8 .text.spi_flash_chip_mxic_opi_erase_sector 00000090  00000000  00000000  0000017e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  9 .text.spi_flash_chip_mxic_opi_erase_block 00000090  00000000  00000000  0000020e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 10 .text.spi_flash_chip_xmic_opi_set_io_mode 00000004  00000000  00000000  0000029e  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+ 11 .text.spi_flash_chip_xmic_opi_config_host_io_mode 0000003a  00000000  00000000  000002a2  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 12 .text.spi_flash_chip_mxic_opi_write 000000b6  00000000  00000000  000002dc  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 13 .text.spi_flash_chip_mxic_opi_page_program 00000098  00000000  00000000  00000392  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 14 .text.spi_flash_chip_mxic_opi_get_data_length_zoom.part.0 00000014  00000000  00000000  0000042a  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 15 .rodata.spi_flash_chip_mxic_opi_read_id.str1.4 0000001a  00000000  00000000  00000440  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 16 .text.spi_flash_chip_mxic_opi_read_id 000000fa  00000000  00000000  0000045a  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 17 .text.spi_flash_chip_mxic_opi_get_write_protect 00000034  00000000  00000000  00000554  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 18 .text.spi_flash_chip_mxic_opi_get_io_mode 00000094  00000000  00000000  00000588  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 19 .text.spi_flash_chip_mxic_opi_read_reg 00000074  00000000  00000000  0000061c  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 20 .rodata.esp_flash_chip_mxic_opi 0000007c  00000000  00000000  00000690  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+ 21 .rodata.chip_name 0000000b  00000000  00000000  0000070c  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 22 .debug_info   00001fa4  00000000  00000000  00000717  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 23 .debug_abbrev 000004d6  00000000  00000000  000026bb  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 24 .debug_loc    00000efe  00000000  00000000  00002b91  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 25 .debug_aranges 00000098  00000000  00000000  00003a8f  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 26 .debug_ranges 00000130  00000000  00000000  00003b27  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 27 .debug_line   0000144a  00000000  00000000  00003c57  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 28 .debug_str    00001d92  00000000  00000000  000050a1  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 29 .comment      00000030  00000000  00000000  00006e33  2**0
+                  CONTENTS, READONLY
+ 30 .note.GNU-stack 00000000  00000000  00000000  00006e63  2**0
+                  CONTENTS, READONLY
+ 31 .debug_frame  00000248  00000000  00000000  00006e64  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 32 .riscv.attributes 00000065  00000000  00000000  000070ac  2**0
+                  CONTENTS, READONLY
+
+spi_flash_chip_th.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .text.spi_flash_chip_th_probe 00000014  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  4 .text.spi_flash_chip_th_get_caps 00000004  00000000  00000000  00000048  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  5 .rodata.esp_flash_chip_th 0000007c  00000000  00000000  0000004c  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+  6 .srodata.chip_name 00000003  00000000  00000000  000000c8  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  7 .debug_info   00000f04  00000000  00000000  000000cb  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+  8 .debug_abbrev 000001f8  00000000  00000000  00000fcf  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+  9 .debug_loc    00000081  00000000  00000000  000011c7  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 10 .debug_aranges 00000028  00000000  00000000  00001248  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 11 .debug_ranges 00000018  00000000  00000000  00001270  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 12 .debug_line   00000382  00000000  00000000  00001288  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 13 .debug_str    00000c9e  00000000  00000000  0000160a  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 14 .comment      00000030  00000000  00000000  000022a8  2**0
+                  CONTENTS, READONLY
+ 15 .note.GNU-stack 00000000  00000000  00000000  000022d8  2**0
+                  CONTENTS, READONLY
+ 16 .debug_frame  00000030  00000000  00000000  000022d8  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 17 .riscv.attributes 00000065  00000000  00000000  00002308  2**0
+                  CONTENTS, READONLY
+
+memspi_host_driver.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .text.memspi_host_read_status_hs 00000046  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  4 .text.memspi_host_erase_chip 00000030  00000000  00000000  0000007a  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  5 .text.memspi_host_set_write_protect 0000003c  00000000  00000000  000000aa  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  6 .text.memspi_host_write_data_slicer 0000003e  00000000  00000000  000000e6  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  7 .text.memspi_host_read_data_slicer 00000032  00000000  00000000  00000124  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  8 .rodata.memspi_host_read_id_hs.str1.4 0000001a  00000000  00000000  00000158  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  9 .text.memspi_host_read_id_hs 0000009c  00000000  00000000  00000172  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 10 .text.memspi_host_flush_cache 0000002a  00000000  00000000  0000020e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 11 .text.memspi_host_erase_sector.part.0 00000014  00000000  00000000  00000238  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 12 .text.memspi_host_erase_sector 0000004e  00000000  00000000  0000024c  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 13 .text.memspi_host_erase_block 0000004e  00000000  00000000  0000029a  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 14 .text.memspi_host_program_page 00000060  00000000  00000000  000002e8  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 15 .text.memspi_host_init_pointers 00000042  00000000  00000000  00000348  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 16 .text.memspi_host_read 0000004e  00000000  00000000  0000038a  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 17 .srodata.TAG  00000007  00000000  00000000  000003d8  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 18 .rodata.esp_flash_gpspi_host 00000058  00000000  00000000  000003e0  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+ 19 .dram1.0      00000058  00000000  00000000  00000438  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+ 20 .debug_info   00004863  00000000  00000000  00000490  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 21 .debug_abbrev 000004f3  00000000  00000000  00004cf3  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 22 .debug_loc    00000b18  00000000  00000000  000051e6  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 23 .debug_aranges 00000080  00000000  00000000  00005cfe  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 24 .debug_ranges 00000088  00000000  00000000  00005d7e  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 25 .debug_line   00000f72  00000000  00000000  00005e06  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 26 .debug_str    00003945  00000000  00000000  00006d78  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 27 .comment      00000030  00000000  00000000  0000a6bd  2**0
+                  CONTENTS, READONLY
+ 28 .note.GNU-stack 00000000  00000000  00000000  0000a6ed  2**0
+                  CONTENTS, READONLY
+ 29 .debug_frame  0000019c  00000000  00000000  0000a6f0  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 30 .riscv.attributes 00000065  00000000  00000000  0000a88c  2**0
+                  CONTENTS, READONLY
+
+spi_flash_blockdev.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .text.esp_flash_blockdev_ioctl 00000010  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  4 .text.esp_flash_blockdev_sync_noop 0000000e  00000000  00000000  00000044  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  5 .text.esp_flash_release_blockdev 0000001c  00000000  00000000  00000052  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  6 .text.esp_flash_blockdev_erase 00000020  00000000  00000000  0000006e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  7 .text.esp_flash_blockdev_write 00000034  00000000  00000000  0000008e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  8 .text.esp_flash_blockdev_read 00000030  00000000  00000000  000000c2  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  9 .text.esp_flash_get_blockdev 0000008c  00000000  00000000  000000f2  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 10 .rodata.esp_flash_blockdev_ops 00000018  00000000  00000000  00000180  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+ 11 .debug_info   0000131a  00000000  00000000  00000198  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 12 .debug_abbrev 000002aa  00000000  00000000  000014b2  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 13 .debug_loc    00000741  00000000  00000000  0000175c  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 14 .debug_aranges 00000050  00000000  00000000  00001e9d  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 15 .debug_ranges 00000040  00000000  00000000  00001eed  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 16 .debug_line   00000781  00000000  00000000  00001f2d  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 17 .debug_str    00000c80  00000000  00000000  000026ae  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 18 .comment      00000030  00000000  00000000  0000332e  2**0
+                  CONTENTS, READONLY
+ 19 .note.GNU-stack 00000000  00000000  00000000  0000335e  2**0
+                  CONTENTS, READONLY
+ 20 .debug_frame  000000a8  00000000  00000000  00003360  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 21 .riscv.attributes 00000065  00000000  00000000  00003408  2**0
+                  CONTENTS, READONLY
+
+cache_utils.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .iram1.6      00000038  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  4 .text.spi_flash_init_lock 00000002  00000000  00000000  0000006c  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  5 .text.spi_flash_op_lock 00000008  00000000  00000000  0000006e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  6 .text.spi_flash_op_unlock 00000008  00000000  00000000  00000076  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  7 .iram1.1      00000020  00000000  00000000  0000007e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  8 .iram1.3      00000018  00000000  00000000  0000009e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  9 .iram1.4      00000008  00000000  00000000  000000b6  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 10 .iram1.5      00000012  00000000  00000000  000000be  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 11 .iram1.0      0000002a  00000000  00000000  000000d0  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 12 .iram1.2      00000022  00000000  00000000  000000fa  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 13 .iram1.7      0000000c  00000000  00000000  0000011c  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 14 .sbss.s_flash_op_cache_state 00000008  00000000  00000000  00000128  2**2
+                  ALLOC
+ 15 .debug_info   0000051b  00000000  00000000  00000128  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 16 .debug_abbrev 0000026e  00000000  00000000  00000643  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 17 .debug_loc    0000010b  00000000  00000000  000008b1  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 18 .debug_aranges 00000078  00000000  00000000  000009bc  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 19 .debug_ranges 00000068  00000000  00000000  00000a34  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 20 .debug_line   00000688  00000000  00000000  00000a9c  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 21 .debug_str    0000060d  00000000  00000000  00001124  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 22 .comment      00000030  00000000  00000000  00001731  2**0
+                  CONTENTS, READONLY
+ 23 .note.GNU-stack 00000000  00000000  00000000  00001761  2**0
+                  CONTENTS, READONLY
+ 24 .debug_frame  00000118  00000000  00000000  00001764  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 25 .riscv.attributes 00000069  00000000  00000000  0000187c  2**0
+                  CONTENTS, READONLY
+
+flash_mmap.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .text.s_find_non_contiguous_block_nums 0000002a  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  4 .text.s_pages_to_bytes 00000018  00000000  00000000  0000005e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  5 .text.s_merge_contiguous_pages 00000066  00000000  00000000  00000076  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  6 .iram1.0      00000050  00000000  00000000  000000dc  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  7 .text.spi_flash_mmap 000000c6  00000000  00000000  0000012c  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  8 .text.spi_flash_mmap_pages 0000013c  00000000  00000000  000001f2  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  9 .text.spi_flash_munmap 0000005e  00000000  00000000  0000032e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 10 .text.spi_flash_mmap_dump 00000010  00000000  00000000  0000038c  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 11 .text.spi_flash_mmap_get_free_pages 00000028  00000000  00000000  0000039c  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 12 .iram1.1      00000076  00000000  00000000  000003c4  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 13 .text.spi_flash_cache2phys 00000028  00000000  00000000  0000043a  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 14 .text.spi_flash_phys2cache 0000003e  00000000  00000000  00000462  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 15 .debug_info   00000f32  00000000  00000000  000004a0  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 16 .debug_abbrev 000003a9  00000000  00000000  000013d2  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 17 .debug_loc    00000e0b  00000000  00000000  0000177b  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 18 .debug_aranges 00000078  00000000  00000000  00002586  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 19 .debug_ranges 00000148  00000000  00000000  000025fe  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 20 .debug_line   00001069  00000000  00000000  00002746  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 21 .debug_str    000008aa  00000000  00000000  000037af  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 22 .comment      00000030  00000000  00000000  00004059  2**0
+                  CONTENTS, READONLY
+ 23 .note.GNU-stack 00000000  00000000  00000000  00004089  2**0
+                  CONTENTS, READONLY
+ 24 .debug_frame  000001d8  00000000  00000000  0000408c  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 25 .riscv.attributes 00000065  00000000  00000000  00004264  2**0
+                  CONTENTS, READONLY
+
+flash_ops.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .iram1.2      0000000a  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  4 .iram1.3      0000000a  00000000  00000000  0000003e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  5 .iram1.4      00000002  00000000  00000000  00000048  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  6 .iram1.5      00000004  00000000  00000000  0000004a  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  7 .iram1.6      00000002  00000000  00000000  0000004e  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  8 .text.esp_mspi_get_io 0000002a  00000000  00000000  00000050  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  9 .text.esp_mspi_pin_reserve 0000005c  00000000  00000000  0000007a  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 10 .iram1.7      00000004  00000000  00000000  000000d6  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+ 11 .srodata.s_mspi_io_num_default 00000006  00000000  00000000  000000dc  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 12 .sbss.s_flash_guard_ops 00000004  00000000  00000000  000000e4  2**2
+                  ALLOC
+ 13 .dram1.1      00000008  00000000  00000000  000000e4  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+ 14 .dram1.0      00000008  00000000  00000000  000000ec  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+ 15 .debug_info   0000039f  00000000  00000000  000000f4  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 16 .debug_abbrev 00000279  00000000  00000000  00000493  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 17 .debug_loc    000000ec  00000000  00000000  0000070c  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 18 .debug_aranges 00000058  00000000  00000000  000007f8  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 19 .debug_ranges 00000068  00000000  00000000  00000850  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 20 .debug_line   000004f4  00000000  00000000  000008b8  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 21 .debug_str    0000061d  00000000  00000000  00000dac  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 22 .comment      00000030  00000000  00000000  000013c9  2**0
+                  CONTENTS, READONLY
+ 23 .note.GNU-stack 00000000  00000000  00000000  000013f9  2**0
+                  CONTENTS, READONLY
+ 24 .debug_frame  000000bc  00000000  00000000  000013fc  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 25 .riscv.attributes 00000065  00000000  00000000  000014b8  2**0
+                  CONTENTS, READONLY
+
+spi_flash_wrap.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .text.spi_flash_wrap_probe_c0 00000014  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  4 .text.spi_flash_wrap_enable_c0 00000032  00000000  00000000  00000048  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  5 .text.spi_flash_wrap_enable_77 0000004e  00000000  00000000  0000007a  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  6 .text.spi_flash_wrap_clear_c0 00000024  00000000  00000000  000000c8  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  7 .text.spi_flash_wrap_clear_77 0000003e  00000000  00000000  000000ec  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  8 .text.spi_flash_wrap_probe 0000003e  00000000  00000000  0000012a  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  9 .text.spi_flash_wrap_enable 0000000c  00000000  00000000  00000168  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 10 .text.spi_flash_wrap_disable 0000000c  00000000  00000000  00000174  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 11 .rodata.spi_flash_support_wrap_size.str1.4 00000042  00000000  00000000  00000180  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 12 .text.spi_flash_support_wrap_size 00000074  00000000  00000000  000001c2  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 13 .sbss.chip_wrap 00000004  00000000  00000000  00000238  2**2
+                  ALLOC
+ 14 .rodata.str1.4 00000010  00000000  00000000  00000238  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 15 .rodata.spi_flash_wrap_list 00000020  00000000  00000000  00000248  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+ 16 .debug_info   00000b4c  00000000  00000000  00000268  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 17 .debug_abbrev 000002c5  00000000  00000000  00000db4  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 18 .debug_loc    0000026a  00000000  00000000  00001079  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 19 .debug_aranges 00000060  00000000  00000000  000012e3  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 20 .debug_ranges 00000050  00000000  00000000  00001343  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 21 .debug_line   000007f4  00000000  00000000  00001393  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 22 .debug_str    0000153f  00000000  00000000  00001b87  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 23 .comment      00000030  00000000  00000000  000030c6  2**0
+                  CONTENTS, READONLY
+ 24 .note.GNU-stack 00000000  00000000  00000000  000030f6  2**0
+                  CONTENTS, READONLY
+ 25 .debug_frame  000000fc  00000000  00000000  000030f8  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 26 .riscv.attributes 00000065  00000000  00000000  000031f4  2**0
+                  CONTENTS, READONLY
+
+esp_flash_api.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .text.spiflash_end_default 00000022  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  4 .text.flash_end_flush_cache 00000064  00000000  00000000  00000056  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  5 .text.read_unique_id 00000042  00000000  00000000  000000ba  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  6 .text.find_region 00000058  00000000  00000000  000000fc  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  7 .text.spiflash_start_core.constprop.0 0000002c  00000000  00000000  00000154  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  8 .text.spiflash_start_default 00000008  00000000  00000000  00000180  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  9 .text.esp_flash_chip_driver_initialized 00000008  00000000  00000000  00000188  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+ 10 .text.check_chip_pointer_default 00000036  00000000  00000000  00000190  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 11 .rodata.detect_spi_flash_chip.str1.4 0000001f  00000000  00000000  000001c8  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 12 .text.detect_spi_flash_chip 000000b6  00000000  00000000  000001e8  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 13 .iram1.3      00000096  00000000  00000000  0000029e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 14 .text.esp_flash_read_chip_id 0000000a  00000000  00000000  00000334  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 15 .text.esp_flash_read_id 0000003e  00000000  00000000  0000033e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 16 .rodata.esp_flash_read_unique_chip_id.str1.4 0000007b  00000000  00000000  0000037c  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 17 .text.esp_flash_read_unique_chip_id 000000ac  00000000  00000000  000003f8  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 18 .text.esp_flash_get_physical_size 00000066  00000000  00000000  000004a4  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 19 .rodata.esp_flash_init.str1.4 000000b2  00000000  00000000  0000050c  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 20 .text.esp_flash_init 00000188  00000000  00000000  000005be  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 21 .text.esp_flash_init_main 000001be  00000000  00000000  00000746  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 22 .text.esp_flash_get_size 0000003c  00000000  00000000  00000904  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 23 .text.esp_flash_erase_region 00000200  00000000  00000000  00000940  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 24 .rodata.esp_flash_erase_chip.str1.4 0000003d  00000000  00000000  00000b40  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 25 .text.esp_flash_erase_chip 00000064  00000000  00000000  00000b7e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 26 .text.esp_flash_get_chip_write_protect 00000058  00000000  00000000  00000be2  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 27 .text.esp_flash_set_chip_write_protect 00000050  00000000  00000000  00000c3a  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 28 .text.esp_flash_get_protectable_regions 0000004c  00000000  00000000  00000c8a  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 29 .text.esp_flash_get_protected_region 000000a2  00000000  00000000  00000cd6  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 30 .text.esp_flash_set_protected_region 000000b0  00000000  00000000  00000d78  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 31 .text.esp_flash_read 00000122  00000000  00000000  00000e28  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 32 .text.esp_flash_write 000001a8  00000000  00000000  00000f4a  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 33 .text.esp_flash_read_encrypted 00000090  00000000  00000000  000010f2  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 34 .text.esp_flash_get_io_mode 00000062  00000000  00000000  00001182  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 35 .text.esp_flash_set_io_mode 00000054  00000000  00000000  000011e4  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 36 .text.esp_flash_write_encrypted 0000025e  00000000  00000000  00001238  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 37 .rodata.esp_flash_suspend_cmd_init.str1.4 000000c0  00000000  00000000  00001498  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 38 .text.esp_flash_suspend_cmd_init 000000c0  00000000  00000000  00001558  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 39 .text.esp_flash_app_disable_protect 0000001c  00000000  00000000  00001618  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 40 .dram1.13     0000001b  00000000  00000000  00001634  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 41 .dram1.11     00000021  00000000  00000000  00001650  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 42 .dram1.9      0000003b  00000000  00000000  00001674  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 43 .dram1.7      0000003e  00000000  00000000  000016b0  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 44 .dram1.5      0000001b  00000000  00000000  000016f0  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 45 .dram1.2      00000004  00000000  00000000  0000170c  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, DATA
+ 46 .dram1.1      00000010  00000000  00000000  00001710  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, DATA
+ 47 .rodata.io_mode_str 000000b4  00000000  00000000  00001720  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 48 .dram1.0      0000000a  00000000  00000000  000017d4  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 49 .debug_info   0000519c  00000000  00000000  000017de  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 50 .debug_abbrev 0000063c  00000000  00000000  0000697a  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 51 .debug_loc    00002432  00000000  00000000  00006fb6  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 52 .debug_aranges 00000118  00000000  00000000  000093e8  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 53 .debug_ranges 00000318  00000000  00000000  00009500  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 54 .debug_line   00003c0e  00000000  00000000  00009818  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 55 .debug_str    00003475  00000000  00000000  0000d426  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 56 .comment      00000030  00000000  00000000  0001089b  2**0
+                  CONTENTS, READONLY
+ 57 .note.GNU-stack 00000000  00000000  00000000  000108cb  2**0
+                  CONTENTS, READONLY
+ 58 .debug_frame  00000580  00000000  00000000  000108cc  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 59 .riscv.attributes 00000065  00000000  00000000  00010e4c  2**0
+                  CONTENTS, READONLY
+
+esp_flash_spi_init.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .text.use_bus_lock 00000006  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  4 .text.bus_using_iomux 00000072  00000000  00000000  0000003a  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  5 .text.cs_using_iomux 0000003e  00000000  00000000  000000ac  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  6 .text.get_host_id_from_chip 0000002a  00000000  00000000  000000ea  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  7 .rodata.acquire_spi_device.str1.4 00000087  00000000  00000000  00000114  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  8 .text.acquire_spi_device 000000f8  00000000  00000000  0000019c  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  9 .iram1.0      00000132  00000000  00000000  00000294  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 10 .text.deinit_gpspi_clock 0000005c  00000000  00000000  000003c6  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 11 .text.s_spi_find_clock_src_pre_div.constprop.0 00000034  00000000  00000000  00000422  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 12 .text.init_gpspi_clock 000000ce  00000000  00000000  00000456  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 13 .text.spi_bus_remove_flash_device 00000050  00000000  00000000  00000524  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 14 .text.spi_bus_add_flash_device 00000154  00000000  00000000  00000574  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 15 .rodata.esp_flash_init_default_chip.str1.4 00000124  00000000  00000000  000006c8  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 16 .text.esp_flash_init_default_chip 000001ca  00000000  00000000  000007ec  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 17 .text.esp_flash_app_init 00000030  00000000  00000000  000009b6  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 18 .rodata.__FUNCTION__.0 0000001c  00000000  00000000  000009e8  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 19 .dram1.2      00000024  00000000  00000000  00000a04  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, DATA
+ 20 .dram1.1      00000030  00000000  00000000  00000a28  2**2
+                  CONTENTS, ALLOC, LOAD, DATA
+ 21 .sbss.esp_flash_default_chip 00000004  00000000  00000000  00000a58  2**2
+                  ALLOC
+ 22 .rodata.TAG   0000000a  00000000  00000000  00000a58  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 23 .debug_info   0000b318  00000000  00000000  00000a62  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 24 .debug_abbrev 00000732  00000000  00000000  0000bd7a  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 25 .debug_loc    00000a1d  00000000  00000000  0000c4ac  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 26 .debug_aranges 00000080  00000000  00000000  0000cec9  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 27 .debug_ranges 00000158  00000000  00000000  0000cf49  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 28 .debug_line   00001ae5  00000000  00000000  0000d0a1  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 29 .debug_str    000076a1  00000000  00000000  0000eb86  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 30 .comment      00000030  00000000  00000000  00016227  2**0
+                  CONTENTS, READONLY
+ 31 .note.GNU-stack 00000000  00000000  00000000  00016257  2**0
+                  CONTENTS, READONLY
+ 32 .debug_frame  000001d8  00000000  00000000  00016258  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 33 .riscv.attributes 00000065  00000000  00000000  00016430  2**0
+                  CONTENTS, READONLY
+
+spi_flash_os_func_app.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .text.use_bus_lock 00000006  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  4 .text.spi_flash_os_yield 00000034  00000000  00000000  0000003a  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  5 .text.spi_flash_os_check_yield 00000062  00000000  00000000  0000006e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  6 .text.release_buffer_malloc 0000000a  00000000  00000000  000000d0  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  7 .text.get_buffer_malloc 00000054  00000000  00000000  000000da  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  8 .text.delay_us 00000016  00000000  00000000  0000012e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  9 .iram1.3      0000000a  00000000  00000000  00000144  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 10 .text.spi23_end 0000002a  00000000  00000000  0000014e  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 11 .iram1.2      00000032  00000000  00000000  00000178  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 12 .text.spi23_start 00000008  00000000  00000000  000001aa  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 13 .text.main_flash_op_status 0000000a  00000000  00000000  000001b2  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 14 .text.main_flash_region_protected 00000046  00000000  00000000  000001bc  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 15 .iram1.1      00000008  00000000  00000000  00000202  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 16 .iram1.4      00000016  00000000  00000000  0000020a  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 17 .iram1.0      00000008  00000000  00000000  00000220  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 18 .iram1.5      00000024  00000000  00000000  00000228  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 19 .text.esp_flash_init_os_functions 00000084  00000000  00000000  0000024c  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 20 .text.esp_flash_deinit_os_functions 0000002c  00000000  00000000  000002d0  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 21 .text.esp_flash_init_main_bus_lock 00000006  00000000  00000000  000002fc  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+ 22 .text.esp_flash_app_enable_os_functions 00000032  00000000  00000000  00000302  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 23 .text.esp_flash_set_dangerous_write_protection 0000001a  00000000  00000000  00000334  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 24 .rodata.esp_flash_spi23_default_os_functions 00000028  00000000  00000000  00000350  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+ 25 .dram1.7      00000028  00000000  00000000  00000378  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+ 26 .dram1.6      00000014  00000000  00000000  000003a0  2**2
+                  CONTENTS, ALLOC, LOAD, DATA
+ 27 .debug_info   0000148e  00000000  00000000  000003b4  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 28 .debug_abbrev 000004a9  00000000  00000000  00001842  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 29 .debug_loc    00000a2e  00000000  00000000  00001ceb  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 30 .debug_aranges 000000c0  00000000  00000000  00002719  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 31 .debug_ranges 000000c8  00000000  00000000  000027d9  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 32 .debug_line   00000f25  00000000  00000000  000028a1  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 33 .debug_str    00000d86  00000000  00000000  000037c6  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 34 .comment      00000030  00000000  00000000  0000454c  2**0
+                  CONTENTS, READONLY
+ 35 .note.GNU-stack 00000000  00000000  00000000  0000457c  2**0
+                  CONTENTS, READONLY
+ 36 .debug_frame  00000238  00000000  00000000  0000457c  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 37 .riscv.attributes 00000065  00000000  00000000  000047b4  2**0
+                  CONTENTS, READONLY
+
+spi_flash_os_func_noos.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .text.delay_us 00000016  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  4 .iram1.1      00000022  00000000  00000000  0000004a  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  5 .iram1.0      00000022  00000000  00000000  0000006c  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  6 .text.get_temp_buffer_not_supported 00000004  00000000  00000000  0000008e  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  7 .text.esp_flash_app_disable_os_functions 0000000e  00000000  00000000  00000092  2**1
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  8 .dram1.2      00000028  00000000  00000000  000000a0  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+  9 .debug_info   00000aa8  00000000  00000000  000000c8  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 10 .debug_abbrev 00000293  00000000  00000000  00000b70  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 11 .debug_loc    0000012d  00000000  00000000  00000e03  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 12 .debug_aranges 00000040  00000000  00000000  00000f30  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 13 .debug_ranges 00000050  00000000  00000000  00000f70  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 14 .debug_line   000005b4  00000000  00000000  00000fc0  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 15 .debug_str    000008a4  00000000  00000000  00001574  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 16 .comment      00000030  00000000  00000000  00001e18  2**0
+                  CONTENTS, READONLY
+ 17 .note.GNU-stack 00000000  00000000  00000000  00001e48  2**0
+                  CONTENTS, READONLY
+ 18 .debug_frame  00000084  00000000  00000000  00001e48  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+ 19 .riscv.attributes 00000069  00000000  00000000  00001ecc  2**0
+                  CONTENTS, READONLY
+
+spi_flash_freq_limit.c.obj:     file format elf32-little
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00000000  00000000  00000000  00000034  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000000  00000000  00000000  00000034  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000000  00000000  00000000  00000034  2**0
+                  ALLOC
+  3 .debug_info   00000079  00000000  00000000  00000034  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+  4 .debug_abbrev 00000026  00000000  00000000  000000ad  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+  5 .debug_aranges 00000018  00000000  00000000  000000d3  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+  6 .debug_line   00000072  00000000  00000000  000000eb  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING, OCTETS
+  7 .debug_str    000002ac  00000000  00000000  0000015d  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+  8 .comment      00000030  00000000  00000000  00000409  2**0
+                  CONTENTS, READONLY
+  9 .note.GNU-stack 00000000  00000000  00000000  00000439  2**0
+                  CONTENTS, READONLY
+ 10 .riscv.attributes 00000065  00000000  00000000  00000439  2**0
+                  CONTENTS, READONLY
diff --git a/tools/ldgen/test/test_generation.py b/tools/ldgen/test/test_generation.py
index 209621d83d..b4ea0588c2 100755
--- a/tools/ldgen/test/test_generation.py
+++ b/tools/ldgen/test/test_generation.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python
 #
-# SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Apache-2.0
 #
 import collections
@@ -12,19 +12,27 @@ import unittest
 from io import StringIO
 
 try:
-    from ldgen.entity import Entity, EntityDB
+    from ldgen.entity import Entity
+    from ldgen.entity import EntityDB
     from ldgen.fragments import parse_fragment_file
-    from ldgen.generation import Generation, GenerationException
+    from ldgen.generation import Generation
+    from ldgen.generation import GenerationException
     from ldgen.linker_script import LinkerScript
-    from ldgen.output_commands import AlignAtAddress, InputSectionDesc, SymbolAtAddress
+    from ldgen.output_commands import AlignAtAddress
+    from ldgen.output_commands import InputSectionDesc
+    from ldgen.output_commands import SymbolAtAddress
     from ldgen.sdkconfig import SDKConfig
 except ImportError:
     sys.path.append(os.path.dirname(os.path.dirname(__file__)))
-    from ldgen.entity import Entity, EntityDB
+    from ldgen.entity import Entity
+    from ldgen.entity import EntityDB
     from ldgen.fragments import parse_fragment_file
-    from ldgen.generation import Generation, GenerationException
+    from ldgen.generation import Generation
+    from ldgen.generation import GenerationException
     from ldgen.linker_script import LinkerScript
-    from ldgen.output_commands import AlignAtAddress, InputSectionDesc, SymbolAtAddress
+    from ldgen.output_commands import AlignAtAddress
+    from ldgen.output_commands import InputSectionDesc
+    from ldgen.output_commands import SymbolAtAddress
     from ldgen.sdkconfig import SDKConfig
 
 ROOT = Entity('*')
@@ -33,12 +41,12 @@ FREERTOS = Entity('libfreertos.a')
 CROUTINE = Entity('libfreertos.a', 'croutine')
 TIMERS = Entity('libfreertos.a', 'timers')
 TEMPERATURE_SENSOR_PERIPH = Entity('libsoc.a', 'temperature_sensor_periph')
+ESP_FLASH_API = Entity('libspi_flash.a', 'esp_flash_api')
 
 FREERTOS2 = Entity('libfreertos2.a')
 
 
 class GenerationTest(unittest.TestCase):
-
     def setUp(self):
         self.generation = Generation()
         self.entities = None
@@ -72,6 +80,9 @@ class GenerationTest(unittest.TestCase):
         with open('data/libsoc.a.txt') as objdump:
             self.entities.add_sections_info(objdump)
 
+        with open('data/libspi_flash.a.txt') as objdump:
+            self.entities.add_sections_info(objdump)
+
         with open('data/linker_script.ld') as linker_script:
             self.linker_script_expect = LinkerScript(linker_script)
 
@@ -121,7 +132,6 @@ class GenerationTest(unittest.TestCase):
 
 
 class DefaultMappingTest(GenerationTest):
-
     def test_rule_generation_default(self):
         # Checks that default rules are generated from
         # the default scheme properly and even if no mappings
@@ -134,7 +144,7 @@ class DefaultMappingTest(GenerationTest):
     def test_default_mapping_lib(self):
         # Mapping a library with default mapping. This should not emit additional rules,
         # other than the default ones.
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -146,7 +156,7 @@ entries:
     def test_default_mapping_obj(self):
         # Mapping an object with default mapping. This should not emit additional rules,
         # other than the default ones.
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -158,7 +168,7 @@ entries:
     def test_default_mapping_symbol(self):
         # Mapping a symbol with default mapping. This should not emit additional rules,
         # other than the default ones.
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -170,7 +180,7 @@ entries:
     def test_default_mapping_all(self):
         # Mapping a library, object, and symbol with default mapping. This should not emit additional rules,
         # other than the default ones.
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -187,7 +197,7 @@ entries:
         #
         # This is a check needed to make sure generation does not generate
         # intermediate commands due to presence of symbol mapping.
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -203,7 +213,7 @@ entries:
         #
         # This is a check needed to make sure generation does not generate
         # intermediate commands due to presence of symbol mapping.
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -230,7 +240,7 @@ class BasicTest(GenerationTest):
         # iram0_text
         #   *(.iram ...)
         #   *libfreertos.a(.literal  ...)                                                                          B
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -260,14 +270,14 @@ entries:
         # There should be exclusions in the default commands for flash_text and flash_rodata:
         #
         # flash_text
-        #   *((EXCLUDE_FILE(libfreertos.a:croutine)) .literal ...)                                                          A
+        #   *((EXCLUDE_FILE(libfreertos.a:croutine)) .literal ...)                                          A
         #
         # Commands placing the entire library in iram, dram should be generated:
         #
         # iram0_text
         #   *(.iram ...)
-        #   *libfreertos.a:croutine(.literal  ...)                                                                          B
-        mapping = u"""
+        #   *libfreertos.a:croutine(.literal  ...)                                                          B
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -295,19 +305,20 @@ entries:
 
     def test_nondefault_mapping_symbol(self):
         # Test mapping entry different from default for symbol.
-        # There should be exclusions in the default commands for flash_text, as well as the implicit intermediate object command
+        # There should be exclusions in the default commands for flash_text, as
+        # well as the implicit intermediate object command
         # with an exclusion from default:
         #
         # flash_text
-        #   *((EXCLUDE_FILE(libfreertos.a:croutine)) .literal ...)                                                          A
-        #   *libfreertos.a:croutine(.literal  .literal.prvCheckDelayedList ...)                                             B
+        #   *((EXCLUDE_FILE(libfreertos.a:croutine)) .literal ...)                                          A
+        #   *libfreertos.a:croutine(.literal  .literal.prvCheckDelayedList ...)                             B
         #
         # Commands placing the entire library in iram should be generated:
         #
         # iram0_text
         #   *(.iram ...)
-        #   *libfreertos.a:croutine(.text.prvCheckPendingReadyList .literal.prvCheckPendingReadyList)                       C
-        mapping = u"""
+        #   *libfreertos.a:croutine(.text.prvCheckPendingReadyList .literal.prvCheckPendingReadyList)       C
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -336,7 +347,76 @@ entries:
         flash_text.append(InputSectionDesc(CROUTINE, set(filtered_sections), []))
 
         # Input section commands in iram_text for #1                                     C
-        iram0_text.append(InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), []))
+        iram0_text.append(
+            InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), [])
+        )
+
+        self.compare_rules(expected, actual)
+
+    def test_nondefault_mapping_symbol_with_suffix(self):
+        # Test a mapping entry that differs from the default for a symbol
+        # generated by the compiler, such as those created during IPA
+        # optimization for constant propagation.
+        #
+        # There should be exclusions in the default commands for flash_text, as
+        # well as the implicit intermediate object command with an exclusion
+        # from default:
+        #
+        # flash_text
+        #   *((EXCLUDE_FILE(*libspi_flash.a:esp_flash_api.*)) .text ...)                                 A
+        #   *libspi_flash.a:esp_flash_api.*(.text.check_chip_pointer_default ...)                        B
+        #
+        # Commands for placing the generated symbol in iram should be created,
+        # and they must also include .text.spiflash_start_core.constprop.0,
+        # even though the placement is specified only for the
+        # spiflash_start_core symbol.
+        #
+        # iram0_text
+        #   *(.iram ...)
+        #   *libspi_flash.a:esp_flash_api.*(.literal.spiflash_start_core .text.spiflash_start_core
+        #                                   .text.spiflash_start_core.constprop.0)                       C
+        mapping = """
+[mapping:test]
+archive: libspi_flash.a
+entries:
+    esp_flash_api:spiflash_start_core (noflash)         #1
+"""
+        self.add_fragments(mapping)
+        actual = self.generation.generate(self.entities, False)
+        expected = self.generate_default_rules()
+
+        flash_text = expected['flash_text']
+        iram0_text = expected['iram0_text']
+
+        # Generate exclusion in flash_text                                                A
+        flash_text[0].exclusions.add(ESP_FLASH_API)
+
+        # Generate intermediate command                                                   B
+        # List all relevant sections except the symbol
+        # being mapped
+        esp_flash_api_sections = self.entities.get_sections('libspi_flash.a', 'esp_flash_api')
+        filtered_sections = fnmatch.filter(esp_flash_api_sections, '.literal.*')
+        filtered_sections.extend(fnmatch.filter(esp_flash_api_sections, '.text.*'))
+
+        filtered_sections = [s for s in filtered_sections if not s.endswith('spiflash_start_core.constprop.0')]
+        filtered_sections.append('.text')
+
+        flash_text.append(InputSectionDesc(ESP_FLASH_API, set(filtered_sections), []))
+
+        # Input section commands in iram_text for #1                                     C
+        iram0_text.append(
+            InputSectionDesc(
+                ESP_FLASH_API,
+                set(
+                    [
+                        '.literal.spiflash_start_core',
+                        '.text.spiflash_start_core',
+                        '.text.spiflash_start_core.constprop.0',
+                    ]
+                ),
+                [],
+            )
+        )
 
         self.compare_rules(expected, actual)
 
@@ -351,14 +431,14 @@ entries:
         # object file, including .debug, .comment and other input section.
         #
         # flash.rodata
-        #   *((EXCLUDE_FILE(*libsoc.a:temperature_sensor_periph.*)) .rodata.* ...)                                          A
-        #   # *libsoc.a:temperature_sensor_periph.*                                                                         X
+        #   *((EXCLUDE_FILE(*libsoc.a:temperature_sensor_periph.*)) .rodata.* ...)                          A
+        #   # *libsoc.a:temperature_sensor_periph.*                                                         X
         #
         # Commands placing the entire library in iram should be generated:
         #
         # dram0_data
-        #   *libsoc.a:temperature_sensor_periph.*(.rodata.temperature_sensor_attribute)                                     B
-        mapping = u"""
+        #   *libsoc.a:temperature_sensor_periph.*(.rodata.temperature_sensor_attribute)                     B
+        mapping = """
 [mapping:test]
 archive: libsoc.a
 entries:
@@ -376,14 +456,15 @@ entries:
         flash_rodata[0].exclusions.add(TEMPERATURE_SENSOR_PERIPH)
 
         # Input section commands in dram0_data for #1                                    B
-        dram0_data.append(InputSectionDesc(TEMPERATURE_SENSOR_PERIPH,
-                                           set(['.rodata.temperature_sensor_attributes']),
-                                           []))
+        dram0_data.append(
+            InputSectionDesc(TEMPERATURE_SENSOR_PERIPH, set(['.rodata.temperature_sensor_attributes']), [])
+        )
 
         self.compare_rules(expected, actual)
 
     def test_default_symbol_nondefault_lib(self):
-        # Test default symbol mapping with different lib mapping. This should create an implicit intermediate object command.
+        # Test default symbol mapping with different lib mapping. This should
+        # create an implicit intermediate object command.
         # The significant targets are flash_text, flash_rodata, iram0_text, dram0_data.
         #
         # flash_text
@@ -403,7 +484,7 @@ entries:
         #  libfreertos.a ( .rodata ...)                                                                     C.2
         #
         # Only default commands are in the other targets.
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -440,7 +521,9 @@ entries:
         iram0_text.append(InputSectionDesc(CROUTINE, set(filtered_sections), []))
 
         # Command for #2                                                                                    B
-        flash_text.append(InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), []))
+        flash_text.append(
+            InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), [])
+        )
 
         self.compare_rules(expected, actual)
 
@@ -465,7 +548,7 @@ entries:
         #   *libfreertos.a:croutine(.rodata ....)                                                                    C.2
         #
         # Only default commands are in the other targets
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -499,7 +582,9 @@ entries:
         dram0_data.append(InputSectionDesc(CROUTINE, flash_rodata[0].sections, []))
 
         # Command for #2                                                                                    B
-        flash_text.append(InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), []))
+        flash_text.append(
+            InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), [])
+        )
 
         self.compare_rules(expected, actual)
 
@@ -532,7 +617,7 @@ entries:
         #  libfreertos.a (EXCLUDE_FILE(libfreertos:croutine) .rodata ...)                                    C
         #
         # For the other targets only the default commands should be present.
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -575,14 +660,16 @@ entries:
         flash_text.append(InputSectionDesc(CROUTINE, set(filtered_sections), []))
 
         # Command for #3                                                                                    D
-        iram0_text.append(InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), []))
+        iram0_text.append(
+            InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), [])
+        )
 
         self.compare_rules(expected, actual)
 
     def test_nondefault_but_same_lib_and_obj(self):
         # Extension of DefaultMappingTest. Commands should not be generated for #2, since it does similar mapping
         # to #1. Output is similar to test_different_mapping_lib.
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -594,7 +681,7 @@ entries:
     def test_nondefault_but_same_lib_and_sym(self):
         # Extension of DefaultMappingTest. Commands should not be generated for #2, since it does similar mapping
         # to #1. Output is similar to test_different_mapping_lib.
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -606,7 +693,7 @@ entries:
     def test_nondefault_but_same_obj_and_sym(self):
         # Commands should not be generated for #2, since it does similar mapping
         # to #1. Output is similar to test_different_mapping_obj.
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -627,7 +714,7 @@ entries:
         # iram0_text
         #
         #
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -659,8 +746,12 @@ entries:
         flash_text.append(InputSectionDesc(CROUTINE, set(filtered_sections), []))
 
         # Commands for #1 & 2
-        iram0_text.append(InputSectionDesc(CROUTINE, set(['.text.prvCheckDelayedList', '.literal.prvCheckDelayedList']), []))
-        iram0_text.append(InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), []))
+        iram0_text.append(
+            InputSectionDesc(CROUTINE, set(['.text.prvCheckDelayedList', '.literal.prvCheckDelayedList']), [])
+        )
+        iram0_text.append(
+            InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), [])
+        )
 
         self.compare_rules(expected, actual)
 
@@ -671,7 +762,7 @@ entries:
         # iram0_text
         #   * (.custom_section)                                  A
         #   * (.iram .iram.*)
-        mapping = u"""
+        mapping = """
 [sections:custom_section]
 entries:
     .custom_section
@@ -700,7 +791,6 @@ entries:
 
 
 class AdvancedTest(GenerationTest):
-
     # Test valid but quirky cases, corner cases, failure cases, and
     # cases involving interaction between schemes, other mapping
     # fragments.
@@ -727,7 +817,7 @@ class AdvancedTest(GenerationTest):
         #   *(.data ..)
         #   *(.dram ...)
         #   *libfreertos.a:croutine(.rodata .rodata.*)                                                               D
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -781,7 +871,7 @@ entries:
         #   *(.data ..)
         #   *(.dram ...)
         #   *libfreertos.a:croutine(.rodata .rodata.*)                                                               D
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -818,7 +908,7 @@ entries:
         # noflash = text -> iram0_text, rodata -> dram0_data
         #
         # This operation should fail.
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -837,7 +927,7 @@ entries:
         # noflash = .text -> iram0_text, .rodata -> dram0_data
         #
         # This operation should fail.
-        mapping = u"""
+        mapping = """
 [sections:custom_text]
 entries:
     .text+
@@ -861,42 +951,42 @@ entries:
         # using another. Another object and symbol is mapped the other way around.
         #
         # flash_text
-        #   *(EXCLUDE_FILE(libfreertos.a:croutine libfreertos.a:timers) .text ...)                                                        A, B
+        #   *(EXCLUDE_FILE(libfreertos.a:croutine libfreertos.a:timers) .text ...)                          A, B
         #
         # flash_rodata
-        #   *(EXCLUDE_FILE(libfreertos.a:croutine libfreertos.a:timers) .rodata ...)                                                      A, B
+        #   *(EXCLUDE_FILE(libfreertos.a:croutine libfreertos.a:timers) .rodata ...)                        A, B
         #
         # dram0_data
-        #   *(EXCLUDE_FILES(libfreertos.a:timers) .data ..)                                                                               B
+        #   *(EXCLUDE_FILES(libfreertos.a:timers) .data ..)                                                 B
         #   *(.dram ...)
-        #   *libfreertos.a:croutine(.rodata .rodata.*)                                                                                    C
-        #   *libfreertos.a:timers(.rodata.prvProcessReceivedCommands ...)                                                                 E
+        #   *libfreertos.a:croutine(.rodata .rodata.*)                                                      C
+        #   *libfreertos.a:timers(.rodata.prvProcessReceivedCommands ...)                                   E
         #
         # dram0_bss
-        #   *(EXCLUDE_FILE(libfreertos.a:timers) .bss .bss.* ...)                                                                         B
-        #   *(EXCLUDE_FILE(libfreertos.a:timers) COMMON)                                                                                  B
+        #   *(EXCLUDE_FILE(libfreertos.a:timers) .bss .bss.* ...)                                           B
+        #   *(EXCLUDE_FILE(libfreertos.a:timers) COMMON)                                                    B
         #
         # iram0_text
         #   *(.iram ...)
-        #   *libfreertos.a:croutine(.literal  .literal.prvCheckDelayedList ...)                                                           C
-        #   *libfreertos.a:timers(.literal  .literal.prvProcessReceivedCommands ...)                                                      E
+        #   *libfreertos.a:croutine(.literal  .literal.prvCheckDelayedList ...)                             C
+        #   *libfreertos.a:timers(.literal  .literal.prvProcessReceivedCommands ...)                        E
         #
         # rtc_text
         #   *(rtc.text .rtc.literal)
-        #   libfreertos.a:croutine (.text.prvCheckPendingReadyList .literal.prvCheckPendingReadyList)                                     F
-        #   libfreertos.a:timers (.text .text.prvCheckForValidListAndQueue ...)                                                           D.2
+        #   libfreertos.a:croutine (.text.prvCheckPendingReadyList .literal.prvCheckPendingReadyList)       F
+        #   libfreertos.a:timers (.text .text.prvCheckForValidListAndQueue ...)                             D.2
         #
         # rtc_data
         #   *(rtc.data)
         #   *(rtc.rodata)
-        #   libfreertos.a:timers (.data .data.*)                                                                                          D
-        #   libfreertos.a:timers (.rodata ...)                                                                                            D.2
+        #   libfreertos.a:timers (.data .data.*)                                                            D
+        #   libfreertos.a:timers (.rodata ...)                                                              D.2
         #
         # rtc_bss
         #   *(rtc.bss .rtc.bss)
-        #   libfreertos.a:timers (.bss .bss.*)                                                                                            D
-        #   libfreertos.a:timers (COMMON)                                                                                                 D
-        mapping = u"""
+        #   libfreertos.a:timers (.bss .bss.*)                                                              D
+        #   libfreertos.a:timers (COMMON)                                                                   D
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -944,7 +1034,9 @@ entries:
 
         # Commands for #4                                                                   F
         # Processed first due to alphabetical ordering
-        rtc_text.append(InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), []))
+        rtc_text.append(
+            InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), [])
+        )
 
         # Commands for #2                                                                   D
         # List all relevant sections excluding #3 for text -> rtc_text and                  D.2
@@ -966,7 +1058,11 @@ entries:
         rtc_bss.append(InputSectionDesc(TIMERS, dram0_bss[1].sections, []))
 
         # Commands for #3                                                                  E
-        iram0_text.append(InputSectionDesc(TIMERS, set(['.text.prvProcessReceivedCommands', '.literal.prvProcessReceivedCommands']), []))
+        iram0_text.append(
+            InputSectionDesc(
+                TIMERS, set(['.text.prvProcessReceivedCommands', '.literal.prvProcessReceivedCommands']), []
+            )
+        )
         dram0_data.append(InputSectionDesc(TIMERS, set(['.rodata.prvProcessReceivedCommands']), []))
 
         self.compare_rules(expected, actual)
@@ -983,7 +1079,7 @@ entries:
         #   * (EXCLUDE_FILE(libfreertos.a libfreertos.a:croutine) .text ...)
         #
         # iram0_text
-        mapping = u"""
+        mapping = """
 [mapping:test_1]
 archive: libfreertos.a
 entries:
@@ -1028,7 +1124,7 @@ entries:
         #
         # Uses the same entries as C_05 but spreads them across
         # two fragments. The output should still be the same.
-        mapping = u"""
+        mapping = """
 [mapping:test_1]
 archive: libfreertos.a
 entries:
@@ -1046,7 +1142,7 @@ entries:
     def test_mapping_same_lib_in_multiple_fragments_conflict(self):
         # Test mapping fragments operating on the same archive
         # with conflicting mappings.
-        mapping = u"""
+        mapping = """
 [mapping:test_1]
 archive: libfreertos.a
 entries:
@@ -1078,7 +1174,7 @@ entries:
         #   libfreertos:croutine(.text.prvCheckPendingReadyList .literal.prvCheckPendingReadyList)              G
         #   libfreertos2:croutine(.text .literal ...)                                                           D
         #   libfreertos2:croutine2(.text .literal ...)                                                          E
-        mapping = u"""
+        mapping = """
 [mapping:freertos2]
 archive: libfreertos2.a
 entries:
@@ -1116,8 +1212,12 @@ entries:
         flash_text.append(InputSectionDesc(CROUTINE, set(filtered_sections), []))
 
         # Command for
-        iram0_text.append(InputSectionDesc(CROUTINE, set(['.text.prvCheckDelayedList', '.literal.prvCheckDelayedList']), []))
-        iram0_text.append(InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), []))
+        iram0_text.append(
+            InputSectionDesc(CROUTINE, set(['.text.prvCheckDelayedList', '.literal.prvCheckDelayedList']), [])
+        )
+        iram0_text.append(
+            InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), [])
+        )
 
         iram0_text.append(InputSectionDesc(Entity(FREERTOS2.archive, 'croutine'), flash_text[0].sections, []))
         iram0_text.append(InputSectionDesc(Entity(FREERTOS2.archive, 'croutine2'), flash_text[0].sections, []))
@@ -1126,7 +1226,7 @@ entries:
 
     def test_ambigious_obj(self):
         # Command generation for ambiguous entry should fail.
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -1143,7 +1243,7 @@ entries:
         #
         # 'custom_scheme' entries conflict the 'default' scheme
         # entries.
-        mapping = u"""
+        mapping = """
 [scheme:custom_scheme]
 entries:
     flash_text -> iram0_text
@@ -1163,7 +1263,7 @@ entries:
         #
         # custom_scheme has the 'iram -> iram0_text' in common with
         # default scheme
-        mapping = u"""
+        mapping = """
 [sections:custom_section]
 entries:
     .custom_section
@@ -1198,7 +1298,7 @@ class ConfigTest(GenerationTest):
     def _test_conditional_on_scheme(self, perf, alt=None):
         # Test that proper commands are generated if using
         # schemes with conditional entries.
-        scheme = u"""
+        scheme = """
 [sections:cond_text_data]
 entries:
     if PERFORMANCE_LEVEL >= 1:
@@ -1215,7 +1315,7 @@ entries:
         cond_text_data -> dram0_data
 """
 
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: lib.a
 entries:
@@ -1250,7 +1350,7 @@ entries:
     def test_conditional_mapping(self, alt=None):
         # Test that proper commands are generated
         # in conditional mapping entries.
-        mapping = u"""
+        mapping = """
 [mapping:default]
 archive: *
 entries:
@@ -1299,7 +1399,7 @@ entries:
     def test_multiple_fragment_same_lib_conditional(self):
         # Test conditional entries on new mapping fragment grammar.
         # across multiple fragments.
-        mapping = u"""
+        mapping = """
 [mapping:default]
 archive: *
 entries:
@@ -1331,7 +1431,6 @@ entries:
 
 
 class FlagTest(GenerationTest):
-
     # Test correct generation of mapping fragment entries
     # with flags.
 
@@ -1362,7 +1461,7 @@ class FlagTest(GenerationTest):
         #   libfreertos.a:croutine(.text .literal ...)                                  I
         #   . = ALIGN(4)                                                                G.2
         #   _sym1_end                                                                   H.2
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -1422,7 +1521,7 @@ entries:
         # iram0_text
         #   *(.iram .iram.*)
         #   libfreertos.a:croutine(.text.prvCheckPendingReadyList ...)                  D
-        mapping = u"""
+        mapping = """
 [mapping:default]
 archive: *
 entries:
@@ -1466,7 +1565,9 @@ entries:
         flash_text.append(SymbolAtAddress('_sym1_end'))
 
         # Command for #3                                               D
-        iram0_text.append(InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), []))
+        iram0_text.append(
+            InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), [])
+        )
 
         self.compare_rules(expected, actual)
 
@@ -1484,7 +1585,7 @@ entries:
         # iram0_text
         #   *(.iram .iram.*)
         #   libfreertos.a:croutine(.text.prvCheckPendingReadyList ...)                  D
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -1523,7 +1624,9 @@ entries:
         flash_text.append(SymbolAtAddress('_sym1_end'))
 
         # Command for #3                                               C
-        iram0_text.append(InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), []))
+        iram0_text.append(
+            InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), [])
+        )
 
         self.compare_rules(expected, actual)
 
@@ -1540,7 +1643,7 @@ entries:
         # iram0_text
         #   *(.iram .iram.*)
         #   libfreertos.a:croutine(.text.prvCheckPendingReadyList ...)                  C
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -1575,7 +1678,9 @@ entries:
         flash_text.append(SymbolAtAddress('_sym1_end'))
 
         # Command for #3                                               C
-        iram0_text.append(InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), []))
+        iram0_text.append(
+            InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), [])
+        )
 
         self.compare_rules(expected, actual)
 
@@ -1591,7 +1696,7 @@ entries:
         # iram0_text
         #   *(.iram .iram.*)
         #   libfreertos.a:croutine(.text.prvCheckPendingReadyList ...)                  D
-        mapping = u"""
+        mapping = """
 [mapping:default]
 archive: *
 entries:
@@ -1636,7 +1741,9 @@ entries:
         flash_text.append(InputSectionDesc(CROUTINE, set(filtered_sections), []))
 
         # Command for #4                                               D
-        iram0_text.append(InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), []))
+        iram0_text.append(
+            InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), [])
+        )
 
         self.compare_rules(expected, actual)
 
@@ -1653,7 +1760,7 @@ entries:
         # iram0_text
         #   *(.iram .iram.*)
         #   libfreertos.a:croutine(.text.prvCheckPendingReadyList ...)                  D
-        mapping = u"""
+        mapping = """
 [mapping:test]
 archive: libfreertos.a
 entries:
@@ -1693,14 +1800,16 @@ entries:
         flash_text.append(InputSectionDesc(CROUTINE, set(filtered_sections), []))
 
         # Command for #3                                               C
-        iram0_text.append(InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), []))
+        iram0_text.append(
+            InputSectionDesc(CROUTINE, set(['.text.prvCheckPendingReadyList', '.literal.prvCheckPendingReadyList']), [])
+        )
 
         self.compare_rules(expected, actual)
 
     def test_flag_additions(self):
         # Test ability to add flags as long as no other mapping fragments
         # does the same thing.
-        mapping = u"""
+        mapping = """
 [mapping:default_add_flag]
 archive: *
 entries:
@@ -1721,7 +1830,7 @@ entries:
     def test_flags_flag_additions_duplicate(self):
         # Test same flags added to same entity - these
         # are ignored.
-        mapping = u"""
+        mapping = """
 [mapping:default_add_flag_1]
 archive: *
 entries:
@@ -1748,7 +1857,7 @@ entries:
     def test_flags_flag_additions_conflict(self):
         # Test condition where multiple fragments specifies flags
         # to same entity - should generate exception.
-        mapping = u"""
+        mapping = """
 [mapping:default_add_flag_1]
 archive: *
 entries: