From a002a043321bf21a2b072e60bb9c828657a1987b Mon Sep 17 00:00:00 2001 From: Aditya Patwardhan Date: Fri, 11 Jul 2025 16:22:10 +0530 Subject: [PATCH] feat(soc): Added soc capabilities related to RNG --- .../src/bootloader_random_esp32c5.c | 4 ++++ components/esp_hw_support/hw_random.c | 13 +++++++++++-- components/esp_system/system_init_fn.txt | 4 ++-- .../soc/esp32c5/include/soc/Kconfig.soc_caps.in | 12 ++++++++++++ components/soc/esp32c5/include/soc/soc_caps.h | 5 +++++ 5 files changed, 34 insertions(+), 4 deletions(-) diff --git a/components/bootloader_support/src/bootloader_random_esp32c5.c b/components/bootloader_support/src/bootloader_random_esp32c5.c index e973d99043..e51923562a 100644 --- a/components/bootloader_support/src/bootloader_random_esp32c5.c +++ b/components/bootloader_support/src/bootloader_random_esp32c5.c @@ -9,6 +9,7 @@ #include "hal/adc_ll.h" #include "hal/adc_types.h" #include "esp_private/regi2c_ctrl.h" +#include "soc/lpperi_reg.h" void bootloader_random_enable(void) { @@ -48,6 +49,9 @@ void bootloader_random_enable(void) adc_ll_digi_set_trigger_interval(200); adc_ll_digi_trigger_enable(); + SET_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_SAMPLE_ENABLE); + REG_SET_FIELD(LPPERI_RNG_CFG_REG, LPPERI_RTC_TIMER_EN, 0x3); + SET_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_TIMER_EN); } void bootloader_random_disable(void) diff --git a/components/esp_hw_support/hw_random.c b/components/esp_hw_support/hw_random.c index 4f43e39d53..705fc9b8d2 100644 --- a/components/esp_hw_support/hw_random.c +++ b/components/esp_hw_support/hw_random.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2016-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -104,9 +104,18 @@ void esp_fill_random(void *buf, size_t len) } #if SOC_RNG_CLOCK_IS_INDEPENDENT && !ESP_TEE_BUILD -ESP_SYSTEM_INIT_FN(init_rng_clock, SECONDARY, BIT(0), 102) +ESP_SYSTEM_INIT_FN(init_rng, SECONDARY, BIT(0), 102) { _lp_clkrst_ll_enable_rng_clock(true); +#if SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE + SET_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_SAMPLE_ENABLE); +#endif + +#if SOC_RNG_RTC_TIMER_ENTROPY_SOURCE + // This would only be effective if the RTC clock is enabled + REG_SET_FIELD(LPPERI_RNG_CFG_REG, LPPERI_RTC_TIMER_EN, 0x3); + SET_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_TIMER_EN); +#endif return ESP_OK; } #endif diff --git a/components/esp_system/system_init_fn.txt b/components/esp_system/system_init_fn.txt index 0d68cf299d..5e1b1c308c 100644 --- a/components/esp_system/system_init_fn.txt +++ b/components/esp_system/system_init_fn.txt @@ -72,8 +72,8 @@ SECONDARY: 100: esp_timer_init_os in components/esp_timer/src/esp_timer.c on ESP # HW stack guard via assist-debug module. SECONDARY: 101: esp_hw_stack_guard_init in components/esp_system/hw_stack_guard.c on ESP_SYSTEM_INIT_ALL_CORES -# RNG module clock was disabled in `esp_perip_clk_init`, if hw_random is used, need to re-ebnabled it in startup -SECONDARY: 102: init_rng_clock in components/esp_hw_support/hw_random.c on BIT(0) +# Initialize RNG (enable clock which is disabled in `esp_perip_clk_init`, configure entropy sources) +SECONDARY: 102: init_rng in components/esp_hw_support/hw_random.c on BIT(0) # Security specific initializations SECONDARY: 103: esp_security_init in components/esp_security/src/init.c on BIT(0) diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index d23b2d83e6..e11e0ea18c 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -1511,6 +1511,14 @@ config SOC_CRYPTO_DPA_PROTECTION_SUPPORTED bool default y +config SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE + bool + default y + +config SOC_RNG_RTC_TIMER_ENTROPY_SOURCE + bool + default y + config SOC_UART_NUM int default 3 @@ -1723,6 +1731,10 @@ config SOC_MODEM_CLOCK_IS_INDEPENDENT bool default y +config SOC_RNG_CLOCK_IS_INDEPENDENT + bool + default y + config SOC_CLK_XTAL32K_SUPPORTED bool default y diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index 9e9c4ee8d2..f1971410b3 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -584,6 +584,10 @@ /*------------------------ Anti DPA (Security) CAPS --------------------------*/ #define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1 +/*-------------------------- RNG CAPS ---------------------------------------*/ +#define SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE 1 +#define SOC_RNG_RTC_TIMER_ENTROPY_SOURCE 1 + /*-------------------------- UART CAPS ---------------------------------------*/ // ESP32-C5 has 3 UARTs (2 HP UART, and 1 LP UART) #define SOC_UART_NUM (3) @@ -668,6 +672,7 @@ /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/ #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1) #define SOC_MODEM_CLOCK_IS_INDEPENDENT (1) +#define SOC_RNG_CLOCK_IS_INDEPENDENT (1) #define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */ #define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< Support to connect an external oscillator, not a crystal */