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refactor(hal/usb): Remove usb_fsls_phy_ll.h

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For targets that only contain a USJ peripheral (and not a DWC OTG), their
'usb_fsls_phy_ll.h' headers only contain a single function
('usb_fsls_phy_ll_int_jtag_enable()') whose feature is already covered by
functions in 'usb_serial_jtag_ll.h'. Thus, this header is redundant.

This commit does the following:

- Remove 'usb_fsls_phy_ll.h' for targets that only contain a USJ peripheral
- Rename 'usb_fsls_phy_[hal|ll].[h|c]' to `usb_wrap_[hal|ll].[h|c]` for targets
that contain a DWC OTG peripheral. This better reflects the underlying peripheral
that the LL header accesses.
This commit is contained in:
Darian Leung
2024-03-14 21:20:33 +08:00
parent 5d091a9bb3
commit a77e5cc718
15 changed files with 30 additions and 160 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_system/port/soc/esp32c3/clk.c
+1 -2
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@@ -22,7 +22,6 @@
#include "soc/i2s_reg.h"
#include "hal/wdt_hal.h"
#include "hal/usb_serial_jtag_ll.h"
#include "hal/usb_fsls_phy_ll.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/esp_clk.h"
#include "soc/syscon_reg.h"
@@ -246,7 +245,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
// Disable USB-Serial-JTAG clock and it's pad if not used
usb_fsls_phy_ll_int_jtag_disable(&USB_SERIAL_JTAG);
usb_serial_jtag_ll_phy_enable_pad(false);
_usb_serial_jtag_ll_enable_bus_clock(false);
#endif
}
components/esp_system/port/soc/esp32c6/clk.c
+1 -2
View File
@@ -40,7 +40,6 @@
#include "hal/lp_core_ll.h"
#include "hal/temperature_sensor_ll.h"
#include "hal/usb_serial_jtag_ll.h"
#include "hal/usb_fsls_phy_ll.h"
#include "esp_private/esp_modem_clock.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/esp_clk.h"
@@ -282,7 +281,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
// Disable USB-Serial-JTAG clock and it's pad if not used
usb_fsls_phy_ll_int_jtag_disable(&USB_SERIAL_JTAG);
usb_serial_jtag_ll_phy_enable_pad(false);
usb_serial_jtag_ll_enable_bus_clock(false);
#endif
}
components/esp_system/port/soc/esp32h2/clk.c
+1 -2
View File
@@ -41,7 +41,6 @@
#include "hal/clk_gate_ll.h"
#include "hal/temperature_sensor_ll.h"
#include "hal/usb_serial_jtag_ll.h"
#include "hal/usb_fsls_phy_ll.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/esp_clk.h"
#include "esp_private/esp_pmu.h"
@@ -273,7 +272,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
// Disable USB-Serial-JTAG clock and it's pad if not used
usb_fsls_phy_ll_int_jtag_disable(&USB_SERIAL_JTAG);
usb_serial_jtag_ll_phy_enable_pad(false);
usb_serial_jtag_ll_enable_bus_clock(false);
#endif
}
components/esp_system/port/soc/esp32s3/clk.c
+1 -2
View File
@@ -22,7 +22,6 @@
#include "soc/i2s_reg.h"
#include "hal/wdt_hal.h"
#include "hal/usb_serial_jtag_ll.h"
#include "hal/usb_fsls_phy_ll.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/esp_clk.h"
#include "bootloader_clock.h"
@@ -265,7 +264,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
// Disable USB-Serial-JTAG clock and it's pad if not used
usb_fsls_phy_ll_int_jtag_disable(&USB_SERIAL_JTAG);
usb_serial_jtag_ll_phy_enable_pad(false);
usb_serial_jtag_ll_enable_bus_clock(false);
#endif
}