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fix(esp_hw_support): clear reserved interrupts that are not applicable for each target

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This commit is contained in:
Omar Chebib
2024-03-12 11:01:51 +08:00
parent 6e4eeec97c
commit a79c6f7f67
21 changed files with 404 additions and 359 deletions
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components/esp_hw_support/include/esp_private/esp_riscv_intr.h
+35 -2
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@@ -9,6 +9,37 @@
#if CONFIG_IDF_TARGET_ARCH_RISCV
#if SOC_INT_CLIC_SUPPORTED
/**
* @brief Checks whether the given interrupt number is reserved either in the given mask or in the
* _mtvt_table, which contains the routines the CPU will jump to when an interrupt or an exception
* occurs, on RISC-V targets.
*
* @param intr_num External interrupt number to check, in range 0~32
* @param rsvd_mask Reserved interrupt mask, where bit i is 1 if interrupt i is reserved.
*
* @returns ESP_CPU_INTR_DESC_FLAG_RESVD if the interrupt is reserved, 0 else
*/
static inline uint32_t esp_riscv_intr_num_flags(int intr_num, uint32_t rsvd_mask)
{
if (rsvd_mask & BIT(intr_num)) {
return ESP_CPU_INTR_DESC_FLAG_RESVD;
}
extern intptr_t _mtvt_table[48];
extern intptr_t _interrupt_handler;
/* The first 16 entries of the array are internal interrupt, ignore them */
const intptr_t destination = _mtvt_table[16 + intr_num];
return (destination != (intptr_t)&_interrupt_handler) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0;
}
#else // !SOC_INT_CLIC_SUPPORTED
#include "esp_cpu.h"
#include "riscv/instruction_decode.h"
@@ -28,9 +59,9 @@ static inline uint32_t esp_riscv_intr_num_flags(int intr_num, uint32_t rsvd_mask
return ESP_CPU_INTR_DESC_FLAG_RESVD;
}
extern int _vector_table;
extern intptr_t _vector_table[32];
extern int _interrupt_handler;
const intptr_t pc = (intptr_t)(&_vector_table + intr_num);
const intptr_t pc = (intptr_t) &_vector_table[intr_num];
/* JAL instructions are relative to the PC they are executed from. */
const intptr_t destination = pc + riscv_decode_offset_from_jal_instruction(pc);
@@ -38,4 +69,6 @@ static inline uint32_t esp_riscv_intr_num_flags(int intr_num, uint32_t rsvd_mask
return (destination != (intptr_t)&_interrupt_handler) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0;
}
#endif // SOC_INT_CLIC_SUPPORTED
#endif // CONFIG_IDF_TARGET_ARCH_RISCV