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refactor(usb/host): Make private hal types USB_DWC specific

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This commit is contained in:
Tomas Rezucha
2023-11-29 16:30:04 +08:00
parent 69d9e7625b
commit b258bbf068
8 changed files with 65 additions and 95 deletions
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components/hal/include/hal/usb_dwc_hal.h
+7 -7
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@@ -22,7 +22,7 @@ NOTE: Thread safety is the responsibility fo the HAL user. All USB Host HAL
#include "soc/usb_dwc_struct.h"
#include "hal/usb_dwc_ll.h"
#endif
#include "hal/usb_types_private.h"
#include "hal/usb_dwc_types.h"
#include "hal/assert.h"
#if SOC_USB_OTG_SUPPORTED
@@ -107,7 +107,7 @@ typedef enum {
typedef struct {
union {
struct {
usb_priv_xfer_type_t type: 2; /**< The type of endpoint */
usb_dwc_xfer_type_t type: 2; /**< The type of endpoint */
uint32_t bEndpointAddress: 8; /**< Endpoint address (containing endpoint number and direction) */
uint32_t mps: 11; /**< Maximum Packet Size */
uint32_t dev_addr: 8; /**< Device Address */
@@ -138,9 +138,9 @@ typedef struct {
};
uint32_t val;
} flags; /**< Flags regarding channel's status and information */
usb_dwc_host_chan_regs_t *regs; /**< Pointer to the channel's register set */
usb_dwc_hal_chan_error_t error; /**< The last error that occurred on the channel */
usb_priv_xfer_type_t type; /**< The transfer type of the channel */
usb_dwc_host_chan_regs_t *regs; /**< Pointer to the channel's register set */
usb_dwc_hal_chan_error_t error; /**< The last error that occurred on the channel */
usb_dwc_xfer_type_t type; /**< The transfer type of the channel */
void *chan_ctx; /**< Context variable for the owner of the channel */
} usb_dwc_hal_chan_t;
@@ -473,9 +473,9 @@ static inline bool usb_dwc_hal_port_check_if_connected(usb_dwc_hal_context_t *ha
* @note This function should only be called after confirming that a device is connected to the host port
*
* @param hal Context of the HAL layer
* @return usb_priv_speed_t Speed of the connected device
* @return usb_dwc_speed_t Speed of the connected device
*/
static inline usb_priv_speed_t usb_dwc_hal_port_get_conn_speed(usb_dwc_hal_context_t *hal)
static inline usb_dwc_speed_t usb_dwc_hal_port_get_conn_speed(usb_dwc_hal_context_t *hal)
{
return usb_dwc_ll_hprt_get_speed(hal->dev);
}
components/hal/include/hal/usb_dwc_ll.h
+10 -37
View File
@@ -16,7 +16,7 @@ extern "C" {
#if SOC_USB_OTG_SUPPORTED
#include "soc/usb_dwc_struct.h"
#endif
#include "hal/usb_types_private.h"
#include "hal/usb_dwc_types.h"
#include "hal/misc.h"
@@ -450,7 +450,7 @@ static inline void usb_dwc_ll_hcfg_set_fsls_pclk_sel(usb_dwc_dev_t *hw)
* @param hw Start address of the DWC_OTG registers
* @param speed Speed to initialize the host port at
*/
static inline void usb_dwc_ll_hcfg_set_defaults(usb_dwc_dev_t *hw, usb_priv_speed_t speed)
static inline void usb_dwc_ll_hcfg_set_defaults(usb_dwc_dev_t *hw, usb_dwc_speed_t speed)
{
hw->hcfg_reg.descdma = 1; //Enable scatt/gatt
hw->hcfg_reg.fslssupp = 1; //FS/LS support only
@@ -459,13 +459,13 @@ static inline void usb_dwc_ll_hcfg_set_defaults(usb_dwc_dev_t *hw, usb_priv_spee
Note: It seems like our PHY has an implicit 8 divider applied when in LS mode,
so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
*/
hw->hcfg_reg.fslspclksel = (speed == USB_PRIV_SPEED_FULL) ? 1 : 2; //PHY clock on esp32-sx for FS/LS-only
hw->hcfg_reg.fslspclksel = (speed == USB_DWC_SPEED_FULL) ? 1 : 2; //PHY clock on esp32-sx for FS/LS-only
hw->hcfg_reg.perschedena = 0; //Disable perio sched
}
// ----------------------------- HFIR Register ---------------------------------
static inline void usb_dwc_ll_hfir_set_defaults(usb_dwc_dev_t *hw, usb_priv_speed_t speed)
static inline void usb_dwc_ll_hfir_set_defaults(usb_dwc_dev_t *hw, usb_dwc_speed_t speed)
{
usb_dwc_hfir_reg_t hfir;
hfir.val = hw->hfir_reg.val;
@@ -475,7 +475,7 @@ static inline void usb_dwc_ll_hfir_set_defaults(usb_dwc_dev_t *hw, usb_priv_spee
Note: It seems like our PHY has an implicit 8 divider applied when in LS mode,
so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
*/
hfir.frint = (speed == USB_PRIV_SPEED_FULL) ? 48000 : 6000; //esp32-sx targets only support FS or LS
hfir.frint = (speed == USB_DWC_SPEED_FULL) ? 48000 : 6000; //esp32-sx targets only support FS or LS
hw->hfir_reg.val = hfir.val;
}
@@ -558,21 +558,9 @@ static inline uint32_t usb_dwc_ll_hflbaddr_get_base_addr(usb_dwc_dev_t *hw)
// ----------------------------- HPRT Register ---------------------------------
static inline usb_priv_speed_t usb_dwc_ll_hprt_get_speed(usb_dwc_dev_t *hw)
static inline usb_dwc_speed_t usb_dwc_ll_hprt_get_speed(usb_dwc_dev_t *hw)
{
usb_priv_speed_t speed = USB_PRIV_SPEED_HIGH;
switch (hw->hprt_reg.prtspd) {
case 0:
speed = USB_PRIV_SPEED_HIGH;
break;
case 1:
speed = USB_PRIV_SPEED_FULL;
break;
case 2:
speed = USB_PRIV_SPEED_LOW;
break;
}
return speed;
return (usb_dwc_speed_t)hw->hprt_reg.prtspd;
}
static inline uint32_t usb_dwc_ll_hprt_get_test_ctl(usb_dwc_dev_t *hw)
@@ -731,24 +719,9 @@ static inline void usb_dwc_ll_hcchar_set_dev_addr(volatile usb_dwc_host_chan_reg
chan->hcchar_reg.devaddr = addr;
}
static inline void usb_dwc_ll_hcchar_set_ep_type(volatile usb_dwc_host_chan_regs_t *chan, usb_priv_xfer_type_t type)
static inline void usb_dwc_ll_hcchar_set_ep_type(volatile usb_dwc_host_chan_regs_t *chan, usb_dwc_xfer_type_t type)
{
uint32_t ep_type;
switch (type) {
case USB_PRIV_XFER_TYPE_CTRL:
ep_type = 0;
break;
case USB_PRIV_XFER_TYPE_ISOCHRONOUS:
ep_type = 1;
break;
case USB_PRIV_XFER_TYPE_BULK:
ep_type = 2;
break;
default: //USB_PRIV_XFER_TYPE_INTR
ep_type = 3;
break;
}
chan->hcchar_reg.eptype = ep_type;
chan->hcchar_reg.eptype = (uint32_t)type;
}
//Indicates whether channel is commuunicating with a LS device connected via a FS hub. Setting this bit to 1 will cause
@@ -773,7 +746,7 @@ static inline void usb_dwc_ll_hcchar_set_mps(volatile usb_dwc_host_chan_regs_t *
chan->hcchar_reg.mps = mps;
}
static inline void usb_dwc_ll_hcchar_init(volatile usb_dwc_host_chan_regs_t *chan, int dev_addr, int ep_num, int mps, usb_priv_xfer_type_t type, bool is_in, bool is_ls)
static inline void usb_dwc_ll_hcchar_init(volatile usb_dwc_host_chan_regs_t *chan, int dev_addr, int ep_num, int mps, usb_dwc_xfer_type_t type, bool is_in, bool is_ls)
{
//Sets all persistent fields of the channel over its lifetimez
usb_dwc_ll_hcchar_set_dev_addr(chan, dev_addr);
components/hal/include/hal/usb_types_private.h → components/hal/include/hal/usb_dwc_types.h
+13 -9
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@@ -20,22 +20,26 @@ extern "C"
/**
* @brief USB speeds supported by the DWC OTG controller
*
* @note usb_dwc_speed_t enum values must match the values of the DWC_OTG prtspd register field
*/
typedef enum {
USB_PRIV_SPEED_HIGH,
USB_PRIV_SPEED_FULL,
USB_PRIV_SPEED_LOW,
} usb_priv_speed_t;
USB_DWC_SPEED_HIGH = 0,
USB_DWC_SPEED_FULL = 1,
USB_DWC_SPEED_LOW = 2,
} usb_dwc_speed_t;
/**
* @brief USB transfer types supported by the DWC OTG controller
*
* @note usb_dwc_xfer_type_t enum values must match the values of the DWC_OTG hcchar register field
*/
typedef enum {
USB_PRIV_XFER_TYPE_CTRL,
USB_PRIV_XFER_TYPE_ISOCHRONOUS,
USB_PRIV_XFER_TYPE_BULK,
USB_PRIV_XFER_TYPE_INTR,
} usb_priv_xfer_type_t;
USB_DWC_XFER_TYPE_CTRL = 0,
USB_DWC_XFER_TYPE_ISOCHRONOUS = 1,
USB_DWC_XFER_TYPE_BULK = 2,
USB_DWC_XFER_TYPE_INTR = 3,
} usb_dwc_xfer_type_t;
/**
* @brief Enumeration of different possible lengths of the periodic frame list
components/hal/include/hal/usb_phy_hal.h
+2 -2
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@@ -7,7 +7,7 @@
#pragma once
#include <stdbool.h>
#include "usb_types_private.h"
#include "usb_dwc_types.h"
#include "usb_phy_types.h"
#include "soc/soc_caps.h"
#if SOC_USB_OTG_SUPPORTED
@@ -72,7 +72,7 @@ void usb_phy_hal_int_load_conf_host(usb_phy_hal_context_t *hal);
* @param hal Context of the HAL layer
* @param speed USB speed
*/
void usb_phy_hal_int_load_conf_dev(usb_phy_hal_context_t *hal, usb_priv_speed_t speed);
void usb_phy_hal_int_load_conf_dev(usb_phy_hal_context_t *hal, usb_phy_speed_t speed);
/**
* @brief Enable/Disable test mode for internal PHY to mimick host-device disconnection