feat(efuse): Add flash efuses for esp32c3
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@@ -9,7 +9,7 @@
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# this will generate new source files, next rebuild all the sources.
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# !!!!!!!!!!! #
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# This file was generated by regtools.py based on the efuses.yaml file with the version: a85f874ae2b6538ca48b7c3db4a79531
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# This file was generated by regtools.py based on the efuses.yaml file with the version: 4622cf9245401eca0eb1df8122449a6d
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WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
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WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
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@@ -63,6 +63,9 @@ WR_DIS.SPI_PAD_CONFIG_D7, EFUSE_BLK0, 20, 1, [] wr_dis
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WR_DIS.WAFER_VERSION_MINOR_LO, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_LO
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WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
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WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR
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WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP
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WR_DIS.FLASH_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_TEMP
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WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR
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WR_DIS.K_RTC_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_RTC_LDO
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WR_DIS.K_DIG_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_DIG_LDO
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WR_DIS.V_RTC_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_RTC_DBIAS20
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@@ -161,6 +164,9 @@ SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, [] SPI PA
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WAFER_VERSION_MINOR_LO, EFUSE_BLK1, 114, 3, [] WAFER_VERSION_MINOR least significant bits
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PKG_VERSION, EFUSE_BLK1, 117, 3, [] Package version
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BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, [] BLK_VERSION_MINOR
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FLASH_CAP, EFUSE_BLK1, 123, 3, [] Flash capacity {0: "None"; 1: "4M"; 2: "2M"; 3: "1M"; 4: "8M"}
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FLASH_TEMP, EFUSE_BLK1, 126, 2, [] Flash temperature {0: "None"; 1: "105C"; 2: "85C"}
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FLASH_VENDOR, EFUSE_BLK1, 128, 3, [] Flash vendor {0: "None"; 1: "XMC"; 2: "GD"; 3: "FM"; 4: "TT"; 5: "ZBIT"}
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K_RTC_LDO, EFUSE_BLK1, 135, 7, [] BLOCK1 K_RTC_LDO
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K_DIG_LDO, EFUSE_BLK1, 142, 7, [] BLOCK1 K_DIG_LDO
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V_RTC_DBIAS20, EFUSE_BLK1, 149, 8, [] BLOCK1 voltage of rtc dbias20
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