test(psram): re-enable 80M psram tests on C5 ECO2

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c

@@ -55,6 +55,7 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)
     // SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
     // in this stage, set divider as 6
     _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_SPLL);
+    // MSPI0 and MSPI1 share this core clock register, but only setting to MSPI0 register is valid
     mspi_timing_ll_set_core_clock(MSPI_TIMING_LL_MSPI_ID_0, MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT);
 }
 

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c

@@ -52,6 +52,7 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)
     // SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz
     // in this stage, set divider as 6
     _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_DEFAULT);
+    // MSPI0 and MSPI1 share this core clock register, but only setting to MSPI0 register is valid
     mspi_timing_ll_set_core_clock(MSPI_TIMING_LL_MSPI_ID_0, MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT);
 }