From bb79e6f2460c078945fd41735f292dfd09c51e9b Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Sun, 18 Jan 2026 04:30:46 +0800 Subject: [PATCH] fix(esp32p4): fix efuse, encryption and other rev_min usage --- .../bootloader_support/src/flash_encrypt.c | 4 +-- .../efuse/esp32p4/include/esp_efuse_chip.h | 4 +-- .../efuse/esp32p4/include/esp_efuse_table.h | 2 +- components/efuse/esp32p4/sources.cmake | 2 +- .../esp32p4/Kconfig.p4_rev3_mspi_workaround | 4 +-- .../esp_hw_support/port/esp32p4/pmu_init.c | 4 +-- .../port/esp32p4/rtc_clk_init.c | 4 +-- .../mipi_dsi_lcd/main/test_mipi_dsi_panel.c | 2 +- components/esp_psram/system_layer/esp_psram.c | 11 +++++--- components/esp_system/port/cpu_start.c | 2 +- .../port/soc/esp32p4/system_internal.c | 25 +++++++++++-------- 11 files changed, 36 insertions(+), 28 deletions(-) diff --git a/components/bootloader_support/src/flash_encrypt.c b/components/bootloader_support/src/flash_encrypt.c index 9e311b156d..baaa948226 100644 --- a/components/bootloader_support/src/flash_encrypt.c +++ b/components/bootloader_support/src/flash_encrypt.c @@ -211,7 +211,7 @@ void esp_flash_encryption_set_release_mode(void) #endif // !CONFIG_IDF_TARGET_ESP32 #if !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_REV_MIN_FULL < 300) -#ifdef SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND +#if SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) { uint8_t xts_pseudo_level = 0; esp_efuse_read_field_blob(ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL, &xts_pseudo_level, ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[0]->bit_count); @@ -485,7 +485,7 @@ bool esp_flash_encryption_cfg_verify_release_mode(void) result &= secure; #if !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_REV_MIN_FULL < 300) -#if SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND +#if SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) { uint8_t xts_pseudo_level = 0; esp_efuse_read_field_blob(ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL, &xts_pseudo_level, ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[0]->bit_count); diff --git a/components/efuse/esp32p4/include/esp_efuse_chip.h b/components/efuse/esp32p4/include/esp_efuse_chip.h index b9e6bcc234..958fa239e9 100644 --- a/components/efuse/esp32p4/include/esp_efuse_chip.h +++ b/components/efuse/esp32p4/include/esp_efuse_chip.h @@ -66,7 +66,7 @@ typedef enum { ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */ ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, /**< ECDSA private key (Expected in little endian order)*/ -#if CONFIG_ESP32P4_REV_MIN_FULL >= 300 +#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P256 = ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY, /**< ECDSA private key (P256) (Expected in little endian order)*/ #endif @@ -82,7 +82,7 @@ typedef enum { ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */ ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY = 12, /**< KM_INIT_KEY */ -#if CONFIG_ESP32P4_REV_MIN_FULL >= 300 +#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 = 13, /**< PSRAM encryption key (XTS_AES_256_KEY_1) */ ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 = 14, /**< PSRAM encryption key (XTS_AES_256_KEY_2) */ ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY = 15, /**< PSRAM encryption key (XTS_AES_128_KEY) */ diff --git a/components/efuse/esp32p4/include/esp_efuse_table.h b/components/efuse/esp32p4/include/esp_efuse_table.h index fed2072d5b..a2803f5bde 100644 --- a/components/efuse/esp32p4/include/esp_efuse_table.h +++ b/components/efuse/esp32p4/include/esp_efuse_table.h @@ -10,7 +10,7 @@ extern "C" { #include "sdkconfig.h" -#if CONFIG_ESP32P4_REV_MIN_FULL >= 300 +#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 #include "esp_efuse_table_v3.0.h" #else #include "esp_efuse_table_v0.0_v2.0.h" diff --git a/components/efuse/esp32p4/sources.cmake b/components/efuse/esp32p4/sources.cmake index 7712caeded..7896c3d353 100644 --- a/components/efuse/esp32p4/sources.cmake +++ b/components/efuse/esp32p4/sources.cmake @@ -4,7 +4,7 @@ set(EFUSE_SOC_SRCS "esp_efuse_rtc_calib.c" ) -if(CONFIG_ESP32P4_REV_MIN_FULL GREATER_EQUAL 300) +if(NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3) list(APPEND EFUSE_SOC_SRCS "esp_efuse_table_v3.0.c" ) diff --git a/components/esp_hw_support/lowpower/port/esp32p4/Kconfig.p4_rev3_mspi_workaround b/components/esp_hw_support/lowpower/port/esp32p4/Kconfig.p4_rev3_mspi_workaround index 5810818f79..8ff9ca2d65 100644 --- a/components/esp_hw_support/lowpower/port/esp32p4/Kconfig.p4_rev3_mspi_workaround +++ b/components/esp_hw_support/lowpower/port/esp32p4/Kconfig.p4_rev3_mspi_workaround @@ -1,10 +1,10 @@ config P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND bool depends on IDF_TARGET_ESP32P4 - default y if ESP32P4_REV_MIN_300 + default y if !ESP32P4_SELECTS_REV_LESS_V3 config P4_REV3_MSPI_WORKAROUND_SIZE hex depends on IDF_TARGET_ESP32P4 - default 0x100 if ESP32P4_REV_MIN_300 + default 0x100 if !ESP32P4_SELECTS_REV_LESS_V3 default 0 diff --git a/components/esp_hw_support/port/esp32p4/pmu_init.c b/components/esp_hw_support/port/esp32p4/pmu_init.c index 2a3b58e542..2dc70eda2f 100644 --- a/components/esp_hw_support/port/esp32p4/pmu_init.c +++ b/components/esp_hw_support/port/esp32p4/pmu_init.c @@ -176,7 +176,7 @@ static void pmu_hp_system_init_default(pmu_context_t *ctx) pmu_hp_system_param_default(mode, ¶m); pmu_hp_system_init(ctx, mode, ¶m); } -#if CONFIG_ESP32P4_REV_MIN_FULL >= 300 +#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 lp_sys_ll_set_hp_mem_lowpower_mode(MEM_AUX_DEEPSLEEP); #endif } @@ -195,7 +195,7 @@ static void pmu_lp_system_init_default(pmu_context_t *ctx) pmu_lp_system_param_default(mode, ¶m); pmu_lp_system_init(ctx, mode, ¶m); } -#if CONFIG_ESP32P4_REV_MIN_FULL >= 300 +#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 lp_sys_ll_set_lp_mem_lowpower_mode(MEM_AUX_DEEPSLEEP); #endif } diff --git a/components/esp_hw_support/port/esp32p4/rtc_clk_init.c b/components/esp_hw_support/port/esp32p4/rtc_clk_init.c index a49598ff2f..c0eaa0f5e0 100644 --- a/components/esp_hw_support/port/esp32p4/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32p4/rtc_clk_init.c @@ -68,7 +68,7 @@ void rtc_clk_init(rtc_clk_config_t cfg) hp_dcmvset = pvt_hp_dcmvset; } // Switch to DCDC -#if CONFIG_ESP32P4_REV_MIN_301 +#if (CONFIG_ESP32P4_REV_MIN_FULL >= 301) unsigned chip_version = efuse_hal_chip_revision(); if (ESP_CHIP_REV_ABOVE(chip_version, 301)) { SET_PERI_REG_MASK(PMU_DCM_CTRL_REG, PMU_DCDC_FB_RES_FORCE_PD); @@ -79,7 +79,7 @@ void rtc_clk_init(rtc_clk_config_t cfg) pmu_ll_hp_set_dcm_vset(&PMU, PMU_MODE_HP_ACTIVE, hp_dcmvset); SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // Hand over control of dbias to pmu esp_rom_delay_us(1000); -#if CONFIG_ESP32P4_REV_MIN_301 +#if (CONFIG_ESP32P4_REV_MIN_FULL >= 301) if (ESP_CHIP_REV_ABOVE(chip_version, 301)) { REG_SET_FIELD(LP_SYSTEM_REG_SYS_CTRL_REG, LP_SYSTEM_REG_LP_FIB_SEL, 0xEF);// lp_fib_sel bit4 set to 0: select dig_fib_reg instead of ana_fib_reg CLEAR_PERI_REG_MASK(PMU_DCM_CTRL_REG, PMU_DCDC_FB_RES_FORCE_PD); diff --git a/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_panel.c b/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_panel.c index 5719c2ef23..ffb4d7dbe9 100644 --- a/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_panel.c +++ b/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_panel.c @@ -330,7 +330,7 @@ TEST_CASE("MIPI DSI draw YUV422 image (EK79007)", "[mipi_dsi]") test_bsp_disable_dsi_phy_power(); } -#if !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_REV_MIN_FULL < 300) +#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 TEST_CASE("MIPI DSI draw Gray8 image (EK79007)", "[mipi_dsi]") { diff --git a/components/esp_psram/system_layer/esp_psram.c b/components/esp_psram/system_layer/esp_psram.c index 8b0251e1e7..1fcb016700 100644 --- a/components/esp_psram/system_layer/esp_psram.c +++ b/components/esp_psram/system_layer/esp_psram.c @@ -167,8 +167,9 @@ static void IRAM_ATTR s_mapping(int v_start, int size) } #endif //CONFIG_IDF_TARGET_ESP32 -#if CONFIG_ESP32P4_REV_MIN_FULL == 300 +#if CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 #include "hal/psram_ctrlr_ll.h" +#include "hal/efuse_hal.h" static void IRAM_ATTR esp_psram_p4_rev3_workaround(void) { spi_mem_s_dev_t backup_reg = {}; @@ -416,8 +417,12 @@ esp_err_t esp_psram_init(void) } } -#if CONFIG_ESP32P4_REV_MIN_FULL == 300 - esp_psram_p4_rev3_workaround(); +#if CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 + // This workaround is only needed for P4 rev 300 (3.0.0) + unsigned chip_revision = efuse_hal_chip_revision(); + if (chip_revision == 300) { + esp_psram_p4_rev3_workaround(); + } #endif uint32_t psram_available_size = 0; diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 8442310c41..2f7e148864 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -671,7 +671,7 @@ NOINLINE_ATTR static void system_early_init(const soc_reset_reason_t *rst_reas) REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING); #endif #elif CONFIG_IDF_TARGET_ESP32P4 -#if CONFIG_ESP32P4_REV_MIN_FULL >= 300 +#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 // In single core mode, the CPU system should ignore the WFI state of core1 when entering WFI autoclock gating mode. REG_CLR_BIT(HP_SYS_CLKRST_CPU_WAITI_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN); #endif diff --git a/components/esp_system/port/soc/esp32p4/system_internal.c b/components/esp_system/port/soc/esp32p4/system_internal.c index a96eb7e45d..80e7feec77 100644 --- a/components/esp_system/port/soc/esp32p4/system_internal.c +++ b/components/esp_system/port/soc/esp32p4/system_internal.c @@ -32,6 +32,7 @@ #include "hal/axi_dma_ll.h" #include "hal/dw_gdma_ll.h" #include "hal/dma2d_ll.h" +#include "hal/efuse_hal.h" void esp_system_reset_modules_on_exit(void) { @@ -123,19 +124,21 @@ void esp_system_reset_modules_on_exit(void) CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_RSA); CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_SHA); -#if CONFIG_ESP32P4_REV_MIN_FULL <= 100 - // enable soc clk and reset parent crypto - SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN); - SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_CRYPTO); - CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_CRYPTO); +#if CONFIG_ESP32P4_REV_MIN_FULL < 101 + if (efuse_hal_chip_revision() < 101) { + // enable soc clk and reset parent crypto + SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN); + SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_CRYPTO); + CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_CRYPTO); - // enable soc clk for key manager - SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN); + // enable soc clk for key manager + SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN); - // enable key manager peripheral clock and reset - SET_PERI_REG_MASK(HP_SYS_CLKRST_PERI_CLK_CTRL25_REG, HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN); - SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_KM); - CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_KM); + // enable key manager peripheral clock and reset + SET_PERI_REG_MASK(HP_SYS_CLKRST_PERI_CLK_CTRL25_REG, HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN); + SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_KM); + CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_KM); + } #endif #if CONFIG_ESP32P4_REV_MIN_FULL == 0