esp32s2: FPGA can boot to Hello World

components/esp_system/port/cpu_start.c

@@ -484,6 +484,7 @@ void IRAM_ATTR call_start_cpu0(void)
 
     intr_matrix_clear();
 
+#ifndef CONFIG_IDF_ENV_FPGA // TODO: on FPGA it should be possible to configure this, not currently working with APB_CLK_FREQ changed
 #ifdef CONFIG_ESP_CONSOLE_UART
     uint32_t clock_hz = rtc_clk_apb_freq_get();
 #if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
@@ -492,6 +493,7 @@ void IRAM_ATTR call_start_cpu0(void)
     esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
     esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
 #endif
+#endif
 
 #if SOC_RTCIO_HOLD_SUPPORTED
     rtcio_hal_unhold_all();

components/esp_system/port/soc/esp32s2/clk.c

@@ -83,8 +83,6 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
     }
     rtc_init(cfg);
 
-    assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
-
     rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);
 
 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
@@ -145,6 +143,9 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
 
 static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
 {
+#ifdef CONFIG_IDF_ENV_FPGA
+    return;
+#endif
     rtc_slow_freq_t rtc_slow_freq = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V;
     uint32_t cal_val = 0;
     /* number of times to repeat 32k XTAL calibration
@@ -283,11 +284,13 @@ __attribute__((weak)) void esp_perip_clk_init(void)
                         DPORT_SPI3_DMA_CLK_EN;
     common_perip_clk1 = 0;
 
+#ifndef CONFIG_IDF_ENV_FPGA
     /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
      * the current is not reduced when disable I2S clock.
      */
     REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
     REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
+#endif // CONFIG_IDF_ENV_FPGA
 
     /* Disable some peripheral clocks. */
     DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, common_perip_clk);