feat(ulp-riscv): Added Kconfig option to enable ULP RISC-V interrupts

This commit adds a Kconfig option, CONFIG_ULP_RISCV_INTERRUPT_ENABLE, to enable interrupts on the ULP RISC-V core on the esp32s2 and esp32s3.
2024-02-12 13:40:57 +01:00
parent 03d6b092c0
commit bc74cf808d
10 changed files with 44 additions and 4 deletions
@@ -2,6 +2,7 @@
 CONFIG_ULP_COPROC_ENABLED=y
 CONFIG_ULP_COPROC_TYPE_RISCV=y
 CONFIG_ULP_COPROC_RESERVE_MEM=4096
+CONFIG_ULP_RISCV_INTERRUPT_ENABLE=y
 # Set log level to Warning to produce clean output
 CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y
 CONFIG_BOOTLOADER_LOG_LEVEL=2