Initial public version
This commit is contained in:
Ivan Grokhotkov
Executable
+102
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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_BB_REG_H_
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#define _SOC_BB_REG_H_
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#define apb_bb_offset 0x6001c000
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#define BB_DLY apb_bb_offset + 0x00009b00 // reg 00
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#define BB_TEST apb_bb_offset + 0x00009b08 // reg 02
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#define BB_TM1 apb_bb_offset + 0x00009b0c // reg 03
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#define BB_TM_CNTL apb_bb_offset + 0x00009b14 // reg 05
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#define BB_DEL_CNTL apb_bb_offset + 0x00009b28 // reg 10
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#define BB_PARAL_CNTL apb_bb_offset + 0x00009b2c // reg 11
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#define BB_FSM1 apb_bb_offset + 0x00009b44 // reg 17
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#define BB_MXG apb_bb_offset + 0x00009b48 // reg 18
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#define BB_MNOF apb_bb_offset + 0x00009b4c // reg 19
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#define BB_SIZE apb_bb_offset + 0x00009b50 // reg 20
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#define BB_TM3a apb_bb_offset + 0x00009b54 // reg 21
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#define BB_TM4a apb_bb_offset + 0x00009b58 // reg 22
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#define BB_GAIN apb_bb_offset + 0x00009b5c // reg 23
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#define BB_CNTL apb_bb_offset + 0x00009b60 // reg 24
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#define BB_CAD apb_bb_offset + 0x00009b64 // reg 25
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#define BB_DET apb_bb_offset + 0x00009b68 // reg 26
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#define BB_DETL apb_bb_offset + 0x00009b6c // reg 27
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#define BB_MASK_PCLL apb_bb_offset + 0x00009d08 // reg 66
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#define BB_MASK_PCLH apb_bb_offset + 0x00009d0c // reg 67
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#define BB_RX_CTRL4 apb_bb_offset + 0x00009d10 // reg 68
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#define BB_RX_CTRL apb_bb_offset + 0x00009d1c // reg 71
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#define BB_RX_CTRL2 apb_bb_offset + 0x00009d20 // reg 72
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#define BB_RX_CTRL3 apb_bb_offset + 0x00009d24 // reg 73
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#define BB_DEL4 apb_bb_offset + 0x00009d40 // reg 80
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#define BB_TM5 apb_bb_offset + 0x00009d44 // reg 81
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#define BB_TM6 apb_bb_offset + 0x00009d48 // reg 82
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#define BB_PMCTRL apb_bb_offset + 0x00009d4c // reg 83
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#define BB_PWR apb_bb_offset + 0x00009d68 // reg 90
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#define BB_BCTRL2 apb_bb_offset + 0x00009d70 // reg 92
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#define BB_MASK_PL apb_bb_offset + 0x00009884 // reg 97
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#define BB_MASK_PCHL apb_bb_offset + 0x00009888 // reg 98
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#define BB_MASK_PCHH apb_bb_offset + 0x0000988c // reg 99
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#define BB_MASK_CL apb_bb_offset + 0x0000989c // reg 103
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#define BB_TONE apb_bb_offset + 0x000098a0 // reg 104
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#define BB_MASK_CH apb_bb_offset + 0x000098d4 // reg 117
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#define BB_SER apb_bb_offset + 0x000098ec // reg 123
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#define BB_GN_TB apb_bb_offset + 0x00009e00 // reg 128
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#define BB_MODE apb_bb_offset + 0x00009c00 // reg 640
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#define BB_TXCTRL apb_bb_offset + 0x00009c04 // reg 641
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#define BB_BCTRL3 apb_bb_offset + 0x00009c08 // reg 642
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#define BB_BCTRL apb_bb_offset + 0x00009c28 // reg 650
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#define BB_SMCTRL apb_bb_offset + 0x00009c48 // reg 658
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#define BB_SMCTRL2 apb_bb_offset + 0x00009c4C // reg 659
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#define BB_TXCNT apb_bb_offset + 0x00009c58 // reg 662
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#define BB_RXCTRL apb_bb_offset + 0x00009c68 // reg 666
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#define BB_TXGAIN apb_bb_offset + 0x00009900 // reg 704
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#define BB_RXS_CNTL apb_bb_offset + 0x00009988 // reg 738
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#define BB_MASK2_PCLL apb_bb_offset + 0x000099a8 // reg 746
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#define BB_MASK2_PCLH apb_bb_offset + 0x000099ac // reg 747
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#define BB_MASK_PH apb_bb_offset + 0x000099b0 // reg 748
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#define BB_MASK2_PCHL apb_bb_offset + 0x000099b8 // reg 750
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#define BB_MASK2_PCHH apb_bb_offset + 0x000099bc // reg 751
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//
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#define BB_TX_TONE_CNTL apb_bb_offset + 0x000099f0 // reg 764
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#define BB_ADD_CNTL0 apb_bb_offset + 0x00009a28 // reg 778
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#define BB_ADD_CNTL2 apb_bb_offset + 0x00009a2c // reg 779
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#define BB_GAIN_CNTL0 apb_bb_offset + 0x00009a34 // reg 781
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#define BB_GAIN_CNTL1 apb_bb_offset + 0x00009a38 // reg 782
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#define BB_GAIN_CNTL2 apb_bb_offset + 0x00009a3c // reg 783
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#define BB_AGCMEM_CTRL apb_bb_offset + 0x00009a68 // reg 794
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#define BB_11B_RECORD apb_bb_offset + 0x00009808 // reg 802
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#define BB_FILTER_CNTL apb_bb_offset + 0x0000980c // reg 803
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#define BB_ANALOG_CTRL1 apb_bb_offset + 0x00009838
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#define BB_ANALOG_CTRL2 apb_bb_offset + 0x0000983c //reg 815
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#define BB_ANALOG_CTRL3 apb_bb_offset + 0x00009840 //reg 816
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#define BB_RFCFG_CTRL0 apb_bb_offset + 0x00009844 //reg 817
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#define BB_RFCFG_CTRL1 apb_bb_offset + 0x00009848 //reg 818
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#define BB_ADD_CNTL1 apb_bb_offset + 0x00009860 //reg824
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#define BB_PA_CNTL apb_bb_offset + 0x00009864 //reg825
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#define BB_RFCFG_CTRL2 apb_bb_offset + 0x0000986c //reg827
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#define BB_RXDEL_CTRL apb_bb_offset + 0x00009d18
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#define BB_RXLENGTH_CTRL apb_bb_offset + 0x00009d1c
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#endif /* _SOC_BB_REG_H_ */
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Executable
+104
@@ -0,0 +1,104 @@
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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_BOOT_MODE_H_
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#define _SOC_BOOT_MODE_H_
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#include "soc.h"
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/*SPI Boot*/
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#define IS_1XXXX(v) (((v)&0x10)==0x10)
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/*HSPI Boot*/
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#define IS_010XX(v) (((v)&0x1c)==0x08)
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/*Download Boot, SDIO/UART0/UART1*/
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#define IS_00XXX(v) (((v)&0x18)==0x00)
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/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/
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#define IS_00X00(v) (((v)&0x1b)==0x00)
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/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/
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#define IS_00X01(v) (((v)&0x1b)==0x01)
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/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/
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#define IS_00X10(v) (((v)&0x1b)==0x02)
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/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/
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#define IS_00X11(v) (((v)&0x1b)==0x03)
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/*ATE/ANALOG Mode*/
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#define IS_01110(v) (((v)&0x1f)==0x0e)
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/*Diagnostic Mode+UART0 download Mode*/
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#define IS_01111(v) (((v)&0x1f)==0x0f)
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/*legacy SPI Boot*/
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#define IS_01100(v) (((v)&0x1f)==0x0c)
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/*SDIO_Slave download Mode V1.1*/
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#define IS_01101(v) (((v)&0x1f)==0x0d)
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#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP))
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/*do not include download mode*/
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#define ETS_IS_UART_BOOT() IS_01111(BOOT_MODE_GET())
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/*all spi boot including spi/hspi/legacy*/
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#define ETS_IS_FLASH_BOOT() (IS_1XXXX(BOOT_MODE_GET()) || IS_010XX(BOOT_MODE_GET()) || IS_01100(BOOT_MODE_GET()))
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/*all faster spi boot including spi/hspi*/
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#define ETS_IS_FAST_FLASH_BOOT() (IS_1XXXX(BOOT_MODE_GET()) || IS_010XX(BOOT_MODE_GET()))
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/*all spi boot including spi/legacy*/
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#define ETS_IS_SPI_FLASH_BOOT() (IS_1XXXX(BOOT_MODE_GET()) || IS_01100(BOOT_MODE_GET()))
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/*all spi boot including hspi/legacy*/
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#define ETS_IS_HSPI_FLASH_BOOT() IS_010XX(BOOT_MODE_GET())
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/*all sdio V2 of failing edge input, failing edge output*/
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#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_00X00(BOOT_MODE_GET())
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/*all sdio V2 of failing edge input, raising edge output*/
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#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_00X01(BOOT_MODE_GET())
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/*all sdio V2 of raising edge input, failing edge output*/
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#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_00X10(BOOT_MODE_GET())
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/*all sdio V2 of raising edge input, raising edge output*/
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#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_00X11(BOOT_MODE_GET())
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/*all sdio V1 of raising edge input, failing edge output*/
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#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_01101(BOOT_MODE_GET())
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/*do not include download mode*/
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#define ETS_IS_SDIO_BOOT() IS_01101(BOOT_MODE_GET())
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/*joint download boot*/
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#define ETS_IS_SDIO_UART_BOOT() IS_00XXX(BOOT_MODE_GET())
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/*ATE mode*/
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#define ETS_IS_ATE_BOOT() IS_01110(BOOT_MODE_GET())
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/*A bit to control flash boot print*/
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#define ETS_IS_PRINT_BOOT() (BOOT_MODE_GET() & 0x2)
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/*used by ETS_IS_SDIO_UART_BOOT*/
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#define SEL_NO_BOOT 0
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#define SEL_SDIO_BOOT BIT0
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#define SEL_UART_BOOT BIT1
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#endif /* _SOC_BOOT_MODE_H_ */
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,422 @@
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_EFUSE_REG_H_
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#define _SOC_EFUSE_REG_H_
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#include "soc.h"
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#define EFUSE_BLK0_RDATA0 (DR_REG_EFUSE_BASE + 0x000)
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#define EFUSE_RD_FLASH_CRYPT_CNT 0x000000FF
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#define EFUSE_RD_FLASH_CRYPT_CNT_S 20
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#define EFUSE_RD_EFUSE_RD_DIS 0x0000000F
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#define EFUSE_RD_EFUSE_RD_DIS_S 16
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#define EFUSE_RD_EFUSE_WR_DIS 0x0000FFFF
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#define EFUSE_RD_EFUSE_WR_DIS_S 0
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#define EFUSE_BLK0_RDATA1 (DR_REG_EFUSE_BASE + 0x004)
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#define EFUSE_RD_WIFI_MAC_CRC_LOW 0xFFFFFFFF
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#define EFUSE_RD_WIFI_MAC_CRC_LOW_S 0
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#define EFUSE_BLK0_RDATA2 (DR_REG_EFUSE_BASE + 0x008)
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#define EFUSE_RD_WIFI_MAC_CRC_HIGH 0x00FFFFFF
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#define EFUSE_RD_WIFI_MAC_CRC_HIGH_S 0
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#define EFUSE_BLK0_RDATA3 (DR_REG_EFUSE_BASE + 0x00c)
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#define EFUSE_RD_CHIP_VER_RESERVE 0x00001FFF
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#define EFUSE_RD_CHIP_VER_RESERVE_S 4
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#define EFUSE_RD_CHIP_VER_DIS_CACHE (BIT(3))
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#define EFUSE_RD_CHIP_VER_DIS_CACHE_S 3
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#define EFUSE_RD_CHIP_VER_32PAD (BIT(2))
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#define EFUSE_RD_CHIP_VER_32PAD_S 2
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#define EFUSE_RD_CHIP_VER_DIS_BT (BIT(1))
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#define EFUSE_RD_CHIP_VER_DIS_BT_S 1
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#define EFUSE_RD_CHIP_VER_DIS_APP_CPU (BIT(0))
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#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_S 0
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#define EFUSE_BLK0_RDATA4 (DR_REG_EFUSE_BASE + 0x010)
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#define EFUSE_RD_SDIO_FORCE (BIT(16))
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#define EFUSE_RD_SDIO_FORCE_S 16
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#define EFUSE_RD_SDIO_TIEH (BIT(15))
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#define EFUSE_RD_SDIO_TIEH_S 15
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#define EFUSE_RD_XPD_SDIO_REG (BIT(14))
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#define EFUSE_RD_XPD_SDIO_REG_S 14
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#define EFUSE_RD_SDIO_DREFL 0x00000003
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#define EFUSE_RD_SDIO_DREFL_S 12
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#define EFUSE_RD_SDIO_DREFM 0x00000003
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#define EFUSE_RD_SDIO_DREFM_S 10
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#define EFUSE_RD_SDIO_DREFH 0x00000003
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#define EFUSE_RD_SDIO_DREFH_S 8
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#define EFUSE_RD_CK8M_FREQ 0x000000FF
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#define EFUSE_RD_CK8M_FREQ_S 0
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#define EFUSE_BLK0_RDATA5 (DR_REG_EFUSE_BASE + 0x014)
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#define EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000F
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#define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28
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#define EFUSE_RD_INST_CONFIG 0x000000FF
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#define EFUSE_RD_INST_CONFIG_S 20
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#define EFUSE_RD_SPI_PAD_CONFIG 0x000FFFFF
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#define EFUSE_RD_SPI_PAD_CONFIG_S 0
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#define EFUSE_BLK0_RDATA6 (DR_REG_EFUSE_BASE + 0x018)
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#define EFUSE_RD_KEY_STATUS (BIT(10))
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#define EFUSE_RD_KEY_STATUS_S 10
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#define EFUSE_RD_DISABLE_DL_CACHE (BIT(9))
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#define EFUSE_RD_DISABLE_DL_CACHE_S 9
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#define EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8))
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#define EFUSE_RD_DISABLE_DL_DECRYPT_S 8
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#define EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7))
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#define EFUSE_RD_DISABLE_DL_ENCRYPT_S 7
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#define EFUSE_RD_DISABLE_JTAG (BIT(6))
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#define EFUSE_RD_DISABLE_JTAG_S 6
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#define EFUSE_RD_ABS_DONE_1 (BIT(5))
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#define EFUSE_RD_ABS_DONE_1_S 5
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#define EFUSE_RD_ABS_DONE_0 (BIT(4))
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#define EFUSE_RD_ABS_DONE_0_S 4
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#define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3))
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#define EFUSE_RD_DISABLE_SDIO_HOST_S 3
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#define EFUSE_RD_DIG_RESERVE (BIT(2))
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#define EFUSE_RD_DIG_RESERVE_S 2
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#define EFUSE_RD_CODING_SCHEME 0x00000003
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#define EFUSE_RD_CODING_SCHEME_S 0
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#define EFUSE_BLK0_WDATA0 (DR_REG_EFUSE_BASE + 0x01c)
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#define EFUSE_FLASH_CRYPT_CNT 0x000000FF
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#define EFUSE_FLASH_CRYPT_CNT_S 20
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#define EFUSE_EFUSE_RD_DIS 0x0000000F
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#define EFUSE_EFUSE_RD_DIS_S 16
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#define EFUSE_EFUSE_WR_DIS 0x0000FFFF
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#define EFUSE_EFUSE_WR_DIS_S 0
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#define EFUSE_BLK0_WDATA1 (DR_REG_EFUSE_BASE + 0x020)
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#define EFUSE_WIFI_MAC_CRC_LOW 0xFFFFFFFF
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#define EFUSE_WIFI_MAC_CRC_LOW_S 0
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#define EFUSE_BLK0_WDATA2 (DR_REG_EFUSE_BASE + 0x024)
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#define EFUSE_WIFI_MAC_CRC_HIGH 0x00FFFFFF
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#define EFUSE_WIFI_MAC_CRC_HIGH_S 0
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#define EFUSE_BLK0_WDATA3 (DR_REG_EFUSE_BASE + 0x028)
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#define EFUSE_CHIP_VER_RESERVE 0x00001FFF
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#define EFUSE_CHIP_VER_RESERVE_S 4
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#define EFUSE_CHIP_VER_DIS_CACHE (BIT(3))
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#define EFUSE_CHIP_VER_DIS_CACHE_S 3
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#define EFUSE_CHIP_VER_32PAD (BIT(2))
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#define EFUSE_CHIP_VER_32PAD_S 2
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#define EFUSE_CHIP_VER_DIS_BT (BIT(1))
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#define EFUSE_CHIP_VER_DIS_BT_S 1
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#define EFUSE_CHIP_VER_DIS_APP_CPU (BIT(0))
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#define EFUSE_CHIP_VER_DIS_APP_CPU_S 0
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#define EFUSE_BLK0_WDATA4 (DR_REG_EFUSE_BASE + 0x02c)
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#define EFUSE_SDIO_FORCE (BIT(16))
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#define EFUSE_SDIO_FORCE_S 16
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#define EFUSE_SDIO_TIEH (BIT(15))
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#define EFUSE_SDIO_TIEH_S 15
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#define EFUSE_XPD_SDIO_REG (BIT(14))
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#define EFUSE_XPD_SDIO_REG_S 14
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#define EFUSE_SDIO_DREFL 0x00000003
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#define EFUSE_SDIO_DREFL_S 12
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#define EFUSE_SDIO_DREFM 0x00000003
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#define EFUSE_SDIO_DREFM_S 10
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#define EFUSE_SDIO_DREFH 0x00000003
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#define EFUSE_SDIO_DREFH_S 8
|
||||
#define EFUSE_CK8M_FREQ 0x000000FF
|
||||
#define EFUSE_CK8M_FREQ_S 0
|
||||
|
||||
#define EFUSE_BLK0_WDATA5 (DR_REG_EFUSE_BASE + 0x030)
|
||||
#define EFUSE_FLASH_CRYPT_CONFIG 0x0000000F
|
||||
#define EFUSE_FLASH_CRYPT_CONFIG_S 28
|
||||
#define EFUSE_INST_CONFIG 0x000000FF
|
||||
#define EFUSE_INST_CONFIG_S 20
|
||||
#define EFUSE_SPI_PAD_CONFIG 0x000FFFFF
|
||||
#define EFUSE_SPI_PAD_CONFIG_S 0
|
||||
|
||||
#define EFUSE_BLK0_WDATA6 (DR_REG_EFUSE_BASE + 0x034)
|
||||
#define EFUSE_KEY_STATUS (BIT(10))
|
||||
#define EFUSE_KEY_STATUS_S 10
|
||||
#define EFUSE_DISABLE_DL_CACHE (BIT(9))
|
||||
#define EFUSE_DISABLE_DL_CACHE_S 9
|
||||
#define EFUSE_DISABLE_DL_DECRYPT (BIT(8))
|
||||
#define EFUSE_DISABLE_DL_DECRYPT_S 8
|
||||
#define EFUSE_DISABLE_DL_ENCRYPT (BIT(7))
|
||||
#define EFUSE_DISABLE_DL_ENCRYPT_S 7
|
||||
#define EFUSE_DISABLE_JTAG (BIT(6))
|
||||
#define EFUSE_DISABLE_JTAG_S 6
|
||||
#define EFUSE_ABS_DONE_1 (BIT(5))
|
||||
#define EFUSE_ABS_DONE_1_S 5
|
||||
#define EFUSE_ABS_DONE_0 (BIT(4))
|
||||
#define EFUSE_ABS_DONE_0_S 4
|
||||
#define EFUSE_DISABLE_SDIO_HOST (BIT(3))
|
||||
#define EFUSE_DISABLE_SDIO_HOST_S 3
|
||||
#define EFUSE_DIG_RESERVE (BIT(2))
|
||||
#define EFUSE_DIG_RESERVE_S 2
|
||||
#define EFUSE_CODING_SCHEME 0x00000003
|
||||
#define EFUSE_CODING_SCHEME_S 0
|
||||
|
||||
#define EFUSE_BLK1_RDATA0 (DR_REG_EFUSE_BASE + 0x038)
|
||||
#define EFUSE_EFUSE_BLK1_DOUT0 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK1_DOUT0_S 0
|
||||
|
||||
#define EFUSE_BLK1_RDATA1 (DR_REG_EFUSE_BASE + 0x03c)
|
||||
#define EFUSE_EFUSE_BLK1_DOUT1 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK1_DOUT1_S 0
|
||||
|
||||
#define EFUSE_BLK1_RDATA2 (DR_REG_EFUSE_BASE + 0x040)
|
||||
#define EFUSE_EFUSE_BLK1_DOUT2 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK1_DOUT2_S 0
|
||||
|
||||
#define EFUSE_BLK1_RDATA3 (DR_REG_EFUSE_BASE + 0x044)
|
||||
#define EFUSE_EFUSE_BLK1_DOUT3 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK1_DOUT3_S 0
|
||||
|
||||
#define EFUSE_BLK1_RDATA4 (DR_REG_EFUSE_BASE + 0x048)
|
||||
#define EFUSE_EFUSE_BLK1_DOUT4 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK1_DOUT4_S 0
|
||||
|
||||
#define EFUSE_BLK1_RDATA5 (DR_REG_EFUSE_BASE + 0x04c)
|
||||
#define EFUSE_EFUSE_BLK1_DOUT5 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK1_DOUT5_S 0
|
||||
|
||||
#define EFUSE_BLK1_RDATA6 (DR_REG_EFUSE_BASE + 0x050)
|
||||
#define EFUSE_EFUSE_BLK1_DOUT6 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK1_DOUT6_S 0
|
||||
|
||||
#define EFUSE_BLK1_RDATA7 (DR_REG_EFUSE_BASE + 0x054)
|
||||
#define EFUSE_EFUSE_BLK1_DOUT7 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK1_DOUT7_S 0
|
||||
|
||||
#define EFUSE_BLK2_RDATA0 (DR_REG_EFUSE_BASE + 0x058)
|
||||
#define EFUSE_EFUSE_BLK2_DOUT0 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK2_DOUT0_S 0
|
||||
|
||||
#define EFUSE_BLK2_RDATA1 (DR_REG_EFUSE_BASE + 0x05c)
|
||||
#define EFUSE_EFUSE_BLK2_DOUT1 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK2_DOUT1_S 0
|
||||
|
||||
#define EFUSE_BLK2_RDATA2 (DR_REG_EFUSE_BASE + 0x060)
|
||||
#define EFUSE_EFUSE_BLK2_DOUT2 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK2_DOUT2_S 0
|
||||
|
||||
#define EFUSE_BLK2_RDATA3 (DR_REG_EFUSE_BASE + 0x064)
|
||||
#define EFUSE_EFUSE_BLK2_DOUT3 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK2_DOUT3_S 0
|
||||
|
||||
#define EFUSE_BLK2_RDATA4 (DR_REG_EFUSE_BASE + 0x068)
|
||||
#define EFUSE_EFUSE_BLK2_DOUT4 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK2_DOUT4_S 0
|
||||
|
||||
#define EFUSE_BLK2_RDATA5 (DR_REG_EFUSE_BASE + 0x06c)
|
||||
#define EFUSE_EFUSE_BLK2_DOUT5 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK2_DOUT5_S 0
|
||||
|
||||
#define EFUSE_BLK2_RDATA6 (DR_REG_EFUSE_BASE + 0x070)
|
||||
#define EFUSE_EFUSE_BLK2_DOUT6 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK2_DOUT6_S 0
|
||||
|
||||
#define EFUSE_BLK2_RDATA7 (DR_REG_EFUSE_BASE + 0x074)
|
||||
#define EFUSE_EFUSE_BLK2_DOUT7 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK2_DOUT7_S 0
|
||||
|
||||
#define EFUSE_BLK3_RDATA0 (DR_REG_EFUSE_BASE + 0x078)
|
||||
#define EFUSE_EFUSE_BLK3_DOUT0 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK3_DOUT0_S 0
|
||||
|
||||
#define EFUSE_BLK3_RDATA1 (DR_REG_EFUSE_BASE + 0x07c)
|
||||
#define EFUSE_EFUSE_BLK3_DOUT1 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK3_DOUT1_S 0
|
||||
|
||||
#define EFUSE_BLK3_RDATA2 (DR_REG_EFUSE_BASE + 0x080)
|
||||
#define EFUSE_EFUSE_BLK3_DOUT2 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK3_DOUT2_S 0
|
||||
|
||||
#define EFUSE_BLK3_RDATA3 (DR_REG_EFUSE_BASE + 0x084)
|
||||
#define EFUSE_EFUSE_BLK3_DOUT3 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK3_DOUT3_S 0
|
||||
|
||||
#define EFUSE_BLK3_RDATA4 (DR_REG_EFUSE_BASE + 0x088)
|
||||
#define EFUSE_EFUSE_BLK3_DOUT4 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK3_DOUT4_S 0
|
||||
|
||||
#define EFUSE_BLK3_RDATA5 (DR_REG_EFUSE_BASE + 0x08c)
|
||||
#define EFUSE_EFUSE_BLK3_DOUT5 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK3_DOUT5_S 0
|
||||
|
||||
#define EFUSE_BLK3_RDATA6 (DR_REG_EFUSE_BASE + 0x090)
|
||||
#define EFUSE_EFUSE_BLK3_DOUT6 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK3_DOUT6_S 0
|
||||
|
||||
#define EFUSE_BLK3_RDATA7 (DR_REG_EFUSE_BASE + 0x094)
|
||||
#define EFUSE_EFUSE_BLK3_DOUT7 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK3_DOUT7_S 0
|
||||
|
||||
#define EFUSE_BLK1_WDATA0 (DR_REG_EFUSE_BASE + 0x098)
|
||||
#define EFUSE_EFUSE_BLK1_DIN0 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK1_DIN0_S 0
|
||||
|
||||
#define EFUSE_BLK1_WDATA1 (DR_REG_EFUSE_BASE + 0x09c)
|
||||
#define EFUSE_EFUSE_BLK1_DIN1 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK1_DIN1_S 0
|
||||
|
||||
#define EFUSE_BLK1_WDATA2 (DR_REG_EFUSE_BASE + 0x0a0)
|
||||
#define EFUSE_EFUSE_BLK1_DIN2 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK1_DIN2_S 0
|
||||
|
||||
#define EFUSE_BLK1_WDATA3 (DR_REG_EFUSE_BASE + 0x0a4)
|
||||
#define EFUSE_EFUSE_BLK1_DIN3 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK1_DIN3_S 0
|
||||
|
||||
#define EFUSE_BLK1_WDATA4 (DR_REG_EFUSE_BASE + 0x0a8)
|
||||
#define EFUSE_EFUSE_BLK1_DIN4 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK1_DIN4_S 0
|
||||
|
||||
#define EFUSE_BLK1_WDATA5 (DR_REG_EFUSE_BASE + 0x0ac)
|
||||
#define EFUSE_EFUSE_BLK1_DIN5 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK1_DIN5_S 0
|
||||
|
||||
#define EFUSE_BLK1_WDATA6 (DR_REG_EFUSE_BASE + 0x0b0)
|
||||
#define EFUSE_EFUSE_BLK1_DIN6 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK1_DIN6_S 0
|
||||
|
||||
#define EFUSE_BLK1_WDATA7 (DR_REG_EFUSE_BASE + 0x0b4)
|
||||
#define EFUSE_EFUSE_BLK1_DIN7 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK1_DIN7_S 0
|
||||
|
||||
#define EFUSE_BLK2_WDATA0 (DR_REG_EFUSE_BASE + 0x0b8)
|
||||
#define EFUSE_EFUSE_BLK2_DIN0 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK2_DIN0_S 0
|
||||
|
||||
#define EFUSE_BLK2_WDATA1 (DR_REG_EFUSE_BASE + 0x0bc)
|
||||
#define EFUSE_EFUSE_BLK2_DIN1 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK2_DIN1_S 0
|
||||
|
||||
#define EFUSE_BLK2_WDATA2 (DR_REG_EFUSE_BASE + 0x0c0)
|
||||
#define EFUSE_EFUSE_BLK2_DIN2 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK2_DIN2_S 0
|
||||
|
||||
#define EFUSE_BLK2_WDATA3 (DR_REG_EFUSE_BASE + 0x0c4)
|
||||
#define EFUSE_EFUSE_BLK2_DIN3 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK2_DIN3_S 0
|
||||
|
||||
#define EFUSE_BLK2_WDATA4 (DR_REG_EFUSE_BASE + 0x0c8)
|
||||
#define EFUSE_EFUSE_BLK2_DIN4 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK2_DIN4_S 0
|
||||
|
||||
#define EFUSE_BLK2_WDATA5 (DR_REG_EFUSE_BASE + 0x0cc)
|
||||
#define EFUSE_EFUSE_BLK2_DIN5 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK2_DIN5_S 0
|
||||
|
||||
#define EFUSE_BLK2_WDATA6 (DR_REG_EFUSE_BASE + 0x0d0)
|
||||
#define EFUSE_EFUSE_BLK2_DIN6 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK2_DIN6_S 0
|
||||
|
||||
#define EFUSE_BLK2_WDATA7 (DR_REG_EFUSE_BASE + 0x0d4)
|
||||
#define EFUSE_EFUSE_BLK2_DIN7 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK2_DIN7_S 0
|
||||
|
||||
#define EFUSE_BLK3_WDATA0 (DR_REG_EFUSE_BASE + 0x0d8)
|
||||
#define EFUSE_EFUSE_BLK3_DIN0 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK3_DIN0_S 0
|
||||
|
||||
#define EFUSE_BLK3_WDATA1 (DR_REG_EFUSE_BASE + 0x0dc)
|
||||
#define EFUSE_EFUSE_BLK3_DIN1 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK3_DIN1_S 0
|
||||
|
||||
#define EFUSE_BLK3_WDATA2 (DR_REG_EFUSE_BASE + 0x0e0)
|
||||
#define EFUSE_EFUSE_BLK3_DIN2 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK3_DIN2_S 0
|
||||
|
||||
#define EFUSE_BLK3_WDATA3 (DR_REG_EFUSE_BASE + 0x0e4)
|
||||
#define EFUSE_EFUSE_BLK3_DIN3 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK3_DIN3_S 0
|
||||
|
||||
#define EFUSE_BLK3_WDATA4 (DR_REG_EFUSE_BASE + 0x0e8)
|
||||
#define EFUSE_EFUSE_BLK3_DIN4 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK3_DIN4_S 0
|
||||
|
||||
#define EFUSE_BLK3_WDATA5 (DR_REG_EFUSE_BASE + 0x0ec)
|
||||
#define EFUSE_EFUSE_BLK3_DIN5 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK3_DIN5_S 0
|
||||
|
||||
#define EFUSE_BLK3_WDATA6 (DR_REG_EFUSE_BASE + 0x0f0)
|
||||
#define EFUSE_EFUSE_BLK3_DIN6 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK3_DIN6_S 0
|
||||
|
||||
#define EFUSE_BLK3_WDATA7 (DR_REG_EFUSE_BASE + 0x0f4)
|
||||
#define EFUSE_EFUSE_BLK3_DIN7 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_BLK3_DIN7_S 0
|
||||
|
||||
#define EFUSE_CLK (DR_REG_EFUSE_BASE + 0x0f8)
|
||||
#define EFUSE_CLK_EN (BIT(16))
|
||||
#define EFUSE_CLK_EN_S 16
|
||||
#define EFUSE_EFUSE_CLK_SEL1 0x000000FF
|
||||
#define EFUSE_EFUSE_CLK_SEL1_S 8
|
||||
#define EFUSE_EFUSE_CLK_SEL0 0x000000FF
|
||||
#define EFUSE_EFUSE_CLK_SEL0_S 0
|
||||
|
||||
#define EFUSE_CONF (DR_REG_EFUSE_BASE + 0x0fc)
|
||||
#define EFUSE_EFUSE_FORCE_NO_WR_RD_DIS (BIT(16))
|
||||
#define EFUSE_EFUSE_FORCE_NO_WR_RD_DIS_S 16
|
||||
#define EFUSE_EFUSE_OP_CODE 0x0000FFFF
|
||||
#define EFUSE_EFUSE_OP_CODE_S 0
|
||||
|
||||
#define EFUSE_STATUS (DR_REG_EFUSE_BASE + 0x100)
|
||||
#define EFUSE_EFUSE_DEBUG 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_DEBUG_S 0
|
||||
|
||||
#define EFUSE_CMD (DR_REG_EFUSE_BASE + 0x104)
|
||||
#define EFUSE_EFUSE_PGM_CMD (BIT(1))
|
||||
#define EFUSE_EFUSE_PGM_CMD_S 1
|
||||
#define EFUSE_EFUSE_READ_CMD (BIT(0))
|
||||
#define EFUSE_EFUSE_READ_CMD_S 0
|
||||
|
||||
#define EFUSE_INT_RAW (DR_REG_EFUSE_BASE + 0x108)
|
||||
#define EFUSE_EFUSE_PGM_DONE_INT_RAW (BIT(1))
|
||||
#define EFUSE_EFUSE_PGM_DONE_INT_RAW_S 1
|
||||
#define EFUSE_EFUSE_READ_DONE_INT_RAW (BIT(0))
|
||||
#define EFUSE_EFUSE_READ_DONE_INT_RAW_S 0
|
||||
|
||||
#define EFUSE_INT_ST (DR_REG_EFUSE_BASE + 0x10c)
|
||||
#define EFUSE_EFUSE_PGM_DONE_INT_ST (BIT(1))
|
||||
#define EFUSE_EFUSE_PGM_DONE_INT_ST_S 1
|
||||
#define EFUSE_EFUSE_READ_DONE_INT_ST (BIT(0))
|
||||
#define EFUSE_EFUSE_READ_DONE_INT_ST_S 0
|
||||
|
||||
#define EFUSE_INT_ENA (DR_REG_EFUSE_BASE + 0x110)
|
||||
#define EFUSE_EFUSE_PGM_DONE_INT_ENA (BIT(1))
|
||||
#define EFUSE_EFUSE_PGM_DONE_INT_ENA_S 1
|
||||
#define EFUSE_EFUSE_READ_DONE_INT_ENA (BIT(0))
|
||||
#define EFUSE_EFUSE_READ_DONE_INT_ENA_S 0
|
||||
|
||||
#define EFUSE_INT_CLR (DR_REG_EFUSE_BASE + 0x114)
|
||||
#define EFUSE_EFUSE_PGM_DONE_INT_CLR (BIT(1))
|
||||
#define EFUSE_EFUSE_PGM_DONE_INT_CLR_S 1
|
||||
#define EFUSE_EFUSE_READ_DONE_INT_CLR (BIT(0))
|
||||
#define EFUSE_EFUSE_READ_DONE_INT_CLR_S 0
|
||||
|
||||
#define EFUSE_DAC_CONF (DR_REG_EFUSE_BASE + 0x118)
|
||||
#define EFUSE_EFUSE_DAC_CLK_PAD_SEL (BIT(8))
|
||||
#define EFUSE_EFUSE_DAC_CLK_PAD_SEL_S 8
|
||||
#define EFUSE_EFUSE_DAC_CLK_DIV 0x000000FF
|
||||
#define EFUSE_EFUSE_DAC_CLK_DIV_S 0
|
||||
|
||||
#define EFUSE_DEC_STATUS (DR_REG_EFUSE_BASE + 0x11c)
|
||||
#define EFUSE_EFUSE_DEC_WARNINGS 0x00000FFF
|
||||
#define EFUSE_EFUSE_DEC_WARNINGS_S 0
|
||||
|
||||
#define EFUSE_DATE (DR_REG_EFUSE_BASE + 0x1FC)
|
||||
#define EFUSE_EFUSE_DATE 0xFFFFFFFF
|
||||
#define EFUSE_EFUSE_DATE_S 0
|
||||
#define EFUSE_EFUSE_DATE_VERSION 0x16042600
|
||||
|
||||
#endif /* _SOC_EFUSE_REG_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,80 @@
|
||||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_GPIO_SD_REG_H_
|
||||
#define _SOC_GPIO_SD_REG_H_
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define SIGMADELTA0 (DR_REG_GPIO_SD_BASE + 0x0000)
|
||||
#define SIGMADELTA_SD0_PRESCALE 0x000000FF
|
||||
#define SIGMADELTA_SD0_PRESCALE_S 8
|
||||
#define SIGMADELTA_SD0_IN 0x000000FF
|
||||
#define SIGMADELTA_SD0_IN_S 0
|
||||
|
||||
#define SIGMADELTA1 (DR_REG_GPIO_SD_BASE + 0x0004)
|
||||
#define SIGMADELTA_SD1_PRESCALE 0x000000FF
|
||||
#define SIGMADELTA_SD1_PRESCALE_S 8
|
||||
#define SIGMADELTA_SD1_IN 0x000000FF
|
||||
#define SIGMADELTA_SD1_IN_S 0
|
||||
|
||||
#define SIGMADELTA2 (DR_REG_GPIO_SD_BASE + 0x0008)
|
||||
#define SIGMADELTA_SD2_PRESCALE 0x000000FF
|
||||
#define SIGMADELTA_SD2_PRESCALE_S 8
|
||||
#define SIGMADELTA_SD2_IN 0x000000FF
|
||||
#define SIGMADELTA_SD2_IN_S 0
|
||||
|
||||
#define SIGMADELTA3 (DR_REG_GPIO_SD_BASE + 0x000c)
|
||||
#define SIGMADELTA_SD3_PRESCALE 0x000000FF
|
||||
#define SIGMADELTA_SD3_PRESCALE_S 8
|
||||
#define SIGMADELTA_SD3_IN 0x000000FF
|
||||
#define SIGMADELTA_SD3_IN_S 0
|
||||
|
||||
#define SIGMADELTA4 (DR_REG_GPIO_SD_BASE + 0x0010)
|
||||
#define SIGMADELTA_SD4_PRESCALE 0x000000FF
|
||||
#define SIGMADELTA_SD4_PRESCALE_S 8
|
||||
#define SIGMADELTA_SD4_IN 0x000000FF
|
||||
#define SIGMADELTA_SD4_IN_S 0
|
||||
|
||||
#define SIGMADELTA5 (DR_REG_GPIO_SD_BASE + 0x0014)
|
||||
#define SIGMADELTA_SD5_PRESCALE 0x000000FF
|
||||
#define SIGMADELTA_SD5_PRESCALE_S 8
|
||||
#define SIGMADELTA_SD5_IN 0x000000FF
|
||||
#define SIGMADELTA_SD5_IN_S 0
|
||||
|
||||
#define SIGMADELTA6 (DR_REG_GPIO_SD_BASE + 0x0018)
|
||||
#define SIGMADELTA_SD6_PRESCALE 0x000000FF
|
||||
#define SIGMADELTA_SD6_PRESCALE_S 8
|
||||
#define SIGMADELTA_SD6_IN 0x000000FF
|
||||
#define SIGMADELTA_SD6_IN_S 0
|
||||
|
||||
#define SIGMADELTA7 (DR_REG_GPIO_SD_BASE + 0x001c)
|
||||
#define SIGMADELTA_SD7_PRESCALE 0x000000FF
|
||||
#define SIGMADELTA_SD7_PRESCALE_S 8
|
||||
#define SIGMADELTA_SD7_IN 0x000000FF
|
||||
#define SIGMADELTA_SD7_IN_S 0
|
||||
|
||||
#define SIGMADELTA_CG (DR_REG_GPIO_SD_BASE + 0x0020)
|
||||
#define SIGMADELTA_GPIO_SD_CLK_EN (BIT(31))
|
||||
#define SIGMADELTA_GPIO_SD_CLK_EN_S 31
|
||||
|
||||
#define SIGMADELTA_MISC (DR_REG_GPIO_SD_BASE + 0x0024)
|
||||
#define SIGMADELTA_SPI_SWAP (BIT(31))
|
||||
#define SIGMADELTA_SPI_SWAP_S 31
|
||||
|
||||
#define SIGMADELTA_VERSION (DR_REG_GPIO_SD_BASE + 0x0028)
|
||||
#define SIGMADELTA_GPIO_SD_DATE 0x0FFFFFFF
|
||||
#define SIGMADELTA_GPIO_SD_DATE_S 0
|
||||
#define SIGMADELTA_GPIO_SD_DATE_VERSION 0x1506190
|
||||
|
||||
#endif /* _SOC_GPIO_SD_REG_H_ */
|
||||
@@ -0,0 +1,422 @@
|
||||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_GPIO_SIG_MAP_H_
|
||||
#define _SOC_GPIO_SIG_MAP_H_
|
||||
|
||||
#define SPICLK_IN_IDX 0
|
||||
#define SPICLK_OUT_IDX 0
|
||||
#define SPIQ_IN_IDX 1
|
||||
#define SPIQ_OUT_IDX 1
|
||||
#define SPID_IN_IDX 2
|
||||
#define SPID_OUT_IDX 2
|
||||
#define SPIHD_IN_IDX 3
|
||||
#define SPIHD_OUT_IDX 3
|
||||
#define SPIWP_IN_IDX 4
|
||||
#define SPIWP_OUT_IDX 4
|
||||
#define SPICS0_IN_IDX 5
|
||||
#define SPICS0_OUT_IDX 5
|
||||
#define SPICS1_IN_IDX 6
|
||||
#define SPICS1_OUT_IDX 6
|
||||
#define SPICS2_IN_IDX 7
|
||||
#define SPICS2_OUT_IDX 7
|
||||
#define HSPICLK_IN_IDX 8
|
||||
#define HSPICLK_OUT_IDX 8
|
||||
#define HSPIQ_IN_IDX 9
|
||||
#define HSPIQ_OUT_IDX 9
|
||||
#define HSPID_IN_IDX 10
|
||||
#define HSPID_OUT_IDX 10
|
||||
#define HSPICS0_IN_IDX 11
|
||||
#define HSPICS0_OUT_IDX 11
|
||||
#define HSPIHD_IN_IDX 12
|
||||
#define HSPIHD_OUT_IDX 12
|
||||
#define HSPIWP_IN_IDX 13
|
||||
#define HSPIWP_OUT_IDX 13
|
||||
#define U0RXD_IN_IDX 14
|
||||
#define U0TXD_OUT_IDX 14
|
||||
#define U0CTS_IN_IDX 15
|
||||
#define U0RTS_OUT_IDX 15
|
||||
#define U0DSR_IN_IDX 16
|
||||
#define U0DTR_OUT_IDX 16
|
||||
#define U1RXD_IN_IDX 17
|
||||
#define U1TXD_OUT_IDX 17
|
||||
#define U1CTS_IN_IDX 18
|
||||
#define U1RTS_OUT_IDX 18
|
||||
#define I2CM_SCL_O_IDX 19
|
||||
#define I2CM_SDA_I_IDX 20
|
||||
#define I2CM_SDA_O_IDX 20
|
||||
#define EXT_I2C_SCL_O_IDX 21
|
||||
#define EXT_I2C_SDA_O_IDX 22
|
||||
#define EXT_I2C_SDA_I_IDX 22
|
||||
#define I2S0O_BCK_IN_IDX 23
|
||||
#define I2S0O_BCK_OUT_IDX 23
|
||||
#define I2S1O_BCK_IN_IDX 24
|
||||
#define I2S1O_BCK_OUT_IDX 24
|
||||
#define I2S0O_WS_IN_IDX 25
|
||||
#define I2S0O_WS_OUT_IDX 25
|
||||
#define I2S1O_WS_IN_IDX 26
|
||||
#define I2S1O_WS_OUT_IDX 26
|
||||
#define I2S0I_BCK_IN_IDX 27
|
||||
#define I2S0I_BCK_OUT_IDX 27
|
||||
#define I2S0I_WS_IN_IDX 28
|
||||
#define I2S0I_WS_OUT_IDX 28
|
||||
#define I2CEXT0_SCL_IN_IDX 29
|
||||
#define I2CEXT0_SCL_OUT_IDX 29
|
||||
#define I2CEXT0_SDA_IN_IDX 30
|
||||
#define I2CEXT0_SDA_OUT_IDX 30
|
||||
#define PWM0_SYNC0_IN_IDX 31
|
||||
#define SDIO_TOHOST_INT_OUT_IDX 31
|
||||
#define PWM0_SYNC1_IN_IDX 32
|
||||
#define PWM0_OUT0A_IDX 32
|
||||
#define PWM0_SYNC2_IN_IDX 33
|
||||
#define PWM0_OUT0B_IDX 33
|
||||
#define PWM0_F0_IN_IDX 34
|
||||
#define PWM0_OUT1A_IDX 34
|
||||
#define PWM0_F1_IN_IDX 35
|
||||
#define PWM0_OUT1B_IDX 35
|
||||
#define PWM0_F2_IN_IDX 36
|
||||
#define PWM0_OUT2A_IDX 36
|
||||
#define GPIO_BT_ACTIVE_IDX 37
|
||||
#define PWM0_OUT2B_IDX 37
|
||||
#define GPIO_BT_PRIORITY_IDX 38
|
||||
#define PCNT_SIG_CH0_IN0_IDX 39
|
||||
#define PCNT_SIG_CH1_IN0_IDX 40
|
||||
#define GPIO_WLAN_ACTIVE_IDX 40
|
||||
#define PCNT_CTRL_CH0_IN0_IDX 41
|
||||
#define BB_DIAG0_IDX 41
|
||||
#define PCNT_CTRL_CH1_IN0_IDX 42
|
||||
#define BB_DIAG1_IDX 42
|
||||
#define PCNT_SIG_CH0_IN1_IDX 43
|
||||
#define BB_DIAG2_IDX 43
|
||||
#define PCNT_SIG_CH1_IN1_IDX 44
|
||||
#define BB_DIAG3_IDX 44
|
||||
#define PCNT_CTRL_CH0_IN1_IDX 45
|
||||
#define BB_DIAG4_IDX 45
|
||||
#define PCNT_CTRL_CH1_IN1_IDX 46
|
||||
#define BB_DIAG5_IDX 46
|
||||
#define PCNT_SIG_CH0_IN2_IDX 47
|
||||
#define BB_DIAG6_IDX 47
|
||||
#define PCNT_SIG_CH1_IN2_IDX 48
|
||||
#define BB_DIAG7_IDX 48
|
||||
#define PCNT_CTRL_CH0_IN2_IDX 49
|
||||
#define BB_DIAG8_IDX 49
|
||||
#define PCNT_CTRL_CH1_IN2_IDX 50
|
||||
#define BB_DIAG9_IDX 50
|
||||
#define PCNT_SIG_CH0_IN3_IDX 51
|
||||
#define BB_DIAG10_IDX 51
|
||||
#define PCNT_SIG_CH1_IN3_IDX 52
|
||||
#define BB_DIAG11_IDX 52
|
||||
#define PCNT_CTRL_CH0_IN3_IDX 53
|
||||
#define BB_DIAG12_IDX 53
|
||||
#define PCNT_CTRL_CH1_IN3_IDX 54
|
||||
#define BB_DIAG13_IDX 54
|
||||
#define PCNT_SIG_CH0_IN4_IDX 55
|
||||
#define BB_DIAG14_IDX 55
|
||||
#define PCNT_SIG_CH1_IN4_IDX 56
|
||||
#define BB_DIAG15_IDX 56
|
||||
#define PCNT_CTRL_CH0_IN4_IDX 57
|
||||
#define BB_DIAG16_IDX 57
|
||||
#define PCNT_CTRL_CH1_IN4_IDX 58
|
||||
#define BB_DIAG17_IDX 58
|
||||
#define BB_DIAG18_IDX 59
|
||||
#define BB_DIAG19_IDX 60
|
||||
#define HSPICS1_IN_IDX 61
|
||||
#define HSPICS1_OUT_IDX 61
|
||||
#define HSPICS2_IN_IDX 62
|
||||
#define HSPICS2_OUT_IDX 62
|
||||
#define VSPICLK_IN_IDX 63
|
||||
#define VSPICLK_OUT_MUX_IDX 63
|
||||
#define VSPIQ_IN_IDX 64
|
||||
#define VSPIQ_OUT_IDX 64
|
||||
#define VSPID_IN_IDX 65
|
||||
#define VSPID_OUT_IDX 65
|
||||
#define VSPIHD_IN_IDX 66
|
||||
#define VSPIHD_OUT_IDX 66
|
||||
#define VSPIWP_IN_IDX 67
|
||||
#define VSPIWP_OUT_IDX 67
|
||||
#define VSPICS0_IN_IDX 68
|
||||
#define VSPICS0_OUT_IDX 68
|
||||
#define VSPICS1_IN_IDX 69
|
||||
#define VSPICS1_OUT_IDX 69
|
||||
#define VSPICS2_IN_IDX 70
|
||||
#define VSPICS2_OUT_IDX 70
|
||||
#define PCNT_SIG_CH0_IN5_IDX 71
|
||||
#define LEDC_HS_SIG_OUT0_IDX 71
|
||||
#define PCNT_SIG_CH1_IN5_IDX 72
|
||||
#define LEDC_HS_SIG_OUT1_IDX 72
|
||||
#define PCNT_CTRL_CH0_IN5_IDX 73
|
||||
#define LEDC_HS_SIG_OUT2_IDX 73
|
||||
#define PCNT_CTRL_CH1_IN5_IDX 74
|
||||
#define LEDC_HS_SIG_OUT3_IDX 74
|
||||
#define PCNT_SIG_CH0_IN6_IDX 75
|
||||
#define LEDC_HS_SIG_OUT4_IDX 75
|
||||
#define PCNT_SIG_CH1_IN6_IDX 76
|
||||
#define LEDC_HS_SIG_OUT5_IDX 76
|
||||
#define PCNT_CTRL_CH0_IN6_IDX 77
|
||||
#define LEDC_HS_SIG_OUT6_IDX 77
|
||||
#define PCNT_CTRL_CH1_IN6_IDX 78
|
||||
#define LEDC_HS_SIG_OUT7_IDX 78
|
||||
#define PCNT_SIG_CH0_IN7_IDX 79
|
||||
#define LEDC_LS_SIG_OUT0_IDX 79
|
||||
#define PCNT_SIG_CH1_IN7_IDX 80
|
||||
#define LEDC_LS_SIG_OUT1_IDX 80
|
||||
#define PCNT_CTRL_CH0_IN7_IDX 81
|
||||
#define LEDC_LS_SIG_OUT2_IDX 81
|
||||
#define PCNT_CTRL_CH1_IN7_IDX 82
|
||||
#define LEDC_LS_SIG_OUT3_IDX 82
|
||||
#define RMT_SIG_IN0_IDX 83
|
||||
#define LEDC_LS_SIG_OUT4_IDX 83
|
||||
#define RMT_SIG_IN1_IDX 84
|
||||
#define LEDC_LS_SIG_OUT5_IDX 84
|
||||
#define RMT_SIG_IN2_IDX 85
|
||||
#define LEDC_LS_SIG_OUT6_IDX 85
|
||||
#define RMT_SIG_IN3_IDX 86
|
||||
#define LEDC_LS_SIG_OUT7_IDX 86
|
||||
#define RMT_SIG_IN4_IDX 87
|
||||
#define RMT_SIG_OUT0_IDX 87
|
||||
#define RMT_SIG_IN5_IDX 88
|
||||
#define RMT_SIG_OUT1_IDX 88
|
||||
#define RMT_SIG_IN6_IDX 89
|
||||
#define RMT_SIG_OUT2_IDX 89
|
||||
#define RMT_SIG_IN7_IDX 90
|
||||
#define RMT_SIG_OUT3_IDX 90
|
||||
#define RMT_SIG_OUT4_IDX 91
|
||||
#define RMT_SIG_OUT5_IDX 92
|
||||
#define EXT_ADC_START_IDX 93
|
||||
#define RMT_SIG_OUT6_IDX 93
|
||||
#define CAN_RX_IDX 94
|
||||
#define RMT_SIG_OUT7_IDX 94
|
||||
#define I2CEXT1_SCL_IN_IDX 95
|
||||
#define I2CEXT1_SCL_OUT_IDX 95
|
||||
#define I2CEXT1_SDA_IN_IDX 96
|
||||
#define I2CEXT1_SDA_OUT_IDX 96
|
||||
#define HOST_CARD_DETECT_N_1_IDX 97
|
||||
#define HOST_CCMD_OD_PULLUP_EN_N_IDX 97
|
||||
#define HOST_CARD_DETECT_N_2_IDX 98
|
||||
#define HOST_RST_N_1_IDX 98
|
||||
#define HOST_CARD_WRITE_PRT_1_IDX 99
|
||||
#define HOST_RST_N_2_IDX 99
|
||||
#define HOST_CARD_WRITE_PRT_2_IDX 100
|
||||
#define GPIO_SD0_OUT_IDX 100
|
||||
#define HOST_CARD_INT_N_1_IDX 101
|
||||
#define GPIO_SD1_OUT_IDX 101
|
||||
#define HOST_CARD_INT_N_2_IDX 102
|
||||
#define GPIO_SD2_OUT_IDX 102
|
||||
#define PWM1_SYNC0_IN_IDX 103
|
||||
#define GPIO_SD3_OUT_IDX 103
|
||||
#define PWM1_SYNC1_IN_IDX 104
|
||||
#define GPIO_SD4_OUT_IDX 104
|
||||
#define PWM1_SYNC2_IN_IDX 105
|
||||
#define GPIO_SD5_OUT_IDX 105
|
||||
#define PWM1_F0_IN_IDX 106
|
||||
#define GPIO_SD6_OUT_IDX 106
|
||||
#define PWM1_F1_IN_IDX 107
|
||||
#define GPIO_SD7_OUT_IDX 107
|
||||
#define PWM1_F2_IN_IDX 108
|
||||
#define PWM1_OUT0A_IDX 108
|
||||
#define PWM0_CAP0_IN_IDX 109
|
||||
#define PWM1_OUT0B_IDX 109
|
||||
#define PWM0_CAP1_IN_IDX 110
|
||||
#define PWM1_OUT1A_IDX 110
|
||||
#define PWM0_CAP2_IN_IDX 111
|
||||
#define PWM1_OUT1B_IDX 111
|
||||
#define PWM1_CAP0_IN_IDX 112
|
||||
#define PWM1_OUT2A_IDX 112
|
||||
#define PWM1_CAP1_IN_IDX 113
|
||||
#define PWM1_OUT2B_IDX 113
|
||||
#define PWM1_CAP2_IN_IDX 114
|
||||
#define PWM2_OUT1H_IDX 114
|
||||
#define PWM2_FLTA_IDX 115
|
||||
#define PWM2_OUT1L_IDX 115
|
||||
#define PWM2_FLTB_IDX 116
|
||||
#define PWM2_OUT2H_IDX 116
|
||||
#define PWM2_CAP1_IN_IDX 117
|
||||
#define PWM2_OUT2L_IDX 117
|
||||
#define PWM2_CAP2_IN_IDX 118
|
||||
#define PWM2_OUT3H_IDX 118
|
||||
#define PWM2_CAP3_IN_IDX 119
|
||||
#define PWM2_OUT3L_IDX 119
|
||||
#define PWM3_FLTA_IDX 120
|
||||
#define PWM2_OUT4H_IDX 120
|
||||
#define PWM3_FLTB_IDX 121
|
||||
#define PWM2_OUT4L_IDX 121
|
||||
#define PWM3_CAP1_IN_IDX 122
|
||||
#define PWM3_CAP2_IN_IDX 123
|
||||
#define CAN_TX_IDX 123
|
||||
#define PWM3_CAP3_IN_IDX 124
|
||||
#define CAN_BUS_OFF_ON_IDX 124
|
||||
#define CAN_CLKOUT_IDX 125
|
||||
#define SPID4_IN_IDX 128
|
||||
#define SPID4_OUT_IDX 128
|
||||
#define SPID5_IN_IDX 129
|
||||
#define SPID5_OUT_IDX 129
|
||||
#define SPID6_IN_IDX 130
|
||||
#define SPID6_OUT_IDX 130
|
||||
#define SPID7_IN_IDX 131
|
||||
#define SPID7_OUT_IDX 131
|
||||
#define HSPID4_IN_IDX 132
|
||||
#define HSPID4_OUT_IDX 132
|
||||
#define HSPID5_IN_IDX 133
|
||||
#define HSPID5_OUT_IDX 133
|
||||
#define HSPID6_IN_IDX 134
|
||||
#define HSPID6_OUT_IDX 134
|
||||
#define HSPID7_IN_IDX 135
|
||||
#define HSPID7_OUT_IDX 135
|
||||
#define VSPID4_IN_IDX 136
|
||||
#define VSPID4_OUT_IDX 136
|
||||
#define VSPID5_IN_IDX 137
|
||||
#define VSPID5_OUT_IDX 137
|
||||
#define VSPID6_IN_IDX 138
|
||||
#define VSPID6_OUT_IDX 138
|
||||
#define VSPID7_IN_IDX 139
|
||||
#define VSPID7_OUT_IDX 139
|
||||
#define I2S0I_DATA_IN0_IDX 140
|
||||
#define I2S0O_DATA_OUT0_IDX 140
|
||||
#define I2S0I_DATA_IN1_IDX 141
|
||||
#define I2S0O_DATA_OUT1_IDX 141
|
||||
#define I2S0I_DATA_IN2_IDX 142
|
||||
#define I2S0O_DATA_OUT2_IDX 142
|
||||
#define I2S0I_DATA_IN3_IDX 143
|
||||
#define I2S0O_DATA_OUT3_IDX 143
|
||||
#define I2S0I_DATA_IN4_IDX 144
|
||||
#define I2S0O_DATA_OUT4_IDX 144
|
||||
#define I2S0I_DATA_IN5_IDX 145
|
||||
#define I2S0O_DATA_OUT5_IDX 145
|
||||
#define I2S0I_DATA_IN6_IDX 146
|
||||
#define I2S0O_DATA_OUT6_IDX 146
|
||||
#define I2S0I_DATA_IN7_IDX 147
|
||||
#define I2S0O_DATA_OUT7_IDX 147
|
||||
#define I2S0I_DATA_IN8_IDX 148
|
||||
#define I2S0O_DATA_OUT8_IDX 148
|
||||
#define I2S0I_DATA_IN9_IDX 149
|
||||
#define I2S0O_DATA_OUT9_IDX 149
|
||||
#define I2S0I_DATA_IN10_IDX 150
|
||||
#define I2S0O_DATA_OUT10_IDX 150
|
||||
#define I2S0I_DATA_IN11_IDX 151
|
||||
#define I2S0O_DATA_OUT11_IDX 151
|
||||
#define I2S0I_DATA_IN12_IDX 152
|
||||
#define I2S0O_DATA_OUT12_IDX 152
|
||||
#define I2S0I_DATA_IN13_IDX 153
|
||||
#define I2S0O_DATA_OUT13_IDX 153
|
||||
#define I2S0I_DATA_IN14_IDX 154
|
||||
#define I2S0O_DATA_OUT14_IDX 154
|
||||
#define I2S0I_DATA_IN15_IDX 155
|
||||
#define I2S0O_DATA_OUT15_IDX 155
|
||||
#define I2S0O_DATA_OUT16_IDX 156
|
||||
#define I2S0O_DATA_OUT17_IDX 157
|
||||
#define I2S0O_DATA_OUT18_IDX 158
|
||||
#define I2S0O_DATA_OUT19_IDX 159
|
||||
#define I2S0O_DATA_OUT20_IDX 160
|
||||
#define I2S0O_DATA_OUT21_IDX 161
|
||||
#define I2S0O_DATA_OUT22_IDX 162
|
||||
#define I2S0O_DATA_OUT23_IDX 163
|
||||
#define I2S1I_BCK_IN_IDX 164
|
||||
#define I2S1I_BCK_OUT_IDX 164
|
||||
#define I2S1I_WS_IN_IDX 165
|
||||
#define I2S1I_WS_OUT_IDX 165
|
||||
#define I2S1I_DATA_IN0_IDX 166
|
||||
#define I2S1O_DATA_OUT0_IDX 166
|
||||
#define I2S1I_DATA_IN1_IDX 167
|
||||
#define I2S1O_DATA_OUT1_IDX 167
|
||||
#define I2S1I_DATA_IN2_IDX 168
|
||||
#define I2S1O_DATA_OUT2_IDX 168
|
||||
#define I2S1I_DATA_IN3_IDX 169
|
||||
#define I2S1O_DATA_OUT3_IDX 169
|
||||
#define I2S1I_DATA_IN4_IDX 170
|
||||
#define I2S1O_DATA_OUT4_IDX 170
|
||||
#define I2S1I_DATA_IN5_IDX 171
|
||||
#define I2S1O_DATA_OUT5_IDX 171
|
||||
#define I2S1I_DATA_IN6_IDX 172
|
||||
#define I2S1O_DATA_OUT6_IDX 172
|
||||
#define I2S1I_DATA_IN7_IDX 173
|
||||
#define I2S1O_DATA_OUT7_IDX 173
|
||||
#define I2S1I_DATA_IN8_IDX 174
|
||||
#define I2S1O_DATA_OUT8_IDX 174
|
||||
#define I2S1I_DATA_IN9_IDX 175
|
||||
#define I2S1O_DATA_OUT9_IDX 175
|
||||
#define I2S1I_DATA_IN10_IDX 176
|
||||
#define I2S1O_DATA_OUT10_IDX 176
|
||||
#define I2S1I_DATA_IN11_IDX 177
|
||||
#define I2S1O_DATA_OUT11_IDX 177
|
||||
#define I2S1I_DATA_IN12_IDX 178
|
||||
#define I2S1O_DATA_OUT12_IDX 178
|
||||
#define I2S1I_DATA_IN13_IDX 179
|
||||
#define I2S1O_DATA_OUT13_IDX 179
|
||||
#define I2S1I_DATA_IN14_IDX 180
|
||||
#define I2S1O_DATA_OUT14_IDX 180
|
||||
#define I2S1I_DATA_IN15_IDX 181
|
||||
#define I2S1O_DATA_OUT15_IDX 181
|
||||
#define I2S1O_DATA_OUT16_IDX 182
|
||||
#define I2S1O_DATA_OUT17_IDX 183
|
||||
#define I2S1O_DATA_OUT18_IDX 184
|
||||
#define I2S1O_DATA_OUT19_IDX 185
|
||||
#define I2S1O_DATA_OUT20_IDX 186
|
||||
#define I2S1O_DATA_OUT21_IDX 187
|
||||
#define I2S1O_DATA_OUT22_IDX 188
|
||||
#define I2S1O_DATA_OUT23_IDX 189
|
||||
#define I2S0I_H_SYNC_IDX 190
|
||||
#define PWM3_OUT1H_IDX 190
|
||||
#define I2S0I_V_SYNC_IDX 191
|
||||
#define PWM3_OUT1L_IDX 191
|
||||
#define I2S0I_H_ENABLE_IDX 192
|
||||
#define PWM3_OUT2H_IDX 192
|
||||
#define I2S1I_H_SYNC_IDX 193
|
||||
#define PWM3_OUT2L_IDX 193
|
||||
#define I2S1I_V_SYNC_IDX 194
|
||||
#define PWM3_OUT3H_IDX 194
|
||||
#define I2S1I_H_ENABLE_IDX 195
|
||||
#define PWM3_OUT3L_IDX 195
|
||||
#define PWM3_OUT4H_IDX 196
|
||||
#define PWM3_OUT4L_IDX 197
|
||||
#define U2RXD_IN_IDX 198
|
||||
#define U2TXD_OUT_IDX 198
|
||||
#define U2CTS_IN_IDX 199
|
||||
#define U2RTS_OUT_IDX 199
|
||||
#define EMAC_MDC_I_IDX 200
|
||||
#define EMAC_MDC_O_IDX 200
|
||||
#define EMAC_MDI_I_IDX 201
|
||||
#define EMAC_MDO_O_IDX 201
|
||||
#define EMAC_CRS_I_IDX 202
|
||||
#define EMAC_CRS_O_IDX 202
|
||||
#define EMAC_COL_I_IDX 203
|
||||
#define EMAC_COL_O_IDX 203
|
||||
#define PCMFSYNC_IN_IDX 204
|
||||
#define BT_AUDIO0_IRQ_IDX 204
|
||||
#define PCMCLK_IN_IDX 205
|
||||
#define BT_AUDIO1_IRQ_IDX 205
|
||||
#define PCMDIN_IDX 206
|
||||
#define BT_AUDIO2_IRQ_IDX 206
|
||||
#define BLE_AUDIO0_IRQ_IDX 207
|
||||
#define BLE_AUDIO1_IRQ_IDX 208
|
||||
#define BLE_AUDIO2_IRQ_IDX 209
|
||||
#define PCMFSYNC_OUT_IDX 210
|
||||
#define PCMCLK_OUT_IDX 211
|
||||
#define PCMDOUT_IDX 212
|
||||
#define BLE_AUDIO_SYNC0_P_IDX 213
|
||||
#define BLE_AUDIO_SYNC1_P_IDX 214
|
||||
#define BLE_AUDIO_SYNC2_P_IDX 215
|
||||
#define ANT_SEL0_IDX 216
|
||||
#define ANT_SEL1_IDX 217
|
||||
#define ANT_SEL2_IDX 218
|
||||
#define ANT_SEL3_IDX 219
|
||||
#define ANT_SEL4_IDX 220
|
||||
#define ANT_SEL5_IDX 221
|
||||
#define ANT_SEL6_IDX 222
|
||||
#define ANT_SEL7_IDX 223
|
||||
#define SIG_IN_FUNC224_IDX 224
|
||||
#define SIG_IN_FUNC225_IDX 225
|
||||
#define SIG_IN_FUNC226_IDX 226
|
||||
#define SIG_IN_FUNC227_IDX 227
|
||||
#define SIG_IN_FUNC228_IDX 228
|
||||
|
||||
#endif /* _SOC_GPIO_SIG_MAP_H_ */
|
||||
@@ -0,0 +1,579 @@
|
||||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_I2S_REG_H_
|
||||
#define _SOC_I2S_REG_H_
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define I2SCONF (DR_REG_I2S_BASE + 0x0008)
|
||||
#define I2S_I2S_SIG_LOOPBACK (BIT(18))
|
||||
#define I2S_I2S_SIG_LOOPBACK_S 18
|
||||
#define I2S_RX_MSB_RIGHT (BIT(17))
|
||||
#define I2S_RX_MSB_RIGHT_S 17
|
||||
#define I2S_TX_MSB_RIGHT (BIT(16))
|
||||
#define I2S_TX_MSB_RIGHT_S 16
|
||||
#define I2S_I2S_RX_MONO (BIT(15))
|
||||
#define I2S_I2S_RX_MONO_S 15
|
||||
#define I2S_I2S_TX_MONO (BIT(14))
|
||||
#define I2S_I2S_TX_MONO_S 14
|
||||
#define I2S_I2S_RX_SHORT_SYNC (BIT(13))
|
||||
#define I2S_I2S_RX_SHORT_SYNC_S 13
|
||||
#define I2S_I2S_TX_SHORT_SYNC (BIT(12))
|
||||
#define I2S_I2S_TX_SHORT_SYNC_S 12
|
||||
#define I2S_RX_MSB_SHIFT (BIT(11))
|
||||
#define I2S_RX_MSB_SHIFT_S 11
|
||||
#define I2S_TX_MSB_SHIFT (BIT(10))
|
||||
#define I2S_TX_MSB_SHIFT_S 10
|
||||
#define I2S_RX_RIGHT_FIRST (BIT(9))
|
||||
#define I2S_RX_RIGHT_FIRST_S 9
|
||||
#define I2S_TX_RIGHT_FIRST (BIT(8))
|
||||
#define I2S_TX_RIGHT_FIRST_S 8
|
||||
#define I2S_RX_SLAVE_MOD (BIT(7))
|
||||
#define I2S_RX_SLAVE_MOD_S 7
|
||||
#define I2S_TX_SLAVE_MOD (BIT(6))
|
||||
#define I2S_TX_SLAVE_MOD_S 6
|
||||
#define I2S_I2S_RX_START (BIT(5))
|
||||
#define I2S_I2S_RX_START_S 5
|
||||
#define I2S_I2S_TX_START (BIT(4))
|
||||
#define I2S_I2S_TX_START_S 4
|
||||
#define I2S_I2S_RX_FIFO_RESET (BIT(3))
|
||||
#define I2S_I2S_RX_FIFO_RESET_S 3
|
||||
#define I2S_I2S_TX_FIFO_RESET (BIT(2))
|
||||
#define I2S_I2S_TX_FIFO_RESET_S 2
|
||||
#define I2S_I2S_RX_RESET (BIT(1))
|
||||
#define I2S_I2S_RX_RESET_S 1
|
||||
#define I2S_I2S_TX_RESET (BIT(0))
|
||||
#define I2S_I2S_TX_RESET_S 0
|
||||
|
||||
#define I2SINT_RAW (DR_REG_I2S_BASE + 0x000c)
|
||||
#define I2S_I2S_OUT_TOTAL_EOF_INT_RAW (BIT(16))
|
||||
#define I2S_I2S_OUT_TOTAL_EOF_INT_RAW_S 16
|
||||
#define I2S_I2S_IN_DSCR_EMPTY_INT_RAW (BIT(15))
|
||||
#define I2S_I2S_IN_DSCR_EMPTY_INT_RAW_S 15
|
||||
#define I2S_I2S_OUT_DSCR_ERR_INT_RAW (BIT(14))
|
||||
#define I2S_I2S_OUT_DSCR_ERR_INT_RAW_S 14
|
||||
#define I2S_I2S_IN_DSCR_ERR_INT_RAW (BIT(13))
|
||||
#define I2S_I2S_IN_DSCR_ERR_INT_RAW_S 13
|
||||
#define I2S_I2S_OUT_EOF_INT_RAW (BIT(12))
|
||||
#define I2S_I2S_OUT_EOF_INT_RAW_S 12
|
||||
#define I2S_I2S_OUT_DONE_INT_RAW (BIT(11))
|
||||
#define I2S_I2S_OUT_DONE_INT_RAW_S 11
|
||||
#define I2S_I2S_IN_ERR_EOF_INT_RAW (BIT(10))
|
||||
#define I2S_I2S_IN_ERR_EOF_INT_RAW_S 10
|
||||
#define I2S_I2S_IN_SUC_EOF_INT_RAW (BIT(9))
|
||||
#define I2S_I2S_IN_SUC_EOF_INT_RAW_S 9
|
||||
#define I2S_I2S_IN_DONE_INT_RAW (BIT(8))
|
||||
#define I2S_I2S_IN_DONE_INT_RAW_S 8
|
||||
#define I2S_I2S_TX_HUNG_INT_RAW (BIT(7))
|
||||
#define I2S_I2S_TX_HUNG_INT_RAW_S 7
|
||||
#define I2S_I2S_RX_HUNG_INT_RAW (BIT(6))
|
||||
#define I2S_I2S_RX_HUNG_INT_RAW_S 6
|
||||
#define I2S_I2S_TX_REMPTY_INT_RAW (BIT(5))
|
||||
#define I2S_I2S_TX_REMPTY_INT_RAW_S 5
|
||||
#define I2S_I2S_TX_WFULL_INT_RAW (BIT(4))
|
||||
#define I2S_I2S_TX_WFULL_INT_RAW_S 4
|
||||
#define I2S_I2S_RX_REMPTY_INT_RAW (BIT(3))
|
||||
#define I2S_I2S_RX_REMPTY_INT_RAW_S 3
|
||||
#define I2S_I2S_RX_WFULL_INT_RAW (BIT(2))
|
||||
#define I2S_I2S_RX_WFULL_INT_RAW_S 2
|
||||
#define I2S_I2S_TX_PUT_DATA_INT_RAW (BIT(1))
|
||||
#define I2S_I2S_TX_PUT_DATA_INT_RAW_S 1
|
||||
#define I2S_I2S_RX_TAKE_DATA_INT_RAW (BIT(0))
|
||||
#define I2S_I2S_RX_TAKE_DATA_INT_RAW_S 0
|
||||
|
||||
#define I2SINT_ST (DR_REG_I2S_BASE + 0x0010)
|
||||
#define I2S_I2S_OUT_TOTAL_EOF_INT_ST (BIT(16))
|
||||
#define I2S_I2S_OUT_TOTAL_EOF_INT_ST_S 16
|
||||
#define I2S_I2S_IN_DSCR_EMPTY_INT_ST (BIT(15))
|
||||
#define I2S_I2S_IN_DSCR_EMPTY_INT_ST_S 15
|
||||
#define I2S_I2S_OUT_DSCR_ERR_INT_ST (BIT(14))
|
||||
#define I2S_I2S_OUT_DSCR_ERR_INT_ST_S 14
|
||||
#define I2S_I2S_IN_DSCR_ERR_INT_ST (BIT(13))
|
||||
#define I2S_I2S_IN_DSCR_ERR_INT_ST_S 13
|
||||
#define I2S_I2S_OUT_EOF_INT_ST (BIT(12))
|
||||
#define I2S_I2S_OUT_EOF_INT_ST_S 12
|
||||
#define I2S_I2S_OUT_DONE_INT_ST (BIT(11))
|
||||
#define I2S_I2S_OUT_DONE_INT_ST_S 11
|
||||
#define I2S_I2S_IN_ERR_EOF_INT_ST (BIT(10))
|
||||
#define I2S_I2S_IN_ERR_EOF_INT_ST_S 10
|
||||
#define I2S_I2S_IN_SUC_EOF_INT_ST (BIT(9))
|
||||
#define I2S_I2S_IN_SUC_EOF_INT_ST_S 9
|
||||
#define I2S_I2S_IN_DONE_INT_ST (BIT(8))
|
||||
#define I2S_I2S_IN_DONE_INT_ST_S 8
|
||||
#define I2S_I2S_TX_HUNG_INT_ST (BIT(7))
|
||||
#define I2S_I2S_TX_HUNG_INT_ST_S 7
|
||||
#define I2S_I2S_RX_HUNG_INT_ST (BIT(6))
|
||||
#define I2S_I2S_RX_HUNG_INT_ST_S 6
|
||||
#define I2S_I2S_TX_REMPTY_INT_ST (BIT(5))
|
||||
#define I2S_I2S_TX_REMPTY_INT_ST_S 5
|
||||
#define I2S_I2S_TX_WFULL_INT_ST (BIT(4))
|
||||
#define I2S_I2S_TX_WFULL_INT_ST_S 4
|
||||
#define I2S_I2S_RX_REMPTY_INT_ST (BIT(3))
|
||||
#define I2S_I2S_RX_REMPTY_INT_ST_S 3
|
||||
#define I2S_I2S_RX_WFULL_INT_ST (BIT(2))
|
||||
#define I2S_I2S_RX_WFULL_INT_ST_S 2
|
||||
#define I2S_I2S_TX_PUT_DATA_INT_ST (BIT(1))
|
||||
#define I2S_I2S_TX_PUT_DATA_INT_ST_S 1
|
||||
#define I2S_I2S_RX_TAKE_DATA_INT_ST (BIT(0))
|
||||
#define I2S_I2S_RX_TAKE_DATA_INT_ST_S 0
|
||||
|
||||
#define I2SINT_ENA (DR_REG_I2S_BASE + 0x0014)
|
||||
#define I2S_I2S_OUT_TOTAL_EOF_INT_ENA (BIT(16))
|
||||
#define I2S_I2S_OUT_TOTAL_EOF_INT_ENA_S 16
|
||||
#define I2S_I2S_IN_DSCR_EMPTY_INT_ENA (BIT(15))
|
||||
#define I2S_I2S_IN_DSCR_EMPTY_INT_ENA_S 15
|
||||
#define I2S_I2S_OUT_DSCR_ERR_INT_ENA (BIT(14))
|
||||
#define I2S_I2S_OUT_DSCR_ERR_INT_ENA_S 14
|
||||
#define I2S_I2S_IN_DSCR_ERR_INT_ENA (BIT(13))
|
||||
#define I2S_I2S_IN_DSCR_ERR_INT_ENA_S 13
|
||||
#define I2S_I2S_OUT_EOF_INT_ENA (BIT(12))
|
||||
#define I2S_I2S_OUT_EOF_INT_ENA_S 12
|
||||
#define I2S_I2S_OUT_DONE_INT_ENA (BIT(11))
|
||||
#define I2S_I2S_OUT_DONE_INT_ENA_S 11
|
||||
#define I2S_I2S_IN_ERR_EOF_INT_ENA (BIT(10))
|
||||
#define I2S_I2S_IN_ERR_EOF_INT_ENA_S 10
|
||||
#define I2S_I2S_IN_SUC_EOF_INT_ENA (BIT(9))
|
||||
#define I2S_I2S_IN_SUC_EOF_INT_ENA_S 9
|
||||
#define I2S_I2S_IN_DONE_INT_ENA (BIT(8))
|
||||
#define I2S_I2S_IN_DONE_INT_ENA_S 8
|
||||
#define I2S_I2S_TX_HUNG_INT_ENA (BIT(7))
|
||||
#define I2S_I2S_TX_HUNG_INT_ENA_S 7
|
||||
#define I2S_I2S_RX_HUNG_INT_ENA (BIT(6))
|
||||
#define I2S_I2S_RX_HUNG_INT_ENA_S 6
|
||||
#define I2S_I2S_TX_REMPTY_INT_ENA (BIT(5))
|
||||
#define I2S_I2S_TX_REMPTY_INT_ENA_S 5
|
||||
#define I2S_I2S_TX_WFULL_INT_ENA (BIT(4))
|
||||
#define I2S_I2S_TX_WFULL_INT_ENA_S 4
|
||||
#define I2S_I2S_RX_REMPTY_INT_ENA (BIT(3))
|
||||
#define I2S_I2S_RX_REMPTY_INT_ENA_S 3
|
||||
#define I2S_I2S_RX_WFULL_INT_ENA (BIT(2))
|
||||
#define I2S_I2S_RX_WFULL_INT_ENA_S 2
|
||||
#define I2S_I2S_TX_PUT_DATA_INT_ENA (BIT(1))
|
||||
#define I2S_I2S_TX_PUT_DATA_INT_ENA_S 1
|
||||
#define I2S_I2S_RX_TAKE_DATA_INT_ENA (BIT(0))
|
||||
#define I2S_I2S_RX_TAKE_DATA_INT_ENA_S 0
|
||||
|
||||
#define I2SINT_CLR (DR_REG_I2S_BASE + 0x0018)
|
||||
#define I2S_I2S_OUT_TOTAL_EOF_INT_CLR (BIT(16))
|
||||
#define I2S_I2S_OUT_TOTAL_EOF_INT_CLR_S 16
|
||||
#define I2S_I2S_IN_DSCR_EMPTY_INT_CLR (BIT(15))
|
||||
#define I2S_I2S_IN_DSCR_EMPTY_INT_CLR_S 15
|
||||
#define I2S_I2S_OUT_DSCR_ERR_INT_CLR (BIT(14))
|
||||
#define I2S_I2S_OUT_DSCR_ERR_INT_CLR_S 14
|
||||
#define I2S_I2S_IN_DSCR_ERR_INT_CLR (BIT(13))
|
||||
#define I2S_I2S_IN_DSCR_ERR_INT_CLR_S 13
|
||||
#define I2S_I2S_OUT_EOF_INT_CLR (BIT(12))
|
||||
#define I2S_I2S_OUT_EOF_INT_CLR_S 12
|
||||
#define I2S_I2S_OUT_DONE_INT_CLR (BIT(11))
|
||||
#define I2S_I2S_OUT_DONE_INT_CLR_S 11
|
||||
#define I2S_I2S_IN_ERR_EOF_INT_CLR (BIT(10))
|
||||
#define I2S_I2S_IN_ERR_EOF_INT_CLR_S 10
|
||||
#define I2S_I2S_IN_SUC_EOF_INT_CLR (BIT(9))
|
||||
#define I2S_I2S_IN_SUC_EOF_INT_CLR_S 9
|
||||
#define I2S_I2S_IN_DONE_INT_CLR (BIT(8))
|
||||
#define I2S_I2S_IN_DONE_INT_CLR_S 8
|
||||
#define I2S_I2S_TX_HUNG_INT_CLR (BIT(7))
|
||||
#define I2S_I2S_TX_HUNG_INT_CLR_S 7
|
||||
#define I2S_I2S_RX_HUNG_INT_CLR (BIT(6))
|
||||
#define I2S_I2S_RX_HUNG_INT_CLR_S 6
|
||||
#define I2S_I2S_TX_REMPTY_INT_CLR (BIT(5))
|
||||
#define I2S_I2S_TX_REMPTY_INT_CLR_S 5
|
||||
#define I2S_I2S_TX_WFULL_INT_CLR (BIT(4))
|
||||
#define I2S_I2S_TX_WFULL_INT_CLR_S 4
|
||||
#define I2S_I2S_RX_REMPTY_INT_CLR (BIT(3))
|
||||
#define I2S_I2S_RX_REMPTY_INT_CLR_S 3
|
||||
#define I2S_I2S_RX_WFULL_INT_CLR (BIT(2))
|
||||
#define I2S_I2S_RX_WFULL_INT_CLR_S 2
|
||||
#define I2S_I2S_PUT_DATA_INT_CLR (BIT(1))
|
||||
#define I2S_I2S_PUT_DATA_INT_CLR_S 1
|
||||
#define I2S_I2S_TAKE_DATA_INT_CLR (BIT(0))
|
||||
#define I2S_I2S_TAKE_DATA_INT_CLR_S 0
|
||||
|
||||
#define I2STIMING (DR_REG_I2S_BASE + 0x001c)
|
||||
#define I2S_TX_BCK_IN_INV (BIT(24))
|
||||
#define I2S_TX_BCK_IN_INV_S 24
|
||||
#define I2S_DATA_ENABLE_DELAY 0x00000003
|
||||
#define I2S_DATA_ENABLE_DELAY_S 22
|
||||
#define I2S_RX_DSYNC_SW (BIT(21))
|
||||
#define I2S_RX_DSYNC_SW_S 21
|
||||
#define I2S_TX_DSYNC_SW (BIT(20))
|
||||
#define I2S_TX_DSYNC_SW_S 20
|
||||
#define I2S_RX_BCK_OUT_DELAY 0x00000003
|
||||
#define I2S_RX_BCK_OUT_DELAY_S 18
|
||||
#define I2S_RX_WS_OUT_DELAY 0x00000003
|
||||
#define I2S_RX_WS_OUT_DELAY_S 16
|
||||
#define I2S_TX_SD_OUT_DELAY 0x00000003
|
||||
#define I2S_TX_SD_OUT_DELAY_S 14
|
||||
#define I2S_TX_WS_OUT_DELAY 0x00000003
|
||||
#define I2S_TX_WS_OUT_DELAY_S 12
|
||||
#define I2S_TX_BCK_OUT_DELAY 0x00000003
|
||||
#define I2S_TX_BCK_OUT_DELAY_S 10
|
||||
#define I2S_RX_SD_IN_DELAY 0x00000003
|
||||
#define I2S_RX_SD_IN_DELAY_S 8
|
||||
#define I2S_RX_WS_IN_DELAY 0x00000003
|
||||
#define I2S_RX_WS_IN_DELAY_S 6
|
||||
#define I2S_RX_BCK_IN_DELAY 0x00000003
|
||||
#define I2S_RX_BCK_IN_DELAY_S 4
|
||||
#define I2S_TX_WS_IN_DELAY 0x00000003
|
||||
#define I2S_TX_WS_IN_DELAY_S 2
|
||||
#define I2S_TX_BCK_IN_DELAY 0x00000003
|
||||
#define I2S_TX_BCK_IN_DELAY_S 0
|
||||
|
||||
#define I2S_FIFO_CONF (DR_REG_I2S_BASE + 0x0020)
|
||||
#define I2S_I2S_RX_FIFO_MOD_FORCE_EN (BIT(20))
|
||||
#define I2S_I2S_RX_FIFO_MOD_FORCE_EN_S 20
|
||||
#define I2S_I2S_TX_FIFO_MOD_FORCE_EN (BIT(19))
|
||||
#define I2S_I2S_TX_FIFO_MOD_FORCE_EN_S 19
|
||||
#define I2S_I2S_RX_FIFO_MOD 0x00000007
|
||||
#define I2S_I2S_RX_FIFO_MOD_S 16
|
||||
#define I2S_I2S_TX_FIFO_MOD 0x00000007
|
||||
#define I2S_I2S_TX_FIFO_MOD_S 13
|
||||
#define I2S_I2S_DSCR_EN (BIT(12))
|
||||
#define I2S_I2S_DSCR_EN_S 12
|
||||
#define I2S_I2S_TX_DATA_NUM 0x0000003F
|
||||
#define I2S_I2S_TX_DATA_NUM_S 6
|
||||
#define I2S_I2S_RX_DATA_NUM 0x0000003F
|
||||
#define I2S_I2S_RX_DATA_NUM_S 0
|
||||
|
||||
#define I2SRXEOF_NUM (DR_REG_I2S_BASE + 0x0024)
|
||||
#define I2S_I2S_RX_EOF_NUM 0xFFFFFFFF
|
||||
#define I2S_I2S_RX_EOF_NUM_S 0
|
||||
|
||||
#define I2SCONF_SIGLE_DATA (DR_REG_I2S_BASE + 0x0028)
|
||||
#define I2S_I2S_SIGLE_DATA 0xFFFFFFFF
|
||||
#define I2S_I2S_SIGLE_DATA_S 0
|
||||
|
||||
#define I2SCONF_CHAN (DR_REG_I2S_BASE + 0x002c)
|
||||
#define I2S_RX_CHAN_MOD 0x00000003
|
||||
#define I2S_RX_CHAN_MOD_S 3
|
||||
#define I2S_TX_CHAN_MOD 0x00000007
|
||||
#define I2S_TX_CHAN_MOD_S 0
|
||||
|
||||
#define I2SOUT_LINK (DR_REG_I2S_BASE + 0x0030)
|
||||
#define I2S_OUTLINK_PARK (BIT(31))
|
||||
#define I2S_OUTLINK_PARK_S 31
|
||||
#define I2S_I2S_OUTLINK_RESTART (BIT(30))
|
||||
#define I2S_I2S_OUTLINK_RESTART_S 30
|
||||
#define I2S_I2S_OUTLINK_START (BIT(29))
|
||||
#define I2S_I2S_OUTLINK_START_S 29
|
||||
#define I2S_I2S_OUTLINK_STOP (BIT(28))
|
||||
#define I2S_I2S_OUTLINK_STOP_S 28
|
||||
#define I2S_I2S_OUTLINK_ADDR 0x000FFFFF
|
||||
#define I2S_I2S_OUTLINK_ADDR_S 0
|
||||
|
||||
#define I2SIN_LINK (DR_REG_I2S_BASE + 0x0034)
|
||||
#define I2S_INLINK_PARK (BIT(31))
|
||||
#define I2S_INLINK_PARK_S 31
|
||||
#define I2S_I2S_INLINK_RESTART (BIT(30))
|
||||
#define I2S_I2S_INLINK_RESTART_S 30
|
||||
#define I2S_I2S_INLINK_START (BIT(29))
|
||||
#define I2S_I2S_INLINK_START_S 29
|
||||
#define I2S_I2S_INLINK_STOP (BIT(28))
|
||||
#define I2S_I2S_INLINK_STOP_S 28
|
||||
#define I2S_I2S_INLINK_ADDR 0x000FFFFF
|
||||
#define I2S_I2S_INLINK_ADDR_S 0
|
||||
|
||||
#define I2S_OUT_EOF_DES_ADDR (DR_REG_I2S_BASE + 0x0038)
|
||||
#define I2S_I2S_OUT_EOF_DES_ADDR 0xFFFFFFFF
|
||||
#define I2S_I2S_OUT_EOF_DES_ADDR_S 0
|
||||
|
||||
#define I2S_IN_EOF_DES_ADDR (DR_REG_I2S_BASE + 0x003c)
|
||||
#define I2S_I2S_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF
|
||||
#define I2S_I2S_IN_SUC_EOF_DES_ADDR_S 0
|
||||
|
||||
#define I2S_OUT_EOF_BFR_DES_ADDR (DR_REG_I2S_BASE + 0x0040)
|
||||
#define I2S_I2S_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF
|
||||
#define I2S_I2S_OUT_EOF_BFR_DES_ADDR_S 0
|
||||
|
||||
#define I2S_AHB_TEST (DR_REG_I2S_BASE + 0x0044)
|
||||
#define I2S_I2S_AHB_TESTADDR 0x00000003
|
||||
#define I2S_I2S_AHB_TESTADDR_S 4
|
||||
#define I2S_I2S_AHB_TESTMODE 0x00000007
|
||||
#define I2S_I2S_AHB_TESTMODE_S 0
|
||||
|
||||
#define I2S_INLINK_DSCR (DR_REG_I2S_BASE + 0x0048)
|
||||
#define I2S_I2S_INLINK_DSCR 0xFFFFFFFF
|
||||
#define I2S_I2S_INLINK_DSCR_S 0
|
||||
|
||||
#define I2S_INLINK_DSCR_BF0 (DR_REG_I2S_BASE + 0x004C)
|
||||
#define I2S_I2S_INLINK_DSCR_BF0 0xFFFFFFFF
|
||||
#define I2S_I2S_INLINK_DSCR_BF0_S 0
|
||||
|
||||
#define I2S_INLINK_DSCR_BF1 (DR_REG_I2S_BASE + 0x0050)
|
||||
#define I2S_I2S_INLINK_DSCR_BF1 0xFFFFFFFF
|
||||
#define I2S_I2S_INLINK_DSCR_BF1_S 0
|
||||
|
||||
#define I2S_OUTLINK_DSCR (DR_REG_I2S_BASE + 0x0054)
|
||||
#define I2S_I2S_OUTLINK_DSCR 0xFFFFFFFF
|
||||
#define I2S_I2S_OUTLINK_DSCR_S 0
|
||||
|
||||
#define I2S_OUTLINK_DSCR_BF0 (DR_REG_I2S_BASE + 0x0058)
|
||||
#define I2S_I2S_OUTLINK_DSCR_BF0 0xFFFFFFFF
|
||||
#define I2S_I2S_OUTLINK_DSCR_BF0_S 0
|
||||
|
||||
#define I2S_OUTLINK_DSCR_BF1 (DR_REG_I2S_BASE + 0x005C)
|
||||
#define I2S_I2S_OUTLINK_DSCR_BF1 0xFFFFFFFF
|
||||
#define I2S_I2S_OUTLINK_DSCR_BF1_S 0
|
||||
|
||||
#define I2S_LC_CONF (DR_REG_I2S_BASE + 0x0060)
|
||||
#define I2S_I2S_MEM_TRANS_EN (BIT(13))
|
||||
#define I2S_I2S_MEM_TRANS_EN_S 13
|
||||
#define I2S_I2S_CHECK_OWNER (BIT(12))
|
||||
#define I2S_I2S_CHECK_OWNER_S 12
|
||||
#define I2S_I2S_OUT_DATA_BURST_EN (BIT(11))
|
||||
#define I2S_I2S_OUT_DATA_BURST_EN_S 11
|
||||
#define I2S_I2S_INDSCR_BURST_EN (BIT(10))
|
||||
#define I2S_I2S_INDSCR_BURST_EN_S 10
|
||||
#define I2S_I2S_OUTDSCR_BURST_EN (BIT(9))
|
||||
#define I2S_I2S_OUTDSCR_BURST_EN_S 9
|
||||
#define I2S_I2S_OUT_EOF_MODE (BIT(8))
|
||||
#define I2S_I2S_OUT_EOF_MODE_S 8
|
||||
#define I2S_I2S_OUT_NO_RESTART_CLR (BIT(7))
|
||||
#define I2S_I2S_OUT_NO_RESTART_CLR_S 7
|
||||
#define I2S_I2S_OUT_AUTO_WRBACK (BIT(6))
|
||||
#define I2S_I2S_OUT_AUTO_WRBACK_S 6
|
||||
#define I2S_I2S_IN_LOOP_TEST (BIT(5))
|
||||
#define I2S_I2S_IN_LOOP_TEST_S 5
|
||||
#define I2S_I2S_OUT_LOOP_TEST (BIT(4))
|
||||
#define I2S_I2S_OUT_LOOP_TEST_S 4
|
||||
#define I2S_I2S_AHBM_RST (BIT(3))
|
||||
#define I2S_I2S_AHBM_RST_S 3
|
||||
#define I2S_I2S_AHBM_FIFO_RST (BIT(2))
|
||||
#define I2S_I2S_AHBM_FIFO_RST_S 2
|
||||
#define I2S_I2S_OUT_RST (BIT(1))
|
||||
#define I2S_I2S_OUT_RST_S 1
|
||||
#define I2S_I2S_IN_RST (BIT(0))
|
||||
#define I2S_I2S_IN_RST_S 0
|
||||
|
||||
#define I2S_OUTFIFO_PUSH (DR_REG_I2S_BASE + 0x0064)
|
||||
#define I2S_I2S_OUTFIFO_PUSH (BIT(16))
|
||||
#define I2S_I2S_OUTFIFO_PUSH_S 16
|
||||
#define I2S_I2S_OUTFIFO_WDATA 0x000001FF
|
||||
#define I2S_I2S_OUTFIFO_WDATA_S 0
|
||||
|
||||
#define I2S_INFIFO_POP (DR_REG_I2S_BASE + 0x0068)
|
||||
#define I2S_I2S_INFIFO_POP (BIT(16))
|
||||
#define I2S_I2S_INFIFO_POP_S 16
|
||||
#define I2S_I2S_INFIFO_RDATA 0x00000FFF
|
||||
#define I2S_I2S_INFIFO_RDATA_S 0
|
||||
|
||||
#define I2S_LC_STATE0 (DR_REG_I2S_BASE + 0x006C)
|
||||
#define I2S_I2S_LC_STATE0 0xFFFFFFFF
|
||||
#define I2S_I2S_LC_STATE0_S 0
|
||||
|
||||
#define I2S_LC_STATE1 (DR_REG_I2S_BASE + 0x0070)
|
||||
#define I2S_I2S_LC_STATE1 0xFFFFFFFF
|
||||
#define I2S_I2S_LC_STATE1_S 0
|
||||
|
||||
#define I2S_LC_HUNG_CONF (DR_REG_I2S_BASE + 0x0074)
|
||||
#define I2S_I2S_LC_FIFO_TIMEOUT_ENA (BIT(11))
|
||||
#define I2S_I2S_LC_FIFO_TIMEOUT_ENA_S 11
|
||||
#define I2S_I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007
|
||||
#define I2S_I2S_LC_FIFO_TIMEOUT_SHIFT_S 8
|
||||
#define I2S_I2S_LC_FIFO_TIMEOUT 0x000000FF
|
||||
#define I2S_I2S_LC_FIFO_TIMEOUT_S 0
|
||||
|
||||
#define I2S_CVSD_CONF0 (DR_REG_I2S_BASE + 0x0080)
|
||||
#define I2S_I2S_CVSD_Y_MIN 0x0000FFFF
|
||||
#define I2S_I2S_CVSD_Y_MIN_S 16
|
||||
#define I2S_I2S_CVSD_Y_MAX 0x0000FFFF
|
||||
#define I2S_I2S_CVSD_Y_MAX_S 0
|
||||
|
||||
#define I2S_CVSD_CONF1 (DR_REG_I2S_BASE + 0x0084)
|
||||
#define I2S_I2S_CVSD_SIGMA_MIN 0x0000FFFF
|
||||
#define I2S_I2S_CVSD_SIGMA_MIN_S 16
|
||||
#define I2S_I2S_CVSD_SIGMA_MAX 0x0000FFFF
|
||||
#define I2S_I2S_CVSD_SIGMA_MAX_S 0
|
||||
|
||||
#define I2S_CVSD_CONF2 (DR_REG_I2S_BASE + 0x0088)
|
||||
#define I2S_I2S_CVSD_H 0x00000007
|
||||
#define I2S_I2S_CVSD_H_S 16
|
||||
#define I2S_I2S_CVSD_BETA 0x000003FF
|
||||
#define I2S_I2S_CVSD_BETA_S 6
|
||||
#define I2S_I2S_CVSD_J 0x00000007
|
||||
#define I2S_I2S_CVSD_J_S 3
|
||||
#define I2S_I2S_CVSD_K 0x00000007
|
||||
#define I2S_I2S_CVSD_K_S 0
|
||||
|
||||
#define I2S_PLC_CONF0 (DR_REG_I2S_BASE + 0x008C)
|
||||
#define I2S_I2S_N_MIN_ERR 0x00000007
|
||||
#define I2S_I2S_N_MIN_ERR_S 25
|
||||
#define I2S_I2S_PACK_LEN_8K 0x0000001F
|
||||
#define I2S_I2S_PACK_LEN_8K_S 20
|
||||
#define I2S_I2S_MAX_SLIDE_SAMPLE 0x000000FF
|
||||
#define I2S_I2S_MAX_SLIDE_SAMPLE_S 12
|
||||
#define I2S_I2S_SHIFT_RATE 0x00000007
|
||||
#define I2S_I2S_SHIFT_RATE_S 9
|
||||
#define I2S_I2S_N_ERR_SEG 0x00000007
|
||||
#define I2S_I2S_N_ERR_SEG_S 6
|
||||
#define I2S_I2S_GOOD_PACK_MAX 0x0000003F
|
||||
#define I2S_I2S_GOOD_PACK_MAX_S 0
|
||||
|
||||
#define I2S_PLC_CONF1 (DR_REG_I2S_BASE + 0x0090)
|
||||
#define I2S_I2S_SLIDE_WIN_LEN 0x000000FF
|
||||
#define I2S_I2S_SLIDE_WIN_LEN_S 24
|
||||
#define I2S_I2S_BAD_OLA_WIN2_PARA 0x000000FF
|
||||
#define I2S_I2S_BAD_OLA_WIN2_PARA_S 16
|
||||
#define I2S_I2S_BAD_OLA_WIN2_PARA_SHIFT 0x0000000F
|
||||
#define I2S_I2S_BAD_OLA_WIN2_PARA_SHIFT_S 12
|
||||
#define I2S_I2S_BAD_CEF_ATTEN_PARA_SHIFT 0x0000000F
|
||||
#define I2S_I2S_BAD_CEF_ATTEN_PARA_SHIFT_S 8
|
||||
#define I2S_I2S_BAD_CEF_ATTEN_PARA 0x000000FF
|
||||
#define I2S_I2S_BAD_CEF_ATTEN_PARA_S 0
|
||||
|
||||
#define I2S_PLC_CONF2 (DR_REG_I2S_BASE + 0x0094)
|
||||
#define I2S_I2S_MIN_PERIOD 0x0000001F
|
||||
#define I2S_I2S_MIN_PERIOD_S 2
|
||||
#define I2S_I2S_CVSD_SEG_MOD 0x00000003
|
||||
#define I2S_I2S_CVSD_SEG_MOD_S 0
|
||||
|
||||
#define I2S_ESCO_CONF0 (DR_REG_I2S_BASE + 0x0098)
|
||||
#define I2S_I2S_PLC2DMA_EN (BIT(12))
|
||||
#define I2S_I2S_PLC2DMA_EN_S 12
|
||||
#define I2S_I2S_PLC_EN (BIT(11))
|
||||
#define I2S_I2S_PLC_EN_S 11
|
||||
#define I2S_I2S_CVSD_DEC_RESET (BIT(10))
|
||||
#define I2S_I2S_CVSD_DEC_RESET_S 10
|
||||
#define I2S_I2S_CVSD_DEC_START (BIT(9))
|
||||
#define I2S_I2S_CVSD_DEC_START_S 9
|
||||
#define I2S_I2S_ESCO_CVSD_INF_EN (BIT(8))
|
||||
#define I2S_I2S_ESCO_CVSD_INF_EN_S 8
|
||||
#define I2S_I2S_ESCO_CVSD_PACK_LEN_8K 0x0000001F
|
||||
#define I2S_I2S_ESCO_CVSD_PACK_LEN_8K_S 3
|
||||
#define I2S_I2S_ESCO_CVSD_DEC_PACK_ERR (BIT(2))
|
||||
#define I2S_I2S_ESCO_CVSD_DEC_PACK_ERR_S 2
|
||||
#define I2S_I2S_ESCO_CHAN_MOD (BIT(1))
|
||||
#define I2S_I2S_ESCO_CHAN_MOD_S 1
|
||||
#define I2S_I2S_ESCO_EN (BIT(0))
|
||||
#define I2S_I2S_ESCO_EN_S 0
|
||||
|
||||
#define I2S_SCO_CONF0 (DR_REG_I2S_BASE + 0x009c)
|
||||
#define I2S_I2S_CVSD_ENC_RESET (BIT(3))
|
||||
#define I2S_I2S_CVSD_ENC_RESET_S 3
|
||||
#define I2S_I2S_CVSD_ENC_START (BIT(2))
|
||||
#define I2S_I2S_CVSD_ENC_START_S 2
|
||||
#define I2S_I2S_SCO_NO_I2S_EN (BIT(1))
|
||||
#define I2S_I2S_SCO_NO_I2S_EN_S 1
|
||||
#define I2S_I2S_SCO_WITH_I2S_EN (BIT(0))
|
||||
#define I2S_I2S_SCO_WITH_I2S_EN_S 0
|
||||
|
||||
#define I2SCONF1 (DR_REG_I2S_BASE + 0x00a0)
|
||||
#define I2S_I2S_TX_ZEROS_RM_EN (BIT(9))
|
||||
#define I2S_I2S_TX_ZEROS_RM_EN_S 9
|
||||
#define I2S_I2S_TX_STOP_EN (BIT(8))
|
||||
#define I2S_I2S_TX_STOP_EN_S 8
|
||||
#define I2S_RX_PCM_BYPASS (BIT(7))
|
||||
#define I2S_RX_PCM_BYPASS_S 7
|
||||
#define I2S_RX_PCM_CONF 0x00000007
|
||||
#define I2S_RX_PCM_CONF_S 4
|
||||
#define I2S_TX_PCM_BYPASS (BIT(3))
|
||||
#define I2S_TX_PCM_BYPASS_S 3
|
||||
#define I2S_TX_PCM_CONF 0x00000007
|
||||
#define I2S_TX_PCM_CONF_S 0
|
||||
|
||||
#define I2S_PD_CONF (DR_REG_I2S_BASE + 0x00a4)
|
||||
#define I2S_PLC_MEM_FORCE_PU (BIT(3))
|
||||
#define I2S_PLC_MEM_FORCE_PU_S 3
|
||||
#define I2S_PLC_MEM_FORCE_PD (BIT(2))
|
||||
#define I2S_PLC_MEM_FORCE_PD_S 2
|
||||
#define I2S_I2S_FIFO_FORCE_PU (BIT(1))
|
||||
#define I2S_I2S_FIFO_FORCE_PU_S 1
|
||||
#define I2S_I2S_FIFO_FORCE_PD (BIT(0))
|
||||
#define I2S_I2S_FIFO_FORCE_PD_S 0
|
||||
|
||||
#define I2SCONF2 (DR_REG_I2S_BASE + 0x00a8)
|
||||
#define I2S_INTER_VALID_EN (BIT(7))
|
||||
#define I2S_INTER_VALID_EN_S 7
|
||||
#define I2S_EXT_ADC_START_EN (BIT(6))
|
||||
#define I2S_EXT_ADC_START_EN_S 6
|
||||
#define I2S_LCD_EN (BIT(5))
|
||||
#define I2S_LCD_EN_S 5
|
||||
#define I2S_DATA_ENABLE (BIT(4))
|
||||
#define I2S_DATA_ENABLE_S 4
|
||||
#define I2S_DATA_ENABLE_TEST_EN (BIT(3))
|
||||
#define I2S_DATA_ENABLE_TEST_EN_S 3
|
||||
#define I2S_LCD_TX_SDX2_EN (BIT(2))
|
||||
#define I2S_LCD_TX_SDX2_EN_S 2
|
||||
#define I2S_LCD_TX_WRX2_EN (BIT(1))
|
||||
#define I2S_LCD_TX_WRX2_EN_S 1
|
||||
#define I2S_CAMERA_EN (BIT(0))
|
||||
#define I2S_CAMERA_EN_S 0
|
||||
|
||||
#define I2S_CLKM_CONF (DR_REG_I2S_BASE + 0x00ac)
|
||||
#define I2S_CLKA_ENA (BIT(21))
|
||||
#define I2S_CLKA_ENA_S 21
|
||||
#define I2S_CLK_EN (BIT(20))
|
||||
#define I2S_CLK_EN_S 20
|
||||
#define I2S_CLKM_DIV_A 0x0000003F
|
||||
#define I2S_CLKM_DIV_A_S 14
|
||||
#define I2S_CLKM_DIV_B 0x0000003F
|
||||
#define I2S_CLKM_DIV_B_S 8
|
||||
#define I2S_CLKM_DIV_NUM 0x000000FF
|
||||
#define I2S_CLKM_DIV_NUM_S 0
|
||||
|
||||
#define I2S_SAMPLE_RATE_CONF (DR_REG_I2S_BASE + 0x00b0)
|
||||
#define I2S_RX_BITS_MOD 0x0000003F
|
||||
#define I2S_RX_BITS_MOD_S 18
|
||||
#define I2S_TX_BITS_MOD 0x0000003F
|
||||
#define I2S_TX_BITS_MOD_S 12
|
||||
#define I2S_RX_BCK_DIV_NUM 0x0000003F
|
||||
#define I2S_RX_BCK_DIV_NUM_S 6
|
||||
#define I2S_TX_BCK_DIV_NUM 0x0000003F
|
||||
#define I2S_TX_BCK_DIV_NUM_S 0
|
||||
|
||||
#define I2S_PDM_CONF (DR_REG_I2S_BASE + 0x00b4)
|
||||
#define I2S_TX_PDM_HP_BYPASS (BIT(25))
|
||||
#define I2S_TX_PDM_HP_BYPASS_S 25
|
||||
#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(24))
|
||||
#define I2S_RX_PDM_SINC_DSR_16_EN_S 24
|
||||
#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT 0x00000003
|
||||
#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S 22
|
||||
#define I2S_TX_PDM_SINC_IN_SHIFT 0x00000003
|
||||
#define I2S_TX_PDM_SINC_IN_SHIFT_S 20
|
||||
#define I2S_TX_PDM_LP_IN_SHIFT 0x00000003
|
||||
#define I2S_TX_PDM_LP_IN_SHIFT_S 18
|
||||
#define I2S_TX_PDM_HP_IN_SHIFT 0x00000003
|
||||
#define I2S_TX_PDM_HP_IN_SHIFT_S 16
|
||||
#define I2S_TX_PDM_PRESCALE 0x000000FF
|
||||
#define I2S_TX_PDM_PRESCALE_S 8
|
||||
#define I2S_TX_PDM_SINC_OSR2 0x0000000F
|
||||
#define I2S_TX_PDM_SINC_OSR2_S 4
|
||||
#define I2S_PDM2PCM_CONV_EN (BIT(3))
|
||||
#define I2S_PDM2PCM_CONV_EN_S 3
|
||||
#define I2S_PCM2PDM_CONV_EN (BIT(2))
|
||||
#define I2S_PCM2PDM_CONV_EN_S 2
|
||||
#define I2S_RX_PDM_EN (BIT(1))
|
||||
#define I2S_RX_PDM_EN_S 1
|
||||
#define I2S_TX_PDM_EN (BIT(0))
|
||||
#define I2S_TX_PDM_EN_S 0
|
||||
|
||||
#define I2S_PDM_FREQ_CONF (DR_REG_I2S_BASE + 0x00b8)
|
||||
#define I2S_TX_PDM_FP 0x000003FF
|
||||
#define I2S_TX_PDM_FP_S 10
|
||||
#define I2S_TX_PDM_FS 0x000003FF
|
||||
#define I2S_TX_PDM_FS_S 0
|
||||
|
||||
#define I2S_STATE (DR_REG_I2S_BASE + 0x00bc)
|
||||
#define I2S_I2S_RX_FIFO_RESET_BACK (BIT(2))
|
||||
#define I2S_I2S_RX_FIFO_RESET_BACK_S 2
|
||||
#define I2S_I2S_TX_FIFO_RESET_BACK (BIT(1))
|
||||
#define I2S_I2S_TX_FIFO_RESET_BACK_S 1
|
||||
#define I2S_I2S_TX_IDLE (BIT(0))
|
||||
#define I2S_I2S_TX_IDLE_S 0
|
||||
|
||||
#define I2S_DATE (DR_REG_I2S_BASE + 0x00fc)
|
||||
#define I2S_I2SDATE 0xFFFFFFFF
|
||||
#define I2S_I2SDATE_S 0
|
||||
|
||||
#endif /* _SOC_I2S_REG_H_ */
|
||||
@@ -0,0 +1,264 @@
|
||||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_IO_MUX_REG_H_
|
||||
#define _SOC_IO_MUX_REG_H_
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define SLP_OE (BIT(0))
|
||||
#define SLP_SEL (BIT(1))
|
||||
#define SLP_PD (BIT(2))
|
||||
#define SLP_PU (BIT(3))
|
||||
#define SLP_IE (BIT(4))
|
||||
#define SLP_DRV 0x3
|
||||
#define SLP_DRV_S 5
|
||||
#define FUN_PD (BIT(7))
|
||||
#define FUN_PU (BIT(8))
|
||||
#define FUN_IE (BIT(9))
|
||||
#define FUN_DRV 0x3
|
||||
#define FUN_DRV_S 10
|
||||
#define MCU_SEL 0x7
|
||||
#define MCU_SEL_S 12
|
||||
|
||||
|
||||
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
|
||||
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
|
||||
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
|
||||
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
|
||||
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
|
||||
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
|
||||
|
||||
#define PIN_CTRL (DR_REG_IO_MUX_BASE +0x00)
|
||||
#define CLK_OUT3 0xf
|
||||
#define CLK_OUT3_S 8
|
||||
#define CLK_OUT2 0xf
|
||||
#define CLK_OUT2_S 4
|
||||
#define CLK_OUT1 0xf
|
||||
#define CLK_OUT1_S 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO36_U (DR_REG_IO_MUX_BASE +0x04)
|
||||
#define FUNC_GPIO36_GPIO36 2
|
||||
#define FUNC_GPIO36_GPIO36_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO37_U (DR_REG_IO_MUX_BASE +0x08)
|
||||
#define FUNC_GPIO37_GPIO37 2
|
||||
#define FUNC_GPIO37_GPIO37_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO38_U (DR_REG_IO_MUX_BASE +0x0c)
|
||||
#define FUNC_GPIO38_GPIO38 2
|
||||
#define FUNC_GPIO38_GPIO38_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO39_U (DR_REG_IO_MUX_BASE +0x10)
|
||||
#define FUNC_GPIO39_GPIO39 2
|
||||
#define FUNC_GPIO39_GPIO39_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO34_U (DR_REG_IO_MUX_BASE +0x14)
|
||||
#define FUNC_GPIO34_GPIO34 2
|
||||
#define FUNC_GPIO34_GPIO34_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO35_U (DR_REG_IO_MUX_BASE +0x18)
|
||||
#define FUNC_GPIO35_GPIO35 2
|
||||
#define FUNC_GPIO35_GPIO35_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO32_U (DR_REG_IO_MUX_BASE +0x1c)
|
||||
#define FUNC_GPIO32_GPIO32 2
|
||||
#define FUNC_GPIO32_GPIO32_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO33_U (DR_REG_IO_MUX_BASE +0x20)
|
||||
#define FUNC_GPIO33_GPIO33 2
|
||||
#define FUNC_GPIO33_GPIO33_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO25_U (DR_REG_IO_MUX_BASE +0x24)
|
||||
#define FUNC_GPIO25_GPIO25 2
|
||||
#define FUNC_GPIO25_GPIO25_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO26_U (DR_REG_IO_MUX_BASE +0x28)
|
||||
#define FUNC_GPIO26_GPIO26 2
|
||||
#define FUNC_GPIO26_GPIO26_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO27_U (DR_REG_IO_MUX_BASE +0x2c)
|
||||
#define FUNC_GPIO27_EMAC_RXD2 5
|
||||
#define FUNC_GPIO27_GPIO27 2
|
||||
#define FUNC_GPIO27_GPIO27_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_MTMS_U (DR_REG_IO_MUX_BASE +0x30)
|
||||
#define FUNC_MTMS_EMAC_TXD2 5
|
||||
#define FUNC_MTMS_SD_CLK 4
|
||||
#define FUNC_MTMS_GPIO14 2
|
||||
#define FUNC_MTMS_HSPICLK 1
|
||||
#define FUNC_MTMS_MTMS 0
|
||||
|
||||
#define PERIPHS_IO_MUX_MTDI_U (DR_REG_IO_MUX_BASE +0x34)
|
||||
#define FUNC_MTDI_EMAC_TXD3 5
|
||||
#define FUNC_MTDI_SD_DATA2 4
|
||||
#define FUNC_MTDI_GPIO12 2
|
||||
#define FUNC_MTDI_HSPIQ 1
|
||||
#define FUNC_MTDI_MTDI 0
|
||||
|
||||
#define PERIPHS_IO_MUX_MTCK_U (DR_REG_IO_MUX_BASE +0x38)
|
||||
#define FUNC_MTCK_EMAC_RX_ER 5
|
||||
#define FUNC_MTCK_SD_DATA3 4
|
||||
#define FUNC_MTCK_U0CTS 3
|
||||
#define FUNC_MTCK_GPIO13 2
|
||||
#define FUNC_MTCK_HSPID 1
|
||||
#define FUNC_MTCK_MTCK 0
|
||||
|
||||
#define PERIPHS_IO_MUX_MTDO_U (DR_REG_IO_MUX_BASE +0x3c)
|
||||
#define FUNC_MTDO_EMAC_RXD3 5
|
||||
#define FUNC_MTDO_SD_CMD 4
|
||||
#define FUNC_MTDO_U0RTS 3
|
||||
#define FUNC_MTDO_GPIO15 2
|
||||
#define FUNC_MTDO_HSPICS0 1
|
||||
#define FUNC_MTDO_MTDO 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO2_U (DR_REG_IO_MUX_BASE +0x40)
|
||||
#define FUNC_GPIO2_EMAC_RX_DV 5
|
||||
#define FUNC_GPIO2_SD_DATA0 4
|
||||
#define FUNC_GPIO2_GPIO2 2
|
||||
#define FUNC_GPIO2_HSPIWP 1
|
||||
#define FUNC_GPIO2_GPIO2_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO0_U (DR_REG_IO_MUX_BASE +0x44)
|
||||
#define FUNC_GPIO0_EMAC_TX_CLK 5
|
||||
#define FUNC_GPIO0_HS2_CMD 3
|
||||
#define FUNC_GPIO0_GPIO0 2
|
||||
#define FUNC_GPIO0_CLK_OUT1 1
|
||||
#define FUNC_GPIO0_GPIO0_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO4_U (DR_REG_IO_MUX_BASE +0x48)
|
||||
#define FUNC_GPIO4_EMAC_TX_ER 5
|
||||
#define FUNC_GPIO4_SD_DATA1 4
|
||||
#define FUNC_GPIO4_GPIO4 2
|
||||
#define FUNC_GPIO4_HSPIHD 1
|
||||
#define FUNC_GPIO4_GPIO4_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO16_U (DR_REG_IO_MUX_BASE +0x4c)
|
||||
#define FUNC_GPIO16_EMAC_CLK_OUT 5
|
||||
#define FUNC_GPIO16_U2RXD 4
|
||||
#define FUNC_GPIO16_HS1_DATA4 3
|
||||
#define FUNC_GPIO16_GPIO16 2
|
||||
#define FUNC_GPIO16_GPIO16_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO17_U (DR_REG_IO_MUX_BASE +0x50)
|
||||
#define FUNC_GPIO17_EMAC_CLK_OUT_180 5
|
||||
#define FUNC_GPIO17_U2TXD 4
|
||||
#define FUNC_GPIO17_HS1_DATA5 3
|
||||
#define FUNC_GPIO17_GPIO17 2
|
||||
#define FUNC_GPIO17_GPIO17_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SD_DATA2_U (DR_REG_IO_MUX_BASE +0x54)
|
||||
#define FUNC_SD_DATA2_U1RXD 4
|
||||
#define FUNC_SD_DATA2_HS1_DATA2 3
|
||||
#define FUNC_SD_DATA2_GPIO9 2
|
||||
#define FUNC_SD_DATA2_SPIHD 1
|
||||
#define FUNC_SD_DATA2_SD_DATA2 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SD_DATA3_U (DR_REG_IO_MUX_BASE +0x58)
|
||||
#define FUNC_SD_DATA3_U1TXD 4
|
||||
#define FUNC_SD_DATA3_HS1_DATA3 3
|
||||
#define FUNC_SD_DATA3_GPIO10 2
|
||||
#define FUNC_SD_DATA3_SPIWP 1
|
||||
#define FUNC_SD_DATA3_SD_DATA3 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SD_CMD_U (DR_REG_IO_MUX_BASE +0x5c)
|
||||
#define FUNC_SD_CMD_U1RTS 4
|
||||
#define FUNC_SD_CMD_HS1_CMD 3
|
||||
#define FUNC_SD_CMD_GPIO11 2
|
||||
#define FUNC_SD_CMD_SPICS0 1
|
||||
#define FUNC_SD_CMD_SD_CMD 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SD_CLK_U (DR_REG_IO_MUX_BASE +0x60)
|
||||
#define FUNC_SD_CLK_U1CTS 4
|
||||
#define FUNC_SD_CLK_HS1_CLK 3
|
||||
#define FUNC_SD_CLK_GPIO6 2
|
||||
#define FUNC_SD_CLK_SPICLK 1
|
||||
#define FUNC_SD_CLK_SD_CLK 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SD_DATA0_U (DR_REG_IO_MUX_BASE +0x64)
|
||||
#define FUNC_SD_DATA0_U2RTS 4
|
||||
#define FUNC_SD_DATA0_HS1_DATA0 3
|
||||
#define FUNC_SD_DATA0_GPIO7 2
|
||||
#define FUNC_SD_DATA0_SPIQ 1
|
||||
#define FUNC_SD_DATA0_SD_DATA0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SD_DATA1_U (DR_REG_IO_MUX_BASE +0x68)
|
||||
#define FUNC_SD_DATA1_U2CTS 4
|
||||
#define FUNC_SD_DATA1_HS1_DATA1 3
|
||||
#define FUNC_SD_DATA1_GPIO8 2
|
||||
#define FUNC_SD_DATA1_SPID 1
|
||||
#define FUNC_SD_DATA1_SD_DATA1 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO5_U (DR_REG_IO_MUX_BASE +0x6c)
|
||||
#define FUNC_GPIO5_EMAC_RX_CLK 5
|
||||
#define FUNC_GPIO5_HS1_DATA6 3
|
||||
#define FUNC_GPIO5_GPIO5 2
|
||||
#define FUNC_GPIO5_VSPICS0 1
|
||||
#define FUNC_GPIO5_GPIO5_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO18_U (DR_REG_IO_MUX_BASE +0x70)
|
||||
#define FUNC_GPIO18_EMAC_TXD0 5
|
||||
#define FUNC_GPIO18_HS1_DATA7 3
|
||||
#define FUNC_GPIO18_GPIO18 2
|
||||
#define FUNC_GPIO18_VSPICLK 1
|
||||
#define FUNC_GPIO18_GPIO18_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO19_U (DR_REG_IO_MUX_BASE +0x74)
|
||||
#define FUNC_GPIO19_EMAC_TXD1 5
|
||||
#define FUNC_GPIO19_HS2_DATA2 3
|
||||
#define FUNC_GPIO19_GPIO19 2
|
||||
#define FUNC_GPIO19_VSPIQ 1
|
||||
#define FUNC_GPIO19_GPIO19_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO20_U (DR_REG_IO_MUX_BASE +0x78)
|
||||
#define FUNC_GPIO20_GPIO20 2
|
||||
#define FUNC_GPIO20_GPIO20_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO21_U (DR_REG_IO_MUX_BASE +0x7c)
|
||||
#define FUNC_GPIO21_EMAC_RXD0 5
|
||||
#define FUNC_GPIO21_HS2_DATA3 3
|
||||
#define FUNC_GPIO21_GPIO21 2
|
||||
#define FUNC_GPIO21_VSPIHD 1
|
||||
#define FUNC_GPIO21_GPIO21_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO22_U (DR_REG_IO_MUX_BASE +0x80)
|
||||
#define FUNC_GPIO22_EMAC_RXD1 5
|
||||
#define FUNC_GPIO22_HS2_CLK 3
|
||||
#define FUNC_GPIO22_GPIO22 2
|
||||
#define FUNC_GPIO22_VSPIWP 1
|
||||
#define FUNC_GPIO22_GPIO22_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U0RXD_U (DR_REG_IO_MUX_BASE +0x84)
|
||||
#define FUNC_U0RXD_HS2_DATA0 3
|
||||
#define FUNC_U0RXD_GPIO3 2
|
||||
#define FUNC_U0RXD_CLK_OUT2 1
|
||||
#define FUNC_U0RXD_U0RXD 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U0TXD_U (DR_REG_IO_MUX_BASE +0x88)
|
||||
#define FUNC_U0TXD_HS2_DATA1 3
|
||||
#define FUNC_U0TXD_GPIO1 2
|
||||
#define FUNC_U0TXD_CLK_OUT3 1
|
||||
#define FUNC_U0TXD_U0TXD 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO23_U (DR_REG_IO_MUX_BASE +0x8c)
|
||||
#define FUNC_GPIO23_EMAC_TX_EN 5
|
||||
#define FUNC_GPIO23_HS1_STROBE 3
|
||||
#define FUNC_GPIO23_GPIO23 2
|
||||
#define FUNC_GPIO23_VSPID 1
|
||||
#define FUNC_GPIO23_GPIO23_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO24_U (DR_REG_IO_MUX_BASE +0x90)
|
||||
#define FUNC_GPIO24_GPIO24 2
|
||||
#define FUNC_GPIO24_GPIO24_0 0
|
||||
|
||||
#endif /* _SOC_IO_MUX_REG_H_ */
|
||||
@@ -0,0 +1,65 @@
|
||||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_PID_H_
|
||||
#define _SOC_PID_H_
|
||||
|
||||
#define PROPID_GEN_BASE 0x3FF1F000
|
||||
//Bits 1..7: 1 if interrupt will be triggering PID change
|
||||
#define PROPID_CONFIG_INTERRUPT_ENABLE ((PROPID_GEN_BASE)+0x000)
|
||||
//Vectors for the various interrupt handlers
|
||||
#define PROPID_CONFIG_INTERRUPT_ADDR_1 ((PROPID_GEN_BASE)+0x004)
|
||||
#define PROPID_CONFIG_INTERRUPT_ADDR_2 ((PROPID_GEN_BASE)+0x008)
|
||||
#define PROPID_CONFIG_INTERRUPT_ADDR_3 ((PROPID_GEN_BASE)+0x00C)
|
||||
#define PROPID_CONFIG_INTERRUPT_ADDR_4 ((PROPID_GEN_BASE)+0x010)
|
||||
#define PROPID_CONFIG_INTERRUPT_ADDR_5 ((PROPID_GEN_BASE)+0x014)
|
||||
#define PROPID_CONFIG_INTERRUPT_ADDR_6 ((PROPID_GEN_BASE)+0x018)
|
||||
#define PROPID_CONFIG_INTERRUPT_ADDR_7 ((PROPID_GEN_BASE)+0x01C)
|
||||
|
||||
//Delay, in CPU cycles, before switching to new PID
|
||||
#define PROPID_CONFIG_PID_DELAY ((PROPID_GEN_BASE)+0x020)
|
||||
#define PROPID_CONFIG_NMI_DELAY ((PROPID_GEN_BASE)+0x024)
|
||||
|
||||
//Last detected interrupt. Set by hw on int.
|
||||
#define PROPID_TABLE_LEVEL ((PROPID_GEN_BASE)+0x028)
|
||||
//PID/prev int data for each int
|
||||
#define PROPID_FROM_1 ((PROPID_GEN_BASE)+0x02C)
|
||||
#define PROPID_FROM_2 ((PROPID_GEN_BASE)+0x030)
|
||||
#define PROPID_FROM_3 ((PROPID_GEN_BASE)+0x034)
|
||||
#define PROPID_FROM_4 ((PROPID_GEN_BASE)+0x038)
|
||||
#define PROPID_FROM_5 ((PROPID_GEN_BASE)+0x03C)
|
||||
#define PROPID_FROM_6 ((PROPID_GEN_BASE)+0x040)
|
||||
#define PROPID_FROM_7 ((PROPID_GEN_BASE)+0x044)
|
||||
#define PROPID_FROM_PID_MASK 0x7
|
||||
#define PROPID_FROM_PID_S 0
|
||||
#define PROPID_FROM_INT_MASK 0xF
|
||||
#define PROPID_FROM_INT_S 3
|
||||
|
||||
//PID to be set after confirm routine
|
||||
#define PROPID_PID_NEW ((PROPID_GEN_BASE)+0x048)
|
||||
//Write to kick off PID change
|
||||
#define PROPID_PID_CONFIRM ((PROPID_GEN_BASE)+0x04c)
|
||||
//current PID?
|
||||
#define PROPID_PID_REG ((PROPID_GEN_BASE)+0x050)
|
||||
|
||||
//Write to mask NMI
|
||||
#define PROPID_PID_NMI_MASK_HW_ENABLE ((PROPID_GEN_BASE)+0x054)
|
||||
//Write to unmask NMI
|
||||
#define PROPID_PID_NMI_MASK_HW_DISABLE ((PROPID_GEN_BASE)+0x058)
|
||||
#define PROPID_PID_NMI_MASK_HW_REG ((PROPID_GEN_BASE)+0x05c)
|
||||
|
||||
//Debug regs
|
||||
#define PROPID_PID ((PROPID_GEN_BASE)+0x060)
|
||||
#define PROPID_NMI_MASK_HW ((PROPID_GEN_BASE)+0x064)
|
||||
|
||||
#endif /* _SOC_PID_H_ */
|
||||
@@ -0,0 +1,751 @@
|
||||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_RTC_CNTL_REG_H_
|
||||
#define _SOC_RTC_CNTL_REG_H_
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define RTC_OPTIONS0 (DR_REG_RTCCNTL_BASE + 0x0)
|
||||
#define RTC_CNTL_SW_SYS_RST (BIT(31))
|
||||
#define RTC_CNTL_SW_SYS_RST_S 31
|
||||
#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30))
|
||||
#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30
|
||||
#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29))
|
||||
#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29
|
||||
#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28))
|
||||
#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28
|
||||
#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27))
|
||||
#define RTC_CNTL_PLL_FORCE_NOISO_S 27
|
||||
#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26))
|
||||
#define RTC_CNTL_XTL_FORCE_NOISO_S 26
|
||||
#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25))
|
||||
#define RTC_CNTL_ANALOG_FORCE_ISO_S 25
|
||||
#define RTC_CNTL_PLL_FORCE_ISO (BIT(24))
|
||||
#define RTC_CNTL_PLL_FORCE_ISO_S 24
|
||||
#define RTC_CNTL_XTL_FORCE_ISO (BIT(23))
|
||||
#define RTC_CNTL_XTL_FORCE_ISO_S 23
|
||||
#define RTC_CNTL_BIAS_CORE_FORCE_PU (BIT(22))
|
||||
#define RTC_CNTL_BIAS_CORE_FORCE_PU_S 22
|
||||
#define RTC_CNTL_BIAS_CORE_FORCE_PD (BIT(21))
|
||||
#define RTC_CNTL_BIAS_CORE_FORCE_PD_S 21
|
||||
#define RTC_CNTL_BIAS_CORE_FOLW_12M (BIT(20))
|
||||
#define RTC_CNTL_BIAS_CORE_FOLW_12M_S 20
|
||||
#define RTC_CNTL_BIAS_I2C_FORCE_PU (BIT(19))
|
||||
#define RTC_CNTL_BIAS_I2C_FORCE_PU_S 19
|
||||
#define RTC_CNTL_BIAS_I2C_FORCE_PD (BIT(18))
|
||||
#define RTC_CNTL_BIAS_I2C_FORCE_PD_S 18
|
||||
#define RTC_CNTL_BIAS_I2C_FOLW_12M (BIT(17))
|
||||
#define RTC_CNTL_BIAS_I2C_FOLW_12M_S 17
|
||||
#define RTC_CNTL_BIAS_FORCE_NOSLEEP (BIT(16))
|
||||
#define RTC_CNTL_BIAS_FORCE_NOSLEEP_S 16
|
||||
#define RTC_CNTL_BIAS_FORCE_SLEEP (BIT(15))
|
||||
#define RTC_CNTL_BIAS_FORCE_SLEEP_S 15
|
||||
#define RTC_CNTL_BIAS_SLEEP_FOLW_12M (BIT(14))
|
||||
#define RTC_CNTL_BIAS_SLEEP_FOLW_12M_S 14
|
||||
#define RTC_CNTL_XTL_FORCE_PU (BIT(13))
|
||||
#define RTC_CNTL_XTL_FORCE_PU_S 13
|
||||
#define RTC_CNTL_XTL_FORCE_PD (BIT(12))
|
||||
#define RTC_CNTL_XTL_FORCE_PD_S 12
|
||||
#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11))
|
||||
#define RTC_CNTL_BBPLL_FORCE_PU_S 11
|
||||
#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10))
|
||||
#define RTC_CNTL_BBPLL_FORCE_PD_S 10
|
||||
#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9))
|
||||
#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9
|
||||
#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8))
|
||||
#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8
|
||||
#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7))
|
||||
#define RTC_CNTL_BB_I2C_FORCE_PU_S 7
|
||||
#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6))
|
||||
#define RTC_CNTL_BB_I2C_FORCE_PD_S 6
|
||||
#define RTC_CNTL_SW_PROCPU_RST (BIT(5))
|
||||
#define RTC_CNTL_SW_PROCPU_RST_S 5
|
||||
#define RTC_CNTL_SW_APPCPU_RST (BIT(4))
|
||||
#define RTC_CNTL_SW_APPCPU_RST_S 4
|
||||
#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003
|
||||
#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2
|
||||
#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003
|
||||
#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0
|
||||
|
||||
#define RTC_SLP_TIMER0 (DR_REG_RTCCNTL_BASE + 0x4)
|
||||
#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF
|
||||
#define RTC_CNTL_SLP_VAL_LO_S 0
|
||||
|
||||
#define RTC_SLP_TIMER1 (DR_REG_RTCCNTL_BASE + 0x8)
|
||||
#define RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN (BIT(16))
|
||||
#define RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN_S 16
|
||||
#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF
|
||||
#define RTC_CNTL_SLP_VAL_HI_S 0
|
||||
|
||||
#define RTC_TIME_UPDATE (DR_REG_RTCCNTL_BASE + 0xc)
|
||||
#define RTC_CNTL_RTC_TIME_UPDATE (BIT(31))
|
||||
#define RTC_CNTL_RTC_TIME_UPDATE_S 31
|
||||
#define RTC_CNTL_RTC_TIME_VALID (BIT(30))
|
||||
#define RTC_CNTL_RTC_TIME_VALID_S 30
|
||||
|
||||
#define RTC_TIME0 (DR_REG_RTCCNTL_BASE + 0x10)
|
||||
#define RTC_CNTL_RTC_TIME_LO 0xFFFFFFFF
|
||||
#define RTC_CNTL_RTC_TIME_LO_S 0
|
||||
|
||||
#define RTC_TIME1 (DR_REG_RTCCNTL_BASE + 0x14)
|
||||
#define RTC_CNTL_RTC_TIME_HI 0x0000FFFF
|
||||
#define RTC_CNTL_RTC_TIME_HI_S 0
|
||||
|
||||
#define RTC_STATE0 (DR_REG_RTCCNTL_BASE + 0x18)
|
||||
#define RTC_CNTL_SLEEP_EN (BIT(31))
|
||||
#define RTC_CNTL_SLEEP_EN_S 31
|
||||
#define RTC_CNTL_SLP_REJECT (BIT(30))
|
||||
#define RTC_CNTL_SLP_REJECT_S 30
|
||||
#define RTC_CNTL_SLP_WAKEUP (BIT(29))
|
||||
#define RTC_CNTL_SLP_WAKEUP_S 29
|
||||
#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28))
|
||||
#define RTC_CNTL_SDIO_ACTIVE_IND_S 28
|
||||
#define RTC_CNTL_SAR_SLP_TIMER_EN (BIT(24))
|
||||
#define RTC_CNTL_SAR_SLP_TIMER_EN_S 24
|
||||
#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(23))
|
||||
#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 23
|
||||
#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22))
|
||||
#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22
|
||||
#define RTC_CNTL_SAR_WAKEUP_FORCE_EN (BIT(21))
|
||||
#define RTC_CNTL_SAR_WAKEUP_FORCE_EN_S 21
|
||||
#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN (BIT(20))
|
||||
#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_S 20
|
||||
|
||||
#define RTC_TIMER1 (DR_REG_RTCCNTL_BASE + 0x1c)
|
||||
#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_S 24
|
||||
#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_S 14
|
||||
#define RTC_CNTL_CK12M_WAIT 0x000000FF
|
||||
#define RTC_CNTL_CK12M_WAIT_S 6
|
||||
#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F
|
||||
#define RTC_CNTL_CPU_STALL_WAIT_S 1
|
||||
#define RTC_CNTL_CPU_STALL_EN (BIT(0))
|
||||
#define RTC_CNTL_CPU_STALL_EN_S 0
|
||||
|
||||
#define RTC_TIMER2 (DR_REG_RTCCNTL_BASE + 0x20)
|
||||
#define RTC_CNTL_MIN_TIME_CK12M_OFF 0x000000FF
|
||||
#define RTC_CNTL_MIN_TIME_CK12M_OFF_S 24
|
||||
#define RTC_CNTL_SAR_TOUCH_START_WAIT 0x000001FF
|
||||
#define RTC_CNTL_SAR_TOUCH_START_WAIT_S 15
|
||||
|
||||
#define RTC_TIMER3 (DR_REG_RTCCNTL_BASE + 0x24)
|
||||
#define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F
|
||||
#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25
|
||||
#define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF
|
||||
#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16
|
||||
#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F
|
||||
#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9
|
||||
#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF
|
||||
#define RTC_CNTL_WIFI_WAIT_TIMER_S 0
|
||||
|
||||
#define RTC_TIMER4 (DR_REG_RTCCNTL_BASE + 0x28)
|
||||
#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F
|
||||
#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25
|
||||
#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF
|
||||
#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16
|
||||
#define RTC_CNTL_RTC_POWERUP_TIMER 0x0000007F
|
||||
#define RTC_CNTL_RTC_POWERUP_TIMER_S 9
|
||||
#define RTC_CNTL_RTC_WAIT_TIMER 0x000001FF
|
||||
#define RTC_CNTL_RTC_WAIT_TIMER_S 0
|
||||
|
||||
#define RTC_TIMER5 (DR_REG_RTCCNTL_BASE + 0x2c)
|
||||
#define RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F
|
||||
#define RTC_CNTL_RTCMEM_POWERUP_TIMER_S 25
|
||||
#define RTC_CNTL_RTCMEM_WAIT_TIMER 0x000001FF
|
||||
#define RTC_CNTL_RTCMEM_WAIT_TIMER_S 16
|
||||
#define RTC_CNTL_MIN_SLP_VAL 0x000000FF
|
||||
#define RTC_CNTL_MIN_SLP_VAL_S 8
|
||||
#define RTC_CNTL_SAR_SUBTIMER_PREDIV 0x000000FF
|
||||
#define RTC_CNTL_SAR_SUBTIMER_PREDIV_S 0
|
||||
|
||||
#define RTC_ANA_CONF (DR_REG_RTCCNTL_BASE + 0x30)
|
||||
#define RTC_CNTL_PLL_I2C_PU (BIT(31))
|
||||
#define RTC_CNTL_PLL_I2C_PU_S 31
|
||||
#define RTC_CNTL_CKGEN_I2C_PU (BIT(30))
|
||||
#define RTC_CNTL_CKGEN_I2C_PU_S 30
|
||||
#define RTC_CNTL_RFRX_PBUS_PU (BIT(28))
|
||||
#define RTC_CNTL_RFRX_PBUS_PU_S 28
|
||||
#define RTC_CNTL_TXRF_I2C_PU (BIT(27))
|
||||
#define RTC_CNTL_TXRF_I2C_PU_S 27
|
||||
#define RTC_CNTL_PVTMON_PU (BIT(26))
|
||||
#define RTC_CNTL_PVTMON_PU_S 26
|
||||
#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25))
|
||||
#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25
|
||||
#define RTC_CNTL_PLLA_FORCE_PU (BIT(24))
|
||||
#define RTC_CNTL_PLLA_FORCE_PU_S 24
|
||||
#define RTC_CNTL_PLLA_FORCE_PD (BIT(23))
|
||||
#define RTC_CNTL_PLLA_FORCE_PD_S 23
|
||||
|
||||
#define RTC_RESET_STATE (DR_REG_RTCCNTL_BASE + 0x34)
|
||||
#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13))
|
||||
#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13
|
||||
#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12))
|
||||
#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12
|
||||
#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F
|
||||
#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6
|
||||
#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F
|
||||
#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0
|
||||
|
||||
#define RTC_WAKEUP_STATE (DR_REG_RTCCNTL_BASE + 0x38)
|
||||
#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(22))
|
||||
#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 22
|
||||
#define RTC_CNTL_RTC_WAKEUP_ENA 0x000007FF
|
||||
#define RTC_CNTL_RTC_WAKEUP_ENA_S 11
|
||||
#define RTC_CNTL_WAKEUP_CAUSE 0x000007FF
|
||||
#define RTC_CNTL_WAKEUP_CAUSE_S 0
|
||||
|
||||
#define INT_ENA_RTC (DR_REG_RTCCNTL_BASE + 0x3c)
|
||||
#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA (BIT(8))
|
||||
#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_S 8
|
||||
#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA (BIT(7))
|
||||
#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_S 7
|
||||
#define RTC_CNTL_RTC_TOUCH_INT_ENA (BIT(6))
|
||||
#define RTC_CNTL_RTC_TOUCH_INT_ENA_S 6
|
||||
#define RTC_CNTL_RTC_SAR_INT_ENA (BIT(5))
|
||||
#define RTC_CNTL_RTC_SAR_INT_ENA_S 5
|
||||
#define RTC_CNTL_RTC_TIME_VALID_INT_ENA (BIT(4))
|
||||
#define RTC_CNTL_RTC_TIME_VALID_INT_ENA_S 4
|
||||
#define RTC_CNTL_RTC_WDT_INT_ENA (BIT(3))
|
||||
#define RTC_CNTL_RTC_WDT_INT_ENA_S 3
|
||||
#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2))
|
||||
#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2
|
||||
#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1))
|
||||
#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1
|
||||
#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0))
|
||||
#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0
|
||||
|
||||
#define INT_RAW_RTC (DR_REG_RTCCNTL_BASE + 0x40)
|
||||
#define RTC_CNTL_RTC_MAIN_TIMER_INT_RAW (BIT(8))
|
||||
#define RTC_CNTL_RTC_MAIN_TIMER_INT_RAW_S 8
|
||||
#define RTC_CNTL_RTC_BROWN_OUT_INT_RAW (BIT(7))
|
||||
#define RTC_CNTL_RTC_BROWN_OUT_INT_RAW_S 7
|
||||
#define RTC_CNTL_RTC_TOUCH_INT_RAW (BIT(6))
|
||||
#define RTC_CNTL_RTC_TOUCH_INT_RAW_S 6
|
||||
#define RTC_CNTL_RTC_SAR_INT_RAW (BIT(5))
|
||||
#define RTC_CNTL_RTC_SAR_INT_RAW_S 5
|
||||
#define RTC_CNTL_RTC_TIME_VALID_INT_RAW (BIT(4))
|
||||
#define RTC_CNTL_RTC_TIME_VALID_INT_RAW_S 4
|
||||
#define RTC_CNTL_RTC_WDT_INT_RAW (BIT(3))
|
||||
#define RTC_CNTL_RTC_WDT_INT_RAW_S 3
|
||||
#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2))
|
||||
#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2
|
||||
#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1))
|
||||
#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1
|
||||
#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0))
|
||||
#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0
|
||||
|
||||
#define INT_ST_RTC (DR_REG_RTCCNTL_BASE + 0x44)
|
||||
#define RTC_CNTL_RTC_MAIN_TIMER_INT_ST (BIT(8))
|
||||
#define RTC_CNTL_RTC_MAIN_TIMER_INT_ST_S 8
|
||||
#define RTC_CNTL_RTC_BROWN_OUT_INT_ST (BIT(7))
|
||||
#define RTC_CNTL_RTC_BROWN_OUT_INT_ST_S 7
|
||||
#define RTC_CNTL_RTC_TOUCH_INT_ST (BIT(6))
|
||||
#define RTC_CNTL_RTC_TOUCH_INT_ST_S 6
|
||||
#define RTC_CNTL_RTC_SAR_INT_ST (BIT(5))
|
||||
#define RTC_CNTL_RTC_SAR_INT_ST_S 5
|
||||
#define RTC_CNTL_RTC_TIME_VALID_INT_ST (BIT(4))
|
||||
#define RTC_CNTL_RTC_TIME_VALID_INT_ST_S 4
|
||||
#define RTC_CNTL_RTC_WDT_INT_ST (BIT(3))
|
||||
#define RTC_CNTL_RTC_WDT_INT_ST_S 3
|
||||
#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2))
|
||||
#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2
|
||||
#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1))
|
||||
#define RTC_CNTL_SLP_REJECT_INT_ST_S 1
|
||||
#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0))
|
||||
#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0
|
||||
|
||||
#define INT_CLR_RTC (DR_REG_RTCCNTL_BASE + 0x48)
|
||||
#define RTC_CNTL_RTC_MAIN_TIMER_INT_CLR (BIT(8))
|
||||
#define RTC_CNTL_RTC_MAIN_TIMER_INT_CLR_S 8
|
||||
#define RTC_CNTL_RTC_BROWN_OUT_INT_CLR (BIT(7))
|
||||
#define RTC_CNTL_RTC_BROWN_OUT_INT_CLR_S 7
|
||||
#define RTC_CNTL_RTC_TOUCH_INT_CLR (BIT(6))
|
||||
#define RTC_CNTL_RTC_TOUCH_INT_CLR_S 6
|
||||
#define RTC_CNTL_RTC_SAR_INT_CLR (BIT(5))
|
||||
#define RTC_CNTL_RTC_SAR_INT_CLR_S 5
|
||||
#define RTC_CNTL_RTC_TIME_VALID_INT_CLR (BIT(4))
|
||||
#define RTC_CNTL_RTC_TIME_VALID_INT_CLR_S 4
|
||||
#define RTC_CNTL_RTC_WDT_INT_CLR (BIT(3))
|
||||
#define RTC_CNTL_RTC_WDT_INT_CLR_S 3
|
||||
#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2))
|
||||
#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2
|
||||
#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1))
|
||||
#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1
|
||||
#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0))
|
||||
#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0
|
||||
|
||||
#define RTC_STORE0 (DR_REG_RTCCNTL_BASE + 0x4c)
|
||||
#define RTC_CNTL_RTC_SCRATCH0 0xFFFFFFFF
|
||||
#define RTC_CNTL_RTC_SCRATCH0_S 0
|
||||
|
||||
#define RTC_STORE1 (DR_REG_RTCCNTL_BASE + 0x50)
|
||||
#define RTC_CNTL_RTC_SCRATCH1 0xFFFFFFFF
|
||||
#define RTC_CNTL_RTC_SCRATCH1_S 0
|
||||
|
||||
#define RTC_STORE2 (DR_REG_RTCCNTL_BASE + 0x54)
|
||||
#define RTC_CNTL_RTC_SCRATCH2 0xFFFFFFFF
|
||||
#define RTC_CNTL_RTC_SCRATCH2_S 0
|
||||
|
||||
#define RTC_STORE3 (DR_REG_RTCCNTL_BASE + 0x58)
|
||||
#define RTC_CNTL_RTC_SCRATCH3 0xFFFFFFFF
|
||||
#define RTC_CNTL_RTC_SCRATCH3_S 0
|
||||
|
||||
#define RTC_EXT_XTL_CONF (DR_REG_RTCCNTL_BASE + 0x5c)
|
||||
#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31))
|
||||
#define RTC_CNTL_XTL_EXT_CTR_EN_S 31
|
||||
#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30))
|
||||
#define RTC_CNTL_XTL_EXT_CTR_LV_S 30
|
||||
|
||||
#define RTC_EXT_WAKEUP_CONF (DR_REG_RTCCNTL_BASE + 0x60)
|
||||
#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31))
|
||||
#define RTC_CNTL_EXT_WAKEUP1_LV_S 31
|
||||
#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30))
|
||||
#define RTC_CNTL_EXT_WAKEUP0_LV_S 30
|
||||
|
||||
#define RTC_SLP_REJECT_CONF (DR_REG_RTCCNTL_BASE + 0x64)
|
||||
#define RTC_CNTL_REJECT_CAUSE 0x0000000F
|
||||
#define RTC_CNTL_REJECT_CAUSE_S 28
|
||||
#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(27))
|
||||
#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 27
|
||||
#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(26))
|
||||
#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 26
|
||||
#define RTC_CNTL_SDIO_REJECT_EN (BIT(25))
|
||||
#define RTC_CNTL_SDIO_REJECT_EN_S 25
|
||||
#define RTC_CNTL_GPIO_REJECT_EN (BIT(24))
|
||||
#define RTC_CNTL_GPIO_REJECT_EN_S 24
|
||||
|
||||
#define RTC_CPU_PERIOD_CONF (DR_REG_RTCCNTL_BASE + 0x68)
|
||||
#define RTC_CNTL_RTC_CPUPERIOD_SEL 0x00000003
|
||||
#define RTC_CNTL_RTC_CPUPERIOD_SEL_S 30
|
||||
#define RTC_CNTL_RTC_CPUSEL_CONF (BIT(29))
|
||||
#define RTC_CNTL_RTC_CPUSEL_CONF_S 29
|
||||
|
||||
#define RTC_SDIO_ACT_CONF (DR_REG_RTCCNTL_BASE + 0x6c)
|
||||
#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF
|
||||
#define RTC_CNTL_SDIO_ACT_DNUM_S 22
|
||||
|
||||
#define RTC_CLK_CONF (DR_REG_RTCCNTL_BASE + 0x70)
|
||||
#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003
|
||||
#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30
|
||||
#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29))
|
||||
#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29
|
||||
#define RTC_CNTL_SOC_CLK_SEL 0x00000003
|
||||
#define RTC_CNTL_SOC_CLK_SEL_S 27
|
||||
#define RTC_CNTL_CK12M_FORCE_PU (BIT(26))
|
||||
#define RTC_CNTL_CK12M_FORCE_PU_S 26
|
||||
#define RTC_CNTL_CK12M_FORCE_PD (BIT(25))
|
||||
#define RTC_CNTL_CK12M_FORCE_PD_S 25
|
||||
#define RTC_CNTL_CK12M_DFREQ 0x000000FF
|
||||
#define RTC_CNTL_CK12M_DFREQ_S 17
|
||||
#define RTC_CNTL_CK12M_FORCE_NOGATING (BIT(16))
|
||||
#define RTC_CNTL_CK12M_FORCE_NOGATING_S 16
|
||||
#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15))
|
||||
#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15
|
||||
#define RTC_CNTL_CK12M_DIV_SEL 0x00000007
|
||||
#define RTC_CNTL_CK12M_DIV_SEL_S 12
|
||||
#define RTC_CNTL_CK12M_DFREQ_FORCE (BIT(11))
|
||||
#define RTC_CNTL_CK12M_DFREQ_FORCE_S 11
|
||||
#define RTC_CNTL_DIG_CLK12M_EN (BIT(10))
|
||||
#define RTC_CNTL_DIG_CLK12M_EN_S 10
|
||||
#define RTC_CNTL_DIG_CLK12M_D256_EN (BIT(9))
|
||||
#define RTC_CNTL_DIG_CLK12M_D256_EN_S 9
|
||||
#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8))
|
||||
#define RTC_CNTL_DIG_XTAL32K_EN_S 8
|
||||
#define RTC_CNTL_ENB_CK12M_DIV (BIT(7))
|
||||
#define RTC_CNTL_ENB_CK12M_DIV_S 7
|
||||
#define RTC_CNTL_ENB_CK12M (BIT(6))
|
||||
#define RTC_CNTL_ENB_CK12M_S 6
|
||||
#define RTC_CNTL_CK12M_DIV 0x00000003
|
||||
#define RTC_CNTL_CK12M_DIV_S 4
|
||||
|
||||
#define RTC_SDIO_CONF (DR_REG_RTCCNTL_BASE + 0x74)
|
||||
#define RTC_CNTL_XPD_SDIO_REG (BIT(31))
|
||||
#define RTC_CNTL_XPD_SDIO_REG_S 31
|
||||
#define RTC_CNTL_DREFH_SDIO 0x00000003
|
||||
#define RTC_CNTL_DREFH_SDIO_S 29
|
||||
#define RTC_CNTL_DREFM_SDIO 0x00000003
|
||||
#define RTC_CNTL_DREFM_SDIO_S 27
|
||||
#define RTC_CNTL_DREFL_SDIO 0x00000003
|
||||
#define RTC_CNTL_DREFL_SDIO_S 25
|
||||
#define RTC_CNTL_REG1P8_READY (BIT(24))
|
||||
#define RTC_CNTL_REG1P8_READY_S 24
|
||||
#define RTC_CNTL_SDIO_TIEH (BIT(23))
|
||||
#define RTC_CNTL_SDIO_TIEH_S 23
|
||||
#define RTC_CNTL_SDIO_FORCE (BIT(22))
|
||||
#define RTC_CNTL_SDIO_FORCE_S 22
|
||||
#define RTC_CNTL_SDIO_REG_PD_EN (BIT(21))
|
||||
#define RTC_CNTL_SDIO_REG_PD_EN_S 21
|
||||
|
||||
#define RTC_BIAS_CONF (DR_REG_RTCCNTL_BASE + 0x78)
|
||||
#define RTC_CNTL_RST_BIAS_I2C (BIT(31))
|
||||
#define RTC_CNTL_RST_BIAS_I2C_S 31
|
||||
#define RTC_CNTL_DEC_HEARTBEAT_WIDTH (BIT(30))
|
||||
#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S 30
|
||||
#define RTC_CNTL_INC_HEARTBEAT_PERIOD (BIT(29))
|
||||
#define RTC_CNTL_INC_HEARTBEAT_PERIOD_S 29
|
||||
#define RTC_CNTL_DEC_HEARTBEAT_PERIOD (BIT(28))
|
||||
#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S 28
|
||||
#define RTC_CNTL_INC_HEARTBEAT_REFRESH (BIT(27))
|
||||
#define RTC_CNTL_INC_HEARTBEAT_REFRESH_S 27
|
||||
#define RTC_CNTL_ENB_SCK_XTAL (BIT(26))
|
||||
#define RTC_CNTL_ENB_SCK_XTAL_S 26
|
||||
#define RTC_CNTL_DBG_ATTEN 0x00000003
|
||||
#define RTC_CNTL_DBG_ATTEN_S 24
|
||||
|
||||
#define RTC_REG (DR_REG_RTCCNTL_BASE + 0x7c)
|
||||
#define RTC_CNTL_RTC_REG_FORCE_PU (BIT(31))
|
||||
#define RTC_CNTL_RTC_REG_FORCE_PU_S 31
|
||||
#define RTC_CNTL_RTC_REG_FORCE_PD (BIT(30))
|
||||
#define RTC_CNTL_RTC_REG_FORCE_PD_S 30
|
||||
#define RTC_CNTL_RTC_DBOOST_FORCE_PU (BIT(29))
|
||||
#define RTC_CNTL_RTC_DBOOST_FORCE_PU_S 29
|
||||
#define RTC_CNTL_RTC_DBOOST_FORCE_PD (BIT(28))
|
||||
#define RTC_CNTL_RTC_DBOOST_FORCE_PD_S 28
|
||||
#define RTC_CNTL_RTC_DBIAS_WAK 0x00000007
|
||||
#define RTC_CNTL_RTC_DBIAS_WAK_S 25
|
||||
#define RTC_CNTL_RTC_DBIAS_SLP 0x00000007
|
||||
#define RTC_CNTL_RTC_DBIAS_SLP_S 22
|
||||
#define RTC_CNTL_SCK_DCAP 0x000000FF
|
||||
#define RTC_CNTL_SCK_DCAP_S 14
|
||||
#define RTC_CNTL_DIG_REG_DBIAS_WAK 0x00000007
|
||||
#define RTC_CNTL_DIG_REG_DBIAS_WAK_S 11
|
||||
#define RTC_CNTL_DIG_REG_DBIAS_SLP 0x00000007
|
||||
#define RTC_CNTL_DIG_REG_DBIAS_SLP_S 8
|
||||
#define RTC_CNTL_SCK_DCAP_FORCE (BIT(7))
|
||||
#define RTC_CNTL_SCK_DCAP_FORCE_S 7
|
||||
|
||||
#define RTC_PWC (DR_REG_RTCCNTL_BASE + 0x80)
|
||||
#define RTC_CNTL_RTC_PD_EN (BIT(20))
|
||||
#define RTC_CNTL_RTC_PD_EN_S 20
|
||||
#define RTC_CNTL_RTC_FORCE_PU (BIT(19))
|
||||
#define RTC_CNTL_RTC_FORCE_PU_S 19
|
||||
#define RTC_CNTL_RTC_FORCE_PD (BIT(18))
|
||||
#define RTC_CNTL_RTC_FORCE_PD_S 18
|
||||
#define RTC_CNTL_RTC_SLOWMEM_PD_EN (BIT(17))
|
||||
#define RTC_CNTL_RTC_SLOWMEM_PD_EN_S 17
|
||||
#define RTC_CNTL_RTC_SLOWMEM_FORCE_PU (BIT(16))
|
||||
#define RTC_CNTL_RTC_SLOWMEM_FORCE_PU_S 16
|
||||
#define RTC_CNTL_RTC_SLOWMEM_FORCE_PD (BIT(15))
|
||||
#define RTC_CNTL_RTC_SLOWMEM_FORCE_PD_S 15
|
||||
#define RTC_CNTL_RTC_FASTMEM_PD_EN (BIT(14))
|
||||
#define RTC_CNTL_RTC_FASTMEM_PD_EN_S 14
|
||||
#define RTC_CNTL_RTC_FASTMEM_FORCE_PU (BIT(13))
|
||||
#define RTC_CNTL_RTC_FASTMEM_FORCE_PU_S 13
|
||||
#define RTC_CNTL_RTC_FASTMEM_FORCE_PD (BIT(12))
|
||||
#define RTC_CNTL_RTC_FASTMEM_FORCE_PD_S 12
|
||||
#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPU (BIT(11))
|
||||
#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPU_S 11
|
||||
#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPD (BIT(10))
|
||||
#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPD_S 10
|
||||
#define RTC_CNTL_RTC_SLOWMEM_FOLW_CPU (BIT(9))
|
||||
#define RTC_CNTL_RTC_SLOWMEM_FOLW_CPU_S 9
|
||||
#define RTC_CNTL_RTC_FASTMEM_FORCE_LPU (BIT(8))
|
||||
#define RTC_CNTL_RTC_FASTMEM_FORCE_LPU_S 8
|
||||
#define RTC_CNTL_RTC_FASTMEM_FORCE_LPD (BIT(7))
|
||||
#define RTC_CNTL_RTC_FASTMEM_FORCE_LPD_S 7
|
||||
#define RTC_CNTL_RTC_FASTMEM_FOLW_CPU (BIT(6))
|
||||
#define RTC_CNTL_RTC_FASTMEM_FOLW_CPU_S 6
|
||||
#define RTC_CNTL_RTC_FORCE_NOISO (BIT(5))
|
||||
#define RTC_CNTL_RTC_FORCE_NOISO_S 5
|
||||
#define RTC_CNTL_RTC_FORCE_ISO (BIT(4))
|
||||
#define RTC_CNTL_RTC_FORCE_ISO_S 4
|
||||
#define RTC_CNTL_RTC_SLOWMEM_FORCE_ISO (BIT(3))
|
||||
#define RTC_CNTL_RTC_SLOWMEM_FORCE_ISO_S 3
|
||||
#define RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO (BIT(2))
|
||||
#define RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO_S 2
|
||||
#define RTC_CNTL_RTC_FASTMEM_FORCE_ISO (BIT(1))
|
||||
#define RTC_CNTL_RTC_FASTMEM_FORCE_ISO_S 1
|
||||
#define RTC_CNTL_RTC_FASTMEM_FORCE_NOISO (BIT(0))
|
||||
#define RTC_CNTL_RTC_FASTMEM_FORCE_NOISO_S 0
|
||||
|
||||
#define DIG_PWC (DR_REG_RTCCNTL_BASE + 0x84)
|
||||
#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31))
|
||||
#define RTC_CNTL_DG_WRAP_PD_EN_S 31
|
||||
#define RTC_CNTL_WIFI_PD_EN (BIT(30))
|
||||
#define RTC_CNTL_WIFI_PD_EN_S 30
|
||||
#define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29))
|
||||
#define RTC_CNTL_INTER_RAM4_PD_EN_S 29
|
||||
#define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28))
|
||||
#define RTC_CNTL_INTER_RAM3_PD_EN_S 28
|
||||
#define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27))
|
||||
#define RTC_CNTL_INTER_RAM2_PD_EN_S 27
|
||||
#define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26))
|
||||
#define RTC_CNTL_INTER_RAM1_PD_EN_S 26
|
||||
#define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25))
|
||||
#define RTC_CNTL_INTER_RAM0_PD_EN_S 25
|
||||
#define RTC_CNTL_ROM0_PD_EN (BIT(24))
|
||||
#define RTC_CNTL_ROM0_PD_EN_S 24
|
||||
#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20))
|
||||
#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20
|
||||
#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19))
|
||||
#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19
|
||||
#define RTC_CNTL_WIFI_FORCE_PU (BIT(18))
|
||||
#define RTC_CNTL_WIFI_FORCE_PU_S 18
|
||||
#define RTC_CNTL_WIFI_FORCE_PD (BIT(17))
|
||||
#define RTC_CNTL_WIFI_FORCE_PD_S 17
|
||||
#define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16))
|
||||
#define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16
|
||||
#define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15))
|
||||
#define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15
|
||||
#define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14))
|
||||
#define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14
|
||||
#define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13))
|
||||
#define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13
|
||||
#define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12))
|
||||
#define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12
|
||||
#define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11))
|
||||
#define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11
|
||||
#define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10))
|
||||
#define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10
|
||||
#define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9))
|
||||
#define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9
|
||||
#define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8))
|
||||
#define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8
|
||||
#define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7))
|
||||
#define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7
|
||||
#define RTC_CNTL_ROM0_FORCE_PU (BIT(6))
|
||||
#define RTC_CNTL_ROM0_FORCE_PU_S 6
|
||||
#define RTC_CNTL_ROM0_FORCE_PD (BIT(5))
|
||||
#define RTC_CNTL_ROM0_FORCE_PD_S 5
|
||||
#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4))
|
||||
#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4
|
||||
#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3))
|
||||
#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3
|
||||
|
||||
#define DIG_ISO (DR_REG_RTCCNTL_BASE + 0x88)
|
||||
#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31))
|
||||
#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31
|
||||
#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30))
|
||||
#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30
|
||||
#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29))
|
||||
#define RTC_CNTL_WIFI_FORCE_NOISO_S 29
|
||||
#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28))
|
||||
#define RTC_CNTL_WIFI_FORCE_ISO_S 28
|
||||
#define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27))
|
||||
#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27
|
||||
#define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26))
|
||||
#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26
|
||||
#define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25))
|
||||
#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25
|
||||
#define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24))
|
||||
#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24
|
||||
#define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23))
|
||||
#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23
|
||||
#define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22))
|
||||
#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22
|
||||
#define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21))
|
||||
#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21
|
||||
#define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20))
|
||||
#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20
|
||||
#define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19))
|
||||
#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19
|
||||
#define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18))
|
||||
#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18
|
||||
#define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17))
|
||||
#define RTC_CNTL_ROM0_FORCE_NOISO_S 17
|
||||
#define RTC_CNTL_ROM0_FORCE_ISO (BIT(16))
|
||||
#define RTC_CNTL_ROM0_FORCE_ISO_S 16
|
||||
#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15))
|
||||
#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15
|
||||
#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14))
|
||||
#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14
|
||||
#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13))
|
||||
#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13
|
||||
#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12))
|
||||
#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12
|
||||
#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11))
|
||||
#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11
|
||||
#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10))
|
||||
#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10
|
||||
#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9))
|
||||
#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9
|
||||
#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8))
|
||||
#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8
|
||||
#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7))
|
||||
#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7
|
||||
|
||||
#define RTC_WDTCONFIG0 (DR_REG_RTCCNTL_BASE + 0x8c)
|
||||
#define RTC_CNTL_WDT_EN (BIT(31))
|
||||
#define RTC_CNTL_WDT_EN_S 31
|
||||
#define RTC_CNTL_WDT_STG0 0x00000007
|
||||
#define RTC_CNTL_WDT_STG0_S 28
|
||||
#define RTC_CNTL_WDT_STG1 0x00000007
|
||||
#define RTC_CNTL_WDT_STG1_S 25
|
||||
#define RTC_CNTL_WDT_STG2 0x00000007
|
||||
#define RTC_CNTL_WDT_STG2_S 22
|
||||
#define RTC_CNTL_WDT_STG3 0x00000007
|
||||
#define RTC_CNTL_WDT_STG3_S 19
|
||||
#define RTC_CNTL_WDT_EDGE_INT_EN (BIT(18))
|
||||
#define RTC_CNTL_WDT_EDGE_INT_EN_S 18
|
||||
#define RTC_CNTL_WDT_LEVEL_INT_EN (BIT(17))
|
||||
#define RTC_CNTL_WDT_LEVEL_INT_EN_S 17
|
||||
#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007
|
||||
#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 14
|
||||
#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007
|
||||
#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 11
|
||||
#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(10))
|
||||
#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 10
|
||||
#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(9))
|
||||
#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 9
|
||||
#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(8))
|
||||
#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 8
|
||||
#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(7))
|
||||
#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 7
|
||||
|
||||
#define RTC_WDTCONFIG1 (DR_REG_RTCCNTL_BASE + 0x90)
|
||||
#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF
|
||||
#define RTC_CNTL_WDT_STG0_HOLD_S 0
|
||||
|
||||
#define RTC_WDTCONFIG2 (DR_REG_RTCCNTL_BASE + 0x94)
|
||||
#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF
|
||||
#define RTC_CNTL_WDT_STG1_HOLD_S 0
|
||||
|
||||
#define RTC_WDTCONFIG3 (DR_REG_RTCCNTL_BASE + 0x98)
|
||||
#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF
|
||||
#define RTC_CNTL_WDT_STG2_HOLD_S 0
|
||||
|
||||
#define RTC_WDTCONFIG4 (DR_REG_RTCCNTL_BASE + 0x9c)
|
||||
#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF
|
||||
#define RTC_CNTL_WDT_STG3_HOLD_S 0
|
||||
|
||||
#define RTC_WDTFEED (DR_REG_RTCCNTL_BASE + 0xa0)
|
||||
#define RTC_CNTL_RTC_WDT_FEED (BIT(31))
|
||||
#define RTC_CNTL_RTC_WDT_FEED_S 31
|
||||
|
||||
#define RTC_WDTWPROTECT (DR_REG_RTCCNTL_BASE + 0xa4)
|
||||
#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF
|
||||
#define RTC_CNTL_WDT_WKEY_S 0
|
||||
|
||||
#define RTC_TEST_MUX (DR_REG_RTCCNTL_BASE + 0xa8)
|
||||
#define RTC_CNTL_DTEST_RTC 0x00000003
|
||||
#define RTC_CNTL_DTEST_RTC_S 30
|
||||
#define RTC_CNTL_ENT_RTC (BIT(29))
|
||||
#define RTC_CNTL_ENT_RTC_S 29
|
||||
|
||||
#define RTC_SW_CPU_STALL (DR_REG_RTCCNTL_BASE + 0xac)
|
||||
#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F
|
||||
#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26
|
||||
#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F
|
||||
#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20
|
||||
|
||||
#define RTC_STORE4 (DR_REG_RTCCNTL_BASE + 0xb0)
|
||||
#define RTC_CNTL_RTC_SCRATCH4 0xFFFFFFFF
|
||||
#define RTC_CNTL_RTC_SCRATCH4_S 0
|
||||
|
||||
#define RTC_STORE5 (DR_REG_RTCCNTL_BASE + 0xb4)
|
||||
#define RTC_CNTL_RTC_SCRATCH5 0xFFFFFFFF
|
||||
#define RTC_CNTL_RTC_SCRATCH5_S 0
|
||||
|
||||
#define RTC_STORE6 (DR_REG_RTCCNTL_BASE + 0xb8)
|
||||
#define RTC_CNTL_RTC_SCRATCH6 0xFFFFFFFF
|
||||
#define RTC_CNTL_RTC_SCRATCH6_S 0
|
||||
|
||||
#define RTC_STORE7 (DR_REG_RTCCNTL_BASE + 0xbc)
|
||||
#define RTC_CNTL_RTC_SCRATCH7 0xFFFFFFFF
|
||||
#define RTC_CNTL_RTC_SCRATCH7_S 0
|
||||
|
||||
#define RTC_DIAG0 (DR_REG_RTCCNTL_BASE + 0xc0)
|
||||
#define RTC_CNTL_RTC_LOW_POWER_DIAG0 0xFFFFFFFF
|
||||
#define RTC_CNTL_RTC_LOW_POWER_DIAG0_S 0
|
||||
|
||||
#define RTC_DIAG1 (DR_REG_RTCCNTL_BASE + 0xc4)
|
||||
#define RTC_CNTL_RTC_LOW_POWER_DIAG1 0xFFFFFFFF
|
||||
#define RTC_CNTL_RTC_LOW_POWER_DIAG1_S 0
|
||||
|
||||
#define RTC_HOLD_FORCE (DR_REG_RTCCNTL_BASE + 0xc8)
|
||||
#define RTC_CNTL_X32N_HOLD_FORCE (BIT(17))
|
||||
#define RTC_CNTL_X32N_HOLD_FORCE_S 17
|
||||
#define RTC_CNTL_X32P_HOLD_FORCE (BIT(16))
|
||||
#define RTC_CNTL_X32P_HOLD_FORCE_S 16
|
||||
#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE (BIT(15))
|
||||
#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_S 15
|
||||
#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE (BIT(14))
|
||||
#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_S 14
|
||||
#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE (BIT(13))
|
||||
#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_S 13
|
||||
#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE (BIT(12))
|
||||
#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_S 12
|
||||
#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE (BIT(11))
|
||||
#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_S 11
|
||||
#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE (BIT(10))
|
||||
#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_S 10
|
||||
#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE (BIT(9))
|
||||
#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_S 9
|
||||
#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE (BIT(8))
|
||||
#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_S 8
|
||||
#define RTC_CNTL_SENSE4_HOLD_FORCE (BIT(7))
|
||||
#define RTC_CNTL_SENSE4_HOLD_FORCE_S 7
|
||||
#define RTC_CNTL_SENSE3_HOLD_FORCE (BIT(6))
|
||||
#define RTC_CNTL_SENSE3_HOLD_FORCE_S 6
|
||||
#define RTC_CNTL_SENSE2_HOLD_FORCE (BIT(5))
|
||||
#define RTC_CNTL_SENSE2_HOLD_FORCE_S 5
|
||||
#define RTC_CNTL_SENSE1_HOLD_FORCE (BIT(4))
|
||||
#define RTC_CNTL_SENSE1_HOLD_FORCE_S 4
|
||||
#define RTC_CNTL_PDAC2_HOLD_FORCE (BIT(3))
|
||||
#define RTC_CNTL_PDAC2_HOLD_FORCE_S 3
|
||||
#define RTC_CNTL_PDAC1_HOLD_FORCE (BIT(2))
|
||||
#define RTC_CNTL_PDAC1_HOLD_FORCE_S 2
|
||||
#define RTC_CNTL_ADC2_HOLD_FORCE (BIT(1))
|
||||
#define RTC_CNTL_ADC2_HOLD_FORCE_S 1
|
||||
#define RTC_CNTL_ADC1_HOLD_FORCE (BIT(0))
|
||||
#define RTC_CNTL_ADC1_HOLD_FORCE_S 0
|
||||
|
||||
#define RTC_EXT_WAKEUP1 (DR_REG_RTCCNTL_BASE + 0xcc)
|
||||
#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(18))
|
||||
#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 18
|
||||
#define RTC_CNTL_EXT_WAKEUP1_SEL 0x0003FFFF
|
||||
#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0
|
||||
|
||||
#define RTC_EXT_WAKEUP1_STATUS (DR_REG_RTCCNTL_BASE + 0xd0)
|
||||
#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x0003FFFF
|
||||
#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0
|
||||
|
||||
#define RTC_BROWN_OUT (DR_REG_RTCCNTL_BASE + 0xd4)
|
||||
#define RTC_CNTL_RTC_BROWN_OUT_DET (BIT(31))
|
||||
#define RTC_CNTL_RTC_BROWN_OUT_DET_S 31
|
||||
#define RTC_CNTL_BROWN_OUT_ENA (BIT(30))
|
||||
#define RTC_CNTL_BROWN_OUT_ENA_S 30
|
||||
#define RTC_CNTL_DBROWN_OUT_THRES 0x00000007
|
||||
#define RTC_CNTL_DBROWN_OUT_THRES_S 27
|
||||
#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26))
|
||||
#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26
|
||||
#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF
|
||||
#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16
|
||||
#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15))
|
||||
#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15
|
||||
#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14))
|
||||
#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14
|
||||
|
||||
#define RTC_MEM_CONF (DR_REG_RTCCNTL_BASE + 0x40 * 4)
|
||||
#define RTC_MEM_CRC_FINISH (BIT(31))
|
||||
#define RTC_MEM_CRC_FINISH_S (31)
|
||||
#define RTC_MEM_CRC_LEN (0x7ff)
|
||||
#define RTC_MEM_CRC_LEN_S (20)
|
||||
#define RTC_MEM_CRC_ADDR (0x7ff)
|
||||
#define RTC_MEM_CRC_ADDR_S (9)
|
||||
#define RTC_MEM_CRC_START (BIT(8))
|
||||
#define RTC_MEM_CRC_START_S (8)
|
||||
#define RTC_MEM_PID_CONF (0xff)
|
||||
#define RTC_MEM_PID_CONF_S (0)
|
||||
|
||||
#define RTC_MEM_CRC_RES (DR_REG_RTCCNTL_BASE + 0x41 * 4)
|
||||
|
||||
|
||||
#define RTC_CNTL_DATE (DR_REG_RTCCNTL_BASE + 0x13c)
|
||||
#define RTC_CNTL_RTC_CNTL_DATE 0x0FFFFFFF
|
||||
#define RTC_CNTL_RTC_CNTL_DATE_S 0
|
||||
#define RTC_CNTL_RTC_CNTL_DATE_VERSION 0x1604280
|
||||
|
||||
#endif /* _SOC_RTC_CNTL_REG_H_ */
|
||||
@@ -0,0 +1,723 @@
|
||||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_RTC_IO_REG_H_
|
||||
#define _SOC_RTC_IO_REG_H_
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define RTC_GPIO_OUT (DR_REG_RTCIO_BASE + 0x0)
|
||||
#define RTC_IO_RTC_GPIO_OUT_DATA 0x0003FFFF
|
||||
#define RTC_IO_RTC_GPIO_OUT_DATA_S 14
|
||||
|
||||
#define RTC_GPIO_OUT_W1TS (DR_REG_RTCIO_BASE + 0x4)
|
||||
#define RTC_IO_RTC_GPIO_OUT_DATA_W1TS 0x0003FFFF
|
||||
#define RTC_IO_RTC_GPIO_OUT_DATA_W1TS_S 14
|
||||
|
||||
#define RTC_GPIO_OUT_W1TC (DR_REG_RTCIO_BASE + 0x8)
|
||||
#define RTC_IO_RTC_GPIO_OUT_DATA_W1TC 0x0003FFFF
|
||||
#define RTC_IO_RTC_GPIO_OUT_DATA_W1TC_S 14
|
||||
|
||||
#define RTC_GPIO_ENABLE (DR_REG_RTCIO_BASE + 0xc)
|
||||
#define RTC_IO_RTC_GPIO_ENABLE 0x0003FFFF
|
||||
#define RTC_IO_RTC_GPIO_ENABLE_S 14
|
||||
|
||||
#define RTC_GPIO_ENABLE_W1TS (DR_REG_RTCIO_BASE + 0x10)
|
||||
#define RTC_IO_RTC_GPIO_ENABLE_W1TS 0x0003FFFF
|
||||
#define RTC_IO_RTC_GPIO_ENABLE_W1TS_S 14
|
||||
|
||||
#define RTC_GPIO_ENABLE_W1TC (DR_REG_RTCIO_BASE + 0x14)
|
||||
#define RTC_IO_RTC_GPIO_ENABLE_W1TC 0x0003FFFF
|
||||
#define RTC_IO_RTC_GPIO_ENABLE_W1TC_S 14
|
||||
|
||||
#define RTC_GPIO_STATUS (DR_REG_RTCIO_BASE + 0x18)
|
||||
#define RTC_IO_RTC_GPIO_STATUS_INT 0x0003FFFF
|
||||
#define RTC_IO_RTC_GPIO_STATUS_INT_S 14
|
||||
|
||||
#define RTC_GPIO_STATUS_W1TS (DR_REG_RTCIO_BASE + 0x1c)
|
||||
#define RTC_IO_RTC_GPIO_STATUS_INT_W1TS 0x0003FFFF
|
||||
#define RTC_IO_RTC_GPIO_STATUS_INT_W1TS_S 14
|
||||
|
||||
#define RTC_GPIO_STATUS_W1TC (DR_REG_RTCIO_BASE + 0x20)
|
||||
#define RTC_IO_RTC_GPIO_STATUS_INT_W1TC 0x0003FFFF
|
||||
#define RTC_IO_RTC_GPIO_STATUS_INT_W1TC_S 14
|
||||
|
||||
#define RTC_GPIO_IN (DR_REG_RTCIO_BASE + 0x24)
|
||||
#define RTC_IO_RTC_GPIO_IN_NEXT 0x0003FFFF
|
||||
#define RTC_IO_RTC_GPIO_IN_NEXT_S 14
|
||||
|
||||
#define RTC_GPIO_PIN0 (DR_REG_RTCIO_BASE + 0x28)
|
||||
#define RTC_IO_RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10))
|
||||
#define RTC_IO_RTC_GPIO_PIN0_WAKEUP_ENABLE_S 10
|
||||
#define RTC_IO_RTC_GPIO_PIN0_INT_TYPE 0x00000007
|
||||
#define RTC_IO_RTC_GPIO_PIN0_INT_TYPE_S 7
|
||||
#define RTC_IO_RTC_GPIO_PIN0_PAD_DRIVER (BIT(2))
|
||||
#define RTC_IO_RTC_GPIO_PIN0_PAD_DRIVER_S 2
|
||||
|
||||
#define RTC_GPIO_PIN1 (DR_REG_RTCIO_BASE + 0x2c)
|
||||
#define RTC_IO_RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10))
|
||||
#define RTC_IO_RTC_GPIO_PIN1_WAKEUP_ENABLE_S 10
|
||||
#define RTC_IO_RTC_GPIO_PIN1_INT_TYPE 0x00000007
|
||||
#define RTC_IO_RTC_GPIO_PIN1_INT_TYPE_S 7
|
||||
#define RTC_IO_RTC_GPIO_PIN1_PAD_DRIVER (BIT(2))
|
||||
#define RTC_IO_RTC_GPIO_PIN1_PAD_DRIVER_S 2
|
||||
|
||||
#define RTC_GPIO_PIN2 (DR_REG_RTCIO_BASE + 0x30)
|
||||
#define RTC_IO_RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10))
|
||||
#define RTC_IO_RTC_GPIO_PIN2_WAKEUP_ENABLE_S 10
|
||||
#define RTC_IO_RTC_GPIO_PIN2_INT_TYPE 0x00000007
|
||||
#define RTC_IO_RTC_GPIO_PIN2_INT_TYPE_S 7
|
||||
#define RTC_IO_RTC_GPIO_PIN2_PAD_DRIVER (BIT(2))
|
||||
#define RTC_IO_RTC_GPIO_PIN2_PAD_DRIVER_S 2
|
||||
|
||||
#define RTC_GPIO_PIN3 (DR_REG_RTCIO_BASE + 0x34)
|
||||
#define RTC_IO_RTC_GPIO_PIN3_WAKEUP_ENABLE (BIT(10))
|
||||
#define RTC_IO_RTC_GPIO_PIN3_WAKEUP_ENABLE_S 10
|
||||
#define RTC_IO_RTC_GPIO_PIN3_INT_TYPE 0x00000007
|
||||
#define RTC_IO_RTC_GPIO_PIN3_INT_TYPE_S 7
|
||||
#define RTC_IO_RTC_GPIO_PIN3_PAD_DRIVER (BIT(2))
|
||||
#define RTC_IO_RTC_GPIO_PIN3_PAD_DRIVER_S 2
|
||||
|
||||
#define RTC_GPIO_PIN4 (DR_REG_RTCIO_BASE + 0x38)
|
||||
#define RTC_IO_RTC_GPIO_PIN4_WAKEUP_ENABLE (BIT(10))
|
||||
#define RTC_IO_RTC_GPIO_PIN4_WAKEUP_ENABLE_S 10
|
||||
#define RTC_IO_RTC_GPIO_PIN4_INT_TYPE 0x00000007
|
||||
#define RTC_IO_RTC_GPIO_PIN4_INT_TYPE_S 7
|
||||
#define RTC_IO_RTC_GPIO_PIN4_PAD_DRIVER (BIT(2))
|
||||
#define RTC_IO_RTC_GPIO_PIN4_PAD_DRIVER_S 2
|
||||
|
||||
#define RTC_GPIO_PIN5 (DR_REG_RTCIO_BASE + 0x3c)
|
||||
#define RTC_IO_RTC_GPIO_PIN5_WAKEUP_ENABLE (BIT(10))
|
||||
#define RTC_IO_RTC_GPIO_PIN5_WAKEUP_ENABLE_S 10
|
||||
#define RTC_IO_RTC_GPIO_PIN5_INT_TYPE 0x00000007
|
||||
#define RTC_IO_RTC_GPIO_PIN5_INT_TYPE_S 7
|
||||
#define RTC_IO_RTC_GPIO_PIN5_PAD_DRIVER (BIT(2))
|
||||
#define RTC_IO_RTC_GPIO_PIN5_PAD_DRIVER_S 2
|
||||
|
||||
#define RTC_GPIO_PIN6 (DR_REG_RTCIO_BASE + 0x40)
|
||||
#define RTC_IO_RTC_GPIO_PIN6_WAKEUP_ENABLE (BIT(10))
|
||||
#define RTC_IO_RTC_GPIO_PIN6_WAKEUP_ENABLE_S 10
|
||||
#define RTC_IO_RTC_GPIO_PIN6_INT_TYPE 0x00000007
|
||||
#define RTC_IO_RTC_GPIO_PIN6_INT_TYPE_S 7
|
||||
#define RTC_IO_RTC_GPIO_PIN6_PAD_DRIVER (BIT(2))
|
||||
#define RTC_IO_RTC_GPIO_PIN6_PAD_DRIVER_S 2
|
||||
|
||||
#define RTC_GPIO_PIN7 (DR_REG_RTCIO_BASE + 0x44)
|
||||
#define RTC_IO_RTC_GPIO_PIN7_WAKEUP_ENABLE (BIT(10))
|
||||
#define RTC_IO_RTC_GPIO_PIN7_WAKEUP_ENABLE_S 10
|
||||
#define RTC_IO_RTC_GPIO_PIN7_INT_TYPE 0x00000007
|
||||
#define RTC_IO_RTC_GPIO_PIN7_INT_TYPE_S 7
|
||||
#define RTC_IO_RTC_GPIO_PIN7_PAD_DRIVER (BIT(2))
|
||||
#define RTC_IO_RTC_GPIO_PIN7_PAD_DRIVER_S 2
|
||||
|
||||
#define RTC_GPIO_PIN8 (DR_REG_RTCIO_BASE + 0x48)
|
||||
#define RTC_IO_RTC_GPIO_PIN8_WAKEUP_ENABLE (BIT(10))
|
||||
#define RTC_IO_RTC_GPIO_PIN8_WAKEUP_ENABLE_S 10
|
||||
#define RTC_IO_RTC_GPIO_PIN8_INT_TYPE 0x00000007
|
||||
#define RTC_IO_RTC_GPIO_PIN8_INT_TYPE_S 7
|
||||
#define RTC_IO_RTC_GPIO_PIN8_PAD_DRIVER (BIT(2))
|
||||
#define RTC_IO_RTC_GPIO_PIN8_PAD_DRIVER_S 2
|
||||
|
||||
#define RTC_GPIO_PIN9 (DR_REG_RTCIO_BASE + 0x4c)
|
||||
#define RTC_IO_RTC_GPIO_PIN9_WAKEUP_ENABLE (BIT(10))
|
||||
#define RTC_IO_RTC_GPIO_PIN9_WAKEUP_ENABLE_S 10
|
||||
#define RTC_IO_RTC_GPIO_PIN9_INT_TYPE 0x00000007
|
||||
#define RTC_IO_RTC_GPIO_PIN9_INT_TYPE_S 7
|
||||
#define RTC_IO_RTC_GPIO_PIN9_PAD_DRIVER (BIT(2))
|
||||
#define RTC_IO_RTC_GPIO_PIN9_PAD_DRIVER_S 2
|
||||
|
||||
#define RTC_GPIO_PIN10 (DR_REG_RTCIO_BASE + 0x50)
|
||||
#define RTC_IO_RTC_GPIO_PIN10_WAKEUP_ENABLE (BIT(10))
|
||||
#define RTC_IO_RTC_GPIO_PIN10_WAKEUP_ENABLE_S 10
|
||||
#define RTC_IO_RTC_GPIO_PIN10_INT_TYPE 0x00000007
|
||||
#define RTC_IO_RTC_GPIO_PIN10_INT_TYPE_S 7
|
||||
#define RTC_IO_RTC_GPIO_PIN10_PAD_DRIVER (BIT(2))
|
||||
#define RTC_IO_RTC_GPIO_PIN10_PAD_DRIVER_S 2
|
||||
|
||||
#define RTC_GPIO_PIN11 (DR_REG_RTCIO_BASE + 0x54)
|
||||
#define RTC_IO_RTC_GPIO_PIN11_WAKEUP_ENABLE (BIT(10))
|
||||
#define RTC_IO_RTC_GPIO_PIN11_WAKEUP_ENABLE_S 10
|
||||
#define RTC_IO_RTC_GPIO_PIN11_INT_TYPE 0x00000007
|
||||
#define RTC_IO_RTC_GPIO_PIN11_INT_TYPE_S 7
|
||||
#define RTC_IO_RTC_GPIO_PIN11_PAD_DRIVER (BIT(2))
|
||||
#define RTC_IO_RTC_GPIO_PIN11_PAD_DRIVER_S 2
|
||||
|
||||
#define RTC_GPIO_PIN12 (DR_REG_RTCIO_BASE + 0x58)
|
||||
#define RTC_IO_RTC_GPIO_PIN12_WAKEUP_ENABLE (BIT(10))
|
||||
#define RTC_IO_RTC_GPIO_PIN12_WAKEUP_ENABLE_S 10
|
||||
#define RTC_IO_RTC_GPIO_PIN12_INT_TYPE 0x00000007
|
||||
#define RTC_IO_RTC_GPIO_PIN12_INT_TYPE_S 7
|
||||
#define RTC_IO_RTC_GPIO_PIN12_PAD_DRIVER (BIT(2))
|
||||
#define RTC_IO_RTC_GPIO_PIN12_PAD_DRIVER_S 2
|
||||
|
||||
#define RTC_GPIO_PIN13 (DR_REG_RTCIO_BASE + 0x5c)
|
||||
#define RTC_IO_RTC_GPIO_PIN13_WAKEUP_ENABLE (BIT(10))
|
||||
#define RTC_IO_RTC_GPIO_PIN13_WAKEUP_ENABLE_S 10
|
||||
#define RTC_IO_RTC_GPIO_PIN13_INT_TYPE 0x00000007
|
||||
#define RTC_IO_RTC_GPIO_PIN13_INT_TYPE_S 7
|
||||
#define RTC_IO_RTC_GPIO_PIN13_PAD_DRIVER (BIT(2))
|
||||
#define RTC_IO_RTC_GPIO_PIN13_PAD_DRIVER_S 2
|
||||
|
||||
#define RTC_GPIO_PIN14 (DR_REG_RTCIO_BASE + 0x60)
|
||||
#define RTC_IO_RTC_GPIO_PIN14_WAKEUP_ENABLE (BIT(10))
|
||||
#define RTC_IO_RTC_GPIO_PIN14_WAKEUP_ENABLE_S 10
|
||||
#define RTC_IO_RTC_GPIO_PIN14_INT_TYPE 0x00000007
|
||||
#define RTC_IO_RTC_GPIO_PIN14_INT_TYPE_S 7
|
||||
#define RTC_IO_RTC_GPIO_PIN14_PAD_DRIVER (BIT(2))
|
||||
#define RTC_IO_RTC_GPIO_PIN14_PAD_DRIVER_S 2
|
||||
|
||||
#define RTC_GPIO_PIN15 (DR_REG_RTCIO_BASE + 0x64)
|
||||
#define RTC_IO_RTC_GPIO_PIN15_WAKEUP_ENABLE (BIT(10))
|
||||
#define RTC_IO_RTC_GPIO_PIN15_WAKEUP_ENABLE_S 10
|
||||
#define RTC_IO_RTC_GPIO_PIN15_INT_TYPE 0x00000007
|
||||
#define RTC_IO_RTC_GPIO_PIN15_INT_TYPE_S 7
|
||||
#define RTC_IO_RTC_GPIO_PIN15_PAD_DRIVER (BIT(2))
|
||||
#define RTC_IO_RTC_GPIO_PIN15_PAD_DRIVER_S 2
|
||||
|
||||
#define RTC_GPIO_PIN16 (DR_REG_RTCIO_BASE + 0x68)
|
||||
#define RTC_IO_RTC_GPIO_PIN16_WAKEUP_ENABLE (BIT(10))
|
||||
#define RTC_IO_RTC_GPIO_PIN16_WAKEUP_ENABLE_S 10
|
||||
#define RTC_IO_RTC_GPIO_PIN16_INT_TYPE 0x00000007
|
||||
#define RTC_IO_RTC_GPIO_PIN16_INT_TYPE_S 7
|
||||
#define RTC_IO_RTC_GPIO_PIN16_PAD_DRIVER (BIT(2))
|
||||
#define RTC_IO_RTC_GPIO_PIN16_PAD_DRIVER_S 2
|
||||
|
||||
#define RTC_GPIO_PIN17 (DR_REG_RTCIO_BASE + 0x6c)
|
||||
#define RTC_IO_RTC_GPIO_PIN17_WAKEUP_ENABLE (BIT(10))
|
||||
#define RTC_IO_RTC_GPIO_PIN17_WAKEUP_ENABLE_S 10
|
||||
#define RTC_IO_RTC_GPIO_PIN17_INT_TYPE 0x00000007
|
||||
#define RTC_IO_RTC_GPIO_PIN17_INT_TYPE_S 7
|
||||
#define RTC_IO_RTC_GPIO_PIN17_PAD_DRIVER (BIT(2))
|
||||
#define RTC_IO_RTC_GPIO_PIN17_PAD_DRIVER_S 2
|
||||
|
||||
#define RTC_DEBUG_SEL (DR_REG_RTCIO_BASE + 0x70)
|
||||
#define RTC_IO_RTC_DEBUG_12M_NO_GATING (BIT(25))
|
||||
#define RTC_IO_RTC_DEBUG_12M_NO_GATING_S 25
|
||||
#define RTC_IO_RTC_DEBUG_SEL4 0x0000001F
|
||||
#define RTC_IO_RTC_DEBUG_SEL4_S 20
|
||||
#define RTC_IO_RTC_DEBUG_SEL3 0x0000001F
|
||||
#define RTC_IO_RTC_DEBUG_SEL3_S 15
|
||||
#define RTC_IO_RTC_DEBUG_SEL2 0x0000001F
|
||||
#define RTC_IO_RTC_DEBUG_SEL2_S 10
|
||||
#define RTC_IO_RTC_DEBUG_SEL1 0x0000001F
|
||||
#define RTC_IO_RTC_DEBUG_SEL1_S 5
|
||||
#define RTC_IO_RTC_DEBUG_SEL0 0x0000001F
|
||||
#define RTC_IO_RTC_DEBUG_SEL0_S 0
|
||||
|
||||
#define DIG_PAD_HOLD (DR_REG_RTCIO_BASE + 0x74)
|
||||
#define RTC_IO_DIG_PAD_HOLD 0xFFFFFFFF
|
||||
#define RTC_IO_DIG_PAD_HOLD_S 0
|
||||
|
||||
#define HALL_SENS (DR_REG_RTCIO_BASE + 0x78)
|
||||
#define RTC_IO_XPD_HALL (BIT(31))
|
||||
#define RTC_IO_XPD_HALL_S 31
|
||||
#define RTC_IO_HALL_PHASE (BIT(30))
|
||||
#define RTC_IO_HALL_PHASE_S 30
|
||||
|
||||
#define SENSOR_PADS (DR_REG_RTCIO_BASE + 0x7c)
|
||||
#define RTC_IO_SENSE1_HOLD (BIT(31))
|
||||
#define RTC_IO_SENSE1_HOLD_S 31
|
||||
#define RTC_IO_SENSE2_HOLD (BIT(30))
|
||||
#define RTC_IO_SENSE2_HOLD_S 30
|
||||
#define RTC_IO_SENSE3_HOLD (BIT(29))
|
||||
#define RTC_IO_SENSE3_HOLD_S 29
|
||||
#define RTC_IO_SENSE4_HOLD (BIT(28))
|
||||
#define RTC_IO_SENSE4_HOLD_S 28
|
||||
#define RTC_IO_SENSE1_MUX_SEL (BIT(27))
|
||||
#define RTC_IO_SENSE1_MUX_SEL_S 27
|
||||
#define RTC_IO_SENSE2_MUX_SEL (BIT(26))
|
||||
#define RTC_IO_SENSE2_MUX_SEL_S 26
|
||||
#define RTC_IO_SENSE3_MUX_SEL (BIT(25))
|
||||
#define RTC_IO_SENSE3_MUX_SEL_S 25
|
||||
#define RTC_IO_SENSE4_MUX_SEL (BIT(24))
|
||||
#define RTC_IO_SENSE4_MUX_SEL_S 24
|
||||
#define RTC_IO_SENSE1_FUN_SEL 0x00000003
|
||||
#define RTC_IO_SENSE1_FUN_SEL_S 22
|
||||
#define RTC_IO_SENSE1_SLP_SEL (BIT(21))
|
||||
#define RTC_IO_SENSE1_SLP_SEL_S 21
|
||||
#define RTC_IO_SENSE1_SLP_IE (BIT(20))
|
||||
#define RTC_IO_SENSE1_SLP_IE_S 20
|
||||
#define RTC_IO_SENSE1_FUN_IE (BIT(19))
|
||||
#define RTC_IO_SENSE1_FUN_IE_S 19
|
||||
#define RTC_IO_SENSE2_FUN_SEL 0x00000003
|
||||
#define RTC_IO_SENSE2_FUN_SEL_S 17
|
||||
#define RTC_IO_SENSE2_SLP_SEL (BIT(16))
|
||||
#define RTC_IO_SENSE2_SLP_SEL_S 16
|
||||
#define RTC_IO_SENSE2_SLP_IE (BIT(15))
|
||||
#define RTC_IO_SENSE2_SLP_IE_S 15
|
||||
#define RTC_IO_SENSE2_FUN_IE (BIT(14))
|
||||
#define RTC_IO_SENSE2_FUN_IE_S 14
|
||||
#define RTC_IO_SENSE3_FUN_SEL 0x00000003
|
||||
#define RTC_IO_SENSE3_FUN_SEL_S 12
|
||||
#define RTC_IO_SENSE3_SLP_SEL (BIT(11))
|
||||
#define RTC_IO_SENSE3_SLP_SEL_S 11
|
||||
#define RTC_IO_SENSE3_SLP_IE (BIT(10))
|
||||
#define RTC_IO_SENSE3_SLP_IE_S 10
|
||||
#define RTC_IO_SENSE3_FUN_IE (BIT(9))
|
||||
#define RTC_IO_SENSE3_FUN_IE_S 9
|
||||
#define RTC_IO_SENSE4_FUN_SEL 0x00000003
|
||||
#define RTC_IO_SENSE4_FUN_SEL_S 7
|
||||
#define RTC_IO_SENSE4_SLP_SEL (BIT(6))
|
||||
#define RTC_IO_SENSE4_SLP_SEL_S 6
|
||||
#define RTC_IO_SENSE4_SLP_IE (BIT(5))
|
||||
#define RTC_IO_SENSE4_SLP_IE_S 5
|
||||
#define RTC_IO_SENSE4_FUN_IE (BIT(4))
|
||||
#define RTC_IO_SENSE4_FUN_IE_S 4
|
||||
|
||||
#define ADC_PAD (DR_REG_RTCIO_BASE + 0x80)
|
||||
#define RTC_IO_ADC1_HOLD (BIT(31))
|
||||
#define RTC_IO_ADC1_HOLD_S 31
|
||||
#define RTC_IO_ADC2_HOLD (BIT(30))
|
||||
#define RTC_IO_ADC2_HOLD_S 30
|
||||
#define RTC_IO_ADC1_MUX_SEL (BIT(29))
|
||||
#define RTC_IO_ADC1_MUX_SEL_S 29
|
||||
#define RTC_IO_ADC2_MUX_SEL (BIT(28))
|
||||
#define RTC_IO_ADC2_MUX_SEL_S 28
|
||||
#define RTC_IO_ADC1_FUN_SEL 0x00000003
|
||||
#define RTC_IO_ADC1_FUN_SEL_S 26
|
||||
#define RTC_IO_ADC1_SLP_SEL (BIT(25))
|
||||
#define RTC_IO_ADC1_SLP_SEL_S 25
|
||||
#define RTC_IO_ADC1_SLP_IE (BIT(24))
|
||||
#define RTC_IO_ADC1_SLP_IE_S 24
|
||||
#define RTC_IO_ADC1_FUN_IE (BIT(23))
|
||||
#define RTC_IO_ADC1_FUN_IE_S 23
|
||||
#define RTC_IO_ADC2_FUN_SEL 0x00000003
|
||||
#define RTC_IO_ADC2_FUN_SEL_S 21
|
||||
#define RTC_IO_ADC2_SLP_SEL (BIT(20))
|
||||
#define RTC_IO_ADC2_SLP_SEL_S 20
|
||||
#define RTC_IO_ADC2_SLP_IE (BIT(19))
|
||||
#define RTC_IO_ADC2_SLP_IE_S 19
|
||||
#define RTC_IO_ADC2_FUN_IE (BIT(18))
|
||||
#define RTC_IO_ADC2_FUN_IE_S 18
|
||||
|
||||
#define PAD_DAC1 (DR_REG_RTCIO_BASE + 0x84)
|
||||
#define RTC_IO_PDAC1_DRV 0x00000003
|
||||
#define RTC_IO_PDAC1_DRV_S 30
|
||||
#define RTC_IO_PDAC1_HOLD (BIT(29))
|
||||
#define RTC_IO_PDAC1_HOLD_S 29
|
||||
#define RTC_IO_PDAC1_RDE (BIT(28))
|
||||
#define RTC_IO_PDAC1_RDE_S 28
|
||||
#define RTC_IO_PDAC1_RUE (BIT(27))
|
||||
#define RTC_IO_PDAC1_RUE_S 27
|
||||
#define RTC_IO_PDAC1_DAC 0x000000FF
|
||||
#define RTC_IO_PDAC1_DAC_S 19
|
||||
#define RTC_IO_PDAC1_XPD_DAC (BIT(18))
|
||||
#define RTC_IO_PDAC1_XPD_DAC_S 18
|
||||
#define RTC_IO_PDAC1_MUX_SEL (BIT(17))
|
||||
#define RTC_IO_PDAC1_MUX_SEL_S 17
|
||||
#define RTC_IO_PDAC1_FUN_SEL 0x00000003
|
||||
#define RTC_IO_PDAC1_FUN_SEL_S 15
|
||||
#define RTC_IO_PDAC1_SLP_SEL (BIT(14))
|
||||
#define RTC_IO_PDAC1_SLP_SEL_S 14
|
||||
#define RTC_IO_PDAC1_SLP_IE (BIT(13))
|
||||
#define RTC_IO_PDAC1_SLP_IE_S 13
|
||||
#define RTC_IO_PDAC1_SLP_OE (BIT(12))
|
||||
#define RTC_IO_PDAC1_SLP_OE_S 12
|
||||
#define RTC_IO_PDAC1_FUN_IE (BIT(11))
|
||||
#define RTC_IO_PDAC1_FUN_IE_S 11
|
||||
#define RTC_IO_PDAC1_DAC_XPD_FORCE (BIT(10))
|
||||
#define RTC_IO_PDAC1_DAC_XPD_FORCE_S 10
|
||||
|
||||
#define PAD_DAC2 (DR_REG_RTCIO_BASE + 0x88)
|
||||
#define RTC_IO_PDAC2_DRV 0x00000003
|
||||
#define RTC_IO_PDAC2_DRV_S 30
|
||||
#define RTC_IO_PDAC2_HOLD (BIT(29))
|
||||
#define RTC_IO_PDAC2_HOLD_S 29
|
||||
#define RTC_IO_PDAC2_RDE (BIT(28))
|
||||
#define RTC_IO_PDAC2_RDE_S 28
|
||||
#define RTC_IO_PDAC2_RUE (BIT(27))
|
||||
#define RTC_IO_PDAC2_RUE_S 27
|
||||
#define RTC_IO_PDAC2_DAC 0x000000FF
|
||||
#define RTC_IO_PDAC2_DAC_S 19
|
||||
#define RTC_IO_PDAC2_XPD_DAC (BIT(18))
|
||||
#define RTC_IO_PDAC2_XPD_DAC_S 18
|
||||
#define RTC_IO_PDAC2_MUX_SEL (BIT(17))
|
||||
#define RTC_IO_PDAC2_MUX_SEL_S 17
|
||||
#define RTC_IO_PDAC2_FUN_SEL 0x00000003
|
||||
#define RTC_IO_PDAC2_FUN_SEL_S 15
|
||||
#define RTC_IO_PDAC2_SLP_SEL (BIT(14))
|
||||
#define RTC_IO_PDAC2_SLP_SEL_S 14
|
||||
#define RTC_IO_PDAC2_SLP_IE (BIT(13))
|
||||
#define RTC_IO_PDAC2_SLP_IE_S 13
|
||||
#define RTC_IO_PDAC2_SLP_OE (BIT(12))
|
||||
#define RTC_IO_PDAC2_SLP_OE_S 12
|
||||
#define RTC_IO_PDAC2_FUN_IE (BIT(11))
|
||||
#define RTC_IO_PDAC2_FUN_IE_S 11
|
||||
#define RTC_IO_PDAC2_DAC_XPD_FORCE (BIT(10))
|
||||
#define RTC_IO_PDAC2_DAC_XPD_FORCE_S 10
|
||||
|
||||
#define XTAL_32K_PAD (DR_REG_RTCIO_BASE + 0x8c)
|
||||
#define RTC_IO_X32N_DRV 0x00000003
|
||||
#define RTC_IO_X32N_DRV_S 30
|
||||
#define RTC_IO_X32N_HOLD (BIT(29))
|
||||
#define RTC_IO_X32N_HOLD_S 29
|
||||
#define RTC_IO_X32N_RDE (BIT(28))
|
||||
#define RTC_IO_X32N_RDE_S 28
|
||||
#define RTC_IO_X32N_RUE (BIT(27))
|
||||
#define RTC_IO_X32N_RUE_S 27
|
||||
#define RTC_IO_X32P_DRV 0x00000003
|
||||
#define RTC_IO_X32P_DRV_S 25
|
||||
#define RTC_IO_X32P_HOLD (BIT(24))
|
||||
#define RTC_IO_X32P_HOLD_S 24
|
||||
#define RTC_IO_X32P_RDE (BIT(23))
|
||||
#define RTC_IO_X32P_RDE_S 23
|
||||
#define RTC_IO_X32P_RUE (BIT(22))
|
||||
#define RTC_IO_X32P_RUE_S 22
|
||||
#define RTC_IO_DAC_XTAL_32K 0x00000003
|
||||
#define RTC_IO_DAC_XTAL_32K_S 20
|
||||
#define RTC_IO_XPD_XTAL_32K (BIT(19))
|
||||
#define RTC_IO_XPD_XTAL_32K_S 19
|
||||
#define RTC_IO_X32N_MUX_SEL (BIT(18))
|
||||
#define RTC_IO_X32N_MUX_SEL_S 18
|
||||
#define RTC_IO_X32P_MUX_SEL (BIT(17))
|
||||
#define RTC_IO_X32P_MUX_SEL_S 17
|
||||
#define RTC_IO_X32N_FUN_SEL 0x00000003
|
||||
#define RTC_IO_X32N_FUN_SEL_S 15
|
||||
#define RTC_IO_X32N_SLP_SEL (BIT(14))
|
||||
#define RTC_IO_X32N_SLP_SEL_S 14
|
||||
#define RTC_IO_X32N_SLP_IE (BIT(13))
|
||||
#define RTC_IO_X32N_SLP_IE_S 13
|
||||
#define RTC_IO_X32N_SLP_OE (BIT(12))
|
||||
#define RTC_IO_X32N_SLP_OE_S 12
|
||||
#define RTC_IO_X32N_FUN_IE (BIT(11))
|
||||
#define RTC_IO_X32N_FUN_IE_S 11
|
||||
#define RTC_IO_X32P_FUN_SEL 0x00000003
|
||||
#define RTC_IO_X32P_FUN_SEL_S 9
|
||||
#define RTC_IO_X32P_SLP_SEL (BIT(8))
|
||||
#define RTC_IO_X32P_SLP_SEL_S 8
|
||||
#define RTC_IO_X32P_SLP_IE (BIT(7))
|
||||
#define RTC_IO_X32P_SLP_IE_S 7
|
||||
#define RTC_IO_X32P_SLP_OE (BIT(6))
|
||||
#define RTC_IO_X32P_SLP_OE_S 6
|
||||
#define RTC_IO_X32P_FUN_IE (BIT(5))
|
||||
#define RTC_IO_X32P_FUN_IE_S 5
|
||||
#define RTC_IO_DRES_XTAL_32K 0x00000003
|
||||
#define RTC_IO_DRES_XTAL_32K_S 3
|
||||
#define RTC_IO_DBIAS_XTAL_32K 0x00000003
|
||||
#define RTC_IO_DBIAS_XTAL_32K_S 1
|
||||
|
||||
#define TOUCH_CFG (DR_REG_RTCIO_BASE + 0x90)
|
||||
#define RTC_IO_TOUCH_XPD_BIAS (BIT(31))
|
||||
#define RTC_IO_TOUCH_XPD_BIAS_S 31
|
||||
#define RTC_IO_TOUCH_DREFH 0x00000003
|
||||
#define RTC_IO_TOUCH_DREFH_S 29
|
||||
#define RTC_IO_TOUCH_DREFL 0x00000003
|
||||
#define RTC_IO_TOUCH_DREFL_S 27
|
||||
#define RTC_IO_TOUCH_DRANGE 0x00000003
|
||||
#define RTC_IO_TOUCH_DRANGE_S 25
|
||||
#define RTC_IO_TOUCH_DCUR 0x00000003
|
||||
#define RTC_IO_TOUCH_DCUR_S 23
|
||||
|
||||
#define TOUCH_PAD0 (DR_REG_RTCIO_BASE + 0x94)
|
||||
#define RTC_IO_TOUCH_PAD0_HOLD (BIT(31))
|
||||
#define RTC_IO_TOUCH_PAD0_HOLD_S 31
|
||||
#define RTC_IO_TOUCH_PAD0_DRV 0x00000003
|
||||
#define RTC_IO_TOUCH_PAD0_DRV_S 29
|
||||
#define RTC_IO_TOUCH_PAD0_RDE (BIT(28))
|
||||
#define RTC_IO_TOUCH_PAD0_RDE_S 28
|
||||
#define RTC_IO_TOUCH_PAD0_RUE (BIT(27))
|
||||
#define RTC_IO_TOUCH_PAD0_RUE_S 27
|
||||
#define RTC_IO_TOUCH_PAD0_DAC 0x00000007
|
||||
#define RTC_IO_TOUCH_PAD0_DAC_S 23
|
||||
#define RTC_IO_TOUCH_PAD0_START (BIT(22))
|
||||
#define RTC_IO_TOUCH_PAD0_START_S 22
|
||||
#define RTC_IO_TOUCH_PAD0_TIE_OPT (BIT(21))
|
||||
#define RTC_IO_TOUCH_PAD0_TIE_OPT_S 21
|
||||
#define RTC_IO_TOUCH_PAD0_XPD (BIT(20))
|
||||
#define RTC_IO_TOUCH_PAD0_XPD_S 20
|
||||
#define RTC_IO_TOUCH_PAD0_MUX_SEL (BIT(19))
|
||||
#define RTC_IO_TOUCH_PAD0_MUX_SEL_S 19
|
||||
#define RTC_IO_TOUCH_PAD0_FUN_SEL 0x00000003
|
||||
#define RTC_IO_TOUCH_PAD0_FUN_SEL_S 17
|
||||
#define RTC_IO_TOUCH_PAD0_SLP_SEL (BIT(16))
|
||||
#define RTC_IO_TOUCH_PAD0_SLP_SEL_S 16
|
||||
#define RTC_IO_TOUCH_PAD0_SLP_IE (BIT(15))
|
||||
#define RTC_IO_TOUCH_PAD0_SLP_IE_S 15
|
||||
#define RTC_IO_TOUCH_PAD0_SLP_OE (BIT(14))
|
||||
#define RTC_IO_TOUCH_PAD0_SLP_OE_S 14
|
||||
#define RTC_IO_TOUCH_PAD0_FUN_IE (BIT(13))
|
||||
#define RTC_IO_TOUCH_PAD0_FUN_IE_S 13
|
||||
#define RTC_IO_TOUCH_PAD0_TO_GPIO (BIT(12))
|
||||
#define RTC_IO_TOUCH_PAD0_TO_GPIO_S 12
|
||||
|
||||
#define TOUCH_PAD1 (DR_REG_RTCIO_BASE + 0x98)
|
||||
#define RTC_IO_TOUCH_PAD1_HOLD (BIT(31))
|
||||
#define RTC_IO_TOUCH_PAD1_HOLD_S 31
|
||||
#define RTC_IO_TOUCH_PAD1_DRV 0x00000003
|
||||
#define RTC_IO_TOUCH_PAD1_DRV_S 29
|
||||
#define RTC_IO_TOUCH_PAD1_RDE (BIT(28))
|
||||
#define RTC_IO_TOUCH_PAD1_RDE_S 28
|
||||
#define RTC_IO_TOUCH_PAD1_RUE (BIT(27))
|
||||
#define RTC_IO_TOUCH_PAD1_RUE_S 27
|
||||
#define RTC_IO_TOUCH_PAD1_DAC 0x00000007
|
||||
#define RTC_IO_TOUCH_PAD1_DAC_S 23
|
||||
#define RTC_IO_TOUCH_PAD1_START (BIT(22))
|
||||
#define RTC_IO_TOUCH_PAD1_START_S 22
|
||||
#define RTC_IO_TOUCH_PAD1_TIE_OPT (BIT(21))
|
||||
#define RTC_IO_TOUCH_PAD1_TIE_OPT_S 21
|
||||
#define RTC_IO_TOUCH_PAD1_XPD (BIT(20))
|
||||
#define RTC_IO_TOUCH_PAD1_XPD_S 20
|
||||
#define RTC_IO_TOUCH_PAD1_MUX_SEL (BIT(19))
|
||||
#define RTC_IO_TOUCH_PAD1_MUX_SEL_S 19
|
||||
#define RTC_IO_TOUCH_PAD1_FUN_SEL 0x00000003
|
||||
#define RTC_IO_TOUCH_PAD1_FUN_SEL_S 17
|
||||
#define RTC_IO_TOUCH_PAD1_SLP_SEL (BIT(16))
|
||||
#define RTC_IO_TOUCH_PAD1_SLP_SEL_S 16
|
||||
#define RTC_IO_TOUCH_PAD1_SLP_IE (BIT(15))
|
||||
#define RTC_IO_TOUCH_PAD1_SLP_IE_S 15
|
||||
#define RTC_IO_TOUCH_PAD1_SLP_OE (BIT(14))
|
||||
#define RTC_IO_TOUCH_PAD1_SLP_OE_S 14
|
||||
#define RTC_IO_TOUCH_PAD1_FUN_IE (BIT(13))
|
||||
#define RTC_IO_TOUCH_PAD1_FUN_IE_S 13
|
||||
#define RTC_IO_TOUCH_PAD1_TO_GPIO (BIT(12))
|
||||
#define RTC_IO_TOUCH_PAD1_TO_GPIO_S 12
|
||||
|
||||
#define TOUCH_PAD2 (DR_REG_RTCIO_BASE + 0x9c)
|
||||
#define RTC_IO_TOUCH_PAD2_HOLD (BIT(31))
|
||||
#define RTC_IO_TOUCH_PAD2_HOLD_S 31
|
||||
#define RTC_IO_TOUCH_PAD2_DRV 0x00000003
|
||||
#define RTC_IO_TOUCH_PAD2_DRV_S 29
|
||||
#define RTC_IO_TOUCH_PAD2_RDE (BIT(28))
|
||||
#define RTC_IO_TOUCH_PAD2_RDE_S 28
|
||||
#define RTC_IO_TOUCH_PAD2_RUE (BIT(27))
|
||||
#define RTC_IO_TOUCH_PAD2_RUE_S 27
|
||||
#define RTC_IO_TOUCH_PAD2_DAC 0x00000007
|
||||
#define RTC_IO_TOUCH_PAD2_DAC_S 23
|
||||
#define RTC_IO_TOUCH_PAD2_START (BIT(22))
|
||||
#define RTC_IO_TOUCH_PAD2_START_S 22
|
||||
#define RTC_IO_TOUCH_PAD2_TIE_OPT (BIT(21))
|
||||
#define RTC_IO_TOUCH_PAD2_TIE_OPT_S 21
|
||||
#define RTC_IO_TOUCH_PAD2_XPD (BIT(20))
|
||||
#define RTC_IO_TOUCH_PAD2_XPD_S 20
|
||||
#define RTC_IO_TOUCH_PAD2_MUX_SEL (BIT(19))
|
||||
#define RTC_IO_TOUCH_PAD2_MUX_SEL_S 19
|
||||
#define RTC_IO_TOUCH_PAD2_FUN_SEL 0x00000003
|
||||
#define RTC_IO_TOUCH_PAD2_FUN_SEL_S 17
|
||||
#define RTC_IO_TOUCH_PAD2_SLP_SEL (BIT(16))
|
||||
#define RTC_IO_TOUCH_PAD2_SLP_SEL_S 16
|
||||
#define RTC_IO_TOUCH_PAD2_SLP_IE (BIT(15))
|
||||
#define RTC_IO_TOUCH_PAD2_SLP_IE_S 15
|
||||
#define RTC_IO_TOUCH_PAD2_SLP_OE (BIT(14))
|
||||
#define RTC_IO_TOUCH_PAD2_SLP_OE_S 14
|
||||
#define RTC_IO_TOUCH_PAD2_FUN_IE (BIT(13))
|
||||
#define RTC_IO_TOUCH_PAD2_FUN_IE_S 13
|
||||
#define RTC_IO_TOUCH_PAD2_TO_GPIO (BIT(12))
|
||||
#define RTC_IO_TOUCH_PAD2_TO_GPIO_S 12
|
||||
|
||||
#define TOUCH_PAD3 (DR_REG_RTCIO_BASE + 0xa0)
|
||||
#define RTC_IO_TOUCH_PAD3_HOLD (BIT(31))
|
||||
#define RTC_IO_TOUCH_PAD3_HOLD_S 31
|
||||
#define RTC_IO_TOUCH_PAD3_DRV 0x00000003
|
||||
#define RTC_IO_TOUCH_PAD3_DRV_S 29
|
||||
#define RTC_IO_TOUCH_PAD3_RDE (BIT(28))
|
||||
#define RTC_IO_TOUCH_PAD3_RDE_S 28
|
||||
#define RTC_IO_TOUCH_PAD3_RUE (BIT(27))
|
||||
#define RTC_IO_TOUCH_PAD3_RUE_S 27
|
||||
#define RTC_IO_TOUCH_PAD3_DAC 0x00000007
|
||||
#define RTC_IO_TOUCH_PAD3_DAC_S 23
|
||||
#define RTC_IO_TOUCH_PAD3_START (BIT(22))
|
||||
#define RTC_IO_TOUCH_PAD3_START_S 22
|
||||
#define RTC_IO_TOUCH_PAD3_TIE_OPT (BIT(21))
|
||||
#define RTC_IO_TOUCH_PAD3_TIE_OPT_S 21
|
||||
#define RTC_IO_TOUCH_PAD3_XPD (BIT(20))
|
||||
#define RTC_IO_TOUCH_PAD3_XPD_S 20
|
||||
#define RTC_IO_TOUCH_PAD3_MUX_SEL (BIT(19))
|
||||
#define RTC_IO_TOUCH_PAD3_MUX_SEL_S 19
|
||||
#define RTC_IO_TOUCH_PAD3_FUN_SEL 0x00000003
|
||||
#define RTC_IO_TOUCH_PAD3_FUN_SEL_S 17
|
||||
#define RTC_IO_TOUCH_PAD3_SLP_SEL (BIT(16))
|
||||
#define RTC_IO_TOUCH_PAD3_SLP_SEL_S 16
|
||||
#define RTC_IO_TOUCH_PAD3_SLP_IE (BIT(15))
|
||||
#define RTC_IO_TOUCH_PAD3_SLP_IE_S 15
|
||||
#define RTC_IO_TOUCH_PAD3_SLP_OE (BIT(14))
|
||||
#define RTC_IO_TOUCH_PAD3_SLP_OE_S 14
|
||||
#define RTC_IO_TOUCH_PAD3_FUN_IE (BIT(13))
|
||||
#define RTC_IO_TOUCH_PAD3_FUN_IE_S 13
|
||||
#define RTC_IO_TOUCH_PAD3_TO_GPIO (BIT(12))
|
||||
#define RTC_IO_TOUCH_PAD3_TO_GPIO_S 12
|
||||
|
||||
#define TOUCH_PAD4 (DR_REG_RTCIO_BASE + 0xa4)
|
||||
#define RTC_IO_TOUCH_PAD4_HOLD (BIT(31))
|
||||
#define RTC_IO_TOUCH_PAD4_HOLD_S 31
|
||||
#define RTC_IO_TOUCH_PAD4_DRV 0x00000003
|
||||
#define RTC_IO_TOUCH_PAD4_DRV_S 29
|
||||
#define RTC_IO_TOUCH_PAD4_RDE (BIT(28))
|
||||
#define RTC_IO_TOUCH_PAD4_RDE_S 28
|
||||
#define RTC_IO_TOUCH_PAD4_RUE (BIT(27))
|
||||
#define RTC_IO_TOUCH_PAD4_RUE_S 27
|
||||
#define RTC_IO_TOUCH_PAD4_DAC 0x00000007
|
||||
#define RTC_IO_TOUCH_PAD4_DAC_S 23
|
||||
#define RTC_IO_TOUCH_PAD4_START (BIT(22))
|
||||
#define RTC_IO_TOUCH_PAD4_START_S 22
|
||||
#define RTC_IO_TOUCH_PAD4_TIE_OPT (BIT(21))
|
||||
#define RTC_IO_TOUCH_PAD4_TIE_OPT_S 21
|
||||
#define RTC_IO_TOUCH_PAD4_XPD (BIT(20))
|
||||
#define RTC_IO_TOUCH_PAD4_XPD_S 20
|
||||
#define RTC_IO_TOUCH_PAD4_MUX_SEL (BIT(19))
|
||||
#define RTC_IO_TOUCH_PAD4_MUX_SEL_S 19
|
||||
#define RTC_IO_TOUCH_PAD4_FUN_SEL 0x00000003
|
||||
#define RTC_IO_TOUCH_PAD4_FUN_SEL_S 17
|
||||
#define RTC_IO_TOUCH_PAD4_SLP_SEL (BIT(16))
|
||||
#define RTC_IO_TOUCH_PAD4_SLP_SEL_S 16
|
||||
#define RTC_IO_TOUCH_PAD4_SLP_IE (BIT(15))
|
||||
#define RTC_IO_TOUCH_PAD4_SLP_IE_S 15
|
||||
#define RTC_IO_TOUCH_PAD4_SLP_OE (BIT(14))
|
||||
#define RTC_IO_TOUCH_PAD4_SLP_OE_S 14
|
||||
#define RTC_IO_TOUCH_PAD4_FUN_IE (BIT(13))
|
||||
#define RTC_IO_TOUCH_PAD4_FUN_IE_S 13
|
||||
#define RTC_IO_TOUCH_PAD4_TO_GPIO (BIT(12))
|
||||
#define RTC_IO_TOUCH_PAD4_TO_GPIO_S 12
|
||||
|
||||
#define TOUCH_PAD5 (DR_REG_RTCIO_BASE + 0xa8)
|
||||
#define RTC_IO_TOUCH_PAD5_HOLD (BIT(31))
|
||||
#define RTC_IO_TOUCH_PAD5_HOLD_S 31
|
||||
#define RTC_IO_TOUCH_PAD5_DRV 0x00000003
|
||||
#define RTC_IO_TOUCH_PAD5_DRV_S 29
|
||||
#define RTC_IO_TOUCH_PAD5_RDE (BIT(28))
|
||||
#define RTC_IO_TOUCH_PAD5_RDE_S 28
|
||||
#define RTC_IO_TOUCH_PAD5_RUE (BIT(27))
|
||||
#define RTC_IO_TOUCH_PAD5_RUE_S 27
|
||||
#define RTC_IO_TOUCH_PAD5_DAC 0x00000007
|
||||
#define RTC_IO_TOUCH_PAD5_DAC_S 23
|
||||
#define RTC_IO_TOUCH_PAD5_START (BIT(22))
|
||||
#define RTC_IO_TOUCH_PAD5_START_S 22
|
||||
#define RTC_IO_TOUCH_PAD5_TIE_OPT (BIT(21))
|
||||
#define RTC_IO_TOUCH_PAD5_TIE_OPT_S 21
|
||||
#define RTC_IO_TOUCH_PAD5_XPD (BIT(20))
|
||||
#define RTC_IO_TOUCH_PAD5_XPD_S 20
|
||||
#define RTC_IO_TOUCH_PAD5_MUX_SEL (BIT(19))
|
||||
#define RTC_IO_TOUCH_PAD5_MUX_SEL_S 19
|
||||
#define RTC_IO_TOUCH_PAD5_FUN_SEL 0x00000003
|
||||
#define RTC_IO_TOUCH_PAD5_FUN_SEL_S 17
|
||||
#define RTC_IO_TOUCH_PAD5_SLP_SEL (BIT(16))
|
||||
#define RTC_IO_TOUCH_PAD5_SLP_SEL_S 16
|
||||
#define RTC_IO_TOUCH_PAD5_SLP_IE (BIT(15))
|
||||
#define RTC_IO_TOUCH_PAD5_SLP_IE_S 15
|
||||
#define RTC_IO_TOUCH_PAD5_SLP_OE (BIT(14))
|
||||
#define RTC_IO_TOUCH_PAD5_SLP_OE_S 14
|
||||
#define RTC_IO_TOUCH_PAD5_FUN_IE (BIT(13))
|
||||
#define RTC_IO_TOUCH_PAD5_FUN_IE_S 13
|
||||
#define RTC_IO_TOUCH_PAD5_TO_GPIO (BIT(12))
|
||||
#define RTC_IO_TOUCH_PAD5_TO_GPIO_S 12
|
||||
|
||||
#define TOUCH_PAD6 (DR_REG_RTCIO_BASE + 0xac)
|
||||
#define RTC_IO_TOUCH_PAD6_HOLD (BIT(31))
|
||||
#define RTC_IO_TOUCH_PAD6_HOLD_S 31
|
||||
#define RTC_IO_TOUCH_PAD6_DRV 0x00000003
|
||||
#define RTC_IO_TOUCH_PAD6_DRV_S 29
|
||||
#define RTC_IO_TOUCH_PAD6_RDE (BIT(28))
|
||||
#define RTC_IO_TOUCH_PAD6_RDE_S 28
|
||||
#define RTC_IO_TOUCH_PAD6_RUE (BIT(27))
|
||||
#define RTC_IO_TOUCH_PAD6_RUE_S 27
|
||||
#define RTC_IO_TOUCH_PAD6_DAC 0x00000007
|
||||
#define RTC_IO_TOUCH_PAD6_DAC_S 23
|
||||
#define RTC_IO_TOUCH_PAD6_START (BIT(22))
|
||||
#define RTC_IO_TOUCH_PAD6_START_S 22
|
||||
#define RTC_IO_TOUCH_PAD6_TIE_OPT (BIT(21))
|
||||
#define RTC_IO_TOUCH_PAD6_TIE_OPT_S 21
|
||||
#define RTC_IO_TOUCH_PAD6_XPD (BIT(20))
|
||||
#define RTC_IO_TOUCH_PAD6_XPD_S 20
|
||||
#define RTC_IO_TOUCH_PAD6_MUX_SEL (BIT(19))
|
||||
#define RTC_IO_TOUCH_PAD6_MUX_SEL_S 19
|
||||
#define RTC_IO_TOUCH_PAD6_FUN_SEL 0x00000003
|
||||
#define RTC_IO_TOUCH_PAD6_FUN_SEL_S 17
|
||||
#define RTC_IO_TOUCH_PAD6_SLP_SEL (BIT(16))
|
||||
#define RTC_IO_TOUCH_PAD6_SLP_SEL_S 16
|
||||
#define RTC_IO_TOUCH_PAD6_SLP_IE (BIT(15))
|
||||
#define RTC_IO_TOUCH_PAD6_SLP_IE_S 15
|
||||
#define RTC_IO_TOUCH_PAD6_SLP_OE (BIT(14))
|
||||
#define RTC_IO_TOUCH_PAD6_SLP_OE_S 14
|
||||
#define RTC_IO_TOUCH_PAD6_FUN_IE (BIT(13))
|
||||
#define RTC_IO_TOUCH_PAD6_FUN_IE_S 13
|
||||
#define RTC_IO_TOUCH_PAD6_TO_GPIO (BIT(12))
|
||||
#define RTC_IO_TOUCH_PAD6_TO_GPIO_S 12
|
||||
|
||||
#define TOUCH_PAD7 (DR_REG_RTCIO_BASE + 0xb0)
|
||||
#define RTC_IO_TOUCH_PAD7_HOLD (BIT(31))
|
||||
#define RTC_IO_TOUCH_PAD7_HOLD_S 31
|
||||
#define RTC_IO_TOUCH_PAD7_DRV 0x00000003
|
||||
#define RTC_IO_TOUCH_PAD7_DRV_S 29
|
||||
#define RTC_IO_TOUCH_PAD7_RDE (BIT(28))
|
||||
#define RTC_IO_TOUCH_PAD7_RDE_S 28
|
||||
#define RTC_IO_TOUCH_PAD7_RUE (BIT(27))
|
||||
#define RTC_IO_TOUCH_PAD7_RUE_S 27
|
||||
#define RTC_IO_TOUCH_PAD7_DAC 0x00000007
|
||||
#define RTC_IO_TOUCH_PAD7_DAC_S 23
|
||||
#define RTC_IO_TOUCH_PAD7_START (BIT(22))
|
||||
#define RTC_IO_TOUCH_PAD7_START_S 22
|
||||
#define RTC_IO_TOUCH_PAD7_TIE_OPT (BIT(21))
|
||||
#define RTC_IO_TOUCH_PAD7_TIE_OPT_S 21
|
||||
#define RTC_IO_TOUCH_PAD7_XPD (BIT(20))
|
||||
#define RTC_IO_TOUCH_PAD7_XPD_S 20
|
||||
#define RTC_IO_TOUCH_PAD7_MUX_SEL (BIT(19))
|
||||
#define RTC_IO_TOUCH_PAD7_MUX_SEL_S 19
|
||||
#define RTC_IO_TOUCH_PAD7_FUN_SEL 0x00000003
|
||||
#define RTC_IO_TOUCH_PAD7_FUN_SEL_S 17
|
||||
#define RTC_IO_TOUCH_PAD7_SLP_SEL (BIT(16))
|
||||
#define RTC_IO_TOUCH_PAD7_SLP_SEL_S 16
|
||||
#define RTC_IO_TOUCH_PAD7_SLP_IE (BIT(15))
|
||||
#define RTC_IO_TOUCH_PAD7_SLP_IE_S 15
|
||||
#define RTC_IO_TOUCH_PAD7_SLP_OE (BIT(14))
|
||||
#define RTC_IO_TOUCH_PAD7_SLP_OE_S 14
|
||||
#define RTC_IO_TOUCH_PAD7_FUN_IE (BIT(13))
|
||||
#define RTC_IO_TOUCH_PAD7_FUN_IE_S 13
|
||||
#define RTC_IO_TOUCH_PAD7_TO_GPIO (BIT(12))
|
||||
#define RTC_IO_TOUCH_PAD7_TO_GPIO_S 12
|
||||
|
||||
#define TOUCH_PAD8 (DR_REG_RTCIO_BASE + 0xb4)
|
||||
#define RTC_IO_TOUCH_PAD8_DAC 0x00000007
|
||||
#define RTC_IO_TOUCH_PAD8_DAC_S 23
|
||||
#define RTC_IO_TOUCH_PAD8_START (BIT(22))
|
||||
#define RTC_IO_TOUCH_PAD8_START_S 22
|
||||
#define RTC_IO_TOUCH_PAD8_TIE_OPT (BIT(21))
|
||||
#define RTC_IO_TOUCH_PAD8_TIE_OPT_S 21
|
||||
#define RTC_IO_TOUCH_PAD8_XPD (BIT(20))
|
||||
#define RTC_IO_TOUCH_PAD8_XPD_S 20
|
||||
#define RTC_IO_TOUCH_PAD8_TO_GPIO (BIT(19))
|
||||
#define RTC_IO_TOUCH_PAD8_TO_GPIO_S 19
|
||||
|
||||
#define TOUCH_PAD9 (DR_REG_RTCIO_BASE + 0xb8)
|
||||
#define RTC_IO_TOUCH_PAD9_DAC 0x00000007
|
||||
#define RTC_IO_TOUCH_PAD9_DAC_S 23
|
||||
#define RTC_IO_TOUCH_PAD9_START (BIT(22))
|
||||
#define RTC_IO_TOUCH_PAD9_START_S 22
|
||||
#define RTC_IO_TOUCH_PAD9_TIE_OPT (BIT(21))
|
||||
#define RTC_IO_TOUCH_PAD9_TIE_OPT_S 21
|
||||
#define RTC_IO_TOUCH_PAD9_XPD (BIT(20))
|
||||
#define RTC_IO_TOUCH_PAD9_XPD_S 20
|
||||
#define RTC_IO_TOUCH_PAD9_TO_GPIO (BIT(19))
|
||||
#define RTC_IO_TOUCH_PAD9_TO_GPIO_S 19
|
||||
|
||||
#define EXT_WAKEUP0 (DR_REG_RTCIO_BASE + 0xbc)
|
||||
#define RTC_IO_EXT_WAKEUP0_SEL 0x0000001F
|
||||
#define RTC_IO_EXT_WAKEUP0_SEL_S 27
|
||||
|
||||
#define XTL_EXT_CTR (DR_REG_RTCIO_BASE + 0xc0)
|
||||
#define RTC_IO_XTL_EXT_CTR_SEL 0x0000001F
|
||||
#define RTC_IO_XTL_EXT_CTR_SEL_S 27
|
||||
|
||||
#define SAR_I2C_IO (DR_REG_RTCIO_BASE + 0xc4)
|
||||
#define RTC_IO_SAR_I2C_SDA_SEL 0x00000003
|
||||
#define RTC_IO_SAR_I2C_SDA_SEL_S 30
|
||||
#define RTC_IO_SAR_I2C_SCL_SEL 0x00000003
|
||||
#define RTC_IO_SAR_I2C_SCL_SEL_S 28
|
||||
#define RTC_IO_SAR_DEBUG_BIT_SEL 0x0000001F
|
||||
#define RTC_IO_SAR_DEBUG_BIT_SEL_S 23
|
||||
|
||||
#define RTC_IO_DATE (DR_REG_RTCIO_BASE + 0xc8)
|
||||
#define RTC_IO_RTC_IO_DATE 0x0FFFFFFF
|
||||
#define RTC_IO_RTC_IO_DATE_S 0
|
||||
#define RTC_IO_RTC_IO_DATE_VERSION 0x1703160
|
||||
|
||||
#endif /* _SOC_RTC_IO_REG_H_ */
|
||||
|
||||
Executable
+270
@@ -0,0 +1,270 @@
|
||||
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _ESP32_SOC_H_
|
||||
#define _ESP32_SOC_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
//Register Bits{{
|
||||
#define BIT31 0x80000000
|
||||
#define BIT30 0x40000000
|
||||
#define BIT29 0x20000000
|
||||
#define BIT28 0x10000000
|
||||
#define BIT27 0x08000000
|
||||
#define BIT26 0x04000000
|
||||
#define BIT25 0x02000000
|
||||
#define BIT24 0x01000000
|
||||
#define BIT23 0x00800000
|
||||
#define BIT22 0x00400000
|
||||
#define BIT21 0x00200000
|
||||
#define BIT20 0x00100000
|
||||
#define BIT19 0x00080000
|
||||
#define BIT18 0x00040000
|
||||
#define BIT17 0x00020000
|
||||
#define BIT16 0x00010000
|
||||
#define BIT15 0x00008000
|
||||
#define BIT14 0x00004000
|
||||
#define BIT13 0x00002000
|
||||
#define BIT12 0x00001000
|
||||
#define BIT11 0x00000800
|
||||
#define BIT10 0x00000400
|
||||
#define BIT9 0x00000200
|
||||
#define BIT8 0x00000100
|
||||
#define BIT7 0x00000080
|
||||
#define BIT6 0x00000040
|
||||
#define BIT5 0x00000020
|
||||
#define BIT4 0x00000010
|
||||
#define BIT3 0x00000008
|
||||
#define BIT2 0x00000004
|
||||
#define BIT1 0x00000002
|
||||
#define BIT0 0x00000001
|
||||
//}}
|
||||
|
||||
//Registers Operation {{
|
||||
#define ETS_UNCACHED_ADDR(addr) (addr)
|
||||
#define ETS_CACHED_ADDR(addr) (addr)
|
||||
|
||||
#define BIT(nr) (1UL << (nr))
|
||||
|
||||
#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
|
||||
#define REG_READ(_r) (*(volatile uint32_t *)(_r))
|
||||
|
||||
#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b))
|
||||
#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b))
|
||||
#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b))
|
||||
#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)))
|
||||
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
|
||||
#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
|
||||
#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
|
||||
#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
|
||||
#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
|
||||
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
|
||||
#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f))
|
||||
#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f) << (_f##_S)))|(((_v) & (_f))<<(_f##_S)))))
|
||||
|
||||
|
||||
#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)))
|
||||
#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)
|
||||
#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
|
||||
#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
|
||||
#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask))
|
||||
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
|
||||
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ))
|
||||
#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask))
|
||||
//}}
|
||||
|
||||
//Periheral Clock {{
|
||||
#define APB_CLK_FREQ_ROM 13*1000000
|
||||
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
|
||||
#define CPU_CLK_FREQ APB_CLK_FREQ
|
||||
#define APB_CLK_FREQ 40*1000000 //unit: Hz
|
||||
#define UART_CLK_FREQ APB_CLK_FREQ
|
||||
//#define WDT_CLK_FREQ APB_CLK_FREQ
|
||||
#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16
|
||||
#define SPI_CLK_DIV 4
|
||||
//#define RTC_CLK_FREQ 32768 //unit:Hz
|
||||
//#define RTC_CLK_FREQ 100000 //unit:Hz
|
||||
//#define CALIB_CLK_MHZ 40
|
||||
#define TICKS_PER_US 13 // CPU is 80MHz
|
||||
//}}
|
||||
|
||||
#if 0
|
||||
//Peripheral device base address define{{
|
||||
#define DR_REG_DPORT_BASE 0x3ff00000
|
||||
#define DR_REG_UART_BASE 0x60000000
|
||||
#define DR_REG_SPI1_BASE 0x60002000 //no
|
||||
#define DR_REG_SPI0_BASE 0x60003000 //no
|
||||
#define DR_REG_GPIO_BASE 0x60004000 //no
|
||||
#define DR_REG_FE2_BASE 0x60005000
|
||||
#define DR_REG_FE_BASE 0x60006000
|
||||
#define DR_REG_TIMER_BASE 0x60007000 //no
|
||||
#define DR_REG_RTCCNTL_BASE 0x60008000
|
||||
#define DR_REG_RTCIO_BASE 0x60008400
|
||||
|
||||
#define DR_REG_RTCMEM0_BASE 0x60021000
|
||||
#define DR_REG_RTCMEM1_BASE 0x60022000
|
||||
#define DR_REG_RTCMEM2_BASE 0x60023000
|
||||
|
||||
#define DR_REG_IO_MUX_BASE 0x60009000 //no
|
||||
#define DR_REG_WDG_BASE 0x6000A000 //no
|
||||
#define DR_REG_HINF_BASE 0x6000B000 //no
|
||||
#define DR_REG_UHCI1_BASE 0x6000C000
|
||||
//#define DR_REG_MISC_BASE 0x6000D000 //no use
|
||||
#define DR_REG_I2C_BASE 0x6000E000 //no
|
||||
#define DR_REG_I2S_BASE 0x6000F000
|
||||
#define DR_REG_UART1_BASE 0x60010000
|
||||
#define DR_REG_BT_BASE 0x60011000
|
||||
//#define DR_REG_BT_BUFFER_BASE 0x60012000 //no use
|
||||
#define DR_REG_I2C_EXT_BASE 0x60013000 //no
|
||||
#define DR_REG_UHCI0_BASE 0x60014000
|
||||
#define DR_REG_SLCHOST_BASE 0x60015000
|
||||
#define DR_REG_RMT_BASE 0x60016000
|
||||
#define DR_REG_PCNT_BASE 0x60017000
|
||||
#define DR_REG_SLC_BASE 0x60018000
|
||||
#define DR_REG_LEDC_BASE 0x60019000
|
||||
#define DR_REG_EFUSE_BASE 0x6001A000
|
||||
#define DR_REG_SPI_ENCRYPT_BASE 0x6001B000
|
||||
#define DR_REG_PWM_BASE 0x6001C000 //no
|
||||
#define DR_REG_TIMERGROUP_BASE 0x6001D000 //no
|
||||
#define DR_REG_TIMERGROUP1_BASE 0x6001E000 //no
|
||||
#define DR_REG_BB_BASE 0x6001F000
|
||||
#define DR_REG_GPIO_SD_BASE 0x60004f00
|
||||
#else
|
||||
#define DR_REG_DPORT_BASE 0x3ff00000
|
||||
#define DR_REG_UART_BASE 0x3ff40000
|
||||
#define DR_REG_SPI1_BASE 0x3ff42000 //no
|
||||
#define DR_REG_SPI0_BASE 0x3ff43000 //no
|
||||
#define DR_REG_GPIO_BASE 0x3ff44000 //no
|
||||
#define DR_REG_FE2_BASE 0x3ff45000
|
||||
#define DR_REG_FE_BASE 0x3ff46000
|
||||
#define DR_REG_TIMER_BASE 0x3ff47000 //no
|
||||
#define DR_REG_RTCCNTL_BASE 0x3ff48000
|
||||
#define DR_REG_RTCIO_BASE 0x3ff48400
|
||||
|
||||
#define DR_REG_RTCMEM0_BASE 0x3ff61000
|
||||
#define DR_REG_RTCMEM1_BASE 0x3ff62000
|
||||
#define DR_REG_RTCMEM2_BASE 0x3ff63000
|
||||
|
||||
#define DR_REG_IO_MUX_BASE 0x3ff49000 //no
|
||||
#define DR_REG_WDG_BASE 0x3ff4A000 //no
|
||||
#define DR_REG_HINF_BASE 0x3ff4B000 //no
|
||||
#define DR_REG_UHCI1_BASE 0x3ff4C000
|
||||
//#define DR_REG_MISC_BASE 0x6000D000 //no use
|
||||
#define DR_REG_I2C_BASE 0x3ff4E000 //no
|
||||
#define DR_REG_I2S_BASE 0x3ff4F000
|
||||
#define DR_REG_I2S1_BASE 0x3ff6D000
|
||||
#define DR_REG_UART1_BASE 0x3ff50000
|
||||
#define DR_REG_BT_BASE 0x3ff51000
|
||||
//#define DR_REG_BT_BUFFER_BASE 0x60012000 //no use
|
||||
#define DR_REG_I2C_EXT_BASE 0x3ff53000 //no
|
||||
#define DR_REG_UHCI0_BASE 0x3ff54000
|
||||
#define DR_REG_SLCHOST_BASE 0x3ff55000
|
||||
#define DR_REG_RMT_BASE 0x3ff56000
|
||||
#define DR_REG_PCNT_BASE 0x3ff57000
|
||||
#define DR_REG_SLC_BASE 0x3ff58000
|
||||
#define DR_REG_LEDC_BASE 0x3ff59000
|
||||
#define DR_REG_EFUSE_BASE 0x3ff5A000
|
||||
#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000
|
||||
#define DR_REG_PWM_BASE 0x3ff5C000 //no
|
||||
#define DR_REG_TIMERS_BASE 0x3ff5F000 //no
|
||||
#define DR_REG_TIMERGROUP1_BASE 0x3ff5E000 //no
|
||||
#define DR_REG_BB_BASE 0x3ff5F000
|
||||
#define DR_REG_GPIO_SD_BASE 0x3ff44f00
|
||||
#endif
|
||||
|
||||
//}}
|
||||
#define REG_SPI_BASE(i) (DR_REG_SPI0_BASE - i*(0x1000))
|
||||
#define PERIPHS_TIMER_BASEDDR DR_REG_TIMER_BASE
|
||||
#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE
|
||||
|
||||
#define UART0_UNHOLD_MASK 0x3
|
||||
#define UART1_UNHOLD_MASK 0x60
|
||||
#define SDIO_UNHOLD_MASK 0xfc
|
||||
#define SPI_UNHOLD_MASK 0xfc
|
||||
|
||||
// TIMER reg {{
|
||||
#define TIMER_REG_READ(addr) READ_PERI_REG(addr)
|
||||
#define TIMER_REG_WRITE(addr, val) WRITE_PERI_REG(addr, val)
|
||||
#define TIMER_SET_REG_MASK(reg, mask) WRITE_PERI_REG(reg, (READ_PERI_REG(reg)|(mask)))
|
||||
/* Returns the current time according to the timer timer. */
|
||||
#define NOW() TIMER_REG_READ(FRC2_COUNT_ADDRESS)
|
||||
//load initial_value to timer1
|
||||
#define FRC1_LOAD_ADDRESS (PERIPHS_TIMER_BASEDDR +0x00)
|
||||
#define FRC1_LOAD_DATA_MSB 22
|
||||
#define FRC1_LOAD_DATA_LSB 0
|
||||
#define FRC1_LOAD_DATA_MASK 0x007fffff
|
||||
|
||||
//timer1's counter value(count from initial_value to 0)
|
||||
#define FRC1_COUNT_ADDRESS (PERIPHS_TIMER_BASEDDR +0x04)
|
||||
#define FRC1_COUNT_DATA_MSB 22
|
||||
#define FRC1_COUNT_DATA_LSB 0
|
||||
#define FRC1_COUNT_DATA_MASK 0x007fffff
|
||||
|
||||
#define FRC1_CTRL_ADDRESS (PERIPHS_TIMER_BASEDDR +0x08)
|
||||
#define FRC1_CTRL_DATA_MSB 7
|
||||
#define FRC1_CTRL_DATA_LSB 0
|
||||
#define FRC1_CTRL_DATA_MASK 0x000000ff
|
||||
|
||||
//clear timer1's interrupt when write this address
|
||||
#define FRC1_INT_ADDRESS (PERIPHS_TIMER_BASEDDR +0x0c)
|
||||
#define FRC1_INT_CLR_MSB 0
|
||||
#define FRC1_INT_CLR_LSB 0
|
||||
#define FRC1_INT_CLR_MASK 0x00000001
|
||||
|
||||
//only used for simulation
|
||||
#define FRC1_TEST_ADDRESS (PERIPHS_TIMER_BASEDDR +0x10)
|
||||
#define FRC1_TEST_MODE_MSB 0
|
||||
#define FRC1_TEST_MODE_LSB 0
|
||||
#define FRC1_TEST_MODE_MASK 0x00000001
|
||||
|
||||
//load initial_value to timer2
|
||||
#define FRC2_LOAD_ADDRESS (PERIPHS_TIMER_BASEDDR +0x20)
|
||||
#define FRC2_LOAD_DATA_MSB 31
|
||||
#define FRC2_LOAD_DATA_LSB 0
|
||||
#define FRC2_LOAD_DATA_MASK 0xffffffff
|
||||
|
||||
//timer2's counter value(count from initial_value to 0)
|
||||
#define FRC2_COUNT_ADDRESS (PERIPHS_TIMER_BASEDDR +0x24)
|
||||
#define FRC2_COUNT_DATA_MSB 31
|
||||
#define FRC2_COUNT_DATA_LSB 0
|
||||
#define FRC2_COUNT_DATA_MASK 0xffffffff
|
||||
|
||||
#define FRC2_CTRL_ADDRESS (PERIPHS_TIMER_BASEDDR +0x28)
|
||||
#define FRC2_CTRL_DATA_MSB 7
|
||||
#define FRC2_CTRL_DATA_LSB 0
|
||||
#define FRC2_CTRL_DATA_MASK 0x000000ff
|
||||
|
||||
//clear interrupt when write this address
|
||||
#define FRC2_INT_ADDRESS (PERIPHS_TIMER_BASEDDR +0x2c)
|
||||
#define FRC2_INT_CLR_MSB 0
|
||||
#define FRC2_INT_CLR_LSB 0
|
||||
#define FRC2_INT_CLR_MASK 0x00000001
|
||||
|
||||
//set Alarm_value for timer2 to generate interrupt
|
||||
#define FRC2_ALARM_ADDRESS (PERIPHS_TIMER_BASEDDR +0x30)
|
||||
#define FRC2_ALARM_DATA_MSB 31
|
||||
#define FRC2_ALARM_DATA_LSB 0
|
||||
#define FRC2_ALARM_DATA_MASK 0xffffffff
|
||||
// }}
|
||||
|
||||
#define SPI_ENCRYPT_CNTL (PERIPHS_SPI_ENCRYPT_BASEADDR + 0x20)
|
||||
#define SPI_ENCRYPT_CNTL_ENA BIT(0)
|
||||
|
||||
#define SPI_ENCRYPT_ADDR (PERIPHS_SPI_ENCRYPT_BASEADDR + 0x24)
|
||||
|
||||
#define SPI_ENCRYPT_CHECKDONE (PERIPHS_SPI_ENCRYPT_BASEADDR + 0x28)
|
||||
#define SPI_ENCRYPT_CHECKDONE_STATUS BIT(0)
|
||||
|
||||
#endif /* _ESP32_SOC_H_ */
|
||||
Executable
+399
@@ -0,0 +1,399 @@
|
||||
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_SPI_REG_H_
|
||||
#define _SOC_SPI_REG_H_
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define SPI_CMD( i ) (REG_SPI_BASE( i ) + 0x0)
|
||||
#define SPI_FLASH_READ (BIT(31))
|
||||
#define SPI_FLASH_WREN (BIT(30))
|
||||
#define SPI_FLASH_WRDI (BIT(29))
|
||||
#define SPI_FLASH_RDID (BIT(28))
|
||||
#define SPI_FLASH_RDSR (BIT(27))
|
||||
#define SPI_FLASH_WRSR (BIT(26))
|
||||
#define SPI_FLASH_PP (BIT(25))
|
||||
#define SPI_FLASH_SE (BIT(24))
|
||||
#define SPI_FLASH_BE (BIT(23))
|
||||
#define SPI_FLASH_CE (BIT(22))
|
||||
#define SPI_FLASH_DP (BIT(21))
|
||||
#define SPI_FLASH_RES (BIT(20))
|
||||
#define SPI_FLASH_HPM (BIT(19))
|
||||
#define SPI_USR (BIT(18))
|
||||
#define SPI_FLASH_PES (BIT(17))
|
||||
#define SPI_FLASH_PER (BIT(16))
|
||||
#define SPI_ADDR( i ) (REG_SPI_BASE( i ) + 0x4)
|
||||
#define SPI_CTRL( i ) (REG_SPI_BASE( i ) + 0x8)
|
||||
#define SPI_WR_BIT_ORDER (BIT(26))
|
||||
#define SPI_RD_BIT_ORDER (BIT(25))
|
||||
#define SPI_FREAD_QIO (BIT(24))
|
||||
#define SPI_FREAD_DIO (BIT(23))
|
||||
#define SPI_WRSR_2B (BIT(22))
|
||||
#define SPI_WP_REG (BIT(21))
|
||||
#define SPI_FREAD_QUAD (BIT(20))
|
||||
#define SPI_RESANDRES (BIT(15))
|
||||
#define SPI_FREAD_DUAL (BIT(14))
|
||||
#define SPI_FASTRD_MODE (BIT(13))
|
||||
#define SPI_WAIT_FLASH_IDLE_EN (BIT(12))
|
||||
#define SPI_TX_CRC_EN (BIT(11))
|
||||
#define SPI_FCS_CRC_EN (BIT(10))
|
||||
#define SPI_CTRL1( i ) (REG_SPI_BASE( i ) + 0xC)
|
||||
#define SPI_CS_HOLD_DELAY 0x0000000F
|
||||
#define SPI_CS_HOLD_DELAY_S 28
|
||||
#define SPI_CS_HOLD_DELAY_RES 0x00000FFF
|
||||
#define SPI_CS_HOLD_DELAY_RES_S 16
|
||||
#define SPI_RD_STATUS( i ) (REG_SPI_BASE( i ) + 0x10)
|
||||
#define SPI_STATUS_EXT 0x000000FF
|
||||
#define SPI_STATUS_EXT_S 24
|
||||
#define SPI_WB_MODE 0x000000FF
|
||||
#define SPI_WB_MODE_S 16
|
||||
#define SPI_STATUS 0x0000FFFF
|
||||
#define SPI_STATUS_S 0
|
||||
|
||||
#define SPI_CTRL2( i ) (REG_SPI_BASE( i ) + 0x14)
|
||||
#define SPI_CS_DELAY_NUM 0x0000000F
|
||||
#define SPI_CS_DELAY_NUM_S 28
|
||||
#define SPI_CS_DELAY_MODE 0x00000003
|
||||
#define SPI_CS_DELAY_MODE_S 26
|
||||
#define SPI_MOSI_DELAY_NUM 0x00000007
|
||||
#define SPI_MOSI_DELAY_NUM_S 23
|
||||
#define SPI_MOSI_DELAY_MODE 0x00000003
|
||||
#define SPI_MOSI_DELAY_MODE_S 21
|
||||
#define SPI_MISO_DELAY_NUM 0x00000007
|
||||
#define SPI_MISO_DELAY_NUM_S 18
|
||||
#define SPI_MISO_DELAY_MODE 0x00000003
|
||||
#define SPI_MISO_DELAY_MODE_S 16
|
||||
#define SPI_CK_OUT_HIGH_MODE 0x0000000F
|
||||
#define SPI_CK_OUT_HIGH_MODE_S 12
|
||||
#define SPI_CK_OUT_LOW_MODE 0x0000000F
|
||||
#define SPI_CK_OUT_LOW_MODE_S 8
|
||||
#define SPI_HOLD_TIME 0x0000000F
|
||||
#define SPI_HOLD_TIME_S 4
|
||||
#define SPI_SETUP_TIME 0x0000000F
|
||||
#define SPI_SETUP_TIME_S 0
|
||||
|
||||
#define SPI_CLOCK( i ) (REG_SPI_BASE( i ) + 0x18)
|
||||
#define SPI_CLK_EQU_SYSCLK (BIT(31))
|
||||
#define SPI_CLKDIV_PRE 0x00001FFF
|
||||
#define SPI_CLKDIV_PRE_S 18
|
||||
#define SPI_CLKCNT_N 0x0000003F
|
||||
#define SPI_CLKCNT_N_S 12
|
||||
#define SPI_CLKCNT_H 0x0000003F
|
||||
#define SPI_CLKCNT_H_S 6
|
||||
#define SPI_CLKCNT_L 0x0000003F
|
||||
#define SPI_CLKCNT_L_S 0
|
||||
|
||||
#define SPI_USER( i ) (REG_SPI_BASE( i ) + 0x1C)
|
||||
#define SPI_USR_COMMAND (BIT(31))
|
||||
#define SPI_USR_ADDR (BIT(30))
|
||||
#define SPI_USR_DUMMY (BIT(29))
|
||||
#define SPI_USR_MISO (BIT(28))
|
||||
#define SPI_USR_MOSI (BIT(27))
|
||||
#define SPI_USR_DUMMY_IDLE (BIT(26))
|
||||
#define SPI_USR_MOSI_HIGHPART (BIT(25))
|
||||
#define SPI_USR_MISO_HIGHPART (BIT(24))
|
||||
#define SPI_USR_PREP_HOLD (BIT(23))
|
||||
#define SPI_USR_CMD_HOLD (BIT(22))
|
||||
#define SPI_USR_ADDR_HOLD (BIT(21))
|
||||
#define SPI_USR_DUMMY_HOLD (BIT(20))
|
||||
#define SPI_USR_DIN_HOLD (BIT(19))
|
||||
#define SPI_USR_DOUT_HOLD (BIT(18))
|
||||
#define SPI_USR_HOLD_POL (BIT(17))
|
||||
#define SPI_SIO (BIT(16))
|
||||
#define SPI_FWRITE_QIO (BIT(15))
|
||||
#define SPI_FWRITE_DIO (BIT(14))
|
||||
#define SPI_FWRITE_QUAD (BIT(13))
|
||||
#define SPI_FWRITE_DUAL (BIT(12))
|
||||
#define SPI_WR_BYTE_ORDER (BIT(11))
|
||||
#define SPI_RD_BYTE_ORDER (BIT(10))
|
||||
#define SPI_CK_OUT_EDGE (BIT(7))
|
||||
#define SPI_CK_I_EDGE (BIT(6))
|
||||
#define SPI_CS_SETUP (BIT(5))
|
||||
#define SPI_CS_HOLD (BIT(4))
|
||||
#define SPI_DOUTDIN (BIT(0))
|
||||
|
||||
#define SPI_USER1( i ) (REG_SPI_BASE( i ) + 0x20)
|
||||
#define SPI_USR_ADDR_BITLEN 0x0000003F
|
||||
#define SPI_USR_ADDR_BITLEN_S 26
|
||||
#define SPI_USR_DUMMY_CYCLELEN 0x000000FF
|
||||
#define SPI_USR_DUMMY_CYCLELEN_S 0
|
||||
|
||||
#define SPI_USER2( i ) (REG_SPI_BASE( i ) + 0x24)
|
||||
#define SPI_USR_COMMAND_BITLEN 0x0000000F
|
||||
#define SPI_USR_COMMAND_BITLEN_S 28
|
||||
#define SPI_USR_COMMAND_VALUE 0x0000FFFF
|
||||
#define SPI_USR_COMMAND_VALUE_S 0
|
||||
|
||||
#define SPI_MOSI_DLEN( i ) (REG_SPI_BASE( i ) + 0x28)
|
||||
#define SPI_USR_MOSI_DBITLEN 0x00FFFFFF
|
||||
#define SPI_USR_MOSI_DBITLEN_S 0
|
||||
|
||||
#define SPI_MISO_DLEN( i ) (REG_SPI_BASE( i ) + 0x2C)
|
||||
#define SPI_USR_MISO_DBITLEN 0x00FFFFFF
|
||||
#define SPI_USR_MISO_DBITLEN_S 0
|
||||
|
||||
#define SPI_SLV_WR_STATUS( i ) (REG_SPI_BASE( i ) + 0x30)
|
||||
#define SPI_PIN( i ) (REG_SPI_BASE( i ) + 0x34)
|
||||
#define SPI_CS_KEEP_ACTIVE (BIT(30))
|
||||
#define SPI_CK_IDLE_EDGE (BIT(29))
|
||||
#define SPI_CSCK_SEL (BIT(19))
|
||||
#define SPI_MASTER_CK_SEL 0x0000001F
|
||||
#define SPI_MASTER_CK_SEL_S 11
|
||||
#define SPI_MASTER_CS_POL 0x0000001F
|
||||
#define SPI_MASTER_CS_POL_S 6
|
||||
#define SPI_CK_DIS (BIT(5))
|
||||
#define SPI_CS2_DIS (BIT(2))
|
||||
#define SPI_CS1_DIS (BIT(1))
|
||||
#define SPI_CS0_DIS (BIT(0))
|
||||
|
||||
#define SPI_SLAVE( i ) (REG_SPI_BASE( i ) + 0x38)
|
||||
#define SPI_SYNC_RESET (BIT(31))
|
||||
#define SPI_SLAVE_MODE (BIT(30))
|
||||
#define SPI_SLV_WR_RD_BUF_EN (BIT(29))
|
||||
#define SPI_SLV_WR_RD_STA_EN (BIT(28))
|
||||
#define SPI_SLV_CMD_DEFINE (BIT(27))
|
||||
#define SPI_TRANS_CNT 0x0000000F
|
||||
#define SPI_TRANS_CNT_S 23
|
||||
#define SPI_SLV_LAST_STATE 0x00000007
|
||||
#define SPI_SLV_LAST_STATE_S 20
|
||||
#define SPI_SLV_LAST_COMMAND 0x00000007
|
||||
#define SPI_SLV_LAST_COMMAND_S 17
|
||||
#define SPI_CS_I_MODE 0x00000003
|
||||
#define SPI_CS_I_MODE_S 10
|
||||
#define SPI_INT_EN 0x0000001F
|
||||
#define SPI_INT_EN_S 5
|
||||
#define SPI_TRANS_DONE (BIT(4))
|
||||
#define SPI_SLV_WR_STA_DONE (BIT(3))
|
||||
#define SPI_SLV_RD_STA_DONE (BIT(2))
|
||||
#define SPI_SLV_WR_BUF_DONE (BIT(1))
|
||||
#define SPI_SLV_RD_BUF_DONE (BIT(0))
|
||||
|
||||
#define SPI_SLAVE1( i ) (REG_SPI_BASE( i ) + 0x3C)
|
||||
#define SPI_SLV_STATUS_BITLEN 0x0000001F
|
||||
#define SPI_SLV_STATUS_BITLEN_S 27
|
||||
#define SPI_SLV_STATUS_FAST_EN (BIT(26))
|
||||
#define SPI_SLV_STATUS_READBACK (BIT(25))
|
||||
#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F
|
||||
#define SPI_SLV_RD_ADDR_BITLEN_S 10
|
||||
#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F
|
||||
#define SPI_SLV_WR_ADDR_BITLEN_S 4
|
||||
#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3))
|
||||
#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2))
|
||||
#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))
|
||||
#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0))
|
||||
|
||||
#define SPI_SLAVE2( i ) (REG_SPI_BASE( i ) + 0x40)
|
||||
#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0x000000FF
|
||||
#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24
|
||||
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF
|
||||
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16
|
||||
#define SPI_SLV_WRSTA_DUMMY_CYCLELEN 0x000000FF
|
||||
#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_S 8
|
||||
#define SPI_SLV_RDSTA_DUMMY_CYCLELEN 0x000000FF
|
||||
#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_S 0
|
||||
|
||||
#define SPI_SLAVE3( i ) (REG_SPI_BASE( i ) + 0x44)
|
||||
#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF
|
||||
#define SPI_SLV_WRSTA_CMD_VALUE_S 24
|
||||
#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF
|
||||
#define SPI_SLV_RDSTA_CMD_VALUE_S 16
|
||||
#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF
|
||||
#define SPI_SLV_WRBUF_CMD_VALUE_S 8
|
||||
#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF
|
||||
#define SPI_SLV_RDBUF_CMD_VALUE_S 0
|
||||
|
||||
#define SPI_SLV_WRBUF_DLEN( i ) (REG_SPI_BASE( i ) + 0x48)
|
||||
#define SPI_SLV_WRBUF_DBITLEN 0x00FFFFFF
|
||||
#define SPI_SLV_WRBUF_DBITLEN_S 0
|
||||
|
||||
#define SPI_SLV_RDBUF_DLEN( i ) (REG_SPI_BASE( i ) + 0x4C)
|
||||
#define SPI_SLV_RDBUF_DBITLEN 0x00FFFFFF
|
||||
#define SPI_SLV_RDBUF_DBITLEN_S 0
|
||||
|
||||
#define SPI_CACHE_FCTRL( i ) (REG_SPI_BASE( i ) + 0x50)
|
||||
#define SPI_CACHE_FLASH_PES_EN (BIT(3))
|
||||
#define SPI_CACHE_FLASH_USR_CMD (BIT(2))
|
||||
#define SPI_CACHE_USR_CMD_4BYTE (BIT(1))
|
||||
#define SPI_CACHE_REQ_EN (BIT(0))
|
||||
|
||||
#define SPI_CACHE_SCTRL( i ) (REG_SPI_BASE( i ) + 0x54)
|
||||
#define SPI_CACHE_SRAM_USR_WCMD (BIT(28))
|
||||
#define SPI_SRAM_ADDR_BITLEN 0x0000003F
|
||||
#define SPI_SRAM_ADDR_BITLEN_S 22
|
||||
#define SPI_SRAM_DUMMY_CYCLELEN 0x000000FF
|
||||
#define SPI_SRAM_DUMMY_CYCLELEN_S 14
|
||||
#define SPI_SRAM_BYTES_LEN 0x000000FF
|
||||
#define SPI_SRAM_BYTES_LEN_S 6
|
||||
#define SPI_CACHE_SRAM_USR_RCMD (BIT(5))
|
||||
#define SPI_USR_RD_SRAM_DUMMY (BIT(4))
|
||||
#define SPI_USR_WR_SRAM_DUMMY (BIT(3))
|
||||
#define SPI_USR_SRAM_QIO (BIT(2))
|
||||
#define SPI_USR_SRAM_DIO (BIT(1))
|
||||
#define SPI_SRAM_CMD( i ) (REG_SPI_BASE( i ) + 0x58)
|
||||
#define SPI_SRAM_RSTIO (BIT(4))
|
||||
#define SPI_SRAM_QIO (BIT(1))
|
||||
#define SPI_SRAM_DIO (BIT(0))
|
||||
|
||||
#define SPI_SRAM_DRD_CMD( i ) (REG_SPI_BASE( i ) + 0x5C)
|
||||
#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F
|
||||
#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28
|
||||
#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF
|
||||
#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S 0
|
||||
|
||||
#define SPI_SRAM_DWR_CMD( i ) (REG_SPI_BASE( i ) + 0x60)
|
||||
#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F
|
||||
#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28
|
||||
#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF
|
||||
#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S 0
|
||||
|
||||
#define SPI_SLV_RD_BIT( i ) (REG_SPI_BASE( i ) + 0x64)
|
||||
#define SPI_SLV_RDATA_BIT 0x00FFFFFF
|
||||
#define SPI_SLV_RDATA_BIT_S 0
|
||||
|
||||
#define SPI_W0( i ) (REG_SPI_BASE( i ) + 0x80)
|
||||
#define SPI_W1( i ) (REG_SPI_BASE( i ) + 0x84)
|
||||
#define SPI_W2( i ) (REG_SPI_BASE( i ) + 0x88)
|
||||
#define SPI_W3( i ) (REG_SPI_BASE( i ) + 0x8C)
|
||||
#define SPI_W4( i ) (REG_SPI_BASE( i ) + 0x90)
|
||||
#define SPI_W5( i ) (REG_SPI_BASE( i ) + 0x94)
|
||||
#define SPI_W6( i ) (REG_SPI_BASE( i ) + 0x98)
|
||||
#define SPI_W7( i ) (REG_SPI_BASE( i ) + 0x9C)
|
||||
#define SPI_W8( i ) (REG_SPI_BASE( i ) + 0xA0)
|
||||
#define SPI_W9( i ) (REG_SPI_BASE( i ) + 0xA4)
|
||||
#define SPI_W10( i ) (REG_SPI_BASE( i ) + 0xA8)
|
||||
#define SPI_W11( i ) (REG_SPI_BASE( i ) + 0xAC)
|
||||
#define SPI_W12( i ) (REG_SPI_BASE( i ) + 0xB0)
|
||||
#define SPI_W13( i ) (REG_SPI_BASE( i ) + 0xB4)
|
||||
#define SPI_W14( i ) (REG_SPI_BASE( i ) + 0xB8)
|
||||
#define SPI_W15( i ) (REG_SPI_BASE( i ) + 0xBC)
|
||||
#define SPI_TX_CRC( i ) (REG_SPI_BASE( i ) + 0xC0)
|
||||
#define SPI_EXT0( i ) (REG_SPI_BASE( i ) + 0xF0)
|
||||
#define SPI_T_PP_ENA (BIT(31))
|
||||
#define SPI_T_PP_SHIFT 0x0000000F
|
||||
#define SPI_T_PP_SHIFT_S 16
|
||||
#define SPI_T_PP_TIME 0x00000FFF
|
||||
#define SPI_T_PP_TIME_S 0
|
||||
|
||||
#define SPI_EXT1( i ) (REG_SPI_BASE( i ) + 0xF4)
|
||||
#define SPI_T_ERASE_ENA (BIT(31))
|
||||
#define SPI_T_ERASE_SHIFT 0x0000000F
|
||||
#define SPI_T_ERASE_SHIFT_S 16
|
||||
#define SPI_T_ERASE_TIME 0x00000FFF
|
||||
#define SPI_T_ERASE_TIME_S 0
|
||||
|
||||
#define SPI_EXT2( i ) (REG_SPI_BASE( i ) + 0xF8)
|
||||
#define SPI_ST 0x00000007
|
||||
#define SPI_ST_S 0
|
||||
|
||||
#define SPI_EXT3( i ) (REG_SPI_BASE( i ) + 0xFC)
|
||||
#define SPI_INT_HOLD_ENA 0x00000003
|
||||
#define SPI_INT_HOLD_ENA_S 0
|
||||
|
||||
#define SPI_DMA_CONF( i ) (REG_SPI_BASE( i ) + 0x100)
|
||||
#define SPI_DMA_CONTINUE (BIT(16))
|
||||
#define SPI_DMA_TX_STOP (BIT(15))
|
||||
#define SPI_DMA_RX_STOP (BIT(14))
|
||||
#define SPI_OUT_DATA_BURST_EN (BIT(12))
|
||||
#define SPI_INDSCR_BURST_EN (BIT(11))
|
||||
#define SPI_OUTDSCR_BURST_EN (BIT(10))
|
||||
#define SPI_OUT_EOF_MODE (BIT(9))
|
||||
#define SPI_OUT_AUTO_WRBACK (BIT(8))
|
||||
#define SPI_OUT_LOOP_TEST (BIT(7))
|
||||
#define SPI_IN_LOOP_TEST (BIT(6))
|
||||
#define SPI_AHBM_RST (BIT(5))
|
||||
#define SPI_AHBM_FIFO_RST (BIT(4))
|
||||
#define SPI_OUT_RST (BIT(3))
|
||||
#define SPI_IN_RST (BIT(2))
|
||||
#define SPI_DMA_OUT_LINK( i ) (REG_SPI_BASE( i ) + 0x104)
|
||||
#define SPI_OUTLINK_RESTART (BIT(30))
|
||||
#define SPI_OUTLINK_START (BIT(29))
|
||||
#define SPI_OUTLINK_STOP (BIT(28))
|
||||
#define SPI_OUTLINK_ADDR 0x000FFFFF
|
||||
#define SPI_OUTLINK_ADDR_S 0
|
||||
|
||||
#define SPI_DMA_IN_LINK( i ) (REG_SPI_BASE( i ) + 0x108)
|
||||
#define SPI_INLINK_RESTART (BIT(30))
|
||||
#define SPI_INLINK_START (BIT(29))
|
||||
#define SPI_INLINK_STOP (BIT(28))
|
||||
#define SPI_INLINK_AUTO_RET (BIT(20))
|
||||
#define SPI_INLINK_ADDR 0x000FFFFF
|
||||
#define SPI_INLINK_ADDR_S 0
|
||||
|
||||
#define SPI_DMA_STATUS( i ) (REG_SPI_BASE( i ) + 0x10C)
|
||||
#define SPI_DMA_TX_EN (BIT(1))
|
||||
#define SPI_DMA_RX_EN (BIT(0))
|
||||
|
||||
#define SPI_DMA_INT_ENA( i ) (REG_SPI_BASE( i ) + 0x110)
|
||||
#define SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8))
|
||||
#define SPI_OUT_EOF_INT_ENA (BIT(7))
|
||||
#define SPI_OUT_DONE_INT_ENA (BIT(6))
|
||||
#define SPI_IN_SUC_EOF_INT_ENA (BIT(5))
|
||||
#define SPI_IN_ERR_EOF_INT_ENA (BIT(4))
|
||||
#define SPI_IN_DONE_INT_ENA (BIT(3))
|
||||
#define SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2))
|
||||
#define SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1))
|
||||
#define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0))
|
||||
|
||||
#define SPI_DMA_INT_RAW( i ) (REG_SPI_BASE( i ) + 0x114)
|
||||
#define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8))
|
||||
#define SPI_OUT_EOF_INT_RAW (BIT(7))
|
||||
#define SPI_OUT_DONE_INT_RAW (BIT(6))
|
||||
#define SPI_IN_SUC_EOF_INT_RAW (BIT(5))
|
||||
#define SPI_IN_ERR_EOF_INT_RAW (BIT(4))
|
||||
#define SPI_IN_DONE_INT_RAW (BIT(3))
|
||||
#define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2))
|
||||
#define SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1))
|
||||
#define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0))
|
||||
|
||||
#define SPI_DMA_INT_ST( i ) (REG_SPI_BASE( i ) + 0x118)
|
||||
#define SPI_OUT_TOTAL_EOF_INT_ST (BIT(8))
|
||||
#define SPI_OUT_EOF_INT_ST (BIT(7))
|
||||
#define SPI_OUT_DONE_INT_ST (BIT(6))
|
||||
#define SPI_IN_SUC_EOF_INT_ST (BIT(5))
|
||||
#define SPI_IN_ERR_EOF_INT_ST (BIT(4))
|
||||
#define SPI_IN_DONE_INT_ST (BIT(3))
|
||||
#define SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2))
|
||||
#define SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1))
|
||||
#define SPI_INLINK_DSCR_EMPTY_INT_ST (BIT(0))
|
||||
|
||||
#define SPI_DMA_INT_CLR( i ) (REG_SPI_BASE( i ) + 0x11C)
|
||||
#define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8))
|
||||
#define SPI_OUT_EOF_INT_CLR (BIT(7))
|
||||
#define SPI_OUT_DONE_INT_CLR (BIT(6))
|
||||
#define SPI_IN_SUC_EOF_INT_CLR (BIT(5))
|
||||
#define SPI_IN_ERR_EOF_INT_CLR (BIT(4))
|
||||
#define SPI_IN_DONE_INT_CLR (BIT(3))
|
||||
#define SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2))
|
||||
#define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1))
|
||||
#define SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0))
|
||||
|
||||
#define SPI_IN_ERR_EOF_DES_ADDR( i ) (REG_SPI_BASE( i ) + 0x120)
|
||||
#define SPI_IN_SUC_EOF_DES_ADDR( i ) (REG_SPI_BASE( i ) + 0x124)
|
||||
#define SPI_INLINK_DSCR( i ) (REG_SPI_BASE( i ) + 0x128)
|
||||
#define SPI_INLINK_DSCR_BF0( i ) (REG_SPI_BASE( i ) + 0x12C)
|
||||
#define SPI_INLINK_DSCR_BF1( i ) (REG_SPI_BASE( i ) + 0x130)
|
||||
#define SPI_OUT_EOF_BFR_DES_ADDR( i ) (REG_SPI_BASE( i ) + 0x134)
|
||||
#define SPI_OUT_EOF_DES_ADDR( i ) (REG_SPI_BASE( i ) + 0x138)
|
||||
#define SPI_OUTLINK_DSCR( i ) (REG_SPI_BASE( i ) + 0x13C)
|
||||
#define SPI_OUTLINK_DSCR_BF0( i ) (REG_SPI_BASE( i ) + 0x140)
|
||||
#define SPI_OUTLINK_DSCR_BF1( i ) (REG_SPI_BASE( i ) + 0x144)
|
||||
#define SPI_DMA_RSTATUS( i ) (REG_SPI_BASE( i ) + 0x148)
|
||||
#define SPI_DMA_TSTATUS( i ) (REG_SPI_BASE( i ) + 0x14C)
|
||||
#define SPI_REG_DATE( i ) (REG_SPI_BASE( i ) + 0x3FC)
|
||||
#define SPI_DATE 0x0FFFFFFF
|
||||
#define SPI_DATE_S 0
|
||||
#define SPI_DATE_VERSION 0x1604290
|
||||
|
||||
#endif /* _SOC_SPI_REG_H_ */
|
||||
@@ -0,0 +1,288 @@
|
||||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_TIMERS_REG_H_
|
||||
#define _SOC_TIMER_REG_H_
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define T0CONFIG (DR_REG_TIMERS_BASE + 0x0000)
|
||||
#define TIMERS_T0_EN (BIT(31))
|
||||
#define TIMERS_T0_EN_S 31
|
||||
#define TIMERS_T0_INCREASE (BIT(30))
|
||||
#define TIMERS_T0_INCREASE_S 30
|
||||
#define TIMERS_T0_AUTORELOAD (BIT(29))
|
||||
#define TIMERS_T0_AUTORELOAD_S 29
|
||||
#define TIMERS_T0_DIVIDER 0x0000FFFF
|
||||
#define TIMERS_T0_DIVIDER_S 13
|
||||
#define TIMERS_T0_EDGE_INT_EN (BIT(12))
|
||||
#define TIMERS_T0_EDGE_INT_EN_S 12
|
||||
#define TIMERS_T0_LEVEL_INT_EN (BIT(11))
|
||||
#define TIMERS_T0_LEVEL_INT_EN_S 11
|
||||
#define TIMERS_T0_ALARM_EN (BIT(10))
|
||||
#define TIMERS_T0_ALARM_EN_S 10
|
||||
|
||||
#define T0LO (DR_REG_TIMERS_BASE + 0x0004)
|
||||
#define TIMERS_T0_LO 0xFFFFFFFF
|
||||
#define TIMERS_T0_LO_S 0
|
||||
|
||||
#define T0HI (DR_REG_TIMERS_BASE + 0x0008)
|
||||
#define TIMERS_T0_HI 0xFFFFFFFF
|
||||
#define TIMERS_T0_HI_S 0
|
||||
|
||||
#define T0UPDATE (DR_REG_TIMERS_BASE + 0x000c)
|
||||
#define TIMERS_T0_UPDATE 0xFFFFFFFF
|
||||
#define TIMERS_T0_UPDATE_S 0
|
||||
|
||||
#define T0ALARMLO (DR_REG_TIMERS_BASE + 0x0010)
|
||||
#define TIMERS_T0_ALARM_LO 0xFFFFFFFF
|
||||
#define TIMERS_T0_ALARM_LO_S 0
|
||||
|
||||
#define T0ALARMHI (DR_REG_TIMERS_BASE + 0x0014)
|
||||
#define TIMERS_T0_ALARM_HI 0xFFFFFFFF
|
||||
#define TIMERS_T0_ALARM_HI_S 0
|
||||
|
||||
#define T0LOADLO (DR_REG_TIMERS_BASE + 0x0018)
|
||||
#define TIMERS_T0_LOAD_LO 0xFFFFFFFF
|
||||
#define TIMERS_T0_LOAD_LO_S 0
|
||||
|
||||
#define T0LOADHI (DR_REG_TIMERS_BASE + 0x001c)
|
||||
#define TIMERS_T0_LOAD_HI 0xFFFFFFFF
|
||||
#define TIMERS_T0_LOAD_HI_S 0
|
||||
|
||||
#define T0LOAD (DR_REG_TIMERS_BASE + 0x0020)
|
||||
#define TIMERS_T0_LOAD 0xFFFFFFFF
|
||||
#define TIMERS_T0_LOAD_S 0
|
||||
|
||||
#define T1CONFIG (DR_REG_TIMERS_BASE + 0x0024)
|
||||
#define TIMERS_T1_EN (BIT(31))
|
||||
#define TIMERS_T1_EN_S 31
|
||||
#define TIMERS_T1_INCREASE (BIT(30))
|
||||
#define TIMERS_T1_INCREASE_S 30
|
||||
#define TIMERS_T1_AUTORELOAD (BIT(29))
|
||||
#define TIMERS_T1_AUTORELOAD_S 29
|
||||
#define TIMERS_T1_DIVIDER 0x0000FFFF
|
||||
#define TIMERS_T1_DIVIDER_S 13
|
||||
#define TIMERS_T1_EDGE_INT_EN (BIT(12))
|
||||
#define TIMERS_T1_EDGE_INT_EN_S 12
|
||||
#define TIMERS_T1_LEVEL_INT_EN (BIT(11))
|
||||
#define TIMERS_T1_LEVEL_INT_EN_S 11
|
||||
#define TIMERS_T1_ALARM_EN (BIT(10))
|
||||
#define TIMERS_T1_ALARM_EN_S 10
|
||||
|
||||
#define T1LO (DR_REG_TIMERS_BASE + 0x0028)
|
||||
#define TIMERS_T1_LO 0xFFFFFFFF
|
||||
#define TIMERS_T1_LO_S 0
|
||||
|
||||
#define T1HI (DR_REG_TIMERS_BASE + 0x002c)
|
||||
#define TIMERS_T1_HI 0xFFFFFFFF
|
||||
#define TIMERS_T1_HI_S 0
|
||||
|
||||
#define T1UPDATE (DR_REG_TIMERS_BASE + 0x0030)
|
||||
#define TIMERS_T1_UPDATE 0xFFFFFFFF
|
||||
#define TIMERS_T1_UPDATE_S 0
|
||||
|
||||
#define T1ALARMLO (DR_REG_TIMERS_BASE + 0x0034)
|
||||
#define TIMERS_T1_ALARM_LO 0xFFFFFFFF
|
||||
#define TIMERS_T1_ALARM_LO_S 0
|
||||
|
||||
#define T1ALARMHI (DR_REG_TIMERS_BASE + 0x0038)
|
||||
#define TIMERS_T1_ALARM_HI 0xFFFFFFFF
|
||||
#define TIMERS_T1_ALARM_HI_S 0
|
||||
|
||||
#define T1LOADLO (DR_REG_TIMERS_BASE + 0x003c)
|
||||
#define TIMERS_T1_LOAD_LO 0xFFFFFFFF
|
||||
#define TIMERS_T1_LOAD_LO_S 0
|
||||
|
||||
#define T1LOADHI (DR_REG_TIMERS_BASE + 0x0040)
|
||||
#define TIMERS_T1_LOAD_HI 0xFFFFFFFF
|
||||
#define TIMERS_T1_LOAD_HI_S 0
|
||||
|
||||
#define T1LOAD (DR_REG_TIMERS_BASE + 0x0044)
|
||||
#define TIMERS_T1_LOAD 0xFFFFFFFF
|
||||
#define TIMERS_T1_LOAD_S 0
|
||||
|
||||
#define WDTCONFIG0 (DR_REG_TIMERS_BASE + 0x0048)
|
||||
#define TIMERS_WDT_EN (BIT(31))
|
||||
#define TIMERS_WDT_EN_S 31
|
||||
#define TIMERS_WDT_STG0 0x00000003
|
||||
#define TIMERS_WDT_STG0_S 29
|
||||
#define TIMERS_WDT_STG1 0x00000003
|
||||
#define TIMERS_WDT_STG1_S 27
|
||||
#define TIMERS_WDT_STG2 0x00000003
|
||||
#define TIMERS_WDT_STG2_S 25
|
||||
#define TIMERS_WDT_STG3 0x00000003
|
||||
#define TIMERS_WDT_STG3_S 23
|
||||
#define TIMERS_WDT_EDGE_INT_EN (BIT(22))
|
||||
#define TIMERS_WDT_EDGE_INT_EN_S 22
|
||||
#define TIMERS_WDT_LEVEL_INT_EN (BIT(21))
|
||||
#define TIMERS_WDT_LEVEL_INT_EN_S 21
|
||||
#define TIMERS_WDT_CPU_RESET_LENGTH 0x00000007
|
||||
#define TIMERS_WDT_CPU_RESET_LENGTH_S 18
|
||||
#define TIMERS_WDT_SYS_RESET_LENGTH 0x00000007
|
||||
#define TIMERS_WDT_SYS_RESET_LENGTH_S 15
|
||||
#define TIMERS_WDT_FLASHBOOT_MOD_EN (BIT(14))
|
||||
#define TIMERS_WDT_FLASHBOOT_MOD_EN_S 14
|
||||
|
||||
#define WDTCONFIG1 (DR_REG_TIMERS_BASE + 0x004c)
|
||||
#define TIMERS_WDT_CLK_PRESCALE 0x0000FFFF
|
||||
#define TIMERS_WDT_CLK_PRESCALE_S 16
|
||||
|
||||
#define WDTCONFIG2 (DR_REG_TIMERS_BASE + 0x0050)
|
||||
#define TIMERS_WDT_STG0_HOLD 0xFFFFFFFF
|
||||
#define TIMERS_WDT_STG0_HOLD_S 0
|
||||
|
||||
#define WDTCONFIG3 (DR_REG_TIMERS_BASE + 0x0054)
|
||||
#define TIMERS_WDT_STG1_HOLD 0xFFFFFFFF
|
||||
#define TIMERS_WDT_STG1_HOLD_S 0
|
||||
|
||||
#define WDTCONFIG4 (DR_REG_TIMERS_BASE + 0x0058)
|
||||
#define TIMERS_WDT_STG2_HOLD 0xFFFFFFFF
|
||||
#define TIMERS_WDT_STG2_HOLD_S 0
|
||||
|
||||
#define WDTCONFIG5 (DR_REG_TIMERS_BASE + 0x005c)
|
||||
#define TIMERS_WDT_STG3_HOLD 0xFFFFFFFF
|
||||
#define TIMERS_WDT_STG3_HOLD_S 0
|
||||
|
||||
#define WDTFEED (DR_REG_TIMERS_BASE + 0x0060)
|
||||
#define TIMERS_WDT_FEED 0xFFFFFFFF
|
||||
#define TIMERS_WDT_FEED_S 0
|
||||
|
||||
#define WDTWPROTECT (DR_REG_TIMERS_BASE + 0x0064)
|
||||
#define TIMERS_WDT_WKEY 0xFFFFFFFF
|
||||
#define TIMERS_WDT_WKEY_S 0
|
||||
|
||||
#define RTCCALICFG (DR_REG_TIMERS_BASE + 0x0068)
|
||||
#define TIMERS_RTC_CALI_START (BIT(31))
|
||||
#define TIMERS_RTC_CALI_START_S 31
|
||||
#define TIMERS_RTC_CALI_MAX 0x00007FFF
|
||||
#define TIMERS_RTC_CALI_MAX_S 16
|
||||
#define TIMERS_RTC_CALI_RDY (BIT(15))
|
||||
#define TIMERS_RTC_CALI_RDY_S 15
|
||||
#define TIMERS_RTC_CALI_CLK_SEL 0x00000003
|
||||
#define TIMERS_RTC_CALI_CLK_SEL_S 13
|
||||
#define TIMERS_RTC_CALI_START_CYCLING (BIT(12))
|
||||
#define TIMERS_RTC_CALI_START_CYCLING_S 12
|
||||
|
||||
#define RTCCALICFG1 (DR_REG_TIMERS_BASE + 0x006c)
|
||||
#define TIMERS_RTC_CALI_VALUE 0x01FFFFFF
|
||||
#define TIMERS_RTC_CALI_VALUE_S 7
|
||||
|
||||
#define LACTCONFIG (DR_REG_TIMERS_BASE + 0x0070)
|
||||
#define TIMERS_LACT_EN (BIT(31))
|
||||
#define TIMERS_LACT_EN_S 31
|
||||
#define TIMERS_LACT_INCREASE (BIT(30))
|
||||
#define TIMERS_LACT_INCREASE_S 30
|
||||
#define TIMERS_LACT_AUTORELOAD (BIT(29))
|
||||
#define TIMERS_LACT_AUTORELOAD_S 29
|
||||
#define TIMERS_LACT_DIVIDER 0x0000FFFF
|
||||
#define TIMERS_LACT_DIVIDER_S 13
|
||||
#define TIMERS_LACT_EDGE_INT_EN (BIT(12))
|
||||
#define TIMERS_LACT_EDGE_INT_EN_S 12
|
||||
#define TIMERS_LACT_LEVEL_INT_EN (BIT(11))
|
||||
#define TIMERS_LACT_LEVEL_INT_EN_S 11
|
||||
#define TIMERS_LACT_ALARM_EN (BIT(10))
|
||||
#define TIMERS_LACT_ALARM_EN_S 10
|
||||
#define TIMERS_LACT_LAC_EN (BIT(9))
|
||||
#define TIMERS_LACT_LAC_EN_S 9
|
||||
#define TIMERS_LACT_CPST_EN (BIT(8))
|
||||
#define TIMERS_LACT_CPST_EN_S 8
|
||||
#define TIMERS_LACT_RTC_ONLY (BIT(7))
|
||||
#define TIMERS_LACT_RTC_ONLY_S 7
|
||||
|
||||
#define LACTRTC (DR_REG_TIMERS_BASE + 0x0074)
|
||||
#define TIMERS_LACT_RTC_STEP_LEN 0x03FFFFFF
|
||||
#define TIMERS_LACT_RTC_STEP_LEN_S 6
|
||||
|
||||
#define LACTLO (DR_REG_TIMERS_BASE + 0x0078)
|
||||
#define TIMERS_LACT_LO 0xFFFFFFFF
|
||||
#define TIMERS_LACT_LO_S 0
|
||||
|
||||
#define LACTHI (DR_REG_TIMERS_BASE + 0x007c)
|
||||
#define TIMERS_LACT_HI 0xFFFFFFFF
|
||||
#define TIMERS_LACT_HI_S 0
|
||||
|
||||
#define LACTUPDATE (DR_REG_TIMERS_BASE + 0x0080)
|
||||
#define TIMERS_LACT_UPDATE 0xFFFFFFFF
|
||||
#define TIMERS_LACT_UPDATE_S 0
|
||||
|
||||
#define LACTALARMLO (DR_REG_TIMERS_BASE + 0x0084)
|
||||
#define TIMERS_LACT_ALARM_LO 0xFFFFFFFF
|
||||
#define TIMERS_LACT_ALARM_LO_S 0
|
||||
|
||||
#define LACTALARMHI (DR_REG_TIMERS_BASE + 0x0088)
|
||||
#define TIMERS_LACT_ALARM_HI 0xFFFFFFFF
|
||||
#define TIMERS_LACT_ALARM_HI_S 0
|
||||
|
||||
#define LACTLOADLO (DR_REG_TIMERS_BASE + 0x008c)
|
||||
#define TIMERS_LACT_LOAD_LO 0xFFFFFFFF
|
||||
#define TIMERS_LACT_LOAD_LO_S 0
|
||||
|
||||
#define LACTLOADHI (DR_REG_TIMERS_BASE + 0x0090)
|
||||
#define TIMERS_LACT_LOAD_HI 0xFFFFFFFF
|
||||
#define TIMERS_LACT_LOAD_HI_S 0
|
||||
|
||||
#define LACTLOAD (DR_REG_TIMERS_BASE + 0x0094)
|
||||
#define TIMERS_LACT_LOAD 0xFFFFFFFF
|
||||
#define TIMERS_LACT_LOAD_S 0
|
||||
|
||||
#define INT_ENA_TIMERS (DR_REG_TIMERS_BASE + 0x0098)
|
||||
#define TIMERS_LACT_INT_ENA (BIT(3))
|
||||
#define TIMERS_LACT_INT_ENA_S 3
|
||||
#define TIMERS_WDT_INT_ENA (BIT(2))
|
||||
#define TIMERS_WDT_INT_ENA_S 2
|
||||
#define TIMERS_T1_INT_ENA (BIT(1))
|
||||
#define TIMERS_T1_INT_ENA_S 1
|
||||
#define TIMERS_T0_INT_ENA (BIT(0))
|
||||
#define TIMERS_T0_INT_ENA_S 0
|
||||
|
||||
#define INT_RAW_TIMERS (DR_REG_TIMERS_BASE + 0x009c)
|
||||
#define TIMERS_LACT_INT_RAW (BIT(3))
|
||||
#define TIMERS_LACT_INT_RAW_S 3
|
||||
#define TIMERS_WDT_INT_RAW (BIT(2))
|
||||
#define TIMERS_WDT_INT_RAW_S 2
|
||||
#define TIMERS_T1_INT_RAW (BIT(1))
|
||||
#define TIMERS_T1_INT_RAW_S 1
|
||||
#define TIMERS_T0_INT_RAW (BIT(0))
|
||||
#define TIMERS_T0_INT_RAW_S 0
|
||||
|
||||
#define INT_ST_TIMERS (DR_REG_TIMERS_BASE + 0x00a0)
|
||||
#define TIMERS_LACT_INT_ST (BIT(3))
|
||||
#define TIMERS_LACT_INT_ST_S 3
|
||||
#define TIMERS_WDT_INT_ST (BIT(2))
|
||||
#define TIMERS_WDT_INT_ST_S 2
|
||||
#define TIMERS_T1_INT_ST (BIT(1))
|
||||
#define TIMERS_T1_INT_ST_S 1
|
||||
#define TIMERS_T0_INT_ST (BIT(0))
|
||||
#define TIMERS_T0_INT_ST_S 0
|
||||
|
||||
#define INT_CLR_TIMERS (DR_REG_TIMERS_BASE + 0x00a4)
|
||||
#define TIMERS_LACT_INT_CLR (BIT(3))
|
||||
#define TIMERS_LACT_INT_CLR_S 3
|
||||
#define TIMERS_WDT_INT_CLR (BIT(2))
|
||||
#define TIMERS_WDT_INT_CLR_S 2
|
||||
#define TIMERS_T1_INT_CLR (BIT(1))
|
||||
#define TIMERS_T1_INT_CLR_S 1
|
||||
#define TIMERS_T0_INT_CLR (BIT(0))
|
||||
#define TIMERS_T0_INT_CLR_S 0
|
||||
|
||||
#define NTIMERS_DATE (DR_REG_TIMERS_BASE + 0x00f8)
|
||||
#define TIMERS_NTIMERS_DATE 0x0FFFFFFF
|
||||
#define TIMERS_NTIMERS_DATE_S 0
|
||||
#define TIMERS_NTIMERS_DATE_VERSION 0x1604290
|
||||
|
||||
#define REGCLK (DR_REG_TIMERS_BASE + 0x00fc)
|
||||
#define TIMERS_CLK_EN (BIT(31))
|
||||
#define TIMERS_CLK_EN_S 31
|
||||
|
||||
#endif /* _SOC_TIMER_REG_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,350 @@
|
||||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_UHCI0_REG_H_
|
||||
#define _SOC_UHCI0_REG_H_
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define UHCI0_CONF0 ( DR_REG_UHCI0_BASE + 0x0)
|
||||
#define UHCI0_UART_RX_BRK_EOF_EN (BIT(22))
|
||||
#define UHCI0_CLK_EN (BIT(21))
|
||||
#define UHCI0_ENCODE_CRC_EN (BIT(20))
|
||||
#define UHCI0_LEN_EOF_EN (BIT(19))
|
||||
#define UHCI0_UART_IDLE_EOF_EN (BIT(18))
|
||||
#define UHCI0_CRC_REC_EN (BIT(17))
|
||||
#define UHCI0_HEAD_EN (BIT(16))
|
||||
#define UHCI0_SEPER_EN (BIT(15))
|
||||
#define UHCI0_MEM_TRANS_EN (BIT(14))
|
||||
#define UHCI0_RX_DATA_BURST_EN (BIT(13))
|
||||
#define UHCI0_TXDSCR_BURST_EN (BIT(12))
|
||||
#define UHCI0_RXDSCR_BURST_EN (BIT(11))
|
||||
#define UHCI0_UART1_CE (BIT(10))
|
||||
#define UHCI0_UART0_CE (BIT(9))
|
||||
#define UHCI0_TO_EOF_MODE (BIT(8))
|
||||
#define UHCI0_RX_NO_RESTART_CLR (BIT(7))
|
||||
#define UHCI0_RX_AUTO_WRBACK (BIT(6))
|
||||
#define UHCI0_RX_LOOP_TEST (BIT(5))
|
||||
#define UHCI0_TX_LOOP_TEST (BIT(4))
|
||||
#define UHCI0_AHBM_RST (BIT(3))
|
||||
#define UHCI0_AHBM_FIFO_RST (BIT(2))
|
||||
#define UHCI0_RX_RST (BIT(1))
|
||||
#define UHCI0_TX_RST (BIT(0))
|
||||
|
||||
#define UHCI0_INT_RAW ( DR_REG_UHCI0_BASE + 0x4)
|
||||
#define UHCI0_UHCI_SEND_A_Q_INT_RAW (BIT(15))
|
||||
#define UHCI0_UHCI_SEND_S_Q_INT_RAW (BIT(14))
|
||||
#define UHCI0_UHCI_TO_TOTAL_EOF_INT_RAW (BIT(13))
|
||||
#define UHCI0_UHCI_RXLINK_EOF_ERR_INT_RAW (BIT(12))
|
||||
#define UHCI0_UHCI_TX_DSCR_EMPTY_INT_RAW (BIT(11))
|
||||
#define UHCI0_UHCI_RX_DSCR_ERR_INT_RAW (BIT(10))
|
||||
#define UHCI0_UHCI_TX_DSCR_ERR_INT_RAW (BIT(9))
|
||||
#define UHCI0_UHCI_TO_EOF_INT_RAW (BIT(8))
|
||||
#define UHCI0_UHCI_RX_DONE_INT_RAW (BIT(7))
|
||||
#define UHCI0_UHCI_FROM_ERR_EOF_INT_RAW (BIT(6))
|
||||
#define UHCI0_UHCI_FROM_SUC_EOF_INT_RAW (BIT(5))
|
||||
#define UHCI0_UHCI_TX_DONE_INT_RAW (BIT(4))
|
||||
#define UHCI0_UHCI_TX_HUNG_INT_RAW (BIT(3))
|
||||
#define UHCI0_UHCI_RX_HUNG_INT_RAW (BIT(2))
|
||||
#define UHCI0_UHCI_TX_START_INT_RAW (BIT(1))
|
||||
#define UHCI0_UHCI_RX_START_INT_RAW (BIT(0))
|
||||
|
||||
#define UHCI0_INT_ST ( DR_REG_UHCI0_BASE + 0x8)
|
||||
#define UHCI0_UHCI_SEND_A_Q_INT_ST (BIT(15))
|
||||
#define UHCI0_UHCI_SEND_S_Q_INT_ST (BIT(14))
|
||||
#define UHCI0_UHCI_TO_TOTAL_EOF_INT_ST (BIT(13))
|
||||
#define UHCI0_UHCI_RXLINK_EOF_ERR_INT_ST (BIT(12))
|
||||
#define UHCI0_UHCI_TX_DSCR_EMPTY_INT_ST (BIT(11))
|
||||
#define UHCI0_UHCI_RX_DSCR_ERR_INT_ST (BIT(10))
|
||||
#define UHCI0_UHCI_TX_DSCR_ERR_INT_ST (BIT(9))
|
||||
#define UHCI0_UHCI_TO_EOF_INT_ST (BIT(8))
|
||||
#define UHCI0_UHCI_RX_DONE_INT_ST (BIT(7))
|
||||
#define UHCI0_UHCI_FROM_ERR_EOF_INT_ST (BIT(6))
|
||||
#define UHCI0_UHCI_FROM_SUC_EOF_INT_ST (BIT(5))
|
||||
#define UHCI0_UHCI_TX_DONE_INT_ST (BIT(4))
|
||||
#define UHCI0_UHCI_TX_HUNG_INT_ST (BIT(3))
|
||||
#define UHCI0_UHCI_RX_HUNG_INT_ST (BIT(2))
|
||||
#define UHCI0_UHCI_TX_START_INT_ST (BIT(1))
|
||||
#define UHCI0_UHCI_RX_START_INT_ST (BIT(0))
|
||||
|
||||
#define UHCI0_INT_ENA ( DR_REG_UHCI0_BASE + 0xC)
|
||||
#define UHCI0_UHCI_SEND_A_Q_INT_ENA (BIT(15))
|
||||
#define UHCI0_UHCI_SEND_S_Q_INT_ENA (BIT(14))
|
||||
#define UHCI0_UHCI_TO_TOTAL_EOF_INT_ENA (BIT(13))
|
||||
#define UHCI0_UHCI_RXLINK_EOF_ERR_INT_ENA (BIT(12))
|
||||
#define UHCI0_UHCI_TX_DSCR_EMPTY_INT_ENA (BIT(11))
|
||||
#define UHCI0_UHCI_RX_DSCR_ERR_INT_ENA (BIT(10))
|
||||
#define UHCI0_UHCI_TX_DSCR_ERR_INT_ENA (BIT(9))
|
||||
#define UHCI0_UHCI_TO_EOF_INT_ENA (BIT(8))
|
||||
#define UHCI0_UHCI_RX_DONE_INT_ENA (BIT(7))
|
||||
#define UHCI0_UHCI_FROM_ERR_EOF_INT_ENA (BIT(6))
|
||||
#define UHCI0_UHCI_FROM_SUC_EOF_INT_ENA (BIT(5))
|
||||
#define UHCI0_UHCI_TX_DONE_INT_ENA (BIT(4))
|
||||
#define UHCI0_UHCI_TX_HUNG_INT_ENA (BIT(3))
|
||||
#define UHCI0_UHCI_RX_HUNG_INT_ENA (BIT(2))
|
||||
#define UHCI0_UHCI_TX_START_INT_ENA (BIT(1))
|
||||
#define UHCI0_UHCI_RX_START_INT_ENA (BIT(0))
|
||||
|
||||
#define UHCI0_INT_CLR ( DR_REG_UHCI0_BASE + 0x10)
|
||||
#define UHCI0_SEND_A_REG_Q_INT_CLR (BIT(15))
|
||||
#define UHCI0_SEND_S_REG_Q_INT_CLR (BIT(14))
|
||||
#define UHCI0_TO_TOTAL_EOF_INT_CLR (BIT(13))
|
||||
#define UHCI0_RXLINK_EOF_ERR_INT_CLR (BIT(12))
|
||||
#define UHCI0_TX_DSCR_EMPTY_INT_CLR (BIT(11))
|
||||
#define UHCI0_RX_DSCR_ERR_INT_CLR (BIT(10))
|
||||
#define UHCI0_TX_DSCR_ERR_INT_CLR (BIT(9))
|
||||
#define UHCI0_TO_EOF_INT_CLR (BIT(8))
|
||||
#define UHCI0_RX_DONE_INT_CLR (BIT(7))
|
||||
#define UHCI0_FROM_ERR_EOF_INT_CLR (BIT(6))
|
||||
#define UHCI0_FROM_SUC_EOF_INT_CLR (BIT(5))
|
||||
#define UHCI0_TX_DONE_INT_CLR (BIT(4))
|
||||
#define UHCI0_TX_HUNG_INT_CLR (BIT(3))
|
||||
#define UHCI0_RX_HUNG_INT_CLR (BIT(2))
|
||||
#define UHCI0_TX_START_INT_CLR (BIT(1))
|
||||
#define UHCI0_RX_START_INT_CLR (BIT(0))
|
||||
|
||||
#define UHCI0_RX_STATUS ( DR_REG_UHCI0_BASE + 0x14)
|
||||
#define UHCI0_RX_EMPTY (BIT(1))
|
||||
#define UHCI0_RX_FULL (BIT(0))
|
||||
|
||||
#define UHCI0_RXFIFO_PUSH ( DR_REG_UHCI0_BASE + 0x18)
|
||||
#define UHCI0_RXFIFO_PUSH_EN (BIT(16))
|
||||
#define UHCI0_RXFIFO_WDATA 0x000001FF
|
||||
#define UHCI0_RXFIFO_WDATA_S 0
|
||||
|
||||
#define UHCI0_TX_STATUS ( DR_REG_UHCI0_BASE + 0x1C)
|
||||
#define UHCI0_UHCI_RX_ERR_CAUSE 0x00000007
|
||||
#define UHCI0_UHCI_RX_ERR_CAUSE_S 4
|
||||
#define UHCI0_TX_EMPTY (BIT(1))
|
||||
#define UHCI0_TX_FULL (BIT(0))
|
||||
|
||||
#define UHCI0_TX_POP ( DR_REG_UHCI0_BASE + 0x20)
|
||||
#define UHCI0_TXFIFO_POP (BIT(16))
|
||||
#define UHCI0_TXFIFO_RDATA 0x00000FFF
|
||||
#define UHCI0_TXFIFO_RDATA_S 0
|
||||
|
||||
#define UHCI0_RX_LINK ( DR_REG_UHCI0_BASE + 0x24)
|
||||
#define UHCI0_UHCI_RXLINK_PARK (BIT(31))
|
||||
#define UHCI0_RXLINK_RESTART (BIT(30))
|
||||
#define UHCI0_RXLINK_START (BIT(29))
|
||||
#define UHCI0_RXLINK_STOP (BIT(28))
|
||||
#define UHCI0_RXLINK_ADDR 0x000FFFFF
|
||||
#define UHCI0_RXLINK_ADDR_S 0
|
||||
|
||||
#define UHCI0_TX_LINK ( DR_REG_UHCI0_BASE + 0x28)
|
||||
#define UHCI0_UHCI_TXLINK_PARK (BIT(31))
|
||||
#define UHCI0_TXLINK_RESTART (BIT(30))
|
||||
#define UHCI0_TXLINK_START (BIT(29))
|
||||
#define UHCI0_TXLINK_STOP (BIT(28))
|
||||
#define UHCI0_TXLINK_AUTO_RET (BIT(20))
|
||||
#define UHCI0_TXLINK_ADDR 0x000FFFFF
|
||||
#define UHCI0_TXLINK_ADDR_S 0
|
||||
|
||||
#define UHCI0_CONF1 ( DR_REG_UHCI0_BASE + 0x2C)
|
||||
#define UHCI0_SW_START (BIT(8))
|
||||
#define UHCI0_WAIT_SW_START (BIT(7))
|
||||
#define UHCI0_CHECK_OWNER (BIT(6))
|
||||
#define UHCI0_TX_ACK_NUM_RE (BIT(5))
|
||||
#define UHCI0_TX_CHECK_SUM_RE (BIT(4))
|
||||
#define UHCI0_SAVE_HEAD (BIT(3))
|
||||
#define UHCI0_CRC_DISABLE (BIT(2))
|
||||
#define UHCI0_CHECK_SEQ_EN (BIT(1))
|
||||
#define UHCI0_CHECK_SUM_EN (BIT(0))
|
||||
|
||||
#define UHCI0_STATE0 ( DR_REG_UHCI0_BASE + 0x30)
|
||||
#define UHCI0_UHCI_STATE0 0xFFFFFFFF
|
||||
#define UHCI0_UHCI_STATE0_S 0
|
||||
|
||||
#define UHCI0_STATE1 ( DR_REG_UHCI0_BASE + 0x34)
|
||||
#define UHCI0_UHCI_STATE1 0xFFFFFFFF
|
||||
#define UHCI0_UHCI_STATE1_S 0
|
||||
|
||||
#define UHCI0_RX_EOF_DES_ADDR ( DR_REG_UHCI0_BASE + 0x38)
|
||||
#define UHCI0_TO_EOF_DES_ADDR 0xFFFFFFFF
|
||||
#define UHCI0_TO_EOF_DES_ADDR_S 0
|
||||
|
||||
#define UHCI0_TX_SUC_EOF_DES_ADDR ( DR_REG_UHCI0_BASE + 0x3C)
|
||||
#define UHCI0_FROM_SUC_EOF_DES_ADDR 0xFFFFFFFF
|
||||
#define UHCI0_FROM_SUC_EOF_DES_ADDR_S 0
|
||||
|
||||
#define UHCI0_TX_ERR_EOF_DES_ADDR ( DR_REG_UHCI0_BASE + 0x40)
|
||||
#define UHCI0_FROM_ERR_EOF_DES_ADDR 0xFFFFFFFF
|
||||
#define UHCI0_FROM_ERR_EOF_DES_ADDR_S 0
|
||||
|
||||
#define UHCI0_RX_EOF_BFR_DES_ADDR ( DR_REG_UHCI0_BASE + 0x44)
|
||||
#define UHCI0_TO_EOF_BFR_DES_ADDR 0xFFFFFFFF
|
||||
#define UHCI0_TO_EOF_BFR_DES_ADDR_S 0
|
||||
|
||||
#define UHCI0_AHB_TEST ( DR_REG_UHCI0_BASE + 0x48)
|
||||
#define UHCI0_AHB_TESTADDR 0x00000003
|
||||
#define UHCI0_AHB_TESTADDR_S 4
|
||||
#define UHCI0_AHB_TESTMODE 0x00000007
|
||||
#define UHCI0_AHB_TESTMODE_S 0
|
||||
|
||||
#define UHCI0_TX_DSCR ( DR_REG_UHCI0_BASE + 0x4C)
|
||||
#define UHCI0_TXLINK_DSCR 0xFFFFFFFF
|
||||
#define UHCI0_TXLINK_DSCR_S 0
|
||||
|
||||
#define UHCI0_TX_DSCR_BF0 ( DR_REG_UHCI0_BASE + 0x50)
|
||||
#define UHCI0_TXLINK_DSCR_BF0 0xFFFFFFFF
|
||||
#define UHCI0_TXLINK_DSCR_BF0_S 0
|
||||
|
||||
#define UHCI0_TX_DSCR_BF1 ( DR_REG_UHCI0_BASE + 0x54)
|
||||
#define UHCI0_TXLINK_DSCR_BF1 0xFFFFFFFF
|
||||
#define UHCI0_TXLINK_DSCR_BF1_S 0
|
||||
|
||||
#define UHCI0_RX_DSCR ( DR_REG_UHCI0_BASE + 0x58)
|
||||
#define UHCI0_RXLINK_DSCR 0xFFFFFFFF
|
||||
#define UHCI0_RXLINK_DSCR_S 0
|
||||
|
||||
#define UHCI0_RX_DSCR_BF0 ( DR_REG_UHCI0_BASE + 0x5C)
|
||||
#define UHCI0_RXLINK_DSCR_BF0 0xFFFFFFFF
|
||||
#define UHCI0_RXLINK_DSCR_BF0_S 0
|
||||
|
||||
#define UHCI0_RX_DSCR_BF1 ( DR_REG_UHCI0_BASE + 0x60)
|
||||
#define UHCI0_RXLINK_DSCR_BF1 0xFFFFFFFF
|
||||
#define UHCI0_RXLINK_DSCR_BF1_S 0
|
||||
|
||||
#define UHCI0_ESCAPE_CONF ( DR_REG_UHCI0_BASE + 0x64)
|
||||
#define UHCI0_RX_13_ESC_EN (BIT(7))
|
||||
#define UHCI0_RX_11_ESC_EN (BIT(6))
|
||||
#define UHCI0_RX_DB_ESC_EN (BIT(5))
|
||||
#define UHCI0_RX_C0_ESC_EN (BIT(4))
|
||||
#define UHCI0_TX_13_ESC_EN (BIT(3))
|
||||
#define UHCI0_TX_11_ESC_EN (BIT(2))
|
||||
#define UHCI0_TX_DB_ESC_EN (BIT(1))
|
||||
#define UHCI0_TX_C0_ESC_EN (BIT(0))
|
||||
|
||||
#define UHCI0_HUNG_CONF ( DR_REG_UHCI0_BASE + 0x68)
|
||||
#define UHCI0_RXFIFO_TIMEOUT_ENA (BIT(23))
|
||||
#define UHCI0_RXFIFO_TIMEOUT_SHIFT 0x00000007
|
||||
#define UHCI0_RXFIFO_TIMEOUT_SHIFT_S 20
|
||||
#define UHCI0_RXFIFO_TIMEOUT 0x000000FF
|
||||
#define UHCI0_RXFIFO_TIMEOUT_S 12
|
||||
#define UHCI0_TXFIFO_TIMEOUT_ENA (BIT(11))
|
||||
#define UHCI0_TXFIFO_TIMEOUT_SHIFT 0x00000007
|
||||
#define UHCI0_TXFIFO_TIMEOUT_SHIFT_S 8
|
||||
#define UHCI0_TXFIFO_TIMEOUT 0x000000FF
|
||||
#define UHCI0_TXFIFO_TIMEOUT_S 0
|
||||
|
||||
#define UHCI0_ACK_NUM ( DR_REG_UHCI0_BASE + 0x6C)
|
||||
|
||||
#define UHCI0_RX_HEAD ( DR_REG_UHCI0_BASE + 0x70)
|
||||
#define UHCI0_UHCI_RX_HEAD 0xFFFFFFFF
|
||||
#define UHCI0_UHCI_RX_HEAD_S 0
|
||||
|
||||
#define UHCI0_QUICK_SENT ( DR_REG_UHCI0_BASE + 0x74)
|
||||
#define UHCI0_ALWAYS_SEND_EN (BIT(7))
|
||||
#define UHCI0_ALWAYS_SEND_NUM 0x00000007
|
||||
#define UHCI0_ALWAYS_SEND_NUM_S 4
|
||||
#define UHCI0_SINGLE_SEND_EN (BIT(3))
|
||||
#define UHCI0_SINGLE_SEND_NUM 0x00000007
|
||||
#define UHCI0_SINGLE_SEND_NUM_S 0
|
||||
|
||||
#define UHCI0_REG_Q0_WORD0 ( DR_REG_UHCI0_BASE + 0x78)
|
||||
#define UHCI0_SEND_Q0_WORD0 0xFFFFFFFF
|
||||
#define UHCI0_SEND_Q0_WORD0_S 0
|
||||
|
||||
#define UHCI0_REG_Q0_WORD1 ( DR_REG_UHCI0_BASE + 0x7C)
|
||||
#define UHCI0_SEND_Q0_WORD1 0xFFFFFFFF
|
||||
#define UHCI0_SEND_Q0_WORD1_S 0
|
||||
|
||||
#define UHCI0_REG_Q1_WORD0 ( DR_REG_UHCI0_BASE + 0x80)
|
||||
#define UHCI0_SEND_Q1_WORD0 0xFFFFFFFF
|
||||
#define UHCI0_SEND_Q1_WORD0_S 0
|
||||
|
||||
#define UHCI0_REG_Q1_WORD1 ( DR_REG_UHCI0_BASE + 0x84)
|
||||
#define UHCI0_SEND_Q1_WORD1 0xFFFFFFFF
|
||||
#define UHCI0_SEND_Q1_WORD1_S 0
|
||||
|
||||
#define UHCI0_REG_Q2_WORD0 ( DR_REG_UHCI0_BASE + 0x88)
|
||||
#define UHCI0_SEND_Q2_WORD0 0xFFFFFFFF
|
||||
#define UHCI0_SEND_Q2_WORD0_S 0
|
||||
|
||||
#define UHCI0_REG_Q2_WORD1 ( DR_REG_UHCI0_BASE + 0x8C)
|
||||
#define UHCI0_SEND_Q2_WORD1 0xFFFFFFFF
|
||||
#define UHCI0_SEND_Q2_WORD1_S 0
|
||||
|
||||
#define UHCI0_REG_Q3_WORD0 ( DR_REG_UHCI0_BASE + 0x90)
|
||||
#define UHCI0_SEND_Q3_WORD0 0xFFFFFFFF
|
||||
#define UHCI0_SEND_Q3_WORD0_S 0
|
||||
|
||||
#define UHCI0_REG_Q3_WORD1 ( DR_REG_UHCI0_BASE + 0x94)
|
||||
#define UHCI0_SEND_Q3_WORD1 0xFFFFFFFF
|
||||
#define UHCI0_SEND_Q3_WORD1_S 0
|
||||
|
||||
#define UHCI0_REG_Q4_WORD0 ( DR_REG_UHCI0_BASE + 0x98)
|
||||
#define UHCI0_SEND_Q4_WORD0 0xFFFFFFFF
|
||||
#define UHCI0_SEND_Q4_WORD0_S 0
|
||||
|
||||
#define UHCI0_REG_Q4_WORD1 ( DR_REG_UHCI0_BASE + 0x9C)
|
||||
#define UHCI0_SEND_Q4_WORD1 0xFFFFFFFF
|
||||
#define UHCI0_SEND_Q4_WORD1_S 0
|
||||
|
||||
#define UHCI0_REG_Q5_WORD0 ( DR_REG_UHCI0_BASE + 0xA0)
|
||||
#define UHCI0_SEND_Q5_WORD0 0xFFFFFFFF
|
||||
#define UHCI0_SEND_Q5_WORD0_S 0
|
||||
|
||||
#define UHCI0_REG_Q5_WORD1 ( DR_REG_UHCI0_BASE + 0xA4)
|
||||
#define UHCI0_SEND_Q5_WORD1 0xFFFFFFFF
|
||||
#define UHCI0_SEND_Q5_WORD1_S 0
|
||||
|
||||
#define UHCI0_REG_Q6_WORD0 ( DR_REG_UHCI0_BASE + 0xA8)
|
||||
#define UHCI0_SEND_Q6_WORD0 0xFFFFFFFF
|
||||
#define UHCI0_SEND_Q6_WORD0_S 0
|
||||
|
||||
#define UHCI0_REG_Q6_WORD1 ( DR_REG_UHCI0_BASE + 0xAC)
|
||||
#define UHCI0_SEND_Q6_WORD1 0xFFFFFFFF
|
||||
#define UHCI0_SEND_Q6_WORD1_S 0
|
||||
|
||||
#define UHCI0_ESC_CONF0 ( DR_REG_UHCI0_BASE + 0xB0)
|
||||
#define UHCI0_SEPER_ESC_CHAR1 0x000000FF
|
||||
#define UHCI0_SEPER_ESC_CHAR1_S 16
|
||||
#define UHCI0_SEPER_ESC_CHAR0 0x000000FF
|
||||
#define UHCI0_SEPER_ESC_CHAR0_S 8
|
||||
#define UHCI0_SEPER_CHAR 0x000000FF
|
||||
#define UHCI0_SEPER_CHAR_S 0
|
||||
|
||||
#define UHCI0_ESC_CONF1 ( DR_REG_UHCI0_BASE + 0xB4)
|
||||
#define UHCI0_ESC_SEQ0_CHAR1 0x000000FF
|
||||
#define UHCI0_ESC_SEQ0_CHAR1_S 16
|
||||
#define UHCI0_ESC_SEQ0_CHAR0 0x000000FF
|
||||
#define UHCI0_ESC_SEQ0_CHAR0_S 8
|
||||
#define UHCI0_ESC_SEQ0 0x000000FF
|
||||
#define UHCI0_ESC_SEQ0_S 0
|
||||
|
||||
#define UHCI0_ESC_CONF2 ( DR_REG_UHCI0_BASE + 0xB8)
|
||||
#define UHCI0_ESC_SEQ1_CHAR1 0x000000FF
|
||||
#define UHCI0_ESC_SEQ1_CHAR1_S 16
|
||||
#define UHCI0_ESC_SEQ1_CHAR0 0x000000FF
|
||||
#define UHCI0_ESC_SEQ1_CHAR0_S 8
|
||||
#define UHCI0_ESC_SEQ1 0x000000FF
|
||||
#define UHCI0_ESC_SEQ1_S 0
|
||||
|
||||
#define UHCI0_ESC_CONF3 ( DR_REG_UHCI0_BASE + 0xBC)
|
||||
#define UHCI0_ESC_SEQ2_CHAR1 0x000000FF
|
||||
#define UHCI0_ESC_SEQ2_CHAR1_S 16
|
||||
#define UHCI0_ESC_SEQ2_CHAR0 0x000000FF
|
||||
#define UHCI0_ESC_SEQ2_CHAR0_S 8
|
||||
#define UHCI0_ESC_SEQ2 0x000000FF
|
||||
#define UHCI0_ESC_SEQ2_S 0
|
||||
|
||||
#define UHCI0_PKT_THRES ( DR_REG_UHCI0_BASE + 0xC0)
|
||||
#define UHCI0_PKT_THRS 0x00001FFF
|
||||
#define UHCI0_PKT_THRS_S 0
|
||||
|
||||
#define UHCI0_DATA ( DR_REG_UHCI0_BASE + 0xFC)
|
||||
#define UHCI0_UHCI_DATA 0xFFFFFFFF
|
||||
#define UHCI0_UHCI_DATA_S 0
|
||||
|
||||
#endif /* _SOC_UHCI0_REG_H_ */
|
||||
Reference in New Issue
Block a user