Initial public version
This commit is contained in:
Ivan Grokhotkov
Executable
+28
@@ -0,0 +1,28 @@
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/* This header is supposed to be obtained from <board>/xtensa/board.h
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using a -I directive passed to the compiler. */
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#error "Unspecified board. Missing -I directive to select supported Xtensa board, usually -I XTENSA_TOOLS_ROOT/xtensa-elf/include/xtensa/<BOARD> (XTENSA_TOOLS_ROOT is root of Xtensa Tools install, see xt-run --show-config=xttools)"
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/*
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* Copyright (c) 2013 Tensilica Inc.
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*
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||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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Executable
+1758
File diff suppressed because it is too large
Load Diff
Executable
+962
@@ -0,0 +1,962 @@
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/*
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* xtensa/cacheasm.h -- assembler-specific cache related definitions
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* that depend on CORE configuration
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*
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* This file is logically part of xtensa/coreasm.h ,
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* but is kept separate for modularity / compilation-performance.
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*/
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/*
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* Copyright (c) 2001-2014 Cadence Design Systems, Inc.
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*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
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#ifndef XTENSA_CACHEASM_H
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#define XTENSA_CACHEASM_H
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#include <xtensa/coreasm.h>
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#include <xtensa/corebits.h>
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#include <xtensa/xtensa-xer.h>
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#include <xtensa/xtensa-versions.h>
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/*
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* This header file defines assembler macros of the form:
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* <x>cache_<func>
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* where <x> is 'i' or 'd' for instruction and data caches,
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* and <func> indicates the function of the macro.
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*
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* The following functions <func> are defined,
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* and apply only to the specified cache (I or D):
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*
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* reset
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* Resets the cache.
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*
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* sync
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* Makes sure any previous cache instructions have been completed;
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* ie. makes sure any previous cache control operations
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* have had full effect and been synchronized to memory.
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* Eg. any invalidate completed [so as not to generate a hit],
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* any writebacks or other pipelined writes written to memory, etc.
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*
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* invalidate_line (single cache line)
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* invalidate_region (specified memory range)
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* invalidate_all (entire cache)
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* Invalidates all cache entries that cache
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* data from the specified memory range.
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* NOTE: locked entries are not invalidated.
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*
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* writeback_line (single cache line)
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* writeback_region (specified memory range)
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* writeback_all (entire cache)
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* Writes back to memory all dirty cache entries
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* that cache data from the specified memory range,
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* and marks these entries as clean.
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* NOTE: on some future implementations, this might
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* also invalidate.
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* NOTE: locked entries are written back, but never invalidated.
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* NOTE: instruction caches never implement writeback.
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*
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* writeback_inv_line (single cache line)
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* writeback_inv_region (specified memory range)
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* writeback_inv_all (entire cache)
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* Writes back to memory all dirty cache entries
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* that cache data from the specified memory range,
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* and invalidates these entries (including all clean
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* cache entries that cache data from that range).
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* NOTE: locked entries are written back but not invalidated.
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* NOTE: instruction caches never implement writeback.
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*
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* lock_line (single cache line)
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* lock_region (specified memory range)
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* Prefetch and lock the specified memory range into cache.
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* NOTE: if any part of the specified memory range cannot
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* be locked, a Load/Store Error (for dcache) or Instruction
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* Fetch Error (for icache) exception occurs. These macros don't
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* do anything special (yet anyway) to handle this situation.
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*
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* unlock_line (single cache line)
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* unlock_region (specified memory range)
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* unlock_all (entire cache)
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* Unlock cache entries that cache the specified memory range.
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* Entries not already locked are unaffected.
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*
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* coherence_on
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* coherence_off
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* Turn off and on cache coherence
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*
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*/
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/*************************** GENERIC -- ALL CACHES ***************************/
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/*
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* The following macros assume the following cache size/parameter limits
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* in the current Xtensa core implementation:
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* cache size: 1024 bytes minimum
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* line size: 16 - 64 bytes
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* way count: 1 - 4
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*
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* Minimum entries per way (ie. per associativity) = 1024 / 64 / 4 = 4
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* Hence the assumption that each loop can execute four cache instructions.
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*
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* Correspondingly, the offset range of instructions is assumed able to cover
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* four lines, ie. offsets {0,1,2,3} * line_size are assumed valid for
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* both hit and indexed cache instructions. Ie. these offsets are all
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* valid: 0, 16, 32, 48, 64, 96, 128, 192 (for line sizes 16, 32, 64).
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* This is true of all original cache instructions
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* (dhi, ihi, dhwb, dhwbi, dii, iii) which have offsets
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* of 0 to 1020 in multiples of 4 (ie. 8 bits shifted by 2).
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* This is also true of subsequent cache instructions
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* (dhu, ihu, diu, iiu, diwb, diwbi, dpfl, ipfl) which have offsets
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* of 0 to 240 in multiples of 16 (ie. 4 bits shifted by 4).
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*
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* (Maximum cache size, currently 32k, doesn't affect the following macros.
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* Cache ways > MMU min page size cause aliasing but that's another matter.)
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*/
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/*
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* Macro to apply an 'indexed' cache instruction to the entire cache.
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*
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* Parameters:
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* cainst instruction/ that takes an address register parameter
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* and an offset parameter (in range 0 .. 3*linesize).
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* size size of cache in bytes
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* linesize size of cache line in bytes (always power-of-2)
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* assoc_or1 number of associativities (ways/sets) in cache
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* if all sets affected by cainst,
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* or 1 if only one set (or not all sets) of the cache
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* is affected by cainst (eg. DIWB or DIWBI [not yet ISA defined]).
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* aa, ab unique address registers (temporaries).
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* awb set to other than a0 if wb type of instruction
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* loopokay 1 allows use of zero-overhead loops, 0 does not
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* immrange range (max value) of cainst's immediate offset parameter, in bytes
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* (NOTE: macro assumes immrange allows power-of-2 number of lines)
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*/
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.macro cache_index_all cainst, size, linesize, assoc_or1, aa, ab, loopokay, maxofs, awb=a0
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// Number of indices in cache (lines per way):
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.set .Lindices, (\size / (\linesize * \assoc_or1))
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// Number of indices processed per loop iteration (max 4):
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.set .Lperloop, .Lindices
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.ifgt .Lperloop - 4
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.set .Lperloop, 4
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.endif
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// Also limit instructions per loop if cache line size exceeds immediate range:
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.set .Lmaxperloop, (\maxofs / \linesize) + 1
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.ifgt .Lperloop - .Lmaxperloop
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.set .Lperloop, .Lmaxperloop
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.endif
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// Avoid addi of 128 which takes two instructions (addmi,addi):
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.ifeq .Lperloop*\linesize - 128
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.ifgt .Lperloop - 1
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.set .Lperloop, .Lperloop / 2
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.endif
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.endif
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// \size byte cache, \linesize byte lines, \assoc_or1 way(s) affected by each \cainst.
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// XCHAL_ERRATUM_497 - don't execute using loop, to reduce the amount of added code
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.ifne (\loopokay & XCHAL_HAVE_LOOPS && !XCHAL_ERRATUM_497)
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movi \aa, .Lindices / .Lperloop // number of loop iterations
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// Possible improvement: need only loop if \aa > 1 ;
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// however \aa == 1 is highly unlikely.
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movi \ab, 0 // to iterate over cache
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loop \aa, .Lend_cachex\@
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.set .Li, 0 ; .rept .Lperloop
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\cainst \ab, .Li*\linesize
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.set .Li, .Li+1 ; .endr
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addi \ab, \ab, .Lperloop*\linesize // move to next line
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.Lend_cachex\@:
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.else
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movi \aa, (\size / \assoc_or1)
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// Possible improvement: need only loop if \aa > 1 ;
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// however \aa == 1 is highly unlikely.
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movi \ab, 0 // to iterate over cache
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.ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // don't use awb if set to a0
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movi \awb, 0
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.endif
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.Lstart_cachex\@:
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.set .Li, 0 ; .rept .Lperloop
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\cainst \ab, .Li*\linesize
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.set .Li, .Li+1 ; .endr
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.ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // do memw after 8 cainst wb instructions
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addi \awb, \awb, .Lperloop
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blti \awb, 8, .Lstart_memw\@
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memw
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movi \awb, 0
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.Lstart_memw\@:
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.endif
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addi \ab, \ab, .Lperloop*\linesize // move to next line
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bltu \ab, \aa, .Lstart_cachex\@
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.endif
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.endm
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/*
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* Macro to apply a 'hit' cache instruction to a memory region,
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* ie. to any cache entries that cache a specified portion (region) of memory.
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* Takes care of the unaligned cases, ie. may apply to one
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* more cache line than $asize / lineSize if $aaddr is not aligned.
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*
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*
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* Parameters are:
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* cainst instruction/macro that takes an address register parameter
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* and an offset parameter (currently always zero)
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* and generates a cache instruction (eg. "dhi", "dhwb", "ihi", etc.)
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* linesize_log2 log2(size of cache line in bytes)
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* addr register containing start address of region (clobbered)
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* asize register containing size of the region in bytes (clobbered)
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* askew unique register used as temporary
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* awb unique register used as temporary for erratum 497.
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*
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* Note: A possible optimization to this macro is to apply the operation
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* to the entire cache if the region exceeds the size of the cache
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* by some empirically determined amount or factor. Some experimentation
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* is required to determine the appropriate factors, which also need
|
||||
* to be tunable if required.
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*/
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.macro cache_hit_region cainst, linesize_log2, addr, asize, askew, awb=a0
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// Make \asize the number of iterations:
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extui \askew, \addr, 0, \linesize_log2 // get unalignment amount of \addr
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add \asize, \asize, \askew // ... and add it to \asize
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addi \asize, \asize, (1 << \linesize_log2) - 1 // round up!
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srli \asize, \asize, \linesize_log2
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// Iterate over region:
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.ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // don't use awb if set to a0
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movi \awb, 0
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.endif
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floopnez \asize, cacheh\@
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\cainst \addr, 0
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.ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // do memw after 8 cainst wb instructions
|
||||
addi \awb, \awb, 1
|
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blti \awb, 8, .Lstart_memw\@
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memw
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||||
movi \awb, 0
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.Lstart_memw\@:
|
||||
.endif
|
||||
addi \addr, \addr, (1 << \linesize_log2) // move to next line
|
||||
floopend \asize, cacheh\@
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||||
.endm
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||||
|
||||
|
||||
|
||||
|
||||
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||||
/*************************** INSTRUCTION CACHE ***************************/
|
||||
|
||||
|
||||
/*
|
||||
* Reset/initialize the instruction cache by simply invalidating it:
|
||||
* (need to unlock first also, if cache locking implemented):
|
||||
*
|
||||
* Parameters:
|
||||
* aa, ab unique address registers (temporaries)
|
||||
*/
|
||||
.macro icache_reset aa, ab, loopokay=0
|
||||
icache_unlock_all \aa, \ab, \loopokay
|
||||
icache_invalidate_all \aa, \ab, \loopokay
|
||||
.endm
|
||||
|
||||
|
||||
/*
|
||||
* Synchronize after an instruction cache operation,
|
||||
* to be sure everything is in sync with memory as to be
|
||||
* expected following any previous instruction cache control operations.
|
||||
*
|
||||
* Even if a config doesn't have caches, an isync is still needed
|
||||
* when instructions in any memory are modified, whether by a loader
|
||||
* or self-modifying code. Therefore, this macro always produces
|
||||
* an isync, whether or not an icache is present.
|
||||
*
|
||||
* Parameters are:
|
||||
* ar an address register (temporary) (currently unused, but may be used in future)
|
||||
*/
|
||||
.macro icache_sync ar
|
||||
isync
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Invalidate a single line of the instruction cache.
|
||||
* Parameters are:
|
||||
* ar address register that contains (virtual) address to invalidate
|
||||
* (may get clobbered in a future implementation, but not currently)
|
||||
* offset (optional) offset to add to \ar to compute effective address to invalidate
|
||||
* (note: some number of lsbits are ignored)
|
||||
*/
|
||||
.macro icache_invalidate_line ar, offset
|
||||
#if XCHAL_ICACHE_SIZE > 0
|
||||
ihi \ar, \offset // invalidate icache line
|
||||
icache_sync \ar
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Invalidate instruction cache entries that cache a specified portion of memory.
|
||||
* Parameters are:
|
||||
* astart start address (register gets clobbered)
|
||||
* asize size of the region in bytes (register gets clobbered)
|
||||
* ac unique register used as temporary
|
||||
*/
|
||||
.macro icache_invalidate_region astart, asize, ac
|
||||
#if XCHAL_ICACHE_SIZE > 0
|
||||
// Instruction cache region invalidation:
|
||||
cache_hit_region ihi, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
|
||||
icache_sync \ac
|
||||
// End of instruction cache region invalidation
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Invalidate entire instruction cache.
|
||||
*
|
||||
* Parameters:
|
||||
* aa, ab unique address registers (temporaries)
|
||||
*/
|
||||
.macro icache_invalidate_all aa, ab, loopokay=1
|
||||
#if XCHAL_ICACHE_SIZE > 0
|
||||
// Instruction cache invalidation:
|
||||
cache_index_all iii, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, XCHAL_ICACHE_WAYS, \aa, \ab, \loopokay, 1020
|
||||
icache_sync \aa
|
||||
// End of instruction cache invalidation
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Lock (prefetch & lock) a single line of the instruction cache.
|
||||
*
|
||||
* Parameters are:
|
||||
* ar address register that contains (virtual) address to lock
|
||||
* (may get clobbered in a future implementation, but not currently)
|
||||
* offset offset to add to \ar to compute effective address to lock
|
||||
* (note: some number of lsbits are ignored)
|
||||
*/
|
||||
.macro icache_lock_line ar, offset
|
||||
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
|
||||
ipfl \ar, \offset /* prefetch and lock icache line */
|
||||
icache_sync \ar
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Lock (prefetch & lock) a specified portion of memory into the instruction cache.
|
||||
* Parameters are:
|
||||
* astart start address (register gets clobbered)
|
||||
* asize size of the region in bytes (register gets clobbered)
|
||||
* ac unique register used as temporary
|
||||
*/
|
||||
.macro icache_lock_region astart, asize, ac
|
||||
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
|
||||
// Instruction cache region lock:
|
||||
cache_hit_region ipfl, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
|
||||
icache_sync \ac
|
||||
// End of instruction cache region lock
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Unlock a single line of the instruction cache.
|
||||
*
|
||||
* Parameters are:
|
||||
* ar address register that contains (virtual) address to unlock
|
||||
* (may get clobbered in a future implementation, but not currently)
|
||||
* offset offset to add to \ar to compute effective address to unlock
|
||||
* (note: some number of lsbits are ignored)
|
||||
*/
|
||||
.macro icache_unlock_line ar, offset
|
||||
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
|
||||
ihu \ar, \offset /* unlock icache line */
|
||||
icache_sync \ar
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Unlock a specified portion of memory from the instruction cache.
|
||||
* Parameters are:
|
||||
* astart start address (register gets clobbered)
|
||||
* asize size of the region in bytes (register gets clobbered)
|
||||
* ac unique register used as temporary
|
||||
*/
|
||||
.macro icache_unlock_region astart, asize, ac
|
||||
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
|
||||
// Instruction cache region unlock:
|
||||
cache_hit_region ihu, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
|
||||
icache_sync \ac
|
||||
// End of instruction cache region unlock
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Unlock entire instruction cache.
|
||||
*
|
||||
* Parameters:
|
||||
* aa, ab unique address registers (temporaries)
|
||||
*/
|
||||
.macro icache_unlock_all aa, ab, loopokay=1
|
||||
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
|
||||
// Instruction cache unlock:
|
||||
cache_index_all iiu, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240
|
||||
icache_sync \aa
|
||||
// End of instruction cache unlock
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*************************** DATA CACHE ***************************/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Reset/initialize the data cache by simply invalidating it
|
||||
* (need to unlock first also, if cache locking implemented):
|
||||
*
|
||||
* Parameters:
|
||||
* aa, ab unique address registers (temporaries)
|
||||
*/
|
||||
.macro dcache_reset aa, ab, loopokay=0
|
||||
dcache_unlock_all \aa, \ab, \loopokay
|
||||
dcache_invalidate_all \aa, \ab, \loopokay
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Synchronize after a data cache operation,
|
||||
* to be sure everything is in sync with memory as to be
|
||||
* expected following any previous data cache control operations.
|
||||
*
|
||||
* Parameters are:
|
||||
* ar an address register (temporary) (currently unused, but may be used in future)
|
||||
*/
|
||||
.macro dcache_sync ar, wbtype=0
|
||||
#if XCHAL_DCACHE_SIZE > 0
|
||||
// No synchronization is needed.
|
||||
// (memw may be desired e.g. after writeback operation to help ensure subsequent
|
||||
// external accesses are seen to follow that writeback, however that's outside
|
||||
// the scope of this macro)
|
||||
|
||||
//dsync
|
||||
.ifne (\wbtype & XCHAL_ERRATUM_497)
|
||||
memw
|
||||
.endif
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Turn on cache coherence.
|
||||
*
|
||||
* WARNING: for RE-201x.x and later hardware, any interrupt that tries
|
||||
* to change MEMCTL will see its changes dropped if the interrupt comes
|
||||
* in the middle of this routine. If this might be an issue, call this
|
||||
* routine with interrupts disabled.
|
||||
*
|
||||
* Parameters are:
|
||||
* ar,at two scratch address registers (both clobbered)
|
||||
*/
|
||||
.macro cache_coherence_on ar at
|
||||
#if XCHAL_DCACHE_IS_COHERENT
|
||||
# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
|
||||
/* Have MEMCTL. Enable snoop responses. */
|
||||
rsr.memctl \ar
|
||||
movi \at, MEMCTL_SNOOP_EN
|
||||
or \ar, \ar, \at
|
||||
wsr.memctl \ar
|
||||
# elif XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MX
|
||||
/* Opt into coherence for MX (for backward compatibility / testing). */
|
||||
movi \ar, 1
|
||||
movi \at, XER_CCON
|
||||
wer \ar, \at
|
||||
extw
|
||||
# endif
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Turn off cache coherence.
|
||||
*
|
||||
* NOTE: this is generally preceded by emptying the cache;
|
||||
* see xthal_cache_coherence_optout() in hal/coherence.c for details.
|
||||
*
|
||||
* WARNING: for RE-201x.x and later hardware, any interrupt that tries
|
||||
* to change MEMCTL will see its changes dropped if the interrupt comes
|
||||
* in the middle of this routine. If this might be an issue, call this
|
||||
* routine with interrupts disabled.
|
||||
*
|
||||
* Parameters are:
|
||||
* ar,at two scratch address registers (both clobbered)
|
||||
*/
|
||||
.macro cache_coherence_off ar at
|
||||
#if XCHAL_DCACHE_IS_COHERENT
|
||||
# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
|
||||
/* Have MEMCTL. Disable snoop responses. */
|
||||
rsr.memctl \ar
|
||||
movi \at, ~MEMCTL_SNOOP_EN
|
||||
and \ar, \ar, \at
|
||||
wsr.memctl \ar
|
||||
# elif XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MX
|
||||
/* Opt out of coherence, for MX (for backward compatibility / testing). */
|
||||
extw
|
||||
movi \at, 0
|
||||
movi \ar, XER_CCON
|
||||
wer \at, \ar
|
||||
extw
|
||||
# endif
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Synchronize after a data store operation,
|
||||
* to be sure the stored data is completely off the processor
|
||||
* (and assuming there is no buffering outside the processor,
|
||||
* that the data is in memory). This may be required to
|
||||
* ensure that the processor's write buffers are emptied.
|
||||
* A MEMW followed by a read guarantees this, by definition.
|
||||
* We also try to make sure the read itself completes.
|
||||
*
|
||||
* Parameters are:
|
||||
* ar an address register (temporary)
|
||||
*/
|
||||
.macro write_sync ar
|
||||
memw // ensure previous memory accesses are complete prior to subsequent memory accesses
|
||||
l32i \ar, sp, 0 // completing this read ensures any previous write has completed, because of MEMW
|
||||
//slot
|
||||
add \ar, \ar, \ar // use the result of the read to help ensure the read completes (in future architectures)
|
||||
.endm
|
||||
|
||||
|
||||
/*
|
||||
* Invalidate a single line of the data cache.
|
||||
* Parameters are:
|
||||
* ar address register that contains (virtual) address to invalidate
|
||||
* (may get clobbered in a future implementation, but not currently)
|
||||
* offset (optional) offset to add to \ar to compute effective address to invalidate
|
||||
* (note: some number of lsbits are ignored)
|
||||
*/
|
||||
.macro dcache_invalidate_line ar, offset
|
||||
#if XCHAL_DCACHE_SIZE > 0
|
||||
dhi \ar, \offset
|
||||
dcache_sync \ar
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Invalidate data cache entries that cache a specified portion of memory.
|
||||
* Parameters are:
|
||||
* astart start address (register gets clobbered)
|
||||
* asize size of the region in bytes (register gets clobbered)
|
||||
* ac unique register used as temporary
|
||||
*/
|
||||
.macro dcache_invalidate_region astart, asize, ac
|
||||
#if XCHAL_DCACHE_SIZE > 0
|
||||
// Data cache region invalidation:
|
||||
cache_hit_region dhi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
|
||||
dcache_sync \ac
|
||||
// End of data cache region invalidation
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Invalidate entire data cache.
|
||||
*
|
||||
* Parameters:
|
||||
* aa, ab unique address registers (temporaries)
|
||||
*/
|
||||
.macro dcache_invalidate_all aa, ab, loopokay=1
|
||||
#if XCHAL_DCACHE_SIZE > 0
|
||||
// Data cache invalidation:
|
||||
cache_index_all dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, XCHAL_DCACHE_WAYS, \aa, \ab, \loopokay, 1020
|
||||
dcache_sync \aa
|
||||
// End of data cache invalidation
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Writeback a single line of the data cache.
|
||||
* Parameters are:
|
||||
* ar address register that contains (virtual) address to writeback
|
||||
* (may get clobbered in a future implementation, but not currently)
|
||||
* offset offset to add to \ar to compute effective address to writeback
|
||||
* (note: some number of lsbits are ignored)
|
||||
*/
|
||||
.macro dcache_writeback_line ar, offset
|
||||
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
|
||||
dhwb \ar, \offset
|
||||
dcache_sync \ar, wbtype=1
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Writeback dirty data cache entries that cache a specified portion of memory.
|
||||
* Parameters are:
|
||||
* astart start address (register gets clobbered)
|
||||
* asize size of the region in bytes (register gets clobbered)
|
||||
* ac unique register used as temporary
|
||||
*/
|
||||
.macro dcache_writeback_region astart, asize, ac, awb
|
||||
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
|
||||
// Data cache region writeback:
|
||||
cache_hit_region dhwb, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac, \awb
|
||||
dcache_sync \ac, wbtype=1
|
||||
// End of data cache region writeback
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Writeback entire data cache.
|
||||
* Parameters:
|
||||
* aa, ab unique address registers (temporaries)
|
||||
*/
|
||||
.macro dcache_writeback_all aa, ab, awb, loopokay=1
|
||||
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
|
||||
// Data cache writeback:
|
||||
cache_index_all diwb, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240, \awb,
|
||||
dcache_sync \aa, wbtype=1
|
||||
// End of data cache writeback
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Writeback and invalidate a single line of the data cache.
|
||||
* Parameters are:
|
||||
* ar address register that contains (virtual) address to writeback and invalidate
|
||||
* (may get clobbered in a future implementation, but not currently)
|
||||
* offset offset to add to \ar to compute effective address to writeback and invalidate
|
||||
* (note: some number of lsbits are ignored)
|
||||
*/
|
||||
.macro dcache_writeback_inv_line ar, offset
|
||||
#if XCHAL_DCACHE_SIZE > 0
|
||||
dhwbi \ar, \offset /* writeback and invalidate dcache line */
|
||||
dcache_sync \ar, wbtype=1
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Writeback and invalidate data cache entries that cache a specified portion of memory.
|
||||
* Parameters are:
|
||||
* astart start address (register gets clobbered)
|
||||
* asize size of the region in bytes (register gets clobbered)
|
||||
* ac unique register used as temporary
|
||||
*/
|
||||
.macro dcache_writeback_inv_region astart, asize, ac, awb
|
||||
#if XCHAL_DCACHE_SIZE > 0
|
||||
// Data cache region writeback and invalidate:
|
||||
cache_hit_region dhwbi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac, \awb
|
||||
dcache_sync \ac, wbtype=1
|
||||
// End of data cache region writeback and invalidate
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Writeback and invalidate entire data cache.
|
||||
* Parameters:
|
||||
* aa, ab unique address registers (temporaries)
|
||||
*/
|
||||
.macro dcache_writeback_inv_all aa, ab, awb, loopokay=1
|
||||
#if XCHAL_DCACHE_SIZE > 0
|
||||
// Data cache writeback and invalidate:
|
||||
#if XCHAL_DCACHE_IS_WRITEBACK
|
||||
cache_index_all diwbi, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240, \awb
|
||||
dcache_sync \aa, wbtype=1
|
||||
#else /*writeback*/
|
||||
// Data cache does not support writeback, so just invalidate: */
|
||||
dcache_invalidate_all \aa, \ab, \loopokay
|
||||
#endif /*writeback*/
|
||||
// End of data cache writeback and invalidate
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Lock (prefetch & lock) a single line of the data cache.
|
||||
*
|
||||
* Parameters are:
|
||||
* ar address register that contains (virtual) address to lock
|
||||
* (may get clobbered in a future implementation, but not currently)
|
||||
* offset offset to add to \ar to compute effective address to lock
|
||||
* (note: some number of lsbits are ignored)
|
||||
*/
|
||||
.macro dcache_lock_line ar, offset
|
||||
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
|
||||
dpfl \ar, \offset /* prefetch and lock dcache line */
|
||||
dcache_sync \ar
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Lock (prefetch & lock) a specified portion of memory into the data cache.
|
||||
* Parameters are:
|
||||
* astart start address (register gets clobbered)
|
||||
* asize size of the region in bytes (register gets clobbered)
|
||||
* ac unique register used as temporary
|
||||
*/
|
||||
.macro dcache_lock_region astart, asize, ac
|
||||
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
|
||||
// Data cache region lock:
|
||||
cache_hit_region dpfl, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
|
||||
dcache_sync \ac
|
||||
// End of data cache region lock
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Unlock a single line of the data cache.
|
||||
*
|
||||
* Parameters are:
|
||||
* ar address register that contains (virtual) address to unlock
|
||||
* (may get clobbered in a future implementation, but not currently)
|
||||
* offset offset to add to \ar to compute effective address to unlock
|
||||
* (note: some number of lsbits are ignored)
|
||||
*/
|
||||
.macro dcache_unlock_line ar, offset
|
||||
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
|
||||
dhu \ar, \offset /* unlock dcache line */
|
||||
dcache_sync \ar
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Unlock a specified portion of memory from the data cache.
|
||||
* Parameters are:
|
||||
* astart start address (register gets clobbered)
|
||||
* asize size of the region in bytes (register gets clobbered)
|
||||
* ac unique register used as temporary
|
||||
*/
|
||||
.macro dcache_unlock_region astart, asize, ac
|
||||
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
|
||||
// Data cache region unlock:
|
||||
cache_hit_region dhu, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
|
||||
dcache_sync \ac
|
||||
// End of data cache region unlock
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Unlock entire data cache.
|
||||
*
|
||||
* Parameters:
|
||||
* aa, ab unique address registers (temporaries)
|
||||
*/
|
||||
.macro dcache_unlock_all aa, ab, loopokay=1
|
||||
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
|
||||
// Data cache unlock:
|
||||
cache_index_all diu, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240
|
||||
dcache_sync \aa
|
||||
// End of data cache unlock
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Get the number of enabled icache ways. Note that this may
|
||||
* be different from the value read from the MEMCTL register.
|
||||
*
|
||||
* Parameters:
|
||||
* aa address register where value is returned
|
||||
*/
|
||||
.macro icache_get_ways aa
|
||||
#if XCHAL_ICACHE_SIZE > 0
|
||||
#if XCHAL_HAVE_ICACHE_DYN_WAYS
|
||||
// Read from MEMCTL and shift/mask
|
||||
rsr \aa, MEMCTL
|
||||
extui \aa, \aa, MEMCTL_ICWU_SHIFT, MEMCTL_ICWU_BITS
|
||||
blti \aa, XCHAL_ICACHE_WAYS, .Licgw
|
||||
movi \aa, XCHAL_ICACHE_WAYS
|
||||
.Licgw:
|
||||
#else
|
||||
// All ways are always enabled
|
||||
movi \aa, XCHAL_ICACHE_WAYS
|
||||
#endif
|
||||
#else
|
||||
// No icache
|
||||
movi \aa, 0
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Set the number of enabled icache ways.
|
||||
*
|
||||
* Parameters:
|
||||
* aa address register specifying number of ways (trashed)
|
||||
* ab,ac address register for scratch use (trashed)
|
||||
*/
|
||||
.macro icache_set_ways aa, ab, ac
|
||||
#if XCHAL_ICACHE_SIZE > 0
|
||||
#if XCHAL_HAVE_ICACHE_DYN_WAYS
|
||||
movi \ac, MEMCTL_ICWU_CLR_MASK // set up to clear bits 18-22
|
||||
rsr \ab, MEMCTL
|
||||
and \ab, \ab, \ac
|
||||
movi \ac, MEMCTL_INV_EN // set bit 23
|
||||
slli \aa, \aa, MEMCTL_ICWU_SHIFT // move to right spot
|
||||
or \ab, \ab, \aa
|
||||
or \ab, \ab, \ac
|
||||
wsr \ab, MEMCTL
|
||||
isync
|
||||
#else
|
||||
// All ways are always enabled
|
||||
#endif
|
||||
#else
|
||||
// No icache
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Get the number of enabled dcache ways. Note that this may
|
||||
* be different from the value read from the MEMCTL register.
|
||||
*
|
||||
* Parameters:
|
||||
* aa address register where value is returned
|
||||
*/
|
||||
.macro dcache_get_ways aa
|
||||
#if XCHAL_DCACHE_SIZE > 0
|
||||
#if XCHAL_HAVE_DCACHE_DYN_WAYS
|
||||
// Read from MEMCTL and shift/mask
|
||||
rsr \aa, MEMCTL
|
||||
extui \aa, \aa, MEMCTL_DCWU_SHIFT, MEMCTL_DCWU_BITS
|
||||
blti \aa, XCHAL_DCACHE_WAYS, .Ldcgw
|
||||
movi \aa, XCHAL_DCACHE_WAYS
|
||||
.Ldcgw:
|
||||
#else
|
||||
// All ways are always enabled
|
||||
movi \aa, XCHAL_DCACHE_WAYS
|
||||
#endif
|
||||
#else
|
||||
// No dcache
|
||||
movi \aa, 0
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Set the number of enabled dcache ways.
|
||||
*
|
||||
* Parameters:
|
||||
* aa address register specifying number of ways (trashed)
|
||||
* ab,ac address register for scratch use (trashed)
|
||||
*/
|
||||
.macro dcache_set_ways aa, ab, ac
|
||||
#if (XCHAL_DCACHE_SIZE > 0) && XCHAL_HAVE_DCACHE_DYN_WAYS
|
||||
movi \ac, MEMCTL_DCWA_CLR_MASK // set up to clear bits 13-17
|
||||
rsr \ab, MEMCTL
|
||||
and \ab, \ab, \ac // clear ways allocatable
|
||||
slli \ac, \aa, MEMCTL_DCWA_SHIFT
|
||||
or \ab, \ab, \ac // set ways allocatable
|
||||
wsr \ab, MEMCTL
|
||||
#if XCHAL_DCACHE_IS_WRITEBACK
|
||||
// Check if the way count is increasing or decreasing
|
||||
extui \ac, \ab, MEMCTL_DCWU_SHIFT, MEMCTL_DCWU_BITS // bits 8-12 - ways in use
|
||||
bge \aa, \ac, .Ldsw3 // equal or increasing
|
||||
slli \ab, \aa, XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_SETWIDTH // start way number
|
||||
slli \ac, \ac, XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_SETWIDTH // end way number
|
||||
.Ldsw1:
|
||||
diwbui.p \ab // auto-increments ab
|
||||
bge \ab, \ac, .Ldsw2
|
||||
beqz \ab, .Ldsw2
|
||||
j .Ldsw1
|
||||
.Ldsw2:
|
||||
rsr \ab, MEMCTL
|
||||
#endif
|
||||
.Ldsw3:
|
||||
// No dirty data to write back, just set the new number of ways
|
||||
movi \ac, MEMCTL_DCWU_CLR_MASK // set up to clear bits 8-12
|
||||
and \ab, \ab, \ac // clear ways in use
|
||||
movi \ac, MEMCTL_INV_EN
|
||||
or \ab, \ab, \ac // set bit 23
|
||||
slli \aa, \aa, MEMCTL_DCWU_SHIFT
|
||||
or \ab, \ab, \aa // set ways in use
|
||||
wsr \ab, MEMCTL
|
||||
#else
|
||||
// No dcache or no way disable support
|
||||
#endif
|
||||
.endm
|
||||
|
||||
#endif /*XTENSA_CACHEASM_H*/
|
||||
|
||||
+436
@@ -0,0 +1,436 @@
|
||||
/*
|
||||
* xtensa/cacheattrasm.h -- assembler-specific CACHEATTR register related definitions
|
||||
* that depend on CORE configuration
|
||||
*
|
||||
* This file is logically part of xtensa/coreasm.h (or perhaps xtensa/cacheasm.h),
|
||||
* but is kept separate for modularity / compilation-performance.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001-2009 Tensilica Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef XTENSA_CACHEATTRASM_H
|
||||
#define XTENSA_CACHEATTRASM_H
|
||||
|
||||
#include <xtensa/coreasm.h>
|
||||
|
||||
/* Determine whether cache attributes are controlled using eight 512MB entries: */
|
||||
#define XCHAL_CA_8X512 (XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR \
|
||||
|| (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY))
|
||||
|
||||
|
||||
/*
|
||||
* This header file defines assembler macros of the form:
|
||||
* <x>cacheattr_<func>
|
||||
* where:
|
||||
* <x> is 'i', 'd' or absent for instruction, data
|
||||
* or both caches; and
|
||||
* <func> indicates the function of the macro.
|
||||
*
|
||||
* The following functions are defined:
|
||||
*
|
||||
* icacheattr_get
|
||||
* Reads I-cache CACHEATTR into a2 (clobbers a3-a5).
|
||||
*
|
||||
* dcacheattr_get
|
||||
* Reads D-cache CACHEATTR into a2 (clobbers a3-a5).
|
||||
* (Note: for configs with a real CACHEATTR register, the
|
||||
* above two macros are identical.)
|
||||
*
|
||||
* cacheattr_set
|
||||
* Writes both I-cache and D-cache CACHEATTRs from a2 (a3-a8 clobbered).
|
||||
* Works even when changing one's own code's attributes.
|
||||
*
|
||||
* icacheattr_is_enabled label
|
||||
* Branches to \label if I-cache appears to have been enabled
|
||||
* (eg. if CACHEATTR contains a cache-enabled attribute).
|
||||
* (clobbers a2-a5,SAR)
|
||||
*
|
||||
* dcacheattr_is_enabled label
|
||||
* Branches to \label if D-cache appears to have been enabled
|
||||
* (eg. if CACHEATTR contains a cache-enabled attribute).
|
||||
* (clobbers a2-a5,SAR)
|
||||
*
|
||||
* cacheattr_is_enabled label
|
||||
* Branches to \label if either I-cache or D-cache appears to have been enabled
|
||||
* (eg. if CACHEATTR contains a cache-enabled attribute).
|
||||
* (clobbers a2-a5,SAR)
|
||||
*
|
||||
* The following macros are only defined under certain conditions:
|
||||
*
|
||||
* icacheattr_set (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
|
||||
* Writes I-cache CACHEATTR from a2 (a3-a8 clobbered).
|
||||
*
|
||||
* dcacheattr_set (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
|
||||
* Writes D-cache CACHEATTR from a2 (a3-a8 clobbered).
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*************************** GENERIC -- ALL CACHES ***************************/
|
||||
|
||||
/*
|
||||
* _cacheattr_get
|
||||
*
|
||||
* (Internal macro.)
|
||||
* Returns value of CACHEATTR register (or closest equivalent) in a2.
|
||||
*
|
||||
* Entry:
|
||||
* (none)
|
||||
* Exit:
|
||||
* a2 value read from CACHEATTR
|
||||
* a3-a5 clobbered (temporaries)
|
||||
*/
|
||||
.macro _cacheattr_get tlb
|
||||
#if XCHAL_HAVE_CACHEATTR
|
||||
rsr a2, CACHEATTR
|
||||
#elif XCHAL_CA_8X512
|
||||
// We have a config that "mimics" CACHEATTR using a simplified
|
||||
// "MMU" composed of a single statically-mapped way.
|
||||
// DTLB and ITLB are independent, so there's no single
|
||||
// cache attribute that can describe both. So for now
|
||||
// just return the DTLB state.
|
||||
movi a5, 0xE0000000
|
||||
movi a2, 0
|
||||
movi a3, XCHAL_SPANNING_WAY
|
||||
1: add a3, a3, a5 // next segment
|
||||
r&tlb&1 a4, a3 // get PPN+CA of segment at 0xE0000000, 0xC0000000, ..., 0
|
||||
dsync // interlock???
|
||||
slli a2, a2, 4
|
||||
extui a4, a4, 0, 4 // extract CA
|
||||
or a2, a2, a4
|
||||
bgeui a3, 16, 1b
|
||||
#else
|
||||
// This macro isn't applicable to arbitrary MMU configurations.
|
||||
// Just return zero.
|
||||
movi a2, 0
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro icacheattr_get
|
||||
_cacheattr_get itlb
|
||||
.endm
|
||||
|
||||
.macro dcacheattr_get
|
||||
_cacheattr_get dtlb
|
||||
.endm
|
||||
|
||||
|
||||
/* Default (powerup/reset) value of CACHEATTR,
|
||||
all BYPASS mode (ie. disabled/bypassed caches): */
|
||||
#if XCHAL_HAVE_PTP_MMU
|
||||
# define XCHAL_CACHEATTR_ALL_BYPASS 0x33333333
|
||||
#else
|
||||
# define XCHAL_CACHEATTR_ALL_BYPASS 0x22222222
|
||||
#endif
|
||||
|
||||
#if XCHAL_CA_8X512
|
||||
|
||||
#if XCHAL_HAVE_PTP_MMU
|
||||
# define XCHAL_FCA_ENAMASK 0x0AA0 /* bitmap of fetch attributes that require enabled icache */
|
||||
# define XCHAL_LCA_ENAMASK 0x0FF0 /* bitmap of load attributes that require enabled dcache */
|
||||
# define XCHAL_SCA_ENAMASK 0x0CC0 /* bitmap of store attributes that require enabled dcache */
|
||||
#else
|
||||
# define XCHAL_FCA_ENAMASK 0x003A /* bitmap of fetch attributes that require enabled icache */
|
||||
# define XCHAL_LCA_ENAMASK 0x0033 /* bitmap of load attributes that require enabled dcache */
|
||||
# define XCHAL_SCA_ENAMASK 0x0033 /* bitmap of store attributes that require enabled dcache */
|
||||
#endif
|
||||
#define XCHAL_LSCA_ENAMASK (XCHAL_LCA_ENAMASK|XCHAL_SCA_ENAMASK) /* l/s attrs requiring enabled dcache */
|
||||
#define XCHAL_ALLCA_ENAMASK (XCHAL_FCA_ENAMASK|XCHAL_LSCA_ENAMASK) /* all attrs requiring enabled caches */
|
||||
|
||||
/*
|
||||
* _cacheattr_is_enabled
|
||||
*
|
||||
* (Internal macro.)
|
||||
* Branches to \label if CACHEATTR in a2 indicates an enabled
|
||||
* cache, using mask in a3.
|
||||
*
|
||||
* Parameters:
|
||||
* label where to branch to if cache is enabled
|
||||
* Entry:
|
||||
* a2 contains CACHEATTR value used to determine whether
|
||||
* caches are enabled
|
||||
* a3 16-bit constant where each bit correspond to
|
||||
* one of the 16 possible CA values (in a CACHEATTR mask);
|
||||
* CA values that indicate the cache is enabled
|
||||
* have their corresponding bit set in this mask
|
||||
* (eg. use XCHAL_xCA_ENAMASK , above)
|
||||
* Exit:
|
||||
* a2,a4,a5 clobbered
|
||||
* SAR clobbered
|
||||
*/
|
||||
.macro _cacheattr_is_enabled label
|
||||
movi a4, 8 // loop 8 times
|
||||
.Lcaife\@:
|
||||
extui a5, a2, 0, 4 // get CA nibble
|
||||
ssr a5 // index into mask according to CA...
|
||||
srl a5, a3 // ...and get CA's mask bit in a5 bit 0
|
||||
bbsi.l a5, 0, \label // if CA indicates cache enabled, jump to label
|
||||
srli a2, a2, 4 // next nibble
|
||||
addi a4, a4, -1
|
||||
bnez a4, .Lcaife\@ // loop for each nibble
|
||||
.endm
|
||||
|
||||
#else /* XCHAL_CA_8X512 */
|
||||
.macro _cacheattr_is_enabled label
|
||||
j \label // macro not applicable, assume caches always enabled
|
||||
.endm
|
||||
#endif /* XCHAL_CA_8X512 */
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* icacheattr_is_enabled
|
||||
*
|
||||
* Branches to \label if I-cache is enabled.
|
||||
*
|
||||
* Parameters:
|
||||
* label where to branch to if icache is enabled
|
||||
* Entry:
|
||||
* (none)
|
||||
* Exit:
|
||||
* a2-a5, SAR clobbered (temporaries)
|
||||
*/
|
||||
.macro icacheattr_is_enabled label
|
||||
#if XCHAL_CA_8X512
|
||||
icacheattr_get
|
||||
movi a3, XCHAL_FCA_ENAMASK
|
||||
#endif
|
||||
_cacheattr_is_enabled \label
|
||||
.endm
|
||||
|
||||
/*
|
||||
* dcacheattr_is_enabled
|
||||
*
|
||||
* Branches to \label if D-cache is enabled.
|
||||
*
|
||||
* Parameters:
|
||||
* label where to branch to if dcache is enabled
|
||||
* Entry:
|
||||
* (none)
|
||||
* Exit:
|
||||
* a2-a5, SAR clobbered (temporaries)
|
||||
*/
|
||||
.macro dcacheattr_is_enabled label
|
||||
#if XCHAL_CA_8X512
|
||||
dcacheattr_get
|
||||
movi a3, XCHAL_LSCA_ENAMASK
|
||||
#endif
|
||||
_cacheattr_is_enabled \label
|
||||
.endm
|
||||
|
||||
/*
|
||||
* cacheattr_is_enabled
|
||||
*
|
||||
* Branches to \label if either I-cache or D-cache is enabled.
|
||||
*
|
||||
* Parameters:
|
||||
* label where to branch to if a cache is enabled
|
||||
* Entry:
|
||||
* (none)
|
||||
* Exit:
|
||||
* a2-a5, SAR clobbered (temporaries)
|
||||
*/
|
||||
.macro cacheattr_is_enabled label
|
||||
#if XCHAL_HAVE_CACHEATTR
|
||||
rsr a2, CACHEATTR
|
||||
movi a3, XCHAL_ALLCA_ENAMASK
|
||||
#elif XCHAL_CA_8X512
|
||||
icacheattr_get
|
||||
movi a3, XCHAL_FCA_ENAMASK
|
||||
_cacheattr_is_enabled \label
|
||||
dcacheattr_get
|
||||
movi a3, XCHAL_LSCA_ENAMASK
|
||||
#endif
|
||||
_cacheattr_is_enabled \label
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* The ISA does not have a defined way to change the
|
||||
* instruction cache attributes of the running code,
|
||||
* ie. of the memory area that encloses the current PC.
|
||||
* However, each micro-architecture (or class of
|
||||
* configurations within a micro-architecture)
|
||||
* provides a way to deal with this issue.
|
||||
*
|
||||
* Here are a few macros used to implement the relevant
|
||||
* approach taken.
|
||||
*/
|
||||
|
||||
#if XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR
|
||||
// We have a config that "mimics" CACHEATTR using a simplified
|
||||
// "MMU" composed of a single statically-mapped way.
|
||||
|
||||
/*
|
||||
* icacheattr_set
|
||||
*
|
||||
* Entry:
|
||||
* a2 cacheattr value to set
|
||||
* Exit:
|
||||
* a2 unchanged
|
||||
* a3-a8 clobbered (temporaries)
|
||||
*/
|
||||
.macro icacheattr_set
|
||||
|
||||
movi a5, 0xE0000000 // mask of upper 3 bits
|
||||
movi a6, 3f // PC where ITLB is set
|
||||
movi a3, XCHAL_SPANNING_WAY // start at region 0 (0 .. 7)
|
||||
mov a7, a2 // copy a2 so it doesn't get clobbered
|
||||
and a6, a6, a5 // upper 3 bits of local PC area
|
||||
j 3f
|
||||
|
||||
// Use micro-architecture specific method.
|
||||
// The following 4-instruction sequence is aligned such that
|
||||
// it all fits within a single I-cache line. Sixteen byte
|
||||
// alignment is sufficient for this (using XCHAL_ICACHE_LINESIZE
|
||||
// actually causes problems because that can be greater than
|
||||
// the alignment of the reset vector, where this macro is often
|
||||
// invoked, which would cause the linker to align the reset
|
||||
// vector code away from the reset vector!!).
|
||||
.begin no-transform
|
||||
.align 16 /*XCHAL_ICACHE_LINESIZE*/
|
||||
1: witlb a4, a3 // write wired PTE (CA, no PPN) of 512MB segment to ITLB
|
||||
isync
|
||||
.end no-transform
|
||||
nop
|
||||
nop
|
||||
|
||||
sub a3, a3, a5 // next segment (add 0x20000000)
|
||||
bltui a3, 16, 4f // done?
|
||||
|
||||
// Note that in the WITLB loop, we don't do any load/stores
|
||||
// (may not be an issue here, but it is important in the DTLB case).
|
||||
2: srli a7, a7, 4 // next CA
|
||||
3:
|
||||
# if XCHAL_HAVE_MIMIC_CACHEATTR
|
||||
extui a4, a7, 0, 4 // extract CA to set
|
||||
# else /* have translation, preserve it: */
|
||||
ritlb1 a8, a3 // get current PPN+CA of segment
|
||||
//dsync // interlock???
|
||||
extui a4, a7, 0, 4 // extract CA to set
|
||||
srli a8, a8, 4 // clear CA but keep PPN ...
|
||||
slli a8, a8, 4 // ...
|
||||
add a4, a4, a8 // combine new CA with PPN to preserve
|
||||
# endif
|
||||
beq a3, a6, 1b // current PC's region? if so, do it in a safe way
|
||||
witlb a4, a3 // write wired PTE (CA [+PPN]) of 512MB segment to ITLB
|
||||
sub a3, a3, a5 // next segment (add 0x20000000)
|
||||
bgeui a3, 16, 2b
|
||||
isync // make sure all ifetch changes take effect
|
||||
4:
|
||||
.endm // icacheattr_set
|
||||
|
||||
|
||||
/*
|
||||
* dcacheattr_set
|
||||
*
|
||||
* Entry:
|
||||
* a2 cacheattr value to set
|
||||
* Exit:
|
||||
* a2 unchanged
|
||||
* a3-a8 clobbered (temporaries)
|
||||
*/
|
||||
|
||||
.macro dcacheattr_set
|
||||
|
||||
movi a5, 0xE0000000 // mask of upper 3 bits
|
||||
movi a3, XCHAL_SPANNING_WAY // start at region 0 (0 .. 7)
|
||||
mov a7, a2 // copy a2 so it doesn't get clobbered
|
||||
// Note that in the WDTLB loop, we don't do any load/stores
|
||||
2: // (including implicit l32r via movi) because it isn't safe.
|
||||
# if XCHAL_HAVE_MIMIC_CACHEATTR
|
||||
extui a4, a7, 0, 4 // extract CA to set
|
||||
# else /* have translation, preserve it: */
|
||||
rdtlb1 a8, a3 // get current PPN+CA of segment
|
||||
//dsync // interlock???
|
||||
extui a4, a7, 0, 4 // extract CA to set
|
||||
srli a8, a8, 4 // clear CA but keep PPN ...
|
||||
slli a8, a8, 4 // ...
|
||||
add a4, a4, a8 // combine new CA with PPN to preserve
|
||||
# endif
|
||||
wdtlb a4, a3 // write wired PTE (CA [+PPN]) of 512MB segment to DTLB
|
||||
sub a3, a3, a5 // next segment (add 0x20000000)
|
||||
srli a7, a7, 4 // next CA
|
||||
bgeui a3, 16, 2b
|
||||
dsync // make sure all data path changes take effect
|
||||
.endm // dcacheattr_set
|
||||
|
||||
#endif /* XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR */
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* cacheattr_set
|
||||
*
|
||||
* Macro that sets the current CACHEATTR safely
|
||||
* (both i and d) according to the current contents of a2.
|
||||
* It works even when changing the cache attributes of
|
||||
* the currently running code.
|
||||
*
|
||||
* Entry:
|
||||
* a2 cacheattr value to set
|
||||
* Exit:
|
||||
* a2 unchanged
|
||||
* a3-a8 clobbered (temporaries)
|
||||
*/
|
||||
.macro cacheattr_set
|
||||
|
||||
#if XCHAL_HAVE_CACHEATTR
|
||||
# if XCHAL_ICACHE_LINESIZE < 4
|
||||
// No i-cache, so can always safely write to CACHEATTR:
|
||||
wsr a2, CACHEATTR
|
||||
# else
|
||||
// The Athens micro-architecture, when using the old
|
||||
// exception architecture option (ie. with the CACHEATTR register)
|
||||
// allows changing the cache attributes of the running code
|
||||
// using the following exact sequence aligned to be within
|
||||
// an instruction cache line. (NOTE: using XCHAL_ICACHE_LINESIZE
|
||||
// alignment actually causes problems because that can be greater
|
||||
// than the alignment of the reset vector, where this macro is often
|
||||
// invoked, which would cause the linker to align the reset
|
||||
// vector code away from the reset vector!!).
|
||||
j 1f
|
||||
.begin no-transform
|
||||
.align 16 /*XCHAL_ICACHE_LINESIZE*/ // align to within an I-cache line
|
||||
1: wsr a2, CACHEATTR
|
||||
isync
|
||||
.end no-transform
|
||||
nop
|
||||
nop
|
||||
# endif
|
||||
#elif XCHAL_CA_8X512
|
||||
// DTLB and ITLB are independent, but to keep semantics
|
||||
// of this macro we simply write to both.
|
||||
icacheattr_set
|
||||
dcacheattr_set
|
||||
#else
|
||||
// This macro isn't applicable to arbitrary MMU configurations.
|
||||
// Do nothing in this case.
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
#endif /*XTENSA_CACHEATTRASM_H*/
|
||||
|
||||
@@ -0,0 +1,655 @@
|
||||
/*
|
||||
* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
|
||||
* processor CORE configuration
|
||||
*
|
||||
* See <xtensa/config/core.h>, which includes this file, for more details.
|
||||
*/
|
||||
|
||||
/* Xtensa processor core configuration information.
|
||||
|
||||
Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef _XTENSA_CORE_CONFIGURATION_H
|
||||
#define _XTENSA_CORE_CONFIGURATION_H
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for Any Code, USER or PRIVILEGED
|
||||
****************************************************************************/
|
||||
|
||||
/*
|
||||
* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
|
||||
* configured, and a value of 0 otherwise. These macros are always defined.
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
ISA
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
|
||||
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
|
||||
#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
|
||||
#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
|
||||
#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
|
||||
#define XCHAL_HAVE_DEBUG 1 /* debug option */
|
||||
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
|
||||
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
|
||||
#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */
|
||||
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
|
||||
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
|
||||
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
|
||||
#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
|
||||
#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
|
||||
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
|
||||
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
|
||||
#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
|
||||
#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
|
||||
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
|
||||
#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
|
||||
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
|
||||
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
|
||||
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
|
||||
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
|
||||
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
|
||||
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
|
||||
/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
|
||||
/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
|
||||
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
|
||||
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
|
||||
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
|
||||
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
|
||||
#define XCHAL_NUM_CONTEXTS 1 /* */
|
||||
#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */
|
||||
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
|
||||
#define XCHAL_HAVE_PRID 1 /* processor ID register */
|
||||
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
|
||||
#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
|
||||
#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
|
||||
#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
|
||||
#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
|
||||
#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
|
||||
#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
|
||||
#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
|
||||
#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
|
||||
#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
|
||||
#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
|
||||
#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
|
||||
|
||||
#define XCHAL_HAVE_FUSION 0 /* Fusion*/
|
||||
#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
|
||||
#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
|
||||
#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
|
||||
#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
|
||||
#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
|
||||
#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
|
||||
#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
|
||||
#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
|
||||
#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */
|
||||
#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */
|
||||
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
|
||||
#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
|
||||
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
|
||||
#define XCHAL_HAVE_HIFI_MINI 0
|
||||
|
||||
|
||||
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
|
||||
#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
|
||||
#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
|
||||
#define XCHAL_HAVE_FP 1 /* single prec floating point */
|
||||
#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */
|
||||
#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */
|
||||
#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */
|
||||
#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */
|
||||
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
|
||||
#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
|
||||
#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
|
||||
#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
|
||||
#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
|
||||
#define XCHAL_HAVE_DFP_ACCEL 1 /* double precision FP acceleration pkg */
|
||||
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
|
||||
|
||||
#define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */
|
||||
#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
|
||||
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
|
||||
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
|
||||
#define XCHAL_HAVE_PDX4 0 /* PDX4 */
|
||||
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
|
||||
#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
|
||||
#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
|
||||
#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
|
||||
#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
|
||||
#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
|
||||
#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
|
||||
#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
|
||||
#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
|
||||
#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
|
||||
#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
|
||||
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
|
||||
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
|
||||
#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
|
||||
#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
|
||||
#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MISC
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
|
||||
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */
|
||||
#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
|
||||
#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
|
||||
#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay
|
||||
(1 = 5-stage, 2 = 7-stage) */
|
||||
#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
|
||||
#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
|
||||
/* In T1050, applies to selected core load and store instructions (see ISA): */
|
||||
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */
|
||||
#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/
|
||||
#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */
|
||||
#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/
|
||||
|
||||
#define XCHAL_SW_VERSION 1100003 /* sw version of this header */
|
||||
|
||||
#define XCHAL_CORE_ID "esp32_v3_49_prod" /* alphanum core name
|
||||
(CoreID) set in the Xtensa
|
||||
Processor Generator */
|
||||
|
||||
#define XCHAL_BUILD_UNIQUE_ID 0x0005FE96 /* 22-bit sw build ID */
|
||||
|
||||
/*
|
||||
* These definitions describe the hardware targeted by this software.
|
||||
*/
|
||||
#define XCHAL_HW_CONFIGID0 0xC2BCFFFE /* ConfigID hi 32 bits*/
|
||||
#define XCHAL_HW_CONFIGID1 0x1CC5FE96 /* ConfigID lo 32 bits*/
|
||||
#define XCHAL_HW_VERSION_NAME "LX6.0.3" /* full version name */
|
||||
#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION 260003 /* major*100+minor */
|
||||
#define XCHAL_HW_REL_LX6 1
|
||||
#define XCHAL_HW_REL_LX6_0 1
|
||||
#define XCHAL_HW_REL_LX6_0_3 1
|
||||
#define XCHAL_HW_CONFIGID_RELIABLE 1
|
||||
/* If software targets a *range* of hardware versions, these are the bounds: */
|
||||
#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION 260003 /* earliest targeted hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION 260003 /* latest targeted hw */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */
|
||||
#define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */
|
||||
#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */
|
||||
#define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */
|
||||
|
||||
#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
|
||||
#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
|
||||
|
||||
#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
|
||||
#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
|
||||
|
||||
#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
|
||||
#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
|
||||
#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
|
||||
#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
|
||||
#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
|
||||
#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
|
||||
#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */
|
||||
#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */
|
||||
#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
|
||||
#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
|
||||
|
||||
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
|
||||
#define XCHAL_HAVE_AXI 0 /* AXI bus */
|
||||
|
||||
#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */
|
||||
#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */
|
||||
|
||||
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
|
||||
|
||||
/* Number of cache sets in log2(lines per way): */
|
||||
#define XCHAL_ICACHE_SETWIDTH 0
|
||||
#define XCHAL_DCACHE_SETWIDTH 0
|
||||
|
||||
/* Cache set associativity (number of ways): */
|
||||
#define XCHAL_ICACHE_WAYS 1
|
||||
#define XCHAL_DCACHE_WAYS 1
|
||||
|
||||
/* Cache features: */
|
||||
#define XCHAL_ICACHE_LINE_LOCKABLE 0
|
||||
#define XCHAL_DCACHE_LINE_LOCKABLE 0
|
||||
#define XCHAL_ICACHE_ECC_PARITY 0
|
||||
#define XCHAL_DCACHE_ECC_PARITY 0
|
||||
|
||||
/* Cache access size in bytes (affects operation of SICW instruction): */
|
||||
#define XCHAL_ICACHE_ACCESS_SIZE 1
|
||||
#define XCHAL_DCACHE_ACCESS_SIZE 1
|
||||
|
||||
#define XCHAL_DCACHE_BANKS 0 /* number of banks */
|
||||
|
||||
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
|
||||
#define XCHAL_CA_BITS 4
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERNAL I/D RAM/ROMs and XLMI
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_NUM_INSTROM 1 /* number of core instr. ROMs */
|
||||
#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */
|
||||
#define XCHAL_NUM_DATAROM 1 /* number of core data ROMs */
|
||||
#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */
|
||||
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
|
||||
#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */
|
||||
|
||||
/* Instruction ROM 0: */
|
||||
#define XCHAL_INSTROM0_VADDR 0x40800000 /* virtual address */
|
||||
#define XCHAL_INSTROM0_PADDR 0x40800000 /* physical address */
|
||||
#define XCHAL_INSTROM0_SIZE 4194304 /* size in bytes */
|
||||
#define XCHAL_INSTROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
|
||||
/* Instruction RAM 0: */
|
||||
#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */
|
||||
#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */
|
||||
#define XCHAL_INSTRAM0_SIZE 4194304 /* size in bytes */
|
||||
#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
|
||||
/* Instruction RAM 1: */
|
||||
#define XCHAL_INSTRAM1_VADDR 0x40400000 /* virtual address */
|
||||
#define XCHAL_INSTRAM1_PADDR 0x40400000 /* physical address */
|
||||
#define XCHAL_INSTRAM1_SIZE 4194304 /* size in bytes */
|
||||
#define XCHAL_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
|
||||
/* Data ROM 0: */
|
||||
#define XCHAL_DATAROM0_VADDR 0x3F400000 /* virtual address */
|
||||
#define XCHAL_DATAROM0_PADDR 0x3F400000 /* physical address */
|
||||
#define XCHAL_DATAROM0_SIZE 4194304 /* size in bytes */
|
||||
#define XCHAL_DATAROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
#define XCHAL_DATAROM0_BANKS 1 /* number of banks */
|
||||
|
||||
/* Data RAM 0: */
|
||||
#define XCHAL_DATARAM0_VADDR 0x3FF80000 /* virtual address */
|
||||
#define XCHAL_DATARAM0_PADDR 0x3FF80000 /* physical address */
|
||||
#define XCHAL_DATARAM0_SIZE 524288 /* size in bytes */
|
||||
#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
|
||||
|
||||
/* Data RAM 1: */
|
||||
#define XCHAL_DATARAM1_VADDR 0x3F800000 /* virtual address */
|
||||
#define XCHAL_DATARAM1_PADDR 0x3F800000 /* physical address */
|
||||
#define XCHAL_DATARAM1_SIZE 4194304 /* size in bytes */
|
||||
#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
#define XCHAL_DATARAM1_BANKS 1 /* number of banks */
|
||||
|
||||
/* XLMI Port 0: */
|
||||
#define XCHAL_XLMI0_VADDR 0x3FF00000 /* virtual address */
|
||||
#define XCHAL_XLMI0_PADDR 0x3FF00000 /* physical address */
|
||||
#define XCHAL_XLMI0_SIZE 524288 /* size in bytes */
|
||||
#define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
|
||||
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERRUPTS and TIMERS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
|
||||
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
|
||||
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
|
||||
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
|
||||
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
|
||||
#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */
|
||||
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
|
||||
#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */
|
||||
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
|
||||
(not including level zero) */
|
||||
#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
|
||||
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
|
||||
|
||||
/* Masks of interrupts at each interrupt level: */
|
||||
#define XCHAL_INTLEVEL1_MASK 0x000637FF
|
||||
#define XCHAL_INTLEVEL2_MASK 0x00380000
|
||||
#define XCHAL_INTLEVEL3_MASK 0x28C08800
|
||||
#define XCHAL_INTLEVEL4_MASK 0x53000000
|
||||
#define XCHAL_INTLEVEL5_MASK 0x84010000
|
||||
#define XCHAL_INTLEVEL6_MASK 0x00000000
|
||||
#define XCHAL_INTLEVEL7_MASK 0x00004000
|
||||
|
||||
/* Masks of interrupts at each range 1..n of interrupt levels: */
|
||||
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF
|
||||
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF
|
||||
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF
|
||||
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF
|
||||
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF
|
||||
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF
|
||||
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF
|
||||
|
||||
/* Level of each interrupt: */
|
||||
#define XCHAL_INT0_LEVEL 1
|
||||
#define XCHAL_INT1_LEVEL 1
|
||||
#define XCHAL_INT2_LEVEL 1
|
||||
#define XCHAL_INT3_LEVEL 1
|
||||
#define XCHAL_INT4_LEVEL 1
|
||||
#define XCHAL_INT5_LEVEL 1
|
||||
#define XCHAL_INT6_LEVEL 1
|
||||
#define XCHAL_INT7_LEVEL 1
|
||||
#define XCHAL_INT8_LEVEL 1
|
||||
#define XCHAL_INT9_LEVEL 1
|
||||
#define XCHAL_INT10_LEVEL 1
|
||||
#define XCHAL_INT11_LEVEL 3
|
||||
#define XCHAL_INT12_LEVEL 1
|
||||
#define XCHAL_INT13_LEVEL 1
|
||||
#define XCHAL_INT14_LEVEL 7
|
||||
#define XCHAL_INT15_LEVEL 3
|
||||
#define XCHAL_INT16_LEVEL 5
|
||||
#define XCHAL_INT17_LEVEL 1
|
||||
#define XCHAL_INT18_LEVEL 1
|
||||
#define XCHAL_INT19_LEVEL 2
|
||||
#define XCHAL_INT20_LEVEL 2
|
||||
#define XCHAL_INT21_LEVEL 2
|
||||
#define XCHAL_INT22_LEVEL 3
|
||||
#define XCHAL_INT23_LEVEL 3
|
||||
#define XCHAL_INT24_LEVEL 4
|
||||
#define XCHAL_INT25_LEVEL 4
|
||||
#define XCHAL_INT26_LEVEL 5
|
||||
#define XCHAL_INT27_LEVEL 3
|
||||
#define XCHAL_INT28_LEVEL 4
|
||||
#define XCHAL_INT29_LEVEL 3
|
||||
#define XCHAL_INT30_LEVEL 4
|
||||
#define XCHAL_INT31_LEVEL 5
|
||||
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
|
||||
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
|
||||
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
|
||||
EXCSAVE/EPS/EPC_n, RFI n) */
|
||||
|
||||
/* Type of each interrupt: */
|
||||
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_PROFILING
|
||||
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
|
||||
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT29_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
|
||||
/* Masks of interrupts for each type of interrupt: */
|
||||
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x20000080
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x50400400
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F
|
||||
#define XCHAL_INTTYPE_MASK_TIMER 0x00018040
|
||||
#define XCHAL_INTTYPE_MASK_NMI 0x00004000
|
||||
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_PROFILING 0x00000800
|
||||
|
||||
/* Interrupt numbers assigned to specific interrupt sources: */
|
||||
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
|
||||
#define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */
|
||||
#define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */
|
||||
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
|
||||
#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
|
||||
#define XCHAL_PROFILING_INTERRUPT 11 /* profiling interrupt */
|
||||
|
||||
/* Interrupt numbers for levels at which only one interrupt is configured: */
|
||||
#define XCHAL_INTLEVEL7_NUM 14
|
||||
/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */
|
||||
|
||||
|
||||
/*
|
||||
* External interrupt mapping.
|
||||
* These macros describe how Xtensa processor interrupt numbers
|
||||
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
|
||||
* map to external BInterrupt<n> pins, for those interrupts
|
||||
* configured as external (level-triggered, edge-triggered, or NMI).
|
||||
* See the Xtensa processor databook for more details.
|
||||
*/
|
||||
|
||||
/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
|
||||
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT9_NUM 12 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT10_NUM 13 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT11_NUM 14 /* (intlevel 7) */
|
||||
#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT14_NUM 19 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT15_NUM 20 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT16_NUM 21 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT17_NUM 22 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT18_NUM 23 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT19_NUM 24 /* (intlevel 4) */
|
||||
#define XCHAL_EXTINT20_NUM 25 /* (intlevel 4) */
|
||||
#define XCHAL_EXTINT21_NUM 26 /* (intlevel 5) */
|
||||
#define XCHAL_EXTINT22_NUM 27 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT23_NUM 28 /* (intlevel 4) */
|
||||
#define XCHAL_EXTINT24_NUM 30 /* (intlevel 4) */
|
||||
#define XCHAL_EXTINT25_NUM 31 /* (intlevel 5) */
|
||||
/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
|
||||
#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_INT8_EXTNUM 6 /* (intlevel 1) */
|
||||
#define XCHAL_INT9_EXTNUM 7 /* (intlevel 1) */
|
||||
#define XCHAL_INT10_EXTNUM 8 /* (intlevel 1) */
|
||||
#define XCHAL_INT12_EXTNUM 9 /* (intlevel 1) */
|
||||
#define XCHAL_INT13_EXTNUM 10 /* (intlevel 1) */
|
||||
#define XCHAL_INT14_EXTNUM 11 /* (intlevel 7) */
|
||||
#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
|
||||
#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
|
||||
#define XCHAL_INT19_EXTNUM 14 /* (intlevel 2) */
|
||||
#define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */
|
||||
#define XCHAL_INT21_EXTNUM 16 /* (intlevel 2) */
|
||||
#define XCHAL_INT22_EXTNUM 17 /* (intlevel 3) */
|
||||
#define XCHAL_INT23_EXTNUM 18 /* (intlevel 3) */
|
||||
#define XCHAL_INT24_EXTNUM 19 /* (intlevel 4) */
|
||||
#define XCHAL_INT25_EXTNUM 20 /* (intlevel 4) */
|
||||
#define XCHAL_INT26_EXTNUM 21 /* (intlevel 5) */
|
||||
#define XCHAL_INT27_EXTNUM 22 /* (intlevel 3) */
|
||||
#define XCHAL_INT28_EXTNUM 23 /* (intlevel 4) */
|
||||
#define XCHAL_INT30_EXTNUM 24 /* (intlevel 4) */
|
||||
#define XCHAL_INT31_EXTNUM 25 /* (intlevel 5) */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
EXCEPTIONS and VECTORS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
|
||||
number: 1 == XEA1 (old)
|
||||
2 == XEA2 (new)
|
||||
0 == XEAX (extern) or TX */
|
||||
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
|
||||
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
|
||||
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
|
||||
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
|
||||
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
|
||||
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
|
||||
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
|
||||
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
|
||||
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
|
||||
#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */
|
||||
#define XCHAL_VECBASE_RESET_PADDR 0x40000000
|
||||
#define XCHAL_RESET_VECBASE_OVERLAP 0
|
||||
|
||||
#define XCHAL_RESET_VECTOR0_VADDR 0x50000000
|
||||
#define XCHAL_RESET_VECTOR0_PADDR 0x50000000
|
||||
#define XCHAL_RESET_VECTOR1_VADDR 0x40000400
|
||||
#define XCHAL_RESET_VECTOR1_PADDR 0x40000400
|
||||
#define XCHAL_RESET_VECTOR_VADDR 0x40000400
|
||||
#define XCHAL_RESET_VECTOR_PADDR 0x40000400
|
||||
#define XCHAL_USER_VECOFS 0x00000340
|
||||
#define XCHAL_USER_VECTOR_VADDR 0x40000340
|
||||
#define XCHAL_USER_VECTOR_PADDR 0x40000340
|
||||
#define XCHAL_KERNEL_VECOFS 0x00000300
|
||||
#define XCHAL_KERNEL_VECTOR_VADDR 0x40000300
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR 0x40000300
|
||||
#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0
|
||||
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
|
||||
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
|
||||
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
|
||||
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
|
||||
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
|
||||
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
|
||||
#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000
|
||||
#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000
|
||||
#define XCHAL_INTLEVEL2_VECOFS 0x00000180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180
|
||||
#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0
|
||||
#define XCHAL_INTLEVEL4_VECOFS 0x00000200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200
|
||||
#define XCHAL_INTLEVEL5_VECOFS 0x00000240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240
|
||||
#define XCHAL_INTLEVEL6_VECOFS 0x00000280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280
|
||||
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
|
||||
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
|
||||
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
|
||||
#define XCHAL_NMI_VECOFS 0x000002C0
|
||||
#define XCHAL_NMI_VECTOR_VADDR 0x400002C0
|
||||
#define XCHAL_NMI_VECTOR_PADDR 0x400002C0
|
||||
#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
|
||||
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
|
||||
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
DEBUG MODULE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* Misc */
|
||||
#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
|
||||
|
||||
/* On-Chip Debug (OCD) */
|
||||
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
|
||||
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
|
||||
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
|
||||
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
|
||||
#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
|
||||
|
||||
/* TRAX (in core) */
|
||||
#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */
|
||||
#define XCHAL_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */
|
||||
#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */
|
||||
#define XCHAL_TRAX_ATB_WIDTH 32 /* ATB width (bits), 0=no ATB */
|
||||
#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
|
||||
|
||||
/* Perf counters */
|
||||
#define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MMU
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* See core-matmap.h header file for more details. */
|
||||
|
||||
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
|
||||
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
|
||||
#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
|
||||
#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
|
||||
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
|
||||
#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
|
||||
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
|
||||
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
|
||||
[autorefill] and protection)
|
||||
usable for an MMU-based OS */
|
||||
/* If none of the above last 4 are set, it's a custom TLB configuration. */
|
||||
|
||||
#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
|
||||
#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
|
||||
#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
|
||||
|
||||
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
|
||||
|
||||
|
||||
#endif /* _XTENSA_CORE_CONFIGURATION_H */
|
||||
|
||||
@@ -0,0 +1,318 @@
|
||||
/*
|
||||
* xtensa/config/core-matmap.h -- Memory access and translation mapping
|
||||
* parameters (CHAL) of the Xtensa processor core configuration.
|
||||
*
|
||||
* If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
|
||||
* this file) for more details.
|
||||
*
|
||||
* In the Xtensa processor products released to date, all parameters
|
||||
* defined in this file are derivable (at least in theory) from
|
||||
* information contained in the core-isa.h header file.
|
||||
* In particular, the following core configuration parameters are relevant:
|
||||
* XCHAL_HAVE_CACHEATTR
|
||||
* XCHAL_HAVE_MIMIC_CACHEATTR
|
||||
* XCHAL_HAVE_XLT_CACHEATTR
|
||||
* XCHAL_HAVE_PTP_MMU
|
||||
* XCHAL_ITLB_ARF_ENTRIES_LOG2
|
||||
* XCHAL_DTLB_ARF_ENTRIES_LOG2
|
||||
* XCHAL_DCACHE_IS_WRITEBACK
|
||||
* XCHAL_ICACHE_SIZE (presence of I-cache)
|
||||
* XCHAL_DCACHE_SIZE (presence of D-cache)
|
||||
* XCHAL_HW_VERSION_MAJOR
|
||||
* XCHAL_HW_VERSION_MINOR
|
||||
*/
|
||||
|
||||
/* Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
|
||||
#ifndef XTENSA_CONFIG_CORE_MATMAP_H
|
||||
#define XTENSA_CONFIG_CORE_MATMAP_H
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE (MEMORY ACCESS) ATTRIBUTES
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
|
||||
/* Cache Attribute encodings -- lists of access modes for each cache attribute: */
|
||||
#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_FAM_BYPASS XCHAL_SEP \
|
||||
XTHAL_FAM_BYPASS XCHAL_SEP \
|
||||
XTHAL_FAM_BYPASS XCHAL_SEP \
|
||||
XTHAL_FAM_BYPASS XCHAL_SEP \
|
||||
XTHAL_FAM_BYPASS XCHAL_SEP \
|
||||
XTHAL_FAM_BYPASS XCHAL_SEP \
|
||||
XTHAL_FAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_FAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_FAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_FAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_FAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_FAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_FAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_FAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_FAM_EXCEPTION
|
||||
#define XCHAL_LCA_LIST XTHAL_LAM_BYPASSG XCHAL_SEP \
|
||||
XTHAL_LAM_BYPASSG XCHAL_SEP \
|
||||
XTHAL_LAM_BYPASSG XCHAL_SEP \
|
||||
XTHAL_LAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_LAM_BYPASSG XCHAL_SEP \
|
||||
XTHAL_LAM_BYPASSG XCHAL_SEP \
|
||||
XTHAL_LAM_BYPASSG XCHAL_SEP \
|
||||
XTHAL_LAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_LAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_LAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_LAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_LAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_LAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_LAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_LAM_BYPASSG XCHAL_SEP \
|
||||
XTHAL_LAM_EXCEPTION
|
||||
#define XCHAL_SCA_LIST XTHAL_SAM_BYPASS XCHAL_SEP \
|
||||
XTHAL_SAM_BYPASS XCHAL_SEP \
|
||||
XTHAL_SAM_BYPASS XCHAL_SEP \
|
||||
XTHAL_SAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_SAM_BYPASS XCHAL_SEP \
|
||||
XTHAL_SAM_BYPASS XCHAL_SEP \
|
||||
XTHAL_SAM_BYPASS XCHAL_SEP \
|
||||
XTHAL_SAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_SAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_SAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_SAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_SAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_SAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_SAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_SAM_BYPASS XCHAL_SEP \
|
||||
XTHAL_SAM_EXCEPTION
|
||||
|
||||
|
||||
/*
|
||||
* Specific encoded cache attribute values of general interest.
|
||||
* If a specific cache mode is not available, the closest available
|
||||
* one is returned instead (eg. writethru instead of writeback,
|
||||
* bypass instead of writethru).
|
||||
*/
|
||||
#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */
|
||||
#define XCHAL_CA_BYPASSBUF 6 /* cache disabled (bypassed) bufferable mode */
|
||||
#define XCHAL_CA_WRITETHRU 2 /* cache enabled (write-through) mode */
|
||||
#define XCHAL_CA_WRITEBACK 2 /* cache enabled (write-back) mode */
|
||||
#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 0 /* write-back no-allocate availability */
|
||||
#define XCHAL_CA_WRITEBACK_NOALLOC 2 /* cache enabled (write-back no-allocate) mode */
|
||||
#define XCHAL_CA_BYPASS_RW 0 /* cache disabled (bypassed) mode (no exec) */
|
||||
#define XCHAL_CA_WRITETHRU_RW 0 /* cache enabled (write-through) mode (no exec) */
|
||||
#define XCHAL_CA_WRITEBACK_RW 0 /* cache enabled (write-back) mode (no exec) */
|
||||
#define XCHAL_CA_WRITEBACK_NOALLOC_RW 0 /* cache enabled (write-back no-allocate) mode (no exec) */
|
||||
#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */
|
||||
#define XCHAL_CA_ISOLATE 0 /* cache isolate (accesses go to cache not memory) mode */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MMU
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* General notes on MMU parameters.
|
||||
*
|
||||
* Terminology:
|
||||
* ASID = address-space ID (acts as an "extension" of virtual addresses)
|
||||
* VPN = virtual page number
|
||||
* PPN = physical page number
|
||||
* CA = encoded cache attribute (access modes)
|
||||
* TLB = translation look-aside buffer (term is stretched somewhat here)
|
||||
* I = instruction (fetch accesses)
|
||||
* D = data (load and store accesses)
|
||||
* way = each TLB (ITLB and DTLB) consists of a number of "ways"
|
||||
* that simultaneously match the virtual address of an access;
|
||||
* a TLB successfully translates a virtual address if exactly
|
||||
* one way matches the vaddr; if none match, it is a miss;
|
||||
* if multiple match, one gets a "multihit" exception;
|
||||
* each way can be independently configured in terms of number of
|
||||
* entries, page sizes, which fields are writable or constant, etc.
|
||||
* set = group of contiguous ways with exactly identical parameters
|
||||
* ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
|
||||
* from the page table and storing it in one of the auto-refill ways;
|
||||
* if this PTE load also misses, a miss exception is posted for s/w.
|
||||
* min-wired = a "min-wired" way can be used to map a single (minimum-sized)
|
||||
* page arbitrarily under program control; it has a single entry,
|
||||
* is non-auto-refill (some other way(s) must be auto-refill),
|
||||
* all its fields (VPN, PPN, ASID, CA) are all writable, and it
|
||||
* supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
|
||||
* restriction is that this be the only page size it supports).
|
||||
*
|
||||
* TLB way entries are virtually indexed.
|
||||
* TLB ways that support multiple page sizes:
|
||||
* - must have all writable VPN and PPN fields;
|
||||
* - can only use one page size at any given time (eg. setup at startup),
|
||||
* selected by the respective ITLBCFG or DTLBCFG special register,
|
||||
* whose bits n*4+3 .. n*4 index the list of page sizes for way n
|
||||
* (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
|
||||
* this list may be sparse for auto-refill ways because auto-refill
|
||||
* ways have independent lists of supported page sizes sharing a
|
||||
* common encoding with PTE entries; the encoding is the index into
|
||||
* this list; unsupported sizes for a given way are zero in the list;
|
||||
* selecting unsupported sizes results in undefined hardware behaviour;
|
||||
* - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
|
||||
*/
|
||||
|
||||
#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
|
||||
#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */
|
||||
#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
|
||||
#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
|
||||
#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */
|
||||
#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */
|
||||
|
||||
|
||||
/*** Instruction TLB: ***/
|
||||
|
||||
#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */
|
||||
#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
|
||||
#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */
|
||||
#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */
|
||||
|
||||
/* Way set to which each way belongs: */
|
||||
#define XCHAL_ITLB_WAY0_SET 0
|
||||
|
||||
/* Ways sets that are used by hardware auto-refill (ARF): */
|
||||
#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */
|
||||
|
||||
/* Way sets that are "min-wired" (see terminology comment above): */
|
||||
#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
|
||||
|
||||
|
||||
/* ITLB way set 0 (group of ways 0 thru 0): */
|
||||
#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
|
||||
#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
|
||||
#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
|
||||
#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
|
||||
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
|
||||
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
|
||||
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
/* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */
|
||||
#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000
|
||||
#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000
|
||||
#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000
|
||||
#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000
|
||||
#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000
|
||||
#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000
|
||||
#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000
|
||||
#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000
|
||||
/* Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero): */
|
||||
#define XCHAL_ITLB_SET0_E0_PPN_CONST 0x00000000
|
||||
#define XCHAL_ITLB_SET0_E1_PPN_CONST 0x20000000
|
||||
#define XCHAL_ITLB_SET0_E2_PPN_CONST 0x40000000
|
||||
#define XCHAL_ITLB_SET0_E3_PPN_CONST 0x60000000
|
||||
#define XCHAL_ITLB_SET0_E4_PPN_CONST 0x80000000
|
||||
#define XCHAL_ITLB_SET0_E5_PPN_CONST 0xA0000000
|
||||
#define XCHAL_ITLB_SET0_E6_PPN_CONST 0xC0000000
|
||||
#define XCHAL_ITLB_SET0_E7_PPN_CONST 0xE0000000
|
||||
/* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */
|
||||
#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02
|
||||
#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02
|
||||
|
||||
|
||||
/*** Data TLB: ***/
|
||||
|
||||
#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */
|
||||
#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
|
||||
#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */
|
||||
#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */
|
||||
|
||||
/* Way set to which each way belongs: */
|
||||
#define XCHAL_DTLB_WAY0_SET 0
|
||||
|
||||
/* Ways sets that are used by hardware auto-refill (ARF): */
|
||||
#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */
|
||||
|
||||
/* Way sets that are "min-wired" (see terminology comment above): */
|
||||
#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
|
||||
|
||||
|
||||
/* DTLB way set 0 (group of ways 0 thru 0): */
|
||||
#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
|
||||
#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
|
||||
#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
|
||||
#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
|
||||
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
|
||||
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
|
||||
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
/* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */
|
||||
#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000
|
||||
#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000
|
||||
#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000
|
||||
#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000
|
||||
#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000
|
||||
#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000
|
||||
#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000
|
||||
#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000
|
||||
/* Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero): */
|
||||
#define XCHAL_DTLB_SET0_E0_PPN_CONST 0x00000000
|
||||
#define XCHAL_DTLB_SET0_E1_PPN_CONST 0x20000000
|
||||
#define XCHAL_DTLB_SET0_E2_PPN_CONST 0x40000000
|
||||
#define XCHAL_DTLB_SET0_E3_PPN_CONST 0x60000000
|
||||
#define XCHAL_DTLB_SET0_E4_PPN_CONST 0x80000000
|
||||
#define XCHAL_DTLB_SET0_E5_PPN_CONST 0xA0000000
|
||||
#define XCHAL_DTLB_SET0_E6_PPN_CONST 0xC0000000
|
||||
#define XCHAL_DTLB_SET0_E7_PPN_CONST 0xE0000000
|
||||
/* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */
|
||||
#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02
|
||||
|
||||
|
||||
|
||||
|
||||
#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,38 @@
|
||||
/* Definitions for Xtensa instructions, types, and protos. */
|
||||
|
||||
/* Customer ID=11657; Build=0x5fe96; Copyright (c) 2003-2004 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
/* NOTE: This file exists only for backward compatibility with T1050
|
||||
and earlier Xtensa releases. It includes only a subset of the
|
||||
available header files. */
|
||||
|
||||
#ifndef _XTENSA_BASE_HEADER
|
||||
#define _XTENSA_BASE_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
#include <xtensa/tie/xt_misc.h>
|
||||
#include <xtensa/tie/xt_booleans.h>
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
#endif /* !_XTENSA_BASE_HEADER */
|
||||
@@ -0,0 +1,117 @@
|
||||
/*
|
||||
* Xtensa Special Register symbolic names
|
||||
*/
|
||||
|
||||
/* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
|
||||
|
||||
/* Customer ID=11657; Build=0x5fe96; Copyright (c) 1998-2002 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef XTENSA_SPECREG_H
|
||||
#define XTENSA_SPECREG_H
|
||||
|
||||
/* Include these special register bitfield definitions, for historical reasons: */
|
||||
#include <xtensa/corebits.h>
|
||||
|
||||
|
||||
/* Special registers: */
|
||||
#define LBEG 0
|
||||
#define LEND 1
|
||||
#define LCOUNT 2
|
||||
#define SAR 3
|
||||
#define BR 4
|
||||
#define SCOMPARE1 12
|
||||
#define ACCLO 16
|
||||
#define ACCHI 17
|
||||
#define MR_0 32
|
||||
#define MR_1 33
|
||||
#define MR_2 34
|
||||
#define MR_3 35
|
||||
#define WINDOWBASE 72
|
||||
#define WINDOWSTART 73
|
||||
#define IBREAKENABLE 96
|
||||
#define MEMCTL 97
|
||||
#define ATOMCTL 99
|
||||
#define DDR 104
|
||||
#define IBREAKA_0 128
|
||||
#define IBREAKA_1 129
|
||||
#define DBREAKA_0 144
|
||||
#define DBREAKA_1 145
|
||||
#define DBREAKC_0 160
|
||||
#define DBREAKC_1 161
|
||||
#define EPC_1 177
|
||||
#define EPC_2 178
|
||||
#define EPC_3 179
|
||||
#define EPC_4 180
|
||||
#define EPC_5 181
|
||||
#define EPC_6 182
|
||||
#define EPC_7 183
|
||||
#define DEPC 192
|
||||
#define EPS_2 194
|
||||
#define EPS_3 195
|
||||
#define EPS_4 196
|
||||
#define EPS_5 197
|
||||
#define EPS_6 198
|
||||
#define EPS_7 199
|
||||
#define EXCSAVE_1 209
|
||||
#define EXCSAVE_2 210
|
||||
#define EXCSAVE_3 211
|
||||
#define EXCSAVE_4 212
|
||||
#define EXCSAVE_5 213
|
||||
#define EXCSAVE_6 214
|
||||
#define EXCSAVE_7 215
|
||||
#define CPENABLE 224
|
||||
#define INTERRUPT 226
|
||||
#define INTENABLE 228
|
||||
#define PS 230
|
||||
#define VECBASE 231
|
||||
#define EXCCAUSE 232
|
||||
#define DEBUGCAUSE 233
|
||||
#define CCOUNT 234
|
||||
#define PRID 235
|
||||
#define ICOUNT 236
|
||||
#define ICOUNTLEVEL 237
|
||||
#define EXCVADDR 238
|
||||
#define CCOMPARE_0 240
|
||||
#define CCOMPARE_1 241
|
||||
#define CCOMPARE_2 242
|
||||
#define MISC_REG_0 244
|
||||
#define MISC_REG_1 245
|
||||
#define MISC_REG_2 246
|
||||
#define MISC_REG_3 247
|
||||
|
||||
/* Special cases (bases of special register series): */
|
||||
#define MR 32
|
||||
#define IBREAKA 128
|
||||
#define DBREAKA 144
|
||||
#define DBREAKC 160
|
||||
#define EPC 176
|
||||
#define EPS 192
|
||||
#define EXCSAVE 208
|
||||
#define CCOMPARE 240
|
||||
|
||||
/* Special names for read-only and write-only interrupt registers: */
|
||||
#define INTREAD 226
|
||||
#define INTSET 226
|
||||
#define INTCLEAR 227
|
||||
|
||||
#endif /* XTENSA_SPECREG_H */
|
||||
|
||||
@@ -0,0 +1,274 @@
|
||||
/*
|
||||
* xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
|
||||
*
|
||||
* NOTE: The location and contents of this file are highly subject to change.
|
||||
*
|
||||
* Source for configuration-independent binaries (which link in a
|
||||
* configuration-specific HAL library) must NEVER include this file.
|
||||
* The HAL itself has historically included this file in some instances,
|
||||
* but this is not appropriate either, because the HAL is meant to be
|
||||
* core-specific but system independent.
|
||||
*/
|
||||
|
||||
/* Customer ID=11657; Build=0x5fe96; Copyright (c) 2000-2010 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
|
||||
#ifndef XTENSA_CONFIG_SYSTEM_H
|
||||
#define XTENSA_CONFIG_SYSTEM_H
|
||||
|
||||
/*#include <xtensa/hal.h>*/
|
||||
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CONFIGURED SOFTWARE OPTIONS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */
|
||||
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
|
||||
|
||||
#define XSHAL_ABI XTHAL_ABI_WINDOWED /* (sw-only option, selected ABI) */
|
||||
/* The above maps to one of the following constants: */
|
||||
#define XTHAL_ABI_WINDOWED 0
|
||||
#define XTHAL_ABI_CALL0 1
|
||||
/* Alternatives: */
|
||||
/*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */
|
||||
/*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */
|
||||
|
||||
#define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */
|
||||
/* The above maps to one of the following constants: */
|
||||
#define XTHAL_CLIB_NEWLIB 0
|
||||
#define XTHAL_CLIB_UCLIBC 1
|
||||
#define XTHAL_CLIB_XCLIB 2
|
||||
/* Alternatives: */
|
||||
/*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */
|
||||
/*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */
|
||||
/*#define XSHAL_XCLIB 0*/ /* set if Xtensa C library selected */
|
||||
|
||||
#define XSHAL_USE_FLOATING_POINT 1
|
||||
|
||||
#define XSHAL_FLOATING_POINT_ABI 0
|
||||
|
||||
/* SW workarounds enabled for HW errata: */
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
DEVICE ADDRESSES
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Strange place to find these, but the configuration GUI
|
||||
* allows moving these around to account for various core
|
||||
* configurations. Specific boards (and their BSP software)
|
||||
* will have specific meanings for these components.
|
||||
*/
|
||||
|
||||
/* I/O Block areas: */
|
||||
#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000
|
||||
#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000
|
||||
#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000
|
||||
|
||||
#define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000
|
||||
#define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000
|
||||
#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
|
||||
|
||||
/* System ROM: */
|
||||
#define XSHAL_ROM_VADDR 0x50000000
|
||||
#define XSHAL_ROM_PADDR 0x50000000
|
||||
#define XSHAL_ROM_SIZE 0x01000000
|
||||
/* Largest available area (free of vectors): */
|
||||
#define XSHAL_ROM_AVAIL_VADDR 0x50000000
|
||||
#define XSHAL_ROM_AVAIL_VSIZE 0x01000000
|
||||
|
||||
/* System RAM: */
|
||||
#define XSHAL_RAM_VADDR 0x60000000
|
||||
#define XSHAL_RAM_PADDR 0x60000000
|
||||
#define XSHAL_RAM_VSIZE 0x20000000
|
||||
#define XSHAL_RAM_PSIZE 0x20000000
|
||||
#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
|
||||
/* Largest available area (free of vectors): */
|
||||
#define XSHAL_RAM_AVAIL_VADDR 0x60000000
|
||||
#define XSHAL_RAM_AVAIL_VSIZE 0x20000000
|
||||
|
||||
/*
|
||||
* Shadow system RAM (same device as system RAM, at different address).
|
||||
* (Emulation boards need this for the SONIC Ethernet driver
|
||||
* when data caches are configured for writeback mode.)
|
||||
* NOTE: on full MMU configs, this points to the BYPASS virtual address
|
||||
* of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
|
||||
* addresses are viewed through the BYPASS static map rather than
|
||||
* the CACHED static map.
|
||||
*/
|
||||
#define XSHAL_RAM_BYPASS_VADDR 0xA0000000
|
||||
#define XSHAL_RAM_BYPASS_PADDR 0xA0000000
|
||||
#define XSHAL_RAM_BYPASS_PSIZE 0x20000000
|
||||
|
||||
/* Alternate system RAM (different device than system RAM): */
|
||||
/*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/
|
||||
/*#define XSHAL_ALTRAM_SIZE ...not configured...*/
|
||||
|
||||
/* Some available location in which to place devices in a simulation (eg. XTMP): */
|
||||
#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000
|
||||
#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000
|
||||
#define XSHAL_SIMIO_PADDR 0xC0000000
|
||||
#define XSHAL_SIMIO_SIZE 0x20000000
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* For use by reference testbench exit and diagnostic routines.
|
||||
*/
|
||||
#define XSHAL_MAGIC_EXIT 0x0
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* DEVICE-ADDRESS DEPENDENT...
|
||||
*
|
||||
* Values written to CACHEATTR special register (or its equivalent)
|
||||
* to enable and disable caches in various modes.
|
||||
*----------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
BACKWARD COMPATIBILITY ...
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* NOTE: the following two macros are DEPRECATED. Use the latter
|
||||
* board-specific macros instead, which are specially tuned for the
|
||||
* particular target environments' memory maps.
|
||||
*/
|
||||
#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
|
||||
#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
GENERIC
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* For the following, a 512MB region is used if it contains a system (PIF) RAM,
|
||||
* system (PIF) ROM, local memory, or XLMI. */
|
||||
|
||||
/* These set any unused 512MB region to cache-BYPASS attribute: */
|
||||
#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22221112 /* enable caches in write-back mode */
|
||||
#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22221112 /* enable caches in write-allocate mode */
|
||||
#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22221112 /* enable caches in write-through mode */
|
||||
#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */
|
||||
#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */
|
||||
|
||||
/* These set any unused 512MB region to ILLEGAL attribute: */
|
||||
#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFFFF111F /* enable caches in write-back mode */
|
||||
#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFF111F /* enable caches in write-allocate mode */
|
||||
#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFFFF111F /* enable caches in write-through mode */
|
||||
#define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFF222F /* disable caches in bypass mode */
|
||||
#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */
|
||||
|
||||
/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch
|
||||
* NULL-pointer dereference bugs; all other unused 512MB regions are set
|
||||
* to cache-BYPASS attribute: */
|
||||
#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222111F /* enable caches in write-back mode */
|
||||
#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2222111F /* enable caches in write-allocate mode */
|
||||
#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2222111F /* enable caches in write-through mode */
|
||||
#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
|
||||
#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
ISS (Instruction Set Simulator) SPECIFIC ...
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* For now, ISS defaults to the TRAPNULL settings: */
|
||||
#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
|
||||
#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
|
||||
#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
|
||||
#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS
|
||||
#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
|
||||
|
||||
#define XSHAL_ISS_PIPE_REGIONS 0
|
||||
#define XSHAL_ISS_SDRAM_REGIONS 0
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
XT2000 BOARD SPECIFIC ...
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* For the following, a 512MB region is used if it contains any system RAM,
|
||||
* system ROM, local memory, XLMI, or other XT2000 board device or memory.
|
||||
* Regions containing devices are forced to cache-BYPASS mode regardless
|
||||
* of whether the macro is _WRITEBACK vs. _BYPASS etc. */
|
||||
|
||||
/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */
|
||||
#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF22111F /* enable caches in write-back mode */
|
||||
#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF22111F /* enable caches in write-allocate mode */
|
||||
#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF22111F /* enable caches in write-through mode */
|
||||
#define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */
|
||||
#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */
|
||||
|
||||
#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */
|
||||
#define XSHAL_XT2000_SDRAM_REGIONS 0x00000440 /* BusInt SDRAM regions */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
VECTOR INFO AND SIZES
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XSHAL_VECTORS_PACKED 0
|
||||
#define XSHAL_STATIC_VECTOR_SELECT 1
|
||||
#define XSHAL_RESET_VECTOR_VADDR 0x40000400
|
||||
#define XSHAL_RESET_VECTOR_PADDR 0x40000400
|
||||
|
||||
/*
|
||||
* Sizes allocated to vectors by the system (memory map) configuration.
|
||||
* These sizes are constrained by core configuration (eg. one vector's
|
||||
* code cannot overflow into another vector) but are dependent on the
|
||||
* system or board (or LSP) memory map configuration.
|
||||
*
|
||||
* Whether or not each vector happens to be in a system ROM is also
|
||||
* a system configuration matter, sometimes useful, included here also:
|
||||
*/
|
||||
#define XSHAL_RESET_VECTOR_SIZE 0x00000300
|
||||
#define XSHAL_RESET_VECTOR_ISROM 0
|
||||
#define XSHAL_USER_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_USER_VECTOR_ISROM 0
|
||||
#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
|
||||
#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
|
||||
#define XSHAL_KERNEL_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_KERNEL_VECTOR_ISROM 0
|
||||
#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
|
||||
#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
|
||||
#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040
|
||||
#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
|
||||
#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178
|
||||
#define XSHAL_WINDOW_VECTORS_ISROM 0
|
||||
#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
|
||||
#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
|
||||
#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_INTLEVEL4_VECTOR_ISROM 0
|
||||
#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_INTLEVEL5_VECTOR_ISROM 0
|
||||
#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_INTLEVEL6_VECTOR_ISROM 0
|
||||
#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE
|
||||
#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM
|
||||
#define XSHAL_NMI_VECTOR_SIZE 0x00000038
|
||||
#define XSHAL_NMI_VECTOR_ISROM 0
|
||||
#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE
|
||||
|
||||
|
||||
#endif /*XTENSA_CONFIG_SYSTEM_H*/
|
||||
|
||||
@@ -0,0 +1,323 @@
|
||||
/*
|
||||
* tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
|
||||
*
|
||||
* NOTE: This header file is not meant to be included directly.
|
||||
*/
|
||||
|
||||
/* This header file contains assembly-language definitions (assembly
|
||||
macros, etc.) for this specific Xtensa processor's TIE extensions
|
||||
and options. It is customized to this Xtensa processor configuration.
|
||||
|
||||
Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef _XTENSA_CORE_TIE_ASM_H
|
||||
#define _XTENSA_CORE_TIE_ASM_H
|
||||
|
||||
/* Selection parameter values for save-area save/restore macros: */
|
||||
/* Option vs. TIE: */
|
||||
#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
|
||||
#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
|
||||
#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
|
||||
/* Whether used automatically by compiler: */
|
||||
#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
|
||||
#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
|
||||
#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
|
||||
/* ABI handling across function calls: */
|
||||
#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
|
||||
#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
|
||||
#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
|
||||
#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
|
||||
/* Misc */
|
||||
#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
|
||||
#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
|
||||
| ((ccuse) & XTHAL_SAS_ANYCC) \
|
||||
| ((abi) & XTHAL_SAS_ANYABI) )
|
||||
|
||||
|
||||
/*
|
||||
* Macro to store all non-coprocessor (extra) custom TIE and optional state
|
||||
* (not including zero-overhead loop registers).
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 4 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters:
|
||||
* continue If macro invoked as part of a larger store sequence, set to 1
|
||||
* if this is not the first in the sequence. Defaults to 0.
|
||||
* ofs Offset from start of larger sequence (from value of first ptr
|
||||
* in sequence) at which to store. Defaults to next available space
|
||||
* (or 0 if <continue> is 0).
|
||||
* select Select what category(ies) of registers to store, as a bitmask
|
||||
* (see XTHAL_SAS_xxx constants). Defaults to all registers.
|
||||
* alloc Select what category(ies) of registers to allocate; if any
|
||||
* category is selected here that is not in <select>, space for
|
||||
* the corresponding registers is skipped without doing any store.
|
||||
*/
|
||||
.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Optional global registers used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
rur.THREADPTR \at1 // threadptr option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
// Optional caller-saved registers used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1012, 4, 4
|
||||
rsr.ACCLO \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
rsr.ACCHI \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1012, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.endif
|
||||
// Optional caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 996, 4, 4
|
||||
rsr.BR \at1 // boolean option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
rsr.SCOMPARE1 \at1 // conditional store option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
rsr.M0 \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+8
|
||||
rsr.M1 \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+12
|
||||
rsr.M2 \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+16
|
||||
rsr.M3 \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+20
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 996, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.endif
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1008, 4, 4
|
||||
rur.F64R_LO \at1 // ureg 234
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
rur.F64R_HI \at1 // ureg 235
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
rur.F64S \at1 // ureg 236
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+8
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1008, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
|
||||
.endif
|
||||
.endm // xchal_ncp_store
|
||||
|
||||
/*
|
||||
* Macro to load all non-coprocessor (extra) custom TIE and optional state
|
||||
* (not including zero-overhead loop registers).
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 4 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters:
|
||||
* continue If macro invoked as part of a larger load sequence, set to 1
|
||||
* if this is not the first in the sequence. Defaults to 0.
|
||||
* ofs Offset from start of larger sequence (from value of first ptr
|
||||
* in sequence) at which to load. Defaults to next available space
|
||||
* (or 0 if <continue> is 0).
|
||||
* select Select what category(ies) of registers to load, as a bitmask
|
||||
* (see XTHAL_SAS_xxx constants). Defaults to all registers.
|
||||
* alloc Select what category(ies) of registers to allocate; if any
|
||||
* category is selected here that is not in <select>, space for
|
||||
* the corresponding registers is skipped without doing any load.
|
||||
*/
|
||||
.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Optional global registers used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
wur.THREADPTR \at1 // threadptr option
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
// Optional caller-saved registers used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1012, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
wsr.ACCLO \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
wsr.ACCHI \at1 // MAC16 option
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1012, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.endif
|
||||
// Optional caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 996, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
wsr.BR \at1 // boolean option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
wsr.SCOMPARE1 \at1 // conditional store option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+8
|
||||
wsr.M0 \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+12
|
||||
wsr.M1 \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+16
|
||||
wsr.M2 \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+20
|
||||
wsr.M3 \at1 // MAC16 option
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 996, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.endif
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1008, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
wur.F64R_LO \at1 // ureg 234
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
wur.F64R_HI \at1 // ureg 235
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+8
|
||||
wur.F64S \at1 // ureg 236
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1008, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
|
||||
.endif
|
||||
.endm // xchal_ncp_load
|
||||
|
||||
|
||||
#define XCHAL_NCP_NUM_ATMPS 1
|
||||
|
||||
/*
|
||||
* Macro to store the state of TIE coprocessor FPU.
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 4 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters are the same as for xchal_ncp_store.
|
||||
*/
|
||||
#define xchal_cp_FPU_store xchal_cp0_store
|
||||
.macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 948, 4, 4
|
||||
rur.FCR \at1 // ureg 232
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
rur.FSR \at1 // ureg 233
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
ssi f0, \ptr, .Lxchal_ofs_+8
|
||||
ssi f1, \ptr, .Lxchal_ofs_+12
|
||||
ssi f2, \ptr, .Lxchal_ofs_+16
|
||||
ssi f3, \ptr, .Lxchal_ofs_+20
|
||||
ssi f4, \ptr, .Lxchal_ofs_+24
|
||||
ssi f5, \ptr, .Lxchal_ofs_+28
|
||||
ssi f6, \ptr, .Lxchal_ofs_+32
|
||||
ssi f7, \ptr, .Lxchal_ofs_+36
|
||||
ssi f8, \ptr, .Lxchal_ofs_+40
|
||||
ssi f9, \ptr, .Lxchal_ofs_+44
|
||||
ssi f10, \ptr, .Lxchal_ofs_+48
|
||||
ssi f11, \ptr, .Lxchal_ofs_+52
|
||||
ssi f12, \ptr, .Lxchal_ofs_+56
|
||||
ssi f13, \ptr, .Lxchal_ofs_+60
|
||||
ssi f14, \ptr, .Lxchal_ofs_+64
|
||||
ssi f15, \ptr, .Lxchal_ofs_+68
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 948, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
|
||||
.endif
|
||||
.endm // xchal_cp0_store
|
||||
|
||||
/*
|
||||
* Macro to load the state of TIE coprocessor FPU.
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 4 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters are the same as for xchal_ncp_load.
|
||||
*/
|
||||
#define xchal_cp_FPU_load xchal_cp0_load
|
||||
.macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 948, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
wur.FCR \at1 // ureg 232
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
wur.FSR \at1 // ureg 233
|
||||
lsi f0, \ptr, .Lxchal_ofs_+8
|
||||
lsi f1, \ptr, .Lxchal_ofs_+12
|
||||
lsi f2, \ptr, .Lxchal_ofs_+16
|
||||
lsi f3, \ptr, .Lxchal_ofs_+20
|
||||
lsi f4, \ptr, .Lxchal_ofs_+24
|
||||
lsi f5, \ptr, .Lxchal_ofs_+28
|
||||
lsi f6, \ptr, .Lxchal_ofs_+32
|
||||
lsi f7, \ptr, .Lxchal_ofs_+36
|
||||
lsi f8, \ptr, .Lxchal_ofs_+40
|
||||
lsi f9, \ptr, .Lxchal_ofs_+44
|
||||
lsi f10, \ptr, .Lxchal_ofs_+48
|
||||
lsi f11, \ptr, .Lxchal_ofs_+52
|
||||
lsi f12, \ptr, .Lxchal_ofs_+56
|
||||
lsi f13, \ptr, .Lxchal_ofs_+60
|
||||
lsi f14, \ptr, .Lxchal_ofs_+64
|
||||
lsi f15, \ptr, .Lxchal_ofs_+68
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 948, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
|
||||
.endif
|
||||
.endm // xchal_cp0_load
|
||||
|
||||
#define XCHAL_CP0_NUM_ATMPS 1
|
||||
#define XCHAL_SA_NUM_ATMPS 1
|
||||
|
||||
/* Empty macros for unconfigured coprocessors: */
|
||||
.macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
|
||||
#endif /*_XTENSA_CORE_TIE_ASM_H*/
|
||||
|
||||
@@ -0,0 +1,182 @@
|
||||
/*
|
||||
* tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
|
||||
*
|
||||
* NOTE: This header file is not meant to be included directly.
|
||||
*/
|
||||
|
||||
/* This header file describes this specific Xtensa processor's TIE extensions
|
||||
that extend basic Xtensa core functionality. It is customized to this
|
||||
Xtensa processor configuration.
|
||||
|
||||
Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef _XTENSA_CORE_TIE_H
|
||||
#define _XTENSA_CORE_TIE_H
|
||||
|
||||
#define XCHAL_CP_NUM 1 /* number of coprocessors */
|
||||
#define XCHAL_CP_MAX 1 /* max CP ID + 1 (0 if none) */
|
||||
#define XCHAL_CP_MASK 0x01 /* bitmask of all CPs by ID */
|
||||
#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
|
||||
|
||||
/* Basic parameters of each coprocessor: */
|
||||
#define XCHAL_CP0_NAME "FPU"
|
||||
#define XCHAL_CP0_IDENT FPU
|
||||
#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */
|
||||
#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */
|
||||
#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
|
||||
|
||||
/* Filler info for unassigned coprocessors, to simplify arrays etc: */
|
||||
#define XCHAL_CP1_SA_SIZE 0
|
||||
#define XCHAL_CP1_SA_ALIGN 1
|
||||
#define XCHAL_CP2_SA_SIZE 0
|
||||
#define XCHAL_CP2_SA_ALIGN 1
|
||||
#define XCHAL_CP3_SA_SIZE 0
|
||||
#define XCHAL_CP3_SA_ALIGN 1
|
||||
#define XCHAL_CP4_SA_SIZE 0
|
||||
#define XCHAL_CP4_SA_ALIGN 1
|
||||
#define XCHAL_CP5_SA_SIZE 0
|
||||
#define XCHAL_CP5_SA_ALIGN 1
|
||||
#define XCHAL_CP6_SA_SIZE 0
|
||||
#define XCHAL_CP6_SA_ALIGN 1
|
||||
#define XCHAL_CP7_SA_SIZE 0
|
||||
#define XCHAL_CP7_SA_ALIGN 1
|
||||
|
||||
/* Save area for non-coprocessor optional and custom (TIE) state: */
|
||||
#define XCHAL_NCP_SA_SIZE 48
|
||||
#define XCHAL_NCP_SA_ALIGN 4
|
||||
|
||||
/* Total save area for optional and custom state (NCP + CPn): */
|
||||
#define XCHAL_TOTAL_SA_SIZE 128 /* with 16-byte align padding */
|
||||
#define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
|
||||
|
||||
/*
|
||||
* Detailed contents of save areas.
|
||||
* NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
|
||||
* before expanding the XCHAL_xxx_SA_LIST() macros.
|
||||
*
|
||||
* XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
|
||||
* dbnum,base,regnum,bitsz,gapsz,reset,x...)
|
||||
*
|
||||
* s = passed from XCHAL_*_LIST(s), eg. to select how to expand
|
||||
* ccused = set if used by compiler without special options or code
|
||||
* abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
|
||||
* kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
|
||||
* opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
|
||||
* name = lowercase reg name (no quotes)
|
||||
* galign = group byte alignment (power of 2) (galign >= align)
|
||||
* align = register byte alignment (power of 2)
|
||||
* asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
|
||||
* (not including any pad bytes required to galign this or next reg)
|
||||
* dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
|
||||
* base = reg shortname w/o index (or sr=special, ur=TIE user reg)
|
||||
* regnum = reg index in regfile, or special/TIE-user reg number
|
||||
* bitsz = number of significant bits (regfile width, or ur/sr mask bits)
|
||||
* gapsz = intervening bits, if bitsz bits not stored contiguously
|
||||
* (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
|
||||
* reset = register reset value (or 0 if undefined at reset)
|
||||
* x = reserved for future use (0 until then)
|
||||
*
|
||||
* To filter out certain registers, e.g. to expand only the non-global
|
||||
* registers used by the compiler, you can do something like this:
|
||||
*
|
||||
* #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
|
||||
* #define SELCC0(p...)
|
||||
* #define SELCC1(abikind,p...) SELAK##abikind(p)
|
||||
* #define SELAK0(p...) REG(p)
|
||||
* #define SELAK1(p...) REG(p)
|
||||
* #define SELAK2(p...)
|
||||
* #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
|
||||
* ...what you want to expand...
|
||||
*/
|
||||
|
||||
#define XCHAL_NCP_SA_NUM 12
|
||||
#define XCHAL_NCP_SA_LIST(s) \
|
||||
XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, f64r_lo, 4, 4, 4,0x03EA, ur,234, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, f64r_hi, 4, 4, 4,0x03EB, ur,235, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, f64s, 4, 4, 4,0x03EC, ur,236, 32,0,0,0)
|
||||
|
||||
#define XCHAL_CP0_SA_NUM 18
|
||||
#define XCHAL_CP0_SA_LIST(s) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0)
|
||||
|
||||
#define XCHAL_CP1_SA_NUM 0
|
||||
#define XCHAL_CP1_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP2_SA_NUM 0
|
||||
#define XCHAL_CP2_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP3_SA_NUM 0
|
||||
#define XCHAL_CP3_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP4_SA_NUM 0
|
||||
#define XCHAL_CP4_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP5_SA_NUM 0
|
||||
#define XCHAL_CP5_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP6_SA_NUM 0
|
||||
#define XCHAL_CP6_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP7_SA_NUM 0
|
||||
#define XCHAL_CP7_SA_LIST(s) /* empty */
|
||||
|
||||
/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
|
||||
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
|
||||
/* Byte length of instruction from its first byte, per FLIX. */
|
||||
#define XCHAL_BYTE0_FORMAT_LENGTHS \
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
|
||||
|
||||
#endif /*_XTENSA_CORE_TIE_H*/
|
||||
|
||||
+456
@@ -0,0 +1,456 @@
|
||||
/*
|
||||
* xtensa/core-macros.h -- C specific definitions
|
||||
* that depend on CORE configuration
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012 Tensilica Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef XTENSA_CACHE_H
|
||||
#define XTENSA_CACHE_H
|
||||
|
||||
#include <xtensa/config/core.h>
|
||||
|
||||
/* Only define things for C code. */
|
||||
#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
|
||||
|
||||
|
||||
|
||||
/*************************** CACHE ***************************/
|
||||
|
||||
/* All the macros are in the lower case now and some of them
|
||||
* share the name with the existing functions from hal.h.
|
||||
* Including this header file will define XTHAL_USE_CACHE_MACROS
|
||||
* which directs hal.h not to use the functions.
|
||||
*
|
||||
|
||||
/*
|
||||
* Single-cache-line operations in C-callable inline assembly.
|
||||
* Essentially macro versions (uppercase) of:
|
||||
*
|
||||
* xthal_icache_line_invalidate(void *addr);
|
||||
* xthal_icache_line_lock(void *addr);
|
||||
* xthal_icache_line_unlock(void *addr);
|
||||
* xthal_icache_sync(void);
|
||||
*
|
||||
* NOTE: unlike the above functions, the following macros do NOT
|
||||
* execute the xthal_icache_sync() as part of each line operation.
|
||||
* This sync must be called explicitly by the caller. This is to
|
||||
* allow better optimization when operating on more than one line.
|
||||
*
|
||||
* xthal_dcache_line_invalidate(void *addr);
|
||||
* xthal_dcache_line_writeback(void *addr);
|
||||
* xthal_dcache_line_writeback_inv(void *addr);
|
||||
* xthal_dcache_line_lock(void *addr);
|
||||
* xthal_dcache_line_unlock(void *addr);
|
||||
* xthal_dcache_sync(void);
|
||||
* xthal_dcache_line_prefetch_for_write(void *addr);
|
||||
* xthal_dcache_line_prefetch_for_read(void *addr);
|
||||
*
|
||||
* All are made memory-barriers, given that's how they're typically used
|
||||
* (ops operate on a whole line, so clobbers all memory not just *addr).
|
||||
*
|
||||
* NOTE: All the block block cache ops and line prefetches are implemented
|
||||
* using intrinsics so they are better optimized regarding memory barriers etc.
|
||||
*
|
||||
* All block downgrade functions exist in two forms: with and without
|
||||
* the 'max' parameter: This parameter allows compiler to optimize
|
||||
* the functions whenever the parameter is smaller than the cache size.
|
||||
*
|
||||
* xthal_dcache_block_invalidate(void *addr, unsigned size);
|
||||
* xthal_dcache_block_writeback(void *addr, unsigned size);
|
||||
* xthal_dcache_block_writeback_inv(void *addr, unsigned size);
|
||||
* xthal_dcache_block_invalidate_max(void *addr, unsigned size, unsigned max);
|
||||
* xthal_dcache_block_writeback_max(void *addr, unsigned size, unsigned max);
|
||||
* xthal_dcache_block_writeback_inv_max(void *addr, unsigned size, unsigned max);
|
||||
*
|
||||
* xthal_dcache_block_prefetch_for_read(void *addr, unsigned size);
|
||||
* xthal_dcache_block_prefetch_for_write(void *addr, unsigned size);
|
||||
* xthal_dcache_block_prefetch_modify(void *addr, unsigned size);
|
||||
* xthal_dcache_block_prefetch_read_write(void *addr, unsigned size);
|
||||
* xthal_dcache_block_prefetch_for_read_grp(void *addr, unsigned size);
|
||||
* xthal_dcache_block_prefetch_for_write_grp(void *addr, unsigned size);
|
||||
* xthal_dcache_block_prefetch_modify_grp(void *addr, unsigned size);
|
||||
* xthal_dcache_block_prefetch_read_write_grp(void *addr, unsigned size)
|
||||
*
|
||||
* xthal_dcache_block_wait();
|
||||
* xthal_dcache_block_required_wait();
|
||||
* xthal_dcache_block_abort();
|
||||
* xthal_dcache_block_prefetch_end();
|
||||
* xthal_dcache_block_newgrp();
|
||||
*/
|
||||
|
||||
/*** INSTRUCTION CACHE ***/
|
||||
|
||||
#define XTHAL_USE_CACHE_MACROS
|
||||
|
||||
#if XCHAL_ICACHE_SIZE > 0
|
||||
# define xthal_icache_line_invalidate(addr) do { void *__a = (void*)(addr); \
|
||||
__asm__ __volatile__("ihi %0, 0" :: "a"(__a) : "memory"); \
|
||||
} while(0)
|
||||
#else
|
||||
# define xthal_icache_line_invalidate(addr) do {/*nothing*/} while(0)
|
||||
#endif
|
||||
|
||||
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
|
||||
# define xthal_icache_line_lock(addr) do { void *__a = (void*)(addr); \
|
||||
__asm__ __volatile__("ipfl %0, 0" :: "a"(__a) : "memory"); \
|
||||
} while(0)
|
||||
# define xthal_icache_line_unlock(addr) do { void *__a = (void*)(addr); \
|
||||
__asm__ __volatile__("ihu %0, 0" :: "a"(__a) : "memory"); \
|
||||
} while(0)
|
||||
#else
|
||||
# define xthal_icache_line_lock(addr) do {/*nothing*/} while(0)
|
||||
# define xthal_icache_line_unlock(addr) do {/*nothing*/} while(0)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Even if a config doesn't have caches, an isync is still needed
|
||||
* when instructions in any memory are modified, whether by a loader
|
||||
* or self-modifying code. Therefore, this macro always produces
|
||||
* an isync, whether or not an icache is present.
|
||||
*/
|
||||
#define xthal_icache_sync() \
|
||||
__asm__ __volatile__("isync":::"memory")
|
||||
|
||||
|
||||
/*** DATA CACHE ***/
|
||||
|
||||
#if XCHAL_DCACHE_SIZE > 0
|
||||
|
||||
# include <xtensa/tie/xt_datacache.h>
|
||||
|
||||
# define xthal_dcache_line_invalidate(addr) do { void *__a = (void*)(addr); \
|
||||
__asm__ __volatile__("dhi %0, 0" :: "a"(__a) : "memory"); \
|
||||
} while(0)
|
||||
# define xthal_dcache_line_writeback(addr) do { void *__a = (void*)(addr); \
|
||||
__asm__ __volatile__("dhwb %0, 0" :: "a"(__a) : "memory"); \
|
||||
} while(0)
|
||||
# define xthal_dcache_line_writeback_inv(addr) do { void *__a = (void*)(addr); \
|
||||
__asm__ __volatile__("dhwbi %0, 0" :: "a"(__a) : "memory"); \
|
||||
} while(0)
|
||||
# define xthal_dcache_sync() \
|
||||
__asm__ __volatile__("" /*"dsync"?*/:::"memory")
|
||||
# define xthal_dcache_line_prefetch_for_read(addr) do { \
|
||||
XT_DPFR((const int*)addr, 0); \
|
||||
} while(0)
|
||||
#else
|
||||
# define xthal_dcache_line_invalidate(addr) do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_line_writeback(addr) do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_line_writeback_inv(addr) do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_sync() __asm__ __volatile__("":::"memory")
|
||||
# define xthal_dcache_line_prefetch_for_read(addr) do {/*nothing*/} while(0)
|
||||
#endif
|
||||
|
||||
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
|
||||
# define xthal_dcache_line_lock(addr) do { void *__a = (void*)(addr); \
|
||||
__asm__ __volatile__("dpfl %0, 0" :: "a"(__a) : "memory"); \
|
||||
} while(0)
|
||||
# define xthal_dcache_line_unlock(addr) do { void *__a = (void*)(addr); \
|
||||
__asm__ __volatile__("dhu %0, 0" :: "a"(__a) : "memory"); \
|
||||
} while(0)
|
||||
#else
|
||||
# define xthal_dcache_line_lock(addr) do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_line_unlock(addr) do {/*nothing*/} while(0)
|
||||
#endif
|
||||
|
||||
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
|
||||
|
||||
# define xthal_dcache_line_prefetch_for_write(addr) do { \
|
||||
XT_DPFW((const int*)addr, 0); \
|
||||
} while(0)
|
||||
#else
|
||||
# define xthal_dcache_line_prefetch_for_write(addr) do {/*nothing*/} while(0)
|
||||
#endif
|
||||
|
||||
|
||||
/***** Block Operations *****/
|
||||
|
||||
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_CACHE_BLOCKOPS
|
||||
|
||||
/* upgrades */
|
||||
|
||||
# define _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, type) \
|
||||
{ \
|
||||
type((const int*)addr, size); \
|
||||
}
|
||||
|
||||
/*downgrades */
|
||||
|
||||
# define _XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, type) \
|
||||
unsigned _s = size; \
|
||||
unsigned _a = addr; \
|
||||
do { \
|
||||
unsigned __s = (_s > XCHAL_DCACHE_SIZE) ? \
|
||||
XCHAL_DCACHE_SIZE : _s; \
|
||||
type((const int*)_a, __s); \
|
||||
_s -= __s; \
|
||||
_a += __s; \
|
||||
} while(_s > 0);
|
||||
|
||||
# define _XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, type, max) \
|
||||
if (max <= XCHAL_DCACHE_SIZE) { \
|
||||
unsigned _s = size; \
|
||||
unsigned _a = addr; \
|
||||
type((const int*)_a, _s); \
|
||||
} \
|
||||
else { \
|
||||
_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, type); \
|
||||
}
|
||||
|
||||
# define xthal_dcache_block_invalidate(addr, size) do { \
|
||||
_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHI_B); \
|
||||
} while(0)
|
||||
# define xthal_dcache_block_writeback(addr, size) do { \
|
||||
_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHWB_B); \
|
||||
} while(0)
|
||||
# define xthal_dcache_block_writeback_inv(addr, size) do { \
|
||||
_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHWBI_B); \
|
||||
} while(0)
|
||||
|
||||
# define xthal_dcache_block_invalidate_max(addr, size, max) do { \
|
||||
_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHI_B, max); \
|
||||
} while(0)
|
||||
# define xthal_dcache_block_writeback_max(addr, size, max) do { \
|
||||
_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHWB_B, max); \
|
||||
} while(0)
|
||||
# define xthal_dcache_block_writeback_inv_max(addr, size, max) do { \
|
||||
_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHWBI_B, max); \
|
||||
} while(0)
|
||||
|
||||
/* upgrades that are performed even with write-thru caches */
|
||||
|
||||
# define xthal_dcache_block_prefetch_read_write(addr, size) do { \
|
||||
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_B); \
|
||||
} while(0)
|
||||
# define xthal_dcache_block_prefetch_read_write_grp(addr, size) do { \
|
||||
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_BF); \
|
||||
} while(0)
|
||||
# define xthal_dcache_block_prefetch_for_read(addr, size) do { \
|
||||
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFR_B); \
|
||||
} while(0)
|
||||
# define xthal_dcache_block_prefetch_for_read_grp(addr, size) do { \
|
||||
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFR_BF); \
|
||||
} while(0)
|
||||
|
||||
/* abort all or end optional block cache operations */
|
||||
# define xthal_dcache_block_abort() do { \
|
||||
XT_PFEND_A(); \
|
||||
} while(0)
|
||||
# define xthal_dcache_block_end() do { \
|
||||
XT_PFEND_O(); \
|
||||
} while(0)
|
||||
|
||||
/* wait for all/required block cache operations to finish */
|
||||
# define xthal_dcache_block_wait() do { \
|
||||
XT_PFWAIT_A(); \
|
||||
} while(0)
|
||||
# define xthal_dcache_block_required_wait() do { \
|
||||
XT_PFWAIT_R(); \
|
||||
} while(0)
|
||||
/* Start a new group */
|
||||
# define xthal_dcache_block_newgrp() do { \
|
||||
XT_PFNXT_F(); \
|
||||
} while(0)
|
||||
#else
|
||||
# define xthal_dcache_block_invalidate(addr, size) do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_block_writeback(addr, size) do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_block_writeback_inv(addr, size) do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_block_invalidate_max(addr, size, max) do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_block_writeback_max(addr, size, max) do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_block_writeback_inv_max(addr, size, max) do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_block_prefetch_read_write(addr, size) do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_block_prefetch_read_write_grp(addr, size) do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_block_prefetch_for_read(addr, size) do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_block_prefetch_for_read_grp(addr, size) do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_block_end() do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_block_abort() do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_block_wait() do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_block_required_wait() do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_block_newgrp() do {/*nothing*/} while(0)
|
||||
#endif
|
||||
|
||||
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_CACHE_BLOCKOPS && XCHAL_DCACHE_IS_WRITEBACK
|
||||
|
||||
# define xthal_dcache_block_prefetch_for_write(addr, size) do { \
|
||||
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_B); \
|
||||
} while(0)
|
||||
# define xthal_dcache_block_prefetch_modify(addr, size) do { \
|
||||
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFM_B); \
|
||||
} while(0)
|
||||
# define xthal_dcache_block_prefetch_for_write_grp(addr, size) do { \
|
||||
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_BF); \
|
||||
} while(0)
|
||||
# define xthal_dcache_block_prefetch_modify_grp(addr, size) do { \
|
||||
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFM_BF); \
|
||||
} while(0)
|
||||
#else
|
||||
# define xthal_dcache_block_prefetch_for_write(addr, size) do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_block_prefetch_modify(addr, size) do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_block_prefetch_for_write_grp(addr, size) do {/*nothing*/} while(0)
|
||||
# define xthal_dcache_block_prefetch_modify_grp(addr, size) do {/*nothing*/} while(0)
|
||||
#endif
|
||||
|
||||
/*************************** INTERRUPTS ***************************/
|
||||
|
||||
/*
|
||||
* Macro versions of:
|
||||
* unsigned xthal_get_intenable( void );
|
||||
* void xthal_set_intenable( unsigned );
|
||||
* unsigned xthal_get_interrupt( void );
|
||||
* void xthal_set_intset( unsigned );
|
||||
* void xthal_set_intclear( unsigned );
|
||||
* unsigned xthal_get_ccount(void);
|
||||
* void xthal_set_ccompare(int, unsigned);
|
||||
* unsigned xthal_get_ccompare(int);
|
||||
*
|
||||
* NOTE: for {set,get}_ccompare, the first argument MUST be a decimal constant.
|
||||
*/
|
||||
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
# define XTHAL_GET_INTENABLE() ({ int __intenable; \
|
||||
__asm__("rsr.intenable %0" : "=a"(__intenable)); \
|
||||
__intenable; })
|
||||
# define XTHAL_SET_INTENABLE(v) do { int __intenable = (int)(v); \
|
||||
__asm__ __volatile__("wsr.intenable %0" :: "a"(__intenable):"memory"); \
|
||||
} while(0)
|
||||
# define XTHAL_GET_INTERRUPT() ({ int __interrupt; \
|
||||
__asm__("rsr.interrupt %0" : "=a"(__interrupt)); \
|
||||
__interrupt; })
|
||||
# define XTHAL_SET_INTSET(v) do { int __interrupt = (int)(v); \
|
||||
__asm__ __volatile__("wsr.intset %0" :: "a"(__interrupt):"memory"); \
|
||||
} while(0)
|
||||
# define XTHAL_SET_INTCLEAR(v) do { int __interrupt = (int)(v); \
|
||||
__asm__ __volatile__("wsr.intclear %0" :: "a"(__interrupt):"memory"); \
|
||||
} while(0)
|
||||
# define XTHAL_GET_CCOUNT() ({ int __ccount; \
|
||||
__asm__("rsr.ccount %0" : "=a"(__ccount)); \
|
||||
__ccount; })
|
||||
# define XTHAL_SET_CCOUNT(v) do { int __ccount = (int)(v); \
|
||||
__asm__ __volatile__("wsr.ccount %0" :: "a"(__ccount):"memory"); \
|
||||
} while(0)
|
||||
# define _XTHAL_GET_CCOMPARE(n) ({ int __ccompare; \
|
||||
__asm__("rsr.ccompare" #n " %0" : "=a"(__ccompare)); \
|
||||
__ccompare; })
|
||||
# define XTHAL_GET_CCOMPARE(n) _XTHAL_GET_CCOMPARE(n)
|
||||
# define _XTHAL_SET_CCOMPARE(n,v) do { int __ccompare = (int)(v); \
|
||||
__asm__ __volatile__("wsr.ccompare" #n " %0 ; esync" :: "a"(__ccompare):"memory"); \
|
||||
} while(0)
|
||||
# define XTHAL_SET_CCOMPARE(n,v) _XTHAL_SET_CCOMPARE(n,v)
|
||||
#else
|
||||
# define XTHAL_GET_INTENABLE() 0
|
||||
# define XTHAL_SET_INTENABLE(v) do {/*nothing*/} while(0)
|
||||
# define XTHAL_GET_INTERRUPT() 0
|
||||
# define XTHAL_SET_INTSET(v) do {/*nothing*/} while(0)
|
||||
# define XTHAL_SET_INTCLEAR(v) do {/*nothing*/} while(0)
|
||||
# define XTHAL_GET_CCOUNT() 0
|
||||
# define XTHAL_SET_CCOUNT(v) do {/*nothing*/} while(0)
|
||||
# define XTHAL_GET_CCOMPARE(n) 0
|
||||
# define XTHAL_SET_CCOMPARE(n,v) do {/*nothing*/} while(0)
|
||||
#endif
|
||||
|
||||
|
||||
/*************************** MISC ***************************/
|
||||
|
||||
/*
|
||||
* Macro or inline versions of:
|
||||
* void xthal_clear_regcached_code( void );
|
||||
* unsigned xthal_get_prid( void );
|
||||
* unsigned xthal_compare_and_set( int *addr, int testval, int setval );
|
||||
*/
|
||||
|
||||
#if XCHAL_HAVE_LOOPS
|
||||
# define XTHAL_CLEAR_REGCACHED_CODE() \
|
||||
__asm__ __volatile__("wsr.lcount %0" :: "a"(0) : "memory")
|
||||
#else
|
||||
# define XTHAL_CLEAR_REGCACHED_CODE() do {/*nothing*/} while(0)
|
||||
#endif
|
||||
|
||||
#if XCHAL_HAVE_PRID
|
||||
# define XTHAL_GET_PRID() ({ int __prid; \
|
||||
__asm__("rsr.prid %0" : "=a"(__prid)); \
|
||||
__prid; })
|
||||
#else
|
||||
# define XTHAL_GET_PRID() 0
|
||||
#endif
|
||||
|
||||
|
||||
static inline unsigned XTHAL_COMPARE_AND_SET( int *addr, int testval, int setval )
|
||||
{
|
||||
int result;
|
||||
|
||||
#if XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION_MAJOR >= 2200
|
||||
__asm__ __volatile__ (
|
||||
" wsr.scompare1 %2 \n"
|
||||
" s32c1i %0, %3, 0 \n"
|
||||
: "=a"(result) : "0" (setval), "a" (testval), "a" (addr)
|
||||
: "memory");
|
||||
#elif XCHAL_HAVE_INTERRUPTS
|
||||
int tmp;
|
||||
__asm__ __volatile__ (
|
||||
" rsil %4, 15 \n" // %4 == saved ps
|
||||
" l32i %0, %3, 0 \n" // %0 == value to test, return val
|
||||
" bne %2, %0, 9f \n" // test
|
||||
" s32i %1, %3, 0 \n" // write the new value
|
||||
"9: wsr.ps %4 ; rsync \n" // restore the PS
|
||||
: "=a"(result)
|
||||
: "0" (setval), "a" (testval), "a" (addr), "a" (tmp)
|
||||
: "memory");
|
||||
#else
|
||||
__asm__ __volatile__ (
|
||||
" l32i %0, %3, 0 \n" // %0 == value to test, return val
|
||||
" bne %2, %0, 9f \n" // test
|
||||
" s32i %1, %3, 0 \n" // write the new value
|
||||
"9: \n"
|
||||
: "=a"(result) : "0" (setval), "a" (testval), "a" (addr)
|
||||
: "memory");
|
||||
#endif
|
||||
return result;
|
||||
}
|
||||
|
||||
#if XCHAL_HAVE_EXTERN_REGS
|
||||
|
||||
static inline unsigned XTHAL_RER (unsigned int reg)
|
||||
{
|
||||
unsigned result;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
" rer %0, %1"
|
||||
: "=a" (result) : "a" (reg) : "memory");
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static inline void XTHAL_WER (unsigned reg, unsigned value)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
" wer %0, %1"
|
||||
: : "a" (value), "a" (reg) : "memory");
|
||||
}
|
||||
|
||||
#endif /* XCHAL_HAVE_EXTERN_REGS */
|
||||
|
||||
#endif /* C code */
|
||||
|
||||
#endif /*XTENSA_CACHE_H*/
|
||||
|
||||
Executable
+939
@@ -0,0 +1,939 @@
|
||||
/*
|
||||
* xtensa/coreasm.h -- assembler-specific definitions that depend on CORE configuration
|
||||
*
|
||||
* Source for configuration-independent binaries (which link in a
|
||||
* configuration-specific HAL library) must NEVER include this file.
|
||||
* It is perfectly normal, however, for the HAL itself to include this file.
|
||||
*
|
||||
* This file must NOT include xtensa/config/system.h. Any assembler
|
||||
* header file that depends on system information should likely go
|
||||
* in a new systemasm.h (or sysasm.h) header file.
|
||||
*
|
||||
* NOTE: macro beqi32 is NOT configuration-dependent, and is placed
|
||||
* here until we have a proper configuration-independent header file.
|
||||
*/
|
||||
|
||||
/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/coreasm.h#3 $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2000-2014 Tensilica Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef XTENSA_COREASM_H
|
||||
#define XTENSA_COREASM_H
|
||||
|
||||
/*
|
||||
* Tell header files this is assembly source, so they can avoid non-assembler
|
||||
* definitions (eg. C types etc):
|
||||
*/
|
||||
#ifndef _ASMLANGUAGE /* conditionalize to avoid cpp warnings (3rd parties might use same macro) */
|
||||
#define _ASMLANGUAGE
|
||||
#endif
|
||||
|
||||
#include <xtensa/config/core.h>
|
||||
#include <xtensa/config/specreg.h>
|
||||
#include <xtensa/config/system.h>
|
||||
|
||||
/*
|
||||
* Assembly-language specific definitions (assembly macros, etc.).
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* find_ms_setbit
|
||||
*
|
||||
* This macro finds the most significant bit that is set in <as>
|
||||
* and return its index + <base> in <ad>, or <base> - 1 if <as> is zero.
|
||||
* The index counts starting at zero for the lsbit, so the return
|
||||
* value ranges from <base>-1 (no bit set) to <base>+31 (msbit set).
|
||||
*
|
||||
* Parameters:
|
||||
* <ad> destination address register (any register)
|
||||
* <as> source address register
|
||||
* <at> temporary address register (must be different than <as>)
|
||||
* <base> constant value added to result (usually 0 or 1)
|
||||
* On entry:
|
||||
* <ad> = undefined if different than <as>
|
||||
* <as> = value whose most significant set bit is to be found
|
||||
* <at> = undefined
|
||||
* no other registers are used by this macro.
|
||||
* On exit:
|
||||
* <ad> = <base> + index of msbit set in original <as>,
|
||||
* = <base> - 1 if original <as> was zero.
|
||||
* <as> clobbered (if not <ad>)
|
||||
* <at> clobbered (if not <ad>)
|
||||
* Example:
|
||||
* find_ms_setbit a0, a4, a0, 0 -- return in a0 index of msbit set in a4
|
||||
*/
|
||||
|
||||
.macro find_ms_setbit ad, as, at, base
|
||||
#if XCHAL_HAVE_NSA
|
||||
movi \at, 31+\base
|
||||
nsau \as, \as // get index of \as, numbered from msbit (32 if absent)
|
||||
sub \ad, \at, \as // get numbering from lsbit (0..31, -1 if absent)
|
||||
#else /* XCHAL_HAVE_NSA */
|
||||
movi \at, \base // start with result of 0 (point to lsbit of 32)
|
||||
|
||||
beqz \as, 2f // special case for zero argument: return -1
|
||||
bltui \as, 0x10000, 1f // is it one of the 16 lsbits? (if so, check lower 16 bits)
|
||||
addi \at, \at, 16 // no, increment result to upper 16 bits (of 32)
|
||||
//srli \as, \as, 16 // check upper half (shift right 16 bits)
|
||||
extui \as, \as, 16, 16 // check upper half (shift right 16 bits)
|
||||
1: bltui \as, 0x100, 1f // is it one of the 8 lsbits? (if so, check lower 8 bits)
|
||||
addi \at, \at, 8 // no, increment result to upper 8 bits (of 16)
|
||||
srli \as, \as, 8 // shift right to check upper 8 bits
|
||||
1: bltui \as, 0x10, 1f // is it one of the 4 lsbits? (if so, check lower 4 bits)
|
||||
addi \at, \at, 4 // no, increment result to upper 4 bits (of 8)
|
||||
srli \as, \as, 4 // shift right 4 bits to check upper half
|
||||
1: bltui \as, 0x4, 1f // is it one of the 2 lsbits? (if so, check lower 2 bits)
|
||||
addi \at, \at, 2 // no, increment result to upper 2 bits (of 4)
|
||||
srli \as, \as, 2 // shift right 2 bits to check upper half
|
||||
1: bltui \as, 0x2, 1f // is it the lsbit?
|
||||
addi \at, \at, 2 // no, increment result to upper bit (of 2)
|
||||
2: addi \at, \at, -1 // (from just above: add 1; from beqz: return -1)
|
||||
//srli \as, \as, 1
|
||||
1: // done! \at contains index of msbit set (or -1 if none set)
|
||||
.if 0x\ad - 0x\at // destination different than \at ? (works because regs are a0-a15)
|
||||
mov \ad, \at // then move result to \ad
|
||||
.endif
|
||||
#endif /* XCHAL_HAVE_NSA */
|
||||
.endm // find_ms_setbit
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* find_ls_setbit
|
||||
*
|
||||
* This macro finds the least significant bit that is set in <as>,
|
||||
* and return its index in <ad>.
|
||||
* Usage is the same as for the find_ms_setbit macro.
|
||||
* Example:
|
||||
* find_ls_setbit a0, a4, a0, 0 -- return in a0 index of lsbit set in a4
|
||||
*/
|
||||
|
||||
.macro find_ls_setbit ad, as, at, base
|
||||
neg \at, \as // keep only the least-significant bit that is set...
|
||||
and \as, \at, \as // ... in \as
|
||||
find_ms_setbit \ad, \as, \at, \base
|
||||
.endm // find_ls_setbit
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* find_ls_one
|
||||
*
|
||||
* Same as find_ls_setbit with base zero.
|
||||
* Source (as) and destination (ad) registers must be different.
|
||||
* Provided for backward compatibility.
|
||||
*/
|
||||
|
||||
.macro find_ls_one ad, as
|
||||
find_ls_setbit \ad, \as, \ad, 0
|
||||
.endm // find_ls_one
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* floop, floopnez, floopgtz, floopend
|
||||
*
|
||||
* These macros are used for fast inner loops that
|
||||
* work whether or not the Loops options is configured.
|
||||
* If the Loops option is configured, they simply use
|
||||
* the zero-overhead LOOP instructions; otherwise
|
||||
* they use explicit decrement and branch instructions.
|
||||
*
|
||||
* They are used in pairs, with floop, floopnez or floopgtz
|
||||
* at the beginning of the loop, and floopend at the end.
|
||||
*
|
||||
* Each pair of loop macro calls must be given the loop count
|
||||
* address register and a unique label for that loop.
|
||||
*
|
||||
* Example:
|
||||
*
|
||||
* movi a3, 16 // loop 16 times
|
||||
* floop a3, myloop1
|
||||
* :
|
||||
* bnez a7, end1 // exit loop if a7 != 0
|
||||
* :
|
||||
* floopend a3, myloop1
|
||||
* end1:
|
||||
*
|
||||
* Like the LOOP instructions, these macros cannot be
|
||||
* nested, must include at least one instruction,
|
||||
* cannot call functions inside the loop, etc.
|
||||
* The loop can be exited by jumping to the instruction
|
||||
* following floopend (or elsewhere outside the loop),
|
||||
* or continued by jumping to a NOP instruction placed
|
||||
* immediately before floopend.
|
||||
*
|
||||
* Unlike LOOP instructions, the register passed to floop*
|
||||
* cannot be used inside the loop, because it is used as
|
||||
* the loop counter if the Loops option is not configured.
|
||||
* And its value is undefined after exiting the loop.
|
||||
* And because the loop counter register is active inside
|
||||
* the loop, you can't easily use this construct to loop
|
||||
* across a register file using ROTW as you might with LOOP
|
||||
* instructions, unless you copy the loop register along.
|
||||
*/
|
||||
|
||||
/* Named label version of the macros: */
|
||||
|
||||
.macro floop ar, endlabel
|
||||
floop_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
|
||||
.endm
|
||||
|
||||
.macro floopnez ar, endlabel
|
||||
floopnez_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
|
||||
.endm
|
||||
|
||||
.macro floopgtz ar, endlabel
|
||||
floopgtz_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
|
||||
.endm
|
||||
|
||||
.macro floopend ar, endlabel
|
||||
floopend_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
|
||||
.endm
|
||||
|
||||
/* Numbered local label version of the macros: */
|
||||
#if 0 /*UNTESTED*/
|
||||
.macro floop89 ar
|
||||
floop_ \ar, 8, 9f
|
||||
.endm
|
||||
|
||||
.macro floopnez89 ar
|
||||
floopnez_ \ar, 8, 9f
|
||||
.endm
|
||||
|
||||
.macro floopgtz89 ar
|
||||
floopgtz_ \ar, 8, 9f
|
||||
.endm
|
||||
|
||||
.macro floopend89 ar
|
||||
floopend_ \ar, 8b, 9
|
||||
.endm
|
||||
#endif /*0*/
|
||||
|
||||
/* Underlying version of the macros: */
|
||||
|
||||
.macro floop_ ar, startlabel, endlabelref
|
||||
.ifdef _infloop_
|
||||
.if _infloop_
|
||||
.err // Error: floop cannot be nested
|
||||
.endif
|
||||
.endif
|
||||
.set _infloop_, 1
|
||||
#if XCHAL_HAVE_LOOPS
|
||||
loop \ar, \endlabelref
|
||||
#else /* XCHAL_HAVE_LOOPS */
|
||||
\startlabel:
|
||||
addi \ar, \ar, -1
|
||||
#endif /* XCHAL_HAVE_LOOPS */
|
||||
.endm // floop_
|
||||
|
||||
.macro floopnez_ ar, startlabel, endlabelref
|
||||
.ifdef _infloop_
|
||||
.if _infloop_
|
||||
.err // Error: floopnez cannot be nested
|
||||
.endif
|
||||
.endif
|
||||
.set _infloop_, 1
|
||||
#if XCHAL_HAVE_LOOPS
|
||||
loopnez \ar, \endlabelref
|
||||
#else /* XCHAL_HAVE_LOOPS */
|
||||
beqz \ar, \endlabelref
|
||||
\startlabel:
|
||||
addi \ar, \ar, -1
|
||||
#endif /* XCHAL_HAVE_LOOPS */
|
||||
.endm // floopnez_
|
||||
|
||||
.macro floopgtz_ ar, startlabel, endlabelref
|
||||
.ifdef _infloop_
|
||||
.if _infloop_
|
||||
.err // Error: floopgtz cannot be nested
|
||||
.endif
|
||||
.endif
|
||||
.set _infloop_, 1
|
||||
#if XCHAL_HAVE_LOOPS
|
||||
loopgtz \ar, \endlabelref
|
||||
#else /* XCHAL_HAVE_LOOPS */
|
||||
bltz \ar, \endlabelref
|
||||
beqz \ar, \endlabelref
|
||||
\startlabel:
|
||||
addi \ar, \ar, -1
|
||||
#endif /* XCHAL_HAVE_LOOPS */
|
||||
.endm // floopgtz_
|
||||
|
||||
|
||||
.macro floopend_ ar, startlabelref, endlabel
|
||||
.ifndef _infloop_
|
||||
.err // Error: floopend without matching floopXXX
|
||||
.endif
|
||||
.ifeq _infloop_
|
||||
.err // Error: floopend without matching floopXXX
|
||||
.endif
|
||||
.set _infloop_, 0
|
||||
#if ! XCHAL_HAVE_LOOPS
|
||||
bnez \ar, \startlabelref
|
||||
#endif /* XCHAL_HAVE_LOOPS */
|
||||
\endlabel:
|
||||
.endm // floopend_
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* crsil -- conditional RSIL (read/set interrupt level)
|
||||
*
|
||||
* Executes the RSIL instruction if it exists, else just reads PS.
|
||||
* The RSIL instruction does not exist in the new exception architecture
|
||||
* if the interrupt option is not selected.
|
||||
*/
|
||||
|
||||
.macro crsil ar, newlevel
|
||||
#if XCHAL_HAVE_OLD_EXC_ARCH || XCHAL_HAVE_INTERRUPTS
|
||||
rsil \ar, \newlevel
|
||||
#else
|
||||
rsr \ar, PS
|
||||
#endif
|
||||
.endm // crsil
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* safe_movi_a0 -- move constant into a0 when L32R is not safe
|
||||
*
|
||||
* This macro is typically used by interrupt/exception handlers.
|
||||
* Loads a 32-bit constant in a0, without using any other register,
|
||||
* and without corrupting the LITBASE register, even when the
|
||||
* value of the LITBASE register is unknown (eg. when application
|
||||
* code and interrupt/exception handling code are built independently,
|
||||
* and thus with independent values of the LITBASE register;
|
||||
* debug monitors are one example of this).
|
||||
*
|
||||
* Worst-case size of resulting code: 17 bytes.
|
||||
*/
|
||||
|
||||
.macro safe_movi_a0 constant
|
||||
#if XCHAL_HAVE_ABSOLUTE_LITERALS
|
||||
/* Contort a PC-relative literal load even though we may be in litbase-relative mode: */
|
||||
j 1f
|
||||
.begin no-transform // ensure what follows is assembled exactly as-is
|
||||
.align 4 // ensure constant and call0 target ...
|
||||
.byte 0 // ... are 4-byte aligned (call0 instruction is 3 bytes long)
|
||||
1: call0 2f // read PC (that follows call0) in a0
|
||||
.long \constant // 32-bit constant to load into a0
|
||||
2:
|
||||
.end no-transform
|
||||
l32i a0, a0, 0 // load constant
|
||||
#else
|
||||
movi a0, \constant // no LITBASE, can assume PC-relative L32R
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* window_spill{4,8,12}
|
||||
*
|
||||
* These macros spill callers' register windows to the stack.
|
||||
* They work for both privileged and non-privileged tasks.
|
||||
* Must be called from a windowed ABI context, eg. within
|
||||
* a windowed ABI function (ie. valid stack frame, window
|
||||
* exceptions enabled, not in exception mode, etc).
|
||||
*
|
||||
* This macro requires a single invocation of the window_spill_common
|
||||
* macro in the same assembly unit and section.
|
||||
*
|
||||
* Note that using window_spill{4,8,12} macros is more efficient
|
||||
* than calling a function implemented using window_spill_function,
|
||||
* because the latter needs extra code to figure out the size of
|
||||
* the call to the spilling function.
|
||||
*
|
||||
* Example usage:
|
||||
*
|
||||
* .text
|
||||
* .align 4
|
||||
* .global some_function
|
||||
* .type some_function,@function
|
||||
* some_function:
|
||||
* entry a1, 16
|
||||
* :
|
||||
* :
|
||||
*
|
||||
* window_spill4 // Spill windows of some_function's callers; preserves a0..a3 only;
|
||||
* // to use window_spill{8,12} in this example function we'd have
|
||||
* // to increase space allocated by the entry instruction, because
|
||||
* // 16 bytes only allows call4; 32 or 48 bytes (+locals) are needed
|
||||
* // for call8/window_spill8 or call12/window_spill12 respectively.
|
||||
*
|
||||
* :
|
||||
*
|
||||
* retw
|
||||
*
|
||||
* window_spill_common // instantiates code used by window_spill4
|
||||
*
|
||||
*
|
||||
* On entry:
|
||||
* none (if window_spill4)
|
||||
* stack frame has enough space allocated for call8 (if window_spill8)
|
||||
* stack frame has enough space allocated for call12 (if window_spill12)
|
||||
* On exit:
|
||||
* a4..a15 clobbered (if window_spill4)
|
||||
* a8..a15 clobbered (if window_spill8)
|
||||
* a12..a15 clobbered (if window_spill12)
|
||||
* no caller windows are in live registers
|
||||
*/
|
||||
|
||||
.macro window_spill4
|
||||
#if XCHAL_HAVE_WINDOWED
|
||||
# if XCHAL_NUM_AREGS == 16
|
||||
movi a15, 0 // for 16-register files, no need to call to reach the end
|
||||
# elif XCHAL_NUM_AREGS == 32
|
||||
call4 .L__wdwspill_assist28 // call deep enough to clear out any live callers
|
||||
# elif XCHAL_NUM_AREGS == 64
|
||||
call4 .L__wdwspill_assist60 // call deep enough to clear out any live callers
|
||||
# endif
|
||||
#endif
|
||||
.endm // window_spill4
|
||||
|
||||
.macro window_spill8
|
||||
#if XCHAL_HAVE_WINDOWED
|
||||
# if XCHAL_NUM_AREGS == 16
|
||||
movi a15, 0 // for 16-register files, no need to call to reach the end
|
||||
# elif XCHAL_NUM_AREGS == 32
|
||||
call8 .L__wdwspill_assist24 // call deep enough to clear out any live callers
|
||||
# elif XCHAL_NUM_AREGS == 64
|
||||
call8 .L__wdwspill_assist56 // call deep enough to clear out any live callers
|
||||
# endif
|
||||
#endif
|
||||
.endm // window_spill8
|
||||
|
||||
.macro window_spill12
|
||||
#if XCHAL_HAVE_WINDOWED
|
||||
# if XCHAL_NUM_AREGS == 16
|
||||
movi a15, 0 // for 16-register files, no need to call to reach the end
|
||||
# elif XCHAL_NUM_AREGS == 32
|
||||
call12 .L__wdwspill_assist20 // call deep enough to clear out any live callers
|
||||
# elif XCHAL_NUM_AREGS == 64
|
||||
call12 .L__wdwspill_assist52 // call deep enough to clear out any live callers
|
||||
# endif
|
||||
#endif
|
||||
.endm // window_spill12
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* window_spill_function
|
||||
*
|
||||
* This macro outputs a function that will spill its caller's callers'
|
||||
* register windows to the stack. Eg. it could be used to implement
|
||||
* a version of xthal_window_spill() that works in non-privileged tasks.
|
||||
* This works for both privileged and non-privileged tasks.
|
||||
*
|
||||
* Typical usage:
|
||||
*
|
||||
* .text
|
||||
* .align 4
|
||||
* .global my_spill_function
|
||||
* .type my_spill_function,@function
|
||||
* my_spill_function:
|
||||
* window_spill_function
|
||||
*
|
||||
* On entry to resulting function:
|
||||
* none
|
||||
* On exit from resulting function:
|
||||
* none (no caller windows are in live registers)
|
||||
*/
|
||||
|
||||
.macro window_spill_function
|
||||
#if XCHAL_HAVE_WINDOWED
|
||||
# if XCHAL_NUM_AREGS == 32
|
||||
entry sp, 48
|
||||
bbci.l a0, 31, 1f // branch if called with call4
|
||||
bbsi.l a0, 30, 2f // branch if called with call12
|
||||
call8 .L__wdwspill_assist16 // called with call8, only need another 8
|
||||
retw
|
||||
1: call12 .L__wdwspill_assist16 // called with call4, only need another 12
|
||||
retw
|
||||
2: call4 .L__wdwspill_assist16 // called with call12, only need another 4
|
||||
retw
|
||||
# elif XCHAL_NUM_AREGS == 64
|
||||
entry sp, 48
|
||||
bbci.l a0, 31, 1f // branch if called with call4
|
||||
bbsi.l a0, 30, 2f // branch if called with call12
|
||||
call4 .L__wdwspill_assist52 // called with call8, only need a call4
|
||||
retw
|
||||
1: call8 .L__wdwspill_assist52 // called with call4, only need a call8
|
||||
retw
|
||||
2: call12 .L__wdwspill_assist40 // called with call12, can skip a call12
|
||||
retw
|
||||
# elif XCHAL_NUM_AREGS == 16
|
||||
entry sp, 16
|
||||
bbci.l a0, 31, 1f // branch if called with call4
|
||||
bbsi.l a0, 30, 2f // branch if called with call12
|
||||
movi a7, 0 // called with call8
|
||||
retw
|
||||
1: movi a11, 0 // called with call4
|
||||
2: retw // if called with call12, everything already spilled
|
||||
|
||||
// movi a15, 0 // trick to spill all but the direct caller
|
||||
// j 1f
|
||||
// // The entry instruction is magical in the assembler (gets auto-aligned)
|
||||
// // so we have to jump to it to avoid falling through the padding.
|
||||
// // We need entry/retw to know where to return.
|
||||
//1: entry sp, 16
|
||||
// retw
|
||||
# else
|
||||
# error "unrecognized address register file size"
|
||||
# endif
|
||||
|
||||
#endif /* XCHAL_HAVE_WINDOWED */
|
||||
window_spill_common
|
||||
.endm // window_spill_function
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* window_spill_common
|
||||
*
|
||||
* Common code used by any number of invocations of the window_spill##
|
||||
* and window_spill_function macros.
|
||||
*
|
||||
* Must be instantiated exactly once within a given assembly unit,
|
||||
* within call/j range of and same section as window_spill##
|
||||
* macro invocations for that assembly unit.
|
||||
* (Is automatically instantiated by the window_spill_function macro.)
|
||||
*/
|
||||
|
||||
.macro window_spill_common
|
||||
#if XCHAL_HAVE_WINDOWED && (XCHAL_NUM_AREGS == 32 || XCHAL_NUM_AREGS == 64)
|
||||
.ifndef .L__wdwspill_defined
|
||||
# if XCHAL_NUM_AREGS >= 64
|
||||
.L__wdwspill_assist60:
|
||||
entry sp, 32
|
||||
call8 .L__wdwspill_assist52
|
||||
retw
|
||||
.L__wdwspill_assist56:
|
||||
entry sp, 16
|
||||
call4 .L__wdwspill_assist52
|
||||
retw
|
||||
.L__wdwspill_assist52:
|
||||
entry sp, 48
|
||||
call12 .L__wdwspill_assist40
|
||||
retw
|
||||
.L__wdwspill_assist40:
|
||||
entry sp, 48
|
||||
call12 .L__wdwspill_assist28
|
||||
retw
|
||||
# endif
|
||||
.L__wdwspill_assist28:
|
||||
entry sp, 48
|
||||
call12 .L__wdwspill_assist16
|
||||
retw
|
||||
.L__wdwspill_assist24:
|
||||
entry sp, 32
|
||||
call8 .L__wdwspill_assist16
|
||||
retw
|
||||
.L__wdwspill_assist20:
|
||||
entry sp, 16
|
||||
call4 .L__wdwspill_assist16
|
||||
retw
|
||||
.L__wdwspill_assist16:
|
||||
entry sp, 16
|
||||
movi a15, 0
|
||||
retw
|
||||
.set .L__wdwspill_defined, 1
|
||||
.endif
|
||||
#endif /* XCHAL_HAVE_WINDOWED with 32 or 64 aregs */
|
||||
.endm // window_spill_common
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* beqi32
|
||||
*
|
||||
* macro implements version of beqi for arbitrary 32-bit immediate value
|
||||
*
|
||||
* beqi32 ax, ay, imm32, label
|
||||
*
|
||||
* Compares value in register ax with imm32 value and jumps to label if
|
||||
* equal. Clobbers register ay if needed
|
||||
*
|
||||
*/
|
||||
.macro beqi32 ax, ay, imm, label
|
||||
.ifeq ((\imm-1) & ~7) // 1..8 ?
|
||||
beqi \ax, \imm, \label
|
||||
.else
|
||||
.ifeq (\imm+1) // -1 ?
|
||||
beqi \ax, \imm, \label
|
||||
.else
|
||||
.ifeq (\imm) // 0 ?
|
||||
beqz \ax, \label
|
||||
.else
|
||||
// We could also handle immediates 10,12,16,32,64,128,256
|
||||
// but it would be a long macro...
|
||||
movi \ay, \imm
|
||||
beq \ax, \ay, \label
|
||||
.endif
|
||||
.endif
|
||||
.endif
|
||||
.endm // beqi32
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* isync_retw_nop
|
||||
*
|
||||
* This macro must be invoked immediately after ISYNC if ISYNC
|
||||
* would otherwise be immediately followed by RETW (or other instruction
|
||||
* modifying WindowBase or WindowStart), in a context where
|
||||
* kernel vector mode may be selected, and level-one interrupts
|
||||
* and window overflows may be enabled, on an XEA1 configuration.
|
||||
*
|
||||
* On hardware with erratum "XEA1KWIN" (see <xtensa/core.h> for details),
|
||||
* XEA1 code must have at least one instruction between ISYNC and RETW if
|
||||
* run in kernel vector mode with interrupts and window overflows enabled.
|
||||
*/
|
||||
.macro isync_retw_nop
|
||||
#if XCHAL_MAYHAVE_ERRATUM_XEA1KWIN
|
||||
nop
|
||||
#endif
|
||||
.endm
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* isync_erratum453
|
||||
*
|
||||
* This macro must be invoked at certain points in the code,
|
||||
* such as in exception and interrupt vectors in particular,
|
||||
* to work around erratum 453.
|
||||
*/
|
||||
.macro isync_erratum453
|
||||
#if XCHAL_ERRATUM_453
|
||||
isync
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* abs
|
||||
*
|
||||
* implements abs on machines that do not have it configured
|
||||
*/
|
||||
|
||||
#if !XCHAL_HAVE_ABS
|
||||
.macro abs arr, ars
|
||||
.ifc \arr, \ars
|
||||
//src equal dest is less efficient
|
||||
bgez \arr, 1f
|
||||
neg \arr, \arr
|
||||
1:
|
||||
.else
|
||||
neg \arr, \ars
|
||||
movgez \arr, \ars, \ars
|
||||
.endif
|
||||
.endm
|
||||
#endif /* !XCHAL_HAVE_ABS */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* addx2
|
||||
*
|
||||
* implements addx2 on machines that do not have it configured
|
||||
*
|
||||
*/
|
||||
|
||||
#if !XCHAL_HAVE_ADDX
|
||||
.macro addx2 arr, ars, art
|
||||
.ifc \arr, \art
|
||||
.ifc \arr, \ars
|
||||
// addx2 a, a, a (not common)
|
||||
.err
|
||||
.else
|
||||
add \arr, \ars, \art
|
||||
add \arr, \ars, \art
|
||||
.endif
|
||||
.else
|
||||
//addx2 a, b, c
|
||||
//addx2 a, a, b
|
||||
//addx2 a, b, b
|
||||
slli \arr, \ars, 1
|
||||
add \arr, \arr, \art
|
||||
.endif
|
||||
.endm
|
||||
#endif /* !XCHAL_HAVE_ADDX */
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* addx4
|
||||
*
|
||||
* implements addx4 on machines that do not have it configured
|
||||
*
|
||||
*/
|
||||
|
||||
#if !XCHAL_HAVE_ADDX
|
||||
.macro addx4 arr, ars, art
|
||||
.ifc \arr, \art
|
||||
.ifc \arr, \ars
|
||||
// addx4 a, a, a (not common)
|
||||
.err
|
||||
.else
|
||||
//# addx4 a, b, a
|
||||
add \arr, \ars, \art
|
||||
add \arr, \ars, \art
|
||||
add \arr, \ars, \art
|
||||
add \arr, \ars, \art
|
||||
.endif
|
||||
.else
|
||||
//addx4 a, b, c
|
||||
//addx4 a, a, b
|
||||
//addx4 a, b, b
|
||||
slli \arr, \ars, 2
|
||||
add \arr, \arr, \art
|
||||
.endif
|
||||
.endm
|
||||
#endif /* !XCHAL_HAVE_ADDX */
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* addx8
|
||||
*
|
||||
* implements addx8 on machines that do not have it configured
|
||||
*
|
||||
*/
|
||||
|
||||
#if !XCHAL_HAVE_ADDX
|
||||
.macro addx8 arr, ars, art
|
||||
.ifc \arr, \art
|
||||
.ifc \arr, \ars
|
||||
//addx8 a, a, a (not common)
|
||||
.err
|
||||
.else
|
||||
//addx8 a, b, a
|
||||
add \arr, \ars, \art
|
||||
add \arr, \ars, \art
|
||||
add \arr, \ars, \art
|
||||
add \arr, \ars, \art
|
||||
add \arr, \ars, \art
|
||||
add \arr, \ars, \art
|
||||
add \arr, \ars, \art
|
||||
add \arr, \ars, \art
|
||||
.endif
|
||||
.else
|
||||
//addx8 a, b, c
|
||||
//addx8 a, a, b
|
||||
//addx8 a, b, b
|
||||
slli \arr, \ars, 3
|
||||
add \arr, \arr, \art
|
||||
.endif
|
||||
.endm
|
||||
#endif /* !XCHAL_HAVE_ADDX */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* rfe_rfue
|
||||
*
|
||||
* Maps to RFUE on XEA1, and RFE on XEA2. No mapping on XEAX.
|
||||
*/
|
||||
|
||||
#if XCHAL_HAVE_XEA1
|
||||
.macro rfe_rfue
|
||||
rfue
|
||||
.endm
|
||||
#elif XCHAL_HAVE_XEA2
|
||||
.macro rfe_rfue
|
||||
rfe
|
||||
.endm
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* abi_entry
|
||||
*
|
||||
* Generate proper function entry sequence for the current ABI
|
||||
* (windowed or call0). Takes care of allocating stack space (up to 1kB)
|
||||
* and saving the return PC, if necessary. The corresponding abi_return
|
||||
* macro does the corresponding stack deallocation and restoring return PC.
|
||||
*
|
||||
* Parameters are:
|
||||
*
|
||||
* locsize Number of bytes to allocate on the stack
|
||||
* for local variables (and for args to pass to
|
||||
* callees, if any calls are made). Defaults to zero.
|
||||
* The macro rounds this up to a multiple of 16.
|
||||
* NOTE: large values are allowed (e.g. up to 1 GB).
|
||||
*
|
||||
* callsize Maximum call size made by this function.
|
||||
* Leave zero (default) for leaf functions, i.e. if
|
||||
* this function makes no calls to other functions.
|
||||
* Otherwise must be set to 4, 8, or 12 according
|
||||
* to whether the "largest" call made is a call[x]4,
|
||||
* call[x]8, or call[x]12 (for call0 ABI, it makes
|
||||
* no difference whether this is set to 4, 8 or 12,
|
||||
* but it must be set to one of these values).
|
||||
*
|
||||
* NOTE: It is up to the caller to align the entry point, declare the
|
||||
* function symbol, make it global, etc.
|
||||
*
|
||||
* NOTE: This macro relies on assembler relaxation for large values
|
||||
* of locsize. It might not work with the no-transform directive.
|
||||
* NOTE: For the call0 ABI, this macro ensures SP is allocated or
|
||||
* de-allocated cleanly, i.e. without temporarily allocating too much
|
||||
* (or allocating negatively!) due to addi relaxation.
|
||||
*
|
||||
* NOTE: Generating the proper sequence and register allocation for
|
||||
* making calls in an ABI independent manner is a separate topic not
|
||||
* covered by this macro.
|
||||
*
|
||||
* NOTE: To access arguments, you can't use a fixed offset from SP.
|
||||
* The offset depends on the ABI, whether the function is leaf, etc.
|
||||
* The simplest method is probably to use the .locsz symbol, which
|
||||
* is set by this macro to the actual number of bytes allocated on
|
||||
* the stack, in other words, to the offset from SP to the arguments.
|
||||
* E.g. for a function whose arguments are all 32-bit integers, you
|
||||
* can get the 7th and 8th arguments (1st and 2nd args stored on stack)
|
||||
* using:
|
||||
* l32i a2, sp, .locsz
|
||||
* l32i a3, sp, .locsz+4
|
||||
* (this example works as long as locsize is under L32I's offset limit
|
||||
* of 1020 minus up to 48 bytes of ABI-specific stack usage;
|
||||
* otherwise you might first need to do "addi a?, sp, .locsz"
|
||||
* or similar sequence).
|
||||
*
|
||||
* NOTE: For call0 ABI, this macro (and abi_return) may clobber a9
|
||||
* (a caller-saved register).
|
||||
*
|
||||
* Examples:
|
||||
* abi_entry
|
||||
* abi_entry 5
|
||||
* abi_entry 22, 8
|
||||
* abi_entry 0, 4
|
||||
*/
|
||||
|
||||
/*
|
||||
* Compute .locsz and .callsz without emitting any instructions.
|
||||
* Used by both abi_entry and abi_return.
|
||||
* Assumes locsize >= 0.
|
||||
*/
|
||||
.macro abi_entry_size locsize=0, callsize=0
|
||||
#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
|
||||
.ifeq \callsize
|
||||
.set .callsz, 16
|
||||
.else
|
||||
.ifeq \callsize-4
|
||||
.set .callsz, 16
|
||||
.else
|
||||
.ifeq \callsize-8
|
||||
.set .callsz, 32
|
||||
.else
|
||||
.ifeq \callsize-12
|
||||
.set .callsz, 48
|
||||
.else
|
||||
.error "abi_entry: invalid call size \callsize"
|
||||
.endif
|
||||
.endif
|
||||
.endif
|
||||
.endif
|
||||
.set .locsz, .callsz + ((\locsize + 15) & -16)
|
||||
#else
|
||||
.set .callsz, \callsize
|
||||
.if .callsz /* if calls, need space for return PC */
|
||||
.set .locsz, (\locsize + 4 + 15) & -16
|
||||
.else
|
||||
.set .locsz, (\locsize + 15) & -16
|
||||
.endif
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro abi_entry locsize=0, callsize=0
|
||||
.iflt \locsize
|
||||
.error "abi_entry: invalid negative size of locals (\locsize)"
|
||||
.endif
|
||||
abi_entry_size \locsize, \callsize
|
||||
#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
|
||||
.ifgt .locsz - 32760 /* .locsz > 32760 (ENTRY's max range)? */
|
||||
/* Funky computation to try to have assembler use addmi efficiently if possible: */
|
||||
entry sp, 0x7F00 + (.locsz & 0xF0)
|
||||
addi a12, sp, - ((.locsz & -0x100) - 0x7F00)
|
||||
movsp sp, a12
|
||||
.else
|
||||
entry sp, .locsz
|
||||
.endif
|
||||
#else
|
||||
.if .locsz
|
||||
.ifle .locsz - 128 /* if locsz <= 128 */
|
||||
addi sp, sp, -.locsz
|
||||
.if .callsz
|
||||
s32i a0, sp, .locsz - 4
|
||||
.endif
|
||||
.elseif .callsz /* locsz > 128, with calls: */
|
||||
movi a9, .locsz - 16 /* note: a9 is caller-saved */
|
||||
addi sp, sp, -16
|
||||
s32i a0, sp, 12
|
||||
sub sp, sp, a9
|
||||
.else /* locsz > 128, no calls: */
|
||||
movi a9, .locsz
|
||||
sub sp, sp, a9
|
||||
.endif /* end */
|
||||
.endif
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* abi_return
|
||||
*
|
||||
* Generate proper function exit sequence for the current ABI
|
||||
* (windowed or call0). Takes care of freeing stack space and
|
||||
* restoring the return PC, if necessary.
|
||||
* NOTE: This macro MUST be invoked following a corresponding
|
||||
* abi_entry macro invocation. For call0 ABI in particular,
|
||||
* all stack and PC restoration are done according to the last
|
||||
* abi_entry macro invoked before this macro in the assembly file.
|
||||
*
|
||||
* Normally this macro takes no arguments. However to allow
|
||||
* for placing abi_return *before* abi_entry (as must be done
|
||||
* for some highly optimized assembly), it optionally takes
|
||||
* exactly the same arguments as abi_entry.
|
||||
*/
|
||||
|
||||
.macro abi_return locsize=-1, callsize=0
|
||||
.ifge \locsize
|
||||
abi_entry_size \locsize, \callsize
|
||||
.endif
|
||||
#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
|
||||
retw
|
||||
#else
|
||||
.if .locsz
|
||||
.iflt .locsz - 128 /* if locsz < 128 */
|
||||
.if .callsz
|
||||
l32i a0, sp, .locsz - 4
|
||||
.endif
|
||||
addi sp, sp, .locsz
|
||||
.elseif .callsz /* locsz >= 128, with calls: */
|
||||
addi a9, sp, .locsz - 16
|
||||
l32i a0, a9, 12
|
||||
addi sp, a9, 16
|
||||
.else /* locsz >= 128, no calls: */
|
||||
movi a9, .locsz
|
||||
add sp, sp, a9
|
||||
.endif /* end */
|
||||
.endif
|
||||
ret
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
/*
|
||||
* HW erratum fixes.
|
||||
*/
|
||||
|
||||
.macro hw_erratum_487_fix
|
||||
#if defined XSHAL_ERRATUM_487_FIX
|
||||
isync
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
#endif /*XTENSA_COREASM_H*/
|
||||
|
||||
Executable
+185
@@ -0,0 +1,185 @@
|
||||
/*
|
||||
* xtensa/corebits.h - Xtensa Special Register field positions, masks, values.
|
||||
*
|
||||
* (In previous releases, these were defined in specreg.h, a generated file.
|
||||
* This file is not generated, ie. it is processor configuration independent.)
|
||||
*/
|
||||
|
||||
/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/corebits.h#2 $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2005-2011 Tensilica Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef XTENSA_COREBITS_H
|
||||
#define XTENSA_COREBITS_H
|
||||
|
||||
/* EXCCAUSE register fields: */
|
||||
#define EXCCAUSE_EXCCAUSE_SHIFT 0
|
||||
#define EXCCAUSE_EXCCAUSE_MASK 0x3F
|
||||
/* EXCCAUSE register values: */
|
||||
/*
|
||||
* General Exception Causes
|
||||
* (values of EXCCAUSE special register set by general exceptions,
|
||||
* which vector to the user, kernel, or double-exception vectors).
|
||||
*/
|
||||
#define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */
|
||||
#define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */
|
||||
#define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */
|
||||
# define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */
|
||||
#define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */
|
||||
# define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */
|
||||
#define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */
|
||||
# define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */
|
||||
#define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */
|
||||
#define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */
|
||||
#define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */
|
||||
#define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */
|
||||
#define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */
|
||||
/* Reserved 10..11 */
|
||||
#define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */
|
||||
#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */
|
||||
#define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */
|
||||
#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */
|
||||
#define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */
|
||||
#define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */
|
||||
#define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */
|
||||
/* Reserved 19 */ /* Size Restriction on IFetch (not implemented) */
|
||||
#define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */
|
||||
/* Reserved 21..23 */
|
||||
#define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */
|
||||
#define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */
|
||||
#define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */
|
||||
/* Reserved 27 */ /* Size Restriction on Load/Store (not implemented) */
|
||||
#define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */
|
||||
#define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */
|
||||
/* Reserved 30..31 */
|
||||
#define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */
|
||||
#define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */
|
||||
#define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */
|
||||
#define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */
|
||||
#define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled */
|
||||
#define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled */
|
||||
#define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */
|
||||
#define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */
|
||||
#define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */
|
||||
/* Reserved 40..63 */
|
||||
|
||||
/* PS register fields: */
|
||||
#define PS_WOE_SHIFT 18
|
||||
#define PS_WOE_MASK 0x00040000
|
||||
#define PS_WOE PS_WOE_MASK
|
||||
#define PS_CALLINC_SHIFT 16
|
||||
#define PS_CALLINC_MASK 0x00030000
|
||||
#define PS_CALLINC(n) (((n)&3)<<PS_CALLINC_SHIFT) /* n = 0..3 */
|
||||
#define PS_OWB_SHIFT 8
|
||||
#define PS_OWB_MASK 0x00000F00
|
||||
#define PS_OWB(n) (((n)&15)<<PS_OWB_SHIFT) /* n = 0..15 (or 0..7) */
|
||||
#define PS_RING_SHIFT 6
|
||||
#define PS_RING_MASK 0x000000C0
|
||||
#define PS_RING(n) (((n)&3)<<PS_RING_SHIFT) /* n = 0..3 */
|
||||
#define PS_UM_SHIFT 5
|
||||
#define PS_UM_MASK 0x00000020
|
||||
#define PS_UM PS_UM_MASK
|
||||
#define PS_EXCM_SHIFT 4
|
||||
#define PS_EXCM_MASK 0x00000010
|
||||
#define PS_EXCM PS_EXCM_MASK
|
||||
#define PS_INTLEVEL_SHIFT 0
|
||||
#define PS_INTLEVEL_MASK 0x0000000F
|
||||
#define PS_INTLEVEL(n) ((n)&PS_INTLEVEL_MASK) /* n = 0..15 */
|
||||
/* Backward compatibility (deprecated): */
|
||||
#define PS_PROGSTACK_SHIFT PS_UM_SHIFT
|
||||
#define PS_PROGSTACK_MASK PS_UM_MASK
|
||||
#define PS_PROG_SHIFT PS_UM_SHIFT
|
||||
#define PS_PROG_MASK PS_UM_MASK
|
||||
#define PS_PROG PS_UM
|
||||
|
||||
/* DBREAKCn register fields: */
|
||||
#define DBREAKC_MASK_SHIFT 0
|
||||
#define DBREAKC_MASK_MASK 0x0000003F
|
||||
#define DBREAKC_LOADBREAK_SHIFT 30
|
||||
#define DBREAKC_LOADBREAK_MASK 0x40000000
|
||||
#define DBREAKC_STOREBREAK_SHIFT 31
|
||||
#define DBREAKC_STOREBREAK_MASK 0x80000000
|
||||
|
||||
/* DEBUGCAUSE register fields: */
|
||||
#define DEBUGCAUSE_DEBUGINT_SHIFT 5
|
||||
#define DEBUGCAUSE_DEBUGINT_MASK 0x20 /* debug interrupt */
|
||||
#define DEBUGCAUSE_BREAKN_SHIFT 4
|
||||
#define DEBUGCAUSE_BREAKN_MASK 0x10 /* BREAK.N instruction */
|
||||
#define DEBUGCAUSE_BREAK_SHIFT 3
|
||||
#define DEBUGCAUSE_BREAK_MASK 0x08 /* BREAK instruction */
|
||||
#define DEBUGCAUSE_DBREAK_SHIFT 2
|
||||
#define DEBUGCAUSE_DBREAK_MASK 0x04 /* DBREAK match */
|
||||
#define DEBUGCAUSE_IBREAK_SHIFT 1
|
||||
#define DEBUGCAUSE_IBREAK_MASK 0x02 /* IBREAK match */
|
||||
#define DEBUGCAUSE_ICOUNT_SHIFT 0
|
||||
#define DEBUGCAUSE_ICOUNT_MASK 0x01 /* ICOUNT would increment to zero */
|
||||
|
||||
/* MESR register fields: */
|
||||
#define MESR_MEME 0x00000001 /* memory error */
|
||||
#define MESR_MEME_SHIFT 0
|
||||
#define MESR_DME 0x00000002 /* double memory error */
|
||||
#define MESR_DME_SHIFT 1
|
||||
#define MESR_RCE 0x00000010 /* recorded memory error */
|
||||
#define MESR_RCE_SHIFT 4
|
||||
#define MESR_LCE
|
||||
#define MESR_LCE_SHIFT ?
|
||||
#define MESR_LCE_L
|
||||
#define MESR_ERRENAB 0x00000100
|
||||
#define MESR_ERRENAB_SHIFT 8
|
||||
#define MESR_ERRTEST 0x00000200
|
||||
#define MESR_ERRTEST_SHIFT 9
|
||||
#define MESR_DATEXC 0x00000400
|
||||
#define MESR_DATEXC_SHIFT 10
|
||||
#define MESR_INSEXC 0x00000800
|
||||
#define MESR_INSEXC_SHIFT 11
|
||||
#define MESR_WAYNUM_SHIFT 16
|
||||
#define MESR_ACCTYPE_SHIFT 20
|
||||
#define MESR_MEMTYPE_SHIFT 24
|
||||
#define MESR_ERRTYPE_SHIFT 30
|
||||
|
||||
/* MEMCTL register fields: */
|
||||
#define MEMCTL_SNOOP_EN_SHIFT 1
|
||||
#define MEMCTL_SNOOP_EN 0x02 /* enable snoop responses (default 0) */
|
||||
#define MEMCTL_L0IBUF_EN_SHIFT 0
|
||||
#define MEMCTL_L0IBUF_EN 0x01 /* enable loop instr. buffer (default 1) */
|
||||
#define MEMCTL_INV_EN_SHIFT 23
|
||||
#define MEMCTL_INV_EN 0x00800000 /* invalidate cache ways being increased */
|
||||
#define MEMCTL_DCWU_SHIFT 8
|
||||
#define MEMCTL_DCWU_BITS 5
|
||||
#define MEMCTL_DCWA_SHIFT 13
|
||||
#define MEMCTL_DCWA_BITS 5
|
||||
#define MEMCTL_ICWU_SHIFT 18
|
||||
#define MEMCTL_ICWU_BITS 5
|
||||
#define MEMCTL_DCWU_MASK 0x00001F00 /* Bits 8-12 dcache ways in use */
|
||||
#define MEMCTL_DCWA_MASK 0x0003E000 /* Bits 13-17 dcache ways allocatable */
|
||||
#define MEMCTL_ICWU_MASK 0x007C0000 /* Bits 18-22 icache ways in use */
|
||||
#define MEMCTL_DCWU_CLR_MASK ~(MEMCTL_DCWU_MASK)
|
||||
#define MEMCTL_DCWA_CLR_MASK ~(MEMCTL_DCWA_MASK)
|
||||
#define MEMCTL_ICWU_CLR_MASK ~(MEMCTL_ICWU_MASK)
|
||||
#define MEMCTL_DCW_CLR_MASK (MEMCTL_DCWU_CLR_MASK | MEMCTL_DCWA_CLR_MASK)
|
||||
#define MEMCTL_IDCW_CLR_MASK (MEMCTL_DCW_CLR_MASK | MEMCTL_ICWU_CLR_MASK)
|
||||
|
||||
|
||||
#endif /*XTENSA_COREBITS_H*/
|
||||
|
||||
Executable
+93
@@ -0,0 +1,93 @@
|
||||
/* Xtensa Debug-FileSystem definitions */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2005-2009 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
#ifndef __DEBUGFS_H__
|
||||
#define __DEBUGFS_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <unistd.h>
|
||||
#include <fcntl.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
int xt_dbfs_open(const char *pathname, int flags, mode_t mode);
|
||||
int xt_dbfs_ftruncate(int fd, off_t length);
|
||||
int xt_dbfs_truncate(const char * filename, off_t length);
|
||||
int xt_dbfs_creat(const char *pathname, mode_t mode);
|
||||
int xt_dbfs_errno(void);
|
||||
int xt_dbfs_lseek(int fd, off_t offset, int whence);
|
||||
ssize_t xt_dbfs_write(int fd, const void * buf, size_t bytes);
|
||||
ssize_t xt_dbfs_open_append_close(const char * filename, int align,
|
||||
const void * buf, size_t bytes);
|
||||
ssize_t xt_dbfs_read(int fd, void * buf, size_t bytes);
|
||||
int xt_dbfs_close(int fd);
|
||||
int xt_dbfs_unlink(const char *pathname);
|
||||
|
||||
/* By default, this function is a wrapper around sbrk, and follows
|
||||
sbrk semantics:
|
||||
|
||||
On success, it returns increment bytes of memory allocated from
|
||||
system memory.
|
||||
|
||||
On failure, it returns 0xFFFFFFFF
|
||||
|
||||
|
||||
If you want to use a method of allocating memory other than sbrk,
|
||||
implement xt_dbfs_sbrk in your own sources, and the linker will
|
||||
automatically use that copy.
|
||||
*/
|
||||
void * xt_dbfs_sbrk(int increment);
|
||||
|
||||
|
||||
|
||||
#ifdef REPLACE_FS_WITH_DBFS
|
||||
#define open xt_dbfs_open
|
||||
#define close xt_dbfs_close
|
||||
#define creat xt_dbfs_creat
|
||||
#define lseek xt_dbfs_lseek
|
||||
#define write xt_dbfs_write
|
||||
#define read xt_dbfs_read
|
||||
#define close xt_dbfs_close
|
||||
#define unlink xt_dbfs_unlink
|
||||
|
||||
#define rmdir NOT_IMPLEMENTED_IN_DBFS
|
||||
#define opendir NOT_IMPLEMENTED_IN_DBFS
|
||||
#define closedir NOT_IMPLEMENTED_IN_DBFS
|
||||
#define dirfs NOT_IMPLEMENTED_IN_DBFS
|
||||
#define readdir NOT_IMPLEMENTED_IN_DBFS
|
||||
#define scandir NOT_IMPLEMENTED_IN_DBFS
|
||||
#define seekdir NOT_IMPLEMENTED_IN_DBFS
|
||||
#define telldir NOT_IMPLEMENTED_IN_DBFS
|
||||
|
||||
#define fcntl NOT_IMPLEMENTED_IN_DBFS
|
||||
#define dup2 NOT_IMPLEMENTED_IN_DBFS
|
||||
#define dup NOT_IMPLEMENTED_IN_DBFS
|
||||
#define flock NOT_IMPLEMENTED_IN_DBFS
|
||||
#define lockf NOT_IMPLEMENTED_IN_DBFS
|
||||
#define link NOT_IMPLEMENTED_IN_DBFS
|
||||
#define stat NOT_IMPLEMENTED_IN_DBFS
|
||||
#define fstat NOT_IMPLEMENTED_IN_DBFS
|
||||
#define lstat NOT_IMPLEMENTED_IN_DBFS
|
||||
#define chmod NOT_IMPLEMENTED_IN_DBFS
|
||||
#define fchmod NOT_IMPLEMENTED_IN_DBFS
|
||||
#define chmown NOT_IMPLEMENTED_IN_DBFS
|
||||
#define lchown NOT_IMPLEMENTED_IN_DBFS
|
||||
#define fchown NOT_IMPLEMENTED_IN_DBFS
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Executable
+45
@@ -0,0 +1,45 @@
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
#ifndef __XT_FEEDBACK_INCLUDED__
|
||||
#define __XT_FEEDBACK_INCLUDED__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* xt_feedback_save_and_reset
|
||||
|
||||
Save and reset the accumulated feedback data.
|
||||
*/
|
||||
extern void xt_feedback_save_and_reset(void);
|
||||
|
||||
/* xt_feedback_enable
|
||||
|
||||
Turn on feedback accumulation. Ordinarily, feedback accumulation is on
|
||||
by default. If you turn it off using xt_feedback_disable, You can turn
|
||||
it on again via this function.
|
||||
*/
|
||||
extern void xt_feedback_enable (void);
|
||||
|
||||
/* xt_feedback_disable
|
||||
|
||||
Turn off feedback accumulation. If you don't want to gather feedback for a
|
||||
portion of your code, use this function and then xt_feedback_enable when
|
||||
you want to start again.
|
||||
*/
|
||||
extern void xt_feedback_disable (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __XT_FEEDBACK_INCLUDED__ */
|
||||
|
||||
Executable
+80
@@ -0,0 +1,80 @@
|
||||
/* Xtensa Debug-FileSystem definitions
|
||||
*
|
||||
* Copyright (c) 2006-2009 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
#ifndef __DEBUGFS_H__
|
||||
#define __DEBUGFS_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <unistd.h>
|
||||
#include <fcntl.h>
|
||||
#include <stdlib.h>
|
||||
#include <errno.h>
|
||||
|
||||
int _gdbio_open_r(void * ptr, const char *pathname, int flags, mode_t mode);
|
||||
int _gdbio_creat_r(void * ptr, const char *pathname, mode_t mode);
|
||||
int _gdbio_lseek_r(void * ptr, int fd, off_t offset, int whence);
|
||||
ssize_t _gdbio_write_r(void * ptr, int fd, const void * buf, size_t bytes);
|
||||
ssize_t _gdbio_read_r(void * ptr, int fd, void * buf, size_t bytes);
|
||||
int _gdbio_close_r(void * ptr, int fd);
|
||||
int _gdbio_unlink_r(void * ptr, const char * pathname);
|
||||
|
||||
static inline
|
||||
int gdbio_open(const char *pathname, int flags, mode_t mode) {
|
||||
return _gdbio_open_r(&errno, pathname, flags, mode);
|
||||
}
|
||||
static inline int
|
||||
gdbio_creat(const char *pathname, mode_t mode) {
|
||||
return _gdbio_open_r(&errno, pathname, O_CREAT|O_WRONLY|O_TRUNC, mode);
|
||||
}
|
||||
static inline int
|
||||
gdbio_errno(void) {
|
||||
return errno;
|
||||
}
|
||||
static inline int
|
||||
gdbio_lseek(int fd, off_t offset, int whence) {
|
||||
return _gdbio_lseek_r(&errno, fd, offset, whence);
|
||||
}
|
||||
static inline
|
||||
ssize_t gdbio_write(int fd, const void * buf, size_t bytes) {
|
||||
return _gdbio_write_r(&errno, fd, buf, bytes);
|
||||
}
|
||||
static inline
|
||||
ssize_t gdbio_read(int fd, void * buf, size_t bytes) {
|
||||
return _gdbio_read_r(&errno, fd, buf, bytes);
|
||||
}
|
||||
static inline int
|
||||
gdbio_close(int fd) {
|
||||
return _gdbio_close_r(&errno, fd);
|
||||
}
|
||||
static inline int
|
||||
gdbio_unlink(const char * pathname) {
|
||||
return _gdbio_unlink_r(&errno, pathname);
|
||||
}
|
||||
|
||||
#ifdef REPLACE_FS_WITH_GDBIO
|
||||
#define open gdbio_open
|
||||
#define close gdbio_close
|
||||
#define creat gdbio_creat
|
||||
#define lseek gdbio_lseek
|
||||
#define write gdbio_write
|
||||
#define read gdbio_read
|
||||
#define close gdbio_close
|
||||
#define unlink gdbio_unlink
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Executable
+1024
File diff suppressed because it is too large
Load Diff
+99
@@ -0,0 +1,99 @@
|
||||
/* Copyright (c) 2011-2012 Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
// These coded instructions, statements, and computer programs are the
|
||||
// copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
// They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
// third parties in any manner, medium, or form, in whole or in part, without
|
||||
// the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
#ifndef _JTAG_XTENSA_H_
|
||||
#define _JTAG_XTENSA_H_
|
||||
|
||||
|
||||
/* ---------------- JTAG registers ------------------ */
|
||||
|
||||
/* -- ER and later JTAG registers */
|
||||
typedef enum {
|
||||
regIR,
|
||||
regBypass,
|
||||
regNAR,
|
||||
regNDR,
|
||||
regIdcode,
|
||||
regPWRCTL,
|
||||
regPWRSTAT,
|
||||
regJtagMAX,
|
||||
} xtensaJtagReg;
|
||||
|
||||
/* -- pre-ER JTAG registers */
|
||||
typedef enum {
|
||||
regOldIR,
|
||||
regOldBypass,
|
||||
regOldDIRW,
|
||||
regOldDIR,
|
||||
regOldDDR,
|
||||
regOldDOSR,
|
||||
regOldESR,
|
||||
regOldDCR,
|
||||
regOldTraxNDR,
|
||||
regOldTraxNAR,
|
||||
regOldMAX
|
||||
} xtensaOldJtagReg;
|
||||
|
||||
|
||||
/* ---------------- JTAG Instructions ------------------ */
|
||||
|
||||
/* -- pre-ER JTAG instructions */
|
||||
typedef enum {
|
||||
ji_EnableOCD = 0x11,
|
||||
ji_DebugInt,
|
||||
ji_RetDebugInt, // TBD: remove
|
||||
ji_DisRetOCD, // TBD: remove
|
||||
ji_ExecuteDI,
|
||||
ji_LoadDI,
|
||||
ji_ScanDDR,
|
||||
ji_ReadDOSR,
|
||||
ji_ScanDCR,
|
||||
ji_LoadWDI,
|
||||
ji_TRAX = 0x1c,
|
||||
ji_BYPASS = 0x1f,
|
||||
} xtensaJtagInstruction;
|
||||
|
||||
typedef enum {
|
||||
OCDNormalMode,
|
||||
OCDRunMode,
|
||||
OCDHaltMode,
|
||||
OCDStepMode
|
||||
} xtensaMode;
|
||||
|
||||
typedef struct {
|
||||
xtensaMode mode;
|
||||
int DRsel;
|
||||
XTMP_core core;
|
||||
XTMP_tap tap;
|
||||
int core_num;
|
||||
jtagReg_t *jtagRegs;
|
||||
void *dap; // used for ARM DAP only
|
||||
bool isBig;
|
||||
int dir_array_option; // used by pre-ER devices only
|
||||
// for testing, below - FIXME - delete later
|
||||
int ocdReg;
|
||||
unsigned int wr_data;
|
||||
XTMP_event start_OCD_trans;
|
||||
bool data_cycle;
|
||||
bool data_pending;
|
||||
} coreSlaveData_t;
|
||||
|
||||
|
||||
enum OCD_ACCESS_TYPE{
|
||||
NEXUS_ACCESS,
|
||||
CS_ACCESS,
|
||||
};
|
||||
|
||||
// pre-ER Xtensa initializiation
|
||||
EXTERN XTMP_deviceStatus
|
||||
XTMP_jtagCoreSlaveEX(XTMP_component component, XTMP_jtagSlave slave, void* mydata);
|
||||
|
||||
extern char *OCDrd;
|
||||
extern char *OCDwr;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,62 @@
|
||||
/*******************************************************************************
|
||||
Copyright (c) 2009-2013 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
These coded instructions, statements, and computer programs are the
|
||||
copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
third parties in any manner, medium, or form, in whole or in part, without
|
||||
the prior written consent of Tensilica Inc.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
lcd-splc780d-4bitmode-board.h Board-specific LCD info for these boards:
|
||||
Avnet AV110 (XT-AV110)
|
||||
Xilinx ML605 (XT-ML605)
|
||||
Xilinx KC705 (XT-KC705)
|
||||
|
||||
Interface between board-independent driver and board-specific header.
|
||||
|
||||
This is used by a board-independent SPLC780D LCD controller (4 bit mode)
|
||||
driver to obtain board-specific information about LCD displays on the board,
|
||||
such as the controller register base address and spacing (a function of how
|
||||
the address lines are connected on the board) and length of the visible window
|
||||
of the display (a function of the LCD panel the controller drives).
|
||||
The driver doesnot refer directly to the board-specific header, which therefore is not
|
||||
constrained to use macro names consistent with other boards.
|
||||
|
||||
!! Must not contain any board-specific macro names (only controller specific) !!
|
||||
|
||||
Included at compile-time via an include path specific to the board.
|
||||
|
||||
The listed boards contain a single MYTech MOC-16216B-B display driven by
|
||||
a Sunplus SPLC870D controller.
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _LCD_SPLC780D_4BIT_BOARD_H
|
||||
#define _LCD_SPLC780D_4BIT_BOARD_H
|
||||
|
||||
#include <xtensa/board.h> /* Board info */
|
||||
|
||||
|
||||
/* Base address of the controller's registers. */
|
||||
#ifdef SPLC780D_4BIT_VADDR
|
||||
#define SPLC780D_4BIT_REGBASE SPLC780D_4BIT_VADDR
|
||||
#endif
|
||||
|
||||
/*
|
||||
The controller's registers are connected at word addresses on these boards.
|
||||
Each byte-wide register appears as the least-significant-byte (LSB) of the
|
||||
word regardless of the endianness of the processor (so if using word accesses
|
||||
then endianness doesn't matter).
|
||||
*/
|
||||
#define SPLC780D_4BIT_REGSPACING 4
|
||||
typedef unsigned splc780d_4bit_reg_t;
|
||||
|
||||
/* Include generic information shared by all boards that use this device. */
|
||||
#include <xtensa/lcd-splc780d-4bitmode.h>
|
||||
|
||||
|
||||
/* Display limits of the LCD panel. */
|
||||
#define DISPLAY_VISIBLE_LEN 16 /* length (chars) of visible window */
|
||||
|
||||
#endif /* _LCD_SPLC780D_4BIT_BOARD_H */
|
||||
|
||||
+105
@@ -0,0 +1,105 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Copyright (c) 2009-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
These coded instructions, statements, and computer programs are the
|
||||
copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
third parties in any manner, medium, or form, in whole or in part, without
|
||||
the prior written consent of Tensilica Inc.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
lcd-SPLC780D-4bitmode.h Generic definitions for Sunplus SPLC780D LCD Controller
|
||||
operating in 4 bit mode.
|
||||
|
||||
This is used by board-support-packages with one or more LCD displays that use
|
||||
a SPLC780D controller in 4 bit mode. A BSP provides a base address for each
|
||||
instance of an SPLC780D LCD controller on the board.
|
||||
|
||||
Note that LCD display operation is almost totally independent of the LCD
|
||||
display, depending almost entirely on the controller. However the display
|
||||
may limit the number of characters of the controller's RAM buffer that are
|
||||
actually visible at one time. The length of the display's visible window
|
||||
is not specifified in this controller-specific header, but comes to the
|
||||
driver from the board-specific "display.h" header.
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _LCD_SPLC780D_4BIT_H_
|
||||
#define _LCD_SPLC780D_4BIT_H_
|
||||
|
||||
|
||||
/* Offsets to controller registers from base. */
|
||||
#define SPLC780D_4BIT_INST 0
|
||||
#define SPLC780D_4BIT_DATA (SPLC780D_4BIT_INST + SPLC780D_4BIT_REGSPACING)
|
||||
|
||||
|
||||
#define SPLC780D_4BIT_INST_INIT1 0xFF /* First command in
|
||||
init sequence */
|
||||
#define SPLC780D_4BIT_INST_INIT2 0x30 /* Second command in
|
||||
init sequence,
|
||||
issued 3 times */
|
||||
#define SPLC780D_4BIT_INST_INIT3 0x20 /* Third and last command
|
||||
in init sequence */
|
||||
#define SPLC780D_4BIT_INST_CLEAR 0x01 /* clear (blank) display) */
|
||||
#define SPLC780D_4BIT_INST_SET_MODE 0x28 /* Set LCD mode. Supported
|
||||
setting is 4 bit data
|
||||
length, 2 lines, 5*8 */
|
||||
#define SPLC780D_4BIT_INST_DSPLY_ON 0x0C /* Set Display ON */
|
||||
#define SPLC780D_4BIT_INST_CRSR_INC 0x06 /* Set cursor moving direction
|
||||
as increment */
|
||||
|
||||
#define SPLC780D_4BIT_LINET_ADDR 0x80 /* clear (blank) display) */
|
||||
#define SPLC780D_4BIT_LINEB_ADDR 0xC0 /* clear (blank) display) */
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
/* C interface to controller registers. */
|
||||
struct splc780d_4bit_s {
|
||||
splc780d_4bit_reg_t inst; /* instruction register */
|
||||
splc780d_4bit_reg_t data; /* data register */
|
||||
};
|
||||
|
||||
typedef volatile struct splc780d_4bit_s splc780d_4bit_t;
|
||||
|
||||
/*
|
||||
Prototypes of high level driver functions.
|
||||
*/
|
||||
|
||||
/* Write an instruction byte to LCD, result in two back to back writes since the
|
||||
* LCD is hooked up in 4 bit mode*/
|
||||
extern void lcd_write_inst_byte(splc780d_4bit_t *lcd, unsigned char inst);
|
||||
|
||||
/* Write a data byte to LCD, result in two back to back writes since the
|
||||
* LCD is hooked up in 4 bit mode*/
|
||||
extern void lcd_write_data_byte(splc780d_4bit_t *lcd, unsigned char data);
|
||||
|
||||
/*
|
||||
Initialize the display with default settings.
|
||||
*/
|
||||
extern void splc780d_4bit_init_default(splc780d_4bit_t *lcd);
|
||||
|
||||
/*
|
||||
Write a single character at a given position (chars from left, starting at 0).
|
||||
Wait long enough afterward for the controller to be ready for more input.
|
||||
Positions beyond the end of the display are ignored.
|
||||
*/
|
||||
extern void splc780d_4bit_write_char(splc780d_4bit_t *lcd, unsigned pos, const char c);
|
||||
|
||||
/*
|
||||
Write a string to the display starting at the left (position 0).
|
||||
Blank-pad to or truncate at the end of the display (overwrites any previous
|
||||
string so don't need to blank the display first).
|
||||
Wait long enough after each char for the controller to be ready for more input.
|
||||
*/
|
||||
extern void splc780d_4bit_write_string(splc780d_4bit_t *lcd, const char *s);
|
||||
|
||||
/*
|
||||
Blank (clear) the entire display.
|
||||
Wait long enough afterward for the controller to be ready for more input.
|
||||
*/
|
||||
extern void splc780d_4bit_blank(splc780d_4bit_t *lcd);
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* _LCD_SPLC780D_4BIT_H_ */
|
||||
|
||||
+151
@@ -0,0 +1,151 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Copyright (c) 2006-2007 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
These coded instructions, statements, and computer programs are the
|
||||
copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
third parties in any manner, medium, or form, in whole or in part, without
|
||||
the prior written consent of Tensilica Inc.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
lcd-SPLC780D.h Generic definitions for Sunplus SPLC780D LCD Controller
|
||||
|
||||
This is used by board-support-packages with one or more LCD displays that use
|
||||
a SPLC780D controller. A BSP provides a base address for each instance of an
|
||||
SPLC780D LCD controller on the board.
|
||||
|
||||
Note that LCD display operation is almost totally independent of the LCD
|
||||
display, depending almost entirely on the controller. However the display
|
||||
may limit the number of characters of the controller's RAM buffer that are
|
||||
actually visible at one time. The length of the display's visible window
|
||||
is not specifified in this controller-specific header, but comes to the
|
||||
driver from the board-specific "display.h" header.
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _LCD_SPLC780D_H_
|
||||
#define _LCD_SPLC780D_H_
|
||||
|
||||
|
||||
/* Offsets to controller registers from base. */
|
||||
#define SPLC780D_INST 0
|
||||
#define SPLC780D_DATA (SPLC780D_INST + SPLC780D_REGSPACING)
|
||||
|
||||
/*
|
||||
Bit fields and their values in the instruction register.
|
||||
These fields are NOT orthogonal - they overlap!
|
||||
Thus only one field may be written at a time, determined by the
|
||||
most-significant 1 bit in the pattern (the field selector).
|
||||
All less significant bits are part of the value of the selected field.
|
||||
The fields and their values are grouped together to emphasize this format.
|
||||
Field selector macro names end in '_' (implying something more needs
|
||||
to be ORed) and the value macros are indented. The pattern written to a
|
||||
bitfield is a bitwise OR of a field selector and one or more values, eg.
|
||||
(SPLC780D_INST_ON_ | SPLC780D_INST_ON_DISPLAY | SPLC780D_INST_ON_CURSOR)
|
||||
A single bit field (eg. SPCL780D_INST_HOME) need not have a value.
|
||||
|
||||
NOTE: Controller requires a software delay after writing to the control
|
||||
or data registers. For the data register it is 38us. For the control
|
||||
register it is 38us for most bit fields, with the following exceptions:
|
||||
SPLC780D_FUNC_ 100us.
|
||||
SPLC780D_INST_CLEAR, SPLC780D_INST_HOME 1520us.
|
||||
For more details and reset timing, see the SUNPLUS SPLC780D data sheet.
|
||||
*/
|
||||
|
||||
#define SPLC780D_INST_CLEAR_ 0x1 /* clear (blank) display) */
|
||||
|
||||
#define SPLC780D_INST_HOME_ 0x2 /* home cursor and shift pos */
|
||||
|
||||
#define SPLC780D_INST_ENTRY_ 0x4 /* combine *ENTRY_* flags below */
|
||||
#define SPLC780D_INST_ENTRY_SHIFT 0x1 /* display shift on entry / not */
|
||||
#define SPLC780D_INST_ENTRY_INCR 0x2 /* cursor incr / decr */
|
||||
#define SPLC780D_INST_ENTRY_DECR 0 /* cursor incr / decr */
|
||||
|
||||
#define SPLC780D_INST_ON_ 0x8 /* combine *ON_* flags below */
|
||||
#define SPLC780D_INST_ON_DISPLAY 0x4 /* display on / off */
|
||||
#define SPLC780D_INST_ON_CURSOR 0x2 /* cursor on / off */
|
||||
#define SPLC780D_INST_ON_BLINK 0x1 /* blink on / off */
|
||||
|
||||
#define SPLC780D_INST_SHIFT_ 0x10 /* combine *SHIFT_* flags below */
|
||||
#define SPLC780D_INST_SHIFT_DISP 0x8 /* shift display / move cursor */
|
||||
#define SPLC780D_INST_SHIFT_CURS 0 /* shift display / move cursor */
|
||||
#define SPLC780D_INST_SHIFT_RIGHT 0x4 /* shift right / left */
|
||||
#define SPLC780D_INST_SHIFT_LEFT 0 /* shift right / left */
|
||||
|
||||
#define SPLC780D_INST_FUNC_ 0x20 /* combine *FUNC_* flags below */
|
||||
#define SPLC780D_INST_FUNC_8BIT 0x10 /* data length 8 bit / 4 bit */
|
||||
#define SPLC780D_INST_FUNC_4BIT 0 /* data length 8 bit / 4 bit */
|
||||
#define SPLC780D_INST_FUNC_2LINE 0x08 /* display lines 2 / 1 */
|
||||
#define SPLC780D_INST_FUNC_1LINE 0 /* display lines 2 / 1 */
|
||||
#define SPLC780D_INST_FUNC_F5x10 0x04 /* character font 5x10 / 5x8 */
|
||||
#define SPLC780D_INST_FUNC_F5x8 0 /* character font 5x10 / 5x8 */
|
||||
/* font must be 5x8 for 2 lines */
|
||||
#define SPLC780D_INST_CGEN_ 0x40 /* set char generator address */
|
||||
#define SPLC780D_INST_CGEN_ADDR 0x3F /* to address in this field */
|
||||
#define SPLC780D_INST_DRAM_ 0x80 /* set display data RAM address */
|
||||
#define SPLC780D_INST_DRAM_ADDR 0x7F /* to address in this field */
|
||||
#define SPLC780D_INST_DRAM_LINE2 0x40 /* address offset to line 2 */
|
||||
/* Controller limits */
|
||||
#define SPLC780D_RAMLEN_1LINE 0x50 /* length of line in RAM (1 line) */
|
||||
#define SPLC780D_RAMLEN_2LINE 0x28 /* length of line in RAM (2 line) */
|
||||
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
/* C interface to controller registers. */
|
||||
struct splc780d_s {
|
||||
splc780d_reg_t inst; /* instruction register */
|
||||
splc780d_reg_t data; /* data register */
|
||||
};
|
||||
|
||||
typedef volatile struct splc780d_s splc780d_t;
|
||||
|
||||
/*
|
||||
Prototypes of high level driver functions.
|
||||
*/
|
||||
|
||||
/*
|
||||
Initialize the display with the FUNC_, ENTRY_ and ON_ fields as specified in
|
||||
terms of the values above. The splc780d_init_default() macro is an example.
|
||||
*/
|
||||
extern void splc780d_init(splc780d_t *lcd,
|
||||
unsigned func, unsigned entry, unsigned on);
|
||||
|
||||
/*
|
||||
Initialize the display to default mode: 8-bit interface, 2 line, 5x8 font,
|
||||
increment cursor on entry, display on (cursor and blinking off).
|
||||
*/
|
||||
#define splc780d_init_default(lcd) \
|
||||
splc780d_init( lcd, \
|
||||
SPLC780D_INST_FUNC_8BIT \
|
||||
| SPLC780D_INST_FUNC_2LINE \
|
||||
| SPLC780D_INST_FUNC_F5x8, \
|
||||
SPLC780D_INST_ENTRY_INCR, \
|
||||
SPLC780D_INST_ON_DISPLAY \
|
||||
)
|
||||
|
||||
/*
|
||||
Write a single character at a given position (chars from left, starting at 0).
|
||||
Wait long enough afterward for the controller to be ready for more input.
|
||||
Positions beyond the end of the display are ignored.
|
||||
*/
|
||||
extern void splc780d_write_char(splc780d_t *lcd, unsigned pos, const char c);
|
||||
|
||||
/*
|
||||
Write a string to the display starting at the left (position 0).
|
||||
Blank-pad to or truncate at the end of the display (overwrites any previous
|
||||
string so don't need to blank the display first).
|
||||
Wait long enough after each char for the controller to be ready for more input.
|
||||
*/
|
||||
extern void splc780d_write_string(splc780d_t *lcd, const char *s);
|
||||
|
||||
/*
|
||||
Blank (clear) the entire display.
|
||||
Wait long enough afterward for the controller to be ready for more input.
|
||||
*/
|
||||
extern void splc780d_blank(splc780d_t *lcd);
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* _LCD_SPLC780D_H_ */
|
||||
|
||||
Executable
+184
@@ -0,0 +1,184 @@
|
||||
// overlay.h -- Overlay manager header file
|
||||
// $Id$
|
||||
|
||||
// Copyright (c) 2013 Tensilica Inc.
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining
|
||||
// a copy of this software and associated documentation files (the
|
||||
// "Software"), to deal in the Software without restriction, including
|
||||
// without limitation the rights to use, copy, modify, merge, publish,
|
||||
// distribute, sublicense, and/or sell copies of the Software, and to
|
||||
// permit persons to whom the Software is furnished to do so, subject to
|
||||
// the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
|
||||
#ifndef OVERLAY_H
|
||||
#define OVERLAY_H
|
||||
|
||||
|
||||
#include <xtensa/xtruntime.h>
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// Define this to turn off overlay support
|
||||
#ifdef XT_DISABLE_OVERLAYS
|
||||
|
||||
#define OVERLAY(n)
|
||||
#define DECLARE_OVERLAY(n)
|
||||
|
||||
#define xt_overlay_map(ov_id)
|
||||
#define xt_overlay_map_async(ov_id) 0
|
||||
#define xt_overlay_map_in_progress() 0
|
||||
#define xt_overlay_get_id() 0
|
||||
#define xt_overlay_get_state(pc) 0
|
||||
#define xt_overlay_check_map(pc,ps,ovstate,sp) 0
|
||||
|
||||
#else
|
||||
|
||||
// Shorthand for convenience and portability.
|
||||
#define OVERLAY(n) __attribute__((overlay(n)))
|
||||
|
||||
// Structure of the overlay table required by gdb and the overlay
|
||||
// manager. Should not be accessed by user code unless overriding
|
||||
// the load process.
|
||||
struct ovly_table {
|
||||
void * vma; // The overlay's mapped address.
|
||||
unsigned int size; // The size of the overlay, in bytes.
|
||||
void * lma; // The overlay's load address.
|
||||
unsigned int mapped; // Non-zero if overlay is currently mapped; zero otherwise.
|
||||
};
|
||||
|
||||
// Constructed by the linker. Required for gdb and for the overlay
|
||||
// manager. Should not be accessed by user code unless overriding
|
||||
// the load process.
|
||||
extern struct ovly_table _ovly_table[];
|
||||
|
||||
// Functions.
|
||||
void xt_overlay_map(int ov_id);
|
||||
int xt_overlay_map_async(int ov_id);
|
||||
int xt_overlay_map_in_progress(void);
|
||||
unsigned int xt_overlay_get_state(unsigned int pc);
|
||||
unsigned int xt_overlay_check_map(unsigned int * pc, unsigned int * ps,
|
||||
unsigned int ovstate, unsigned int sp);
|
||||
int xt_overlay_start_map(void * dst, void * src, unsigned int len, int ov_id);
|
||||
int xt_overlay_is_mapping(int ov_id);
|
||||
void xt_overlay_fatal_error(int ov_id);
|
||||
|
||||
|
||||
// Returns the current overlay ID. If no overlay is mapped or an overlay
|
||||
// is in the middle of being mapped, returns -1. Inlined to avoid calling
|
||||
// out of overlay (wastes cycles, can end up reading wrong ID on interrupt
|
||||
// activity).
|
||||
//
|
||||
static inline int xt_overlay_get_id(void)
|
||||
{
|
||||
#pragma always_inline
|
||||
extern short _mapping_id;
|
||||
extern short _ovly_id;
|
||||
|
||||
int ret;
|
||||
unsigned int flags = XTOS_SET_INTLEVEL(15);
|
||||
|
||||
if (_mapping_id >= 0) {
|
||||
ret = -1;
|
||||
}
|
||||
else {
|
||||
ret = _ovly_id;
|
||||
}
|
||||
|
||||
XTOS_RESTORE_INTLEVEL(flags);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
// The following macros are used to declare numbered overlays and generate
|
||||
// the corresponding call stubs. Use as follows:
|
||||
//
|
||||
// DECLARE_OVERLAY(n)
|
||||
//
|
||||
// See documentation for more details.
|
||||
|
||||
//#include <xtensa/config/core-isa.h>
|
||||
|
||||
// At this time overlays are not supported without windowing.
|
||||
#if defined(__XTENSA_WINDOWED_ABI__)
|
||||
|
||||
#define xstr(x) str(x)
|
||||
#define str(x) #x
|
||||
|
||||
// At entry, register a8 holds the return address and a9 holds the target
|
||||
// function address. This stub saves a8 on the stack at (SP - 20) which
|
||||
// is the only location that is safe for us to use. Then it allocates 32
|
||||
// bytes on the stack for working storage, loads the overlay number into
|
||||
// a8, and jumps to the common handler. The common handler will make sure
|
||||
// that the called function is loaded into memory before calling it.
|
||||
// NOTE: we are using the stack area normally reserved for nested functions.
|
||||
// This means nested functions cannot be used when overlays are in use.
|
||||
|
||||
#define CALL_IN(num) \
|
||||
asm(".section .gnu.linkonce.t.overlay.call." xstr(num) ".text, \"ax\"\n" \
|
||||
".global _overlay_call_in_" xstr(num) "_\n" \
|
||||
".align 4\n" \
|
||||
"_overlay_call_in_" xstr(num) "_:\n" \
|
||||
"s32e a8, a1, -20\n" \
|
||||
"addi a8, a1, -32\n" \
|
||||
"movsp a1, a8\n" \
|
||||
"movi a8, " xstr(num) "\n" \
|
||||
"j _overlay_call_in_common\n" \
|
||||
".size _overlay_call_in_" xstr(num) "_, . - _overlay_call_in_" xstr(num) "_\n");
|
||||
|
||||
// The call-out stub first calls the target function, then loads the overlay
|
||||
// number into register a14 and jumps to the common handler. The handler will
|
||||
// make sure that the caller function is present in memory before returning.
|
||||
// Note that registers a10-a13 may contain return values so must be preserved.
|
||||
//
|
||||
// Because we came here via a call4, the return address is in a4, and the top
|
||||
// 2 bits are set to the window increment. We'll restore the top 2 bits of
|
||||
// the return address from the called function's address, assuming that both
|
||||
// are in the same 1 GB segment. For now this is always true.
|
||||
|
||||
#define CALL_OUT(num) \
|
||||
asm(".section .gnu.linkonce.t.overlay.call." xstr(num) ".text, \"ax\"\n" \
|
||||
".global _overlay_call_out_" xstr(num) "_\n" \
|
||||
".align 4\n" \
|
||||
"_overlay_call_out_" xstr(num) "_:\n" \
|
||||
"slli a4, a4, 2\n" \
|
||||
"srli a4, a4, 2\n" \
|
||||
"extui a8, a9, 30, 2\n" \
|
||||
"slli a8, a8, 30\n" \
|
||||
"or a4, a4, a8\n" \
|
||||
"callx8 a9\n" \
|
||||
"movi a14, " xstr(num) "\n" \
|
||||
"j _overlay_call_out_common\n" \
|
||||
".size _overlay_call_out_" xstr(num) "_, . - _overlay_call_out_" xstr(num) "_\n");
|
||||
|
||||
// Generate a call-in and a call-out stub for each overlay.
|
||||
|
||||
#define DECLARE_OVERLAY(num) \
|
||||
CALL_IN(num) \
|
||||
CALL_OUT(num)
|
||||
|
||||
#endif // defined(__XTENSA_WINDOWED_ABI__)
|
||||
|
||||
#endif // XT_DISABLE_OVERLAYS
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // OVERLAY_H
|
||||
|
||||
+140
@@ -0,0 +1,140 @@
|
||||
// overlay_os_asm.h -- Overlay manager assembly macros for OS use.
|
||||
// $Id$
|
||||
|
||||
// Copyright (c) 2013 Tensilica Inc.
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining
|
||||
// a copy of this software and associated documentation files (the
|
||||
// "Software"), to deal in the Software without restriction, including
|
||||
// without limitation the rights to use, copy, modify, merge, publish,
|
||||
// distribute, sublicense, and/or sell copies of the Software, and to
|
||||
// permit persons to whom the Software is furnished to do so, subject to
|
||||
// the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
|
||||
#ifndef OVERLAY_OS_ASM_H
|
||||
#define OVERLAY_OS_ASM_H
|
||||
|
||||
// The macros in here are intended to be used by RTOS task switch code
|
||||
// to check overlay status. Such code is usually in assembly and cannot
|
||||
// call C code without penalty. For C code usage, it is best to use the
|
||||
// corresponding C functions from the library.
|
||||
|
||||
|
||||
// Inline assembly version of xt_overlay_get_state(). The arguments are
|
||||
// three AR registers (a0-a15):
|
||||
//
|
||||
// "pcreg" - should contain the outgoing task's PC, i.e. the point at
|
||||
// which the task got interrupted. The return value is also
|
||||
// returned in this register.
|
||||
// "sr1/2" - Scratch registers. These must be distinct from "pcreg".
|
||||
//
|
||||
// The return value is a 32-bit result that should be saved with the
|
||||
// task context and passed as-is to xt_overlay_check_map.
|
||||
|
||||
.macro _xt_overlay_get_state pcreg sr1 sr2
|
||||
|
||||
movi \sr1, _mapping_id
|
||||
movi \sr2, _ovly_id
|
||||
l16si \sr1, \sr1, 0
|
||||
l16ui \sr2, \sr2, 0
|
||||
slli \sr1, \sr1, 16
|
||||
or \pcreg, \sr1, \sr2
|
||||
|
||||
.endm
|
||||
|
||||
|
||||
// Inline assembly version of xt_overlay_check_map(). It requires 5 AR
|
||||
// registers (a0-a15) as arguments.
|
||||
//
|
||||
// "pcreg" - should contain the interrupted task's PC, i.e. the point
|
||||
// at which the task got interrupted. This will be adjusted
|
||||
// if required.
|
||||
// "psreg" - should contain the interrupted task's PS. This will be
|
||||
// adjusted if required.
|
||||
// "ovreg" - should contain the overlay state on entry. Contents may
|
||||
// be clobbered.
|
||||
// "spreg" - should contain the tasks stack pointer on entry.
|
||||
// "sr1" - Scratch register. Must be distinct from any of the above.
|
||||
//
|
||||
// The return values are "pcreg" and "psreg" and these must be used
|
||||
// to update the task's PC and PS.
|
||||
// Note that this macro may store data below the "spreg" pointer. If
|
||||
// it does, then it will also disable interrupts via the PS, so that
|
||||
// the task resumes with all interrupts disabled (to avoid corrupting
|
||||
// this data).
|
||||
//
|
||||
// (SP - 24) Overlay ID to restore
|
||||
// (SP - 28) Task PC
|
||||
// (SP - 32) Task PS
|
||||
|
||||
.macro _xt_overlay_check_map pcreg psreg ovreg spreg sr1
|
||||
|
||||
// There are four cases to deal with:
|
||||
//
|
||||
// _ovly_id = -1, _mapping_id = -1
|
||||
// No overlay is mapped or mapping, nothing to do.
|
||||
//
|
||||
// _ovly_id >= 0, _mapping_id = -1
|
||||
// An overlay was mapped, check PC to see if we need a restore.
|
||||
//
|
||||
// _ovly_id = -1, _mapping_id >= 0
|
||||
// An overlay is being mapped. Either it belongs to this task, which
|
||||
// implies that the PC is in the mapping function, or it does not
|
||||
// belong to this task. Either way there is nothing to do.
|
||||
//
|
||||
// _ovly_id >= 0, _mapping_id >= 0
|
||||
// Illegal, cannot happen by design. Don't need to handle this.
|
||||
//
|
||||
// So, the logic is to check _ovly_id first. If this is >= 0, then
|
||||
// we check the task PC. If the PC is in the regions of interest then
|
||||
// we'll patch the return PC to invoke xt_overlay_restore.
|
||||
|
||||
.L1:
|
||||
extui \sr1, \ovreg, 0, 16 // Extract _ovly_id
|
||||
bbsi.l \sr1, 15, .Lno // If -1 then we're done
|
||||
mov \ovreg, \sr1 // Restore this one
|
||||
|
||||
// Next check the PC to see if it falls within the ranges of interest.
|
||||
|
||||
.L2:
|
||||
movi \sr1, _overlay_vma // Is PC < VMA range ?
|
||||
bltu \pcreg, \sr1, .L3
|
||||
movi \sr1, _overlay_vma_end // Is PC > VMA range ?
|
||||
bgeu \pcreg, \sr1, .L3
|
||||
j .L4 // PC is in VMA range
|
||||
.L3:
|
||||
movi \sr1, _overlay_call_stubs_start // Is PC < call stubs range ?
|
||||
bltu \pcreg, \sr1, .Lno
|
||||
movi \sr1, _overlay_call_stubs_end // Is PC > call stubs range ?
|
||||
bgeu \pcreg, \sr1, .Lno
|
||||
|
||||
// If we get here then a restore is needed. Save the overlay ID, PC and PS.
|
||||
// Return modified PC and PS so that xt_overlay_restore() will execute in
|
||||
// the context of the task when resumed. Note that the OS resumption code
|
||||
// may expect PS.EXCM to be set so we leave it as is in the return value.
|
||||
|
||||
.L4:
|
||||
s32e \ovreg, \spreg, -24 // Save overlay ID
|
||||
s32e \pcreg, \spreg, -28 // Save task PC
|
||||
s32e \psreg, \spreg, -32 // Save task PS
|
||||
movi \pcreg, xt_overlay_restore // Adjust resumption PC
|
||||
movi \sr1, 15
|
||||
or \psreg, \psreg, \sr1 // Set intlevel to highest
|
||||
.Lno:
|
||||
|
||||
.endm
|
||||
|
||||
#endif // OVERLAY_OS_ASM_H
|
||||
|
||||
Executable
+60
@@ -0,0 +1,60 @@
|
||||
/* Copyright (c) 2004-2006 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
/ These coded instructions, statements, and computer programs are the
|
||||
/ copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
/ They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
/ third parties in any manner, medium, or form, in whole or in part, without
|
||||
/ the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* sim.h
|
||||
*
|
||||
* Definitions and prototypes for specific ISS SIMCALLs
|
||||
* (ie. outside the standard C library).
|
||||
*/
|
||||
|
||||
#ifndef _INC_SIM_H_
|
||||
#define _INC_SIM_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Shortcuts for enabling/disabling profiling in the Xtensa ISS */
|
||||
extern void xt_iss_profile_enable(void);
|
||||
extern void xt_iss_profile_disable(void);
|
||||
|
||||
/* Shortcut for setting the trace level in the Xtensa ISS */
|
||||
extern void xt_iss_trace_level(unsigned level);
|
||||
|
||||
/* Generic interface for passing client commands in the Xtensa ISS:
|
||||
* returns 0 on success, -1 on failure.
|
||||
*/
|
||||
extern int xt_iss_client_command(const char *client, const char *command);
|
||||
|
||||
/* Interface for switching simulation modes in the Xtensa ISS:
|
||||
* returns 0 on success, -1 on failure.
|
||||
*/
|
||||
#define XT_ISS_CYCLE_ACCURATE 0
|
||||
#define XT_ISS_FUNCTIONAL 1
|
||||
extern int xt_iss_switch_mode(int mode);
|
||||
|
||||
|
||||
/* Interface for waiting on a system synchronization event */
|
||||
extern void xt_iss_event_wait(unsigned event_id);
|
||||
|
||||
/* Interface for firing a system synchronization event */
|
||||
extern void xt_iss_event_fire(unsigned event_id);
|
||||
|
||||
/* Interface for invoking a user simcall action,
|
||||
* which can be registered in XTMP or XTSC.
|
||||
*/
|
||||
extern int xt_iss_simcall(int arg1, int arg2, int arg3,
|
||||
int arg4, int arg5, int arg6);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*_INC_SIM_H_*/
|
||||
|
||||
Executable
+71
@@ -0,0 +1,71 @@
|
||||
/*
|
||||
* Copyright (c) 2001 Tensilica Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/* simboard.h - Xtensa ISS "Board" specific definitions */
|
||||
|
||||
#ifndef _INC_SIMBOARD_H_
|
||||
#define _INC_SIMBOARD_H_
|
||||
|
||||
#include <xtensa/config/core.h>
|
||||
#include <xtensa/config/system.h>
|
||||
|
||||
|
||||
/*
|
||||
* Device addresses.
|
||||
*/
|
||||
|
||||
/* System ROM: */
|
||||
#define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE
|
||||
#ifdef XSHAL_ROM_VADDR
|
||||
#define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR
|
||||
#endif
|
||||
#ifdef XSHAL_ROM_PADDR
|
||||
#define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR
|
||||
#endif
|
||||
|
||||
/* System RAM: */
|
||||
#define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE
|
||||
#ifdef XSHAL_RAM_VADDR
|
||||
#define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR
|
||||
#endif
|
||||
#ifdef XSHAL_RAM_PADDR
|
||||
#define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Things that depend on device addresses.
|
||||
*/
|
||||
|
||||
#define XTBOARD_CACHEATTR_WRITEBACK XSHAL_ISS_CACHEATTR_WRITEBACK
|
||||
#define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_ISS_CACHEATTR_WRITEALLOC
|
||||
#define XTBOARD_CACHEATTR_WRITETHRU XSHAL_ISS_CACHEATTR_WRITETHRU
|
||||
#define XTBOARD_CACHEATTR_BYPASS XSHAL_ISS_CACHEATTR_BYPASS
|
||||
#define XTBOARD_CACHEATTR_DEFAULT XSHAL_ISS_CACHEATTR_DEFAULT
|
||||
|
||||
#define XTBOARD_BUSINT_PIPE_REGIONS 0
|
||||
#define XTBOARD_BUSINT_SDRAM_REGIONS 0
|
||||
|
||||
|
||||
#endif /*_INC_SIMBOARD_H_*/
|
||||
|
||||
+139
@@ -0,0 +1,139 @@
|
||||
/* Error numbers for Xtensa ISS semihosting. */
|
||||
|
||||
/* Copyright (c) 2003 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
These coded instructions, statements, and computer programs are the
|
||||
copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
third parties in any manner, medium, or form, in whole or in part, without
|
||||
the prior written consent of Tensilica Inc. */
|
||||
|
||||
#ifndef _SIMCALL_ERRNO_H
|
||||
#define _SIMCALL_ERRNO_H
|
||||
|
||||
/* Define the error numbers (using the default newlib values) with prefixes
|
||||
so they can be used in ISS without conflicting with the host values. */
|
||||
|
||||
#define _SIMC_EPERM 1
|
||||
#define _SIMC_ENOENT 2
|
||||
#define _SIMC_ESRCH 3
|
||||
#define _SIMC_EINTR 4
|
||||
#define _SIMC_EIO 5
|
||||
#define _SIMC_ENXIO 6
|
||||
#define _SIMC_E2BIG 7
|
||||
#define _SIMC_ENOEXEC 8
|
||||
#define _SIMC_EBADF 9
|
||||
#define _SIMC_ECHILD 10
|
||||
#define _SIMC_EAGAIN 11
|
||||
#define _SIMC_ENOMEM 12
|
||||
#define _SIMC_EACCES 13
|
||||
#define _SIMC_EFAULT 14
|
||||
#define _SIMC_ENOTBLK 15
|
||||
#define _SIMC_EBUSY 16
|
||||
#define _SIMC_EEXIST 17
|
||||
#define _SIMC_EXDEV 18
|
||||
#define _SIMC_ENODEV 19
|
||||
#define _SIMC_ENOTDIR 20
|
||||
#define _SIMC_EISDIR 21
|
||||
#define _SIMC_EINVAL 22
|
||||
#define _SIMC_ENFILE 23
|
||||
#define _SIMC_EMFILE 24
|
||||
#define _SIMC_ENOTTY 25
|
||||
#define _SIMC_ETXTBSY 26
|
||||
#define _SIMC_EFBIG 27
|
||||
#define _SIMC_ENOSPC 28
|
||||
#define _SIMC_ESPIPE 29
|
||||
#define _SIMC_EROFS 30
|
||||
#define _SIMC_EMLINK 31
|
||||
#define _SIMC_EPIPE 32
|
||||
#define _SIMC_EDOM 33
|
||||
#define _SIMC_ERANGE 34
|
||||
#define _SIMC_ENOMSG 35
|
||||
#define _SIMC_EIDRM 36
|
||||
#define _SIMC_ECHRNG 37
|
||||
#define _SIMC_EL2NSYNC 38
|
||||
#define _SIMC_EL3HLT 39
|
||||
#define _SIMC_EL3RST 40
|
||||
#define _SIMC_ELNRNG 41
|
||||
#define _SIMC_EUNATCH 42
|
||||
#define _SIMC_ENOCSI 43
|
||||
#define _SIMC_EL2HLT 44
|
||||
#define _SIMC_EDEADLK 45
|
||||
#define _SIMC_ENOLCK 46
|
||||
#define _SIMC_EBADE 50
|
||||
#define _SIMC_EBADR 51
|
||||
#define _SIMC_EXFULL 52
|
||||
#define _SIMC_ENOANO 53
|
||||
#define _SIMC_EBADRQC 54
|
||||
#define _SIMC_EBADSLT 55
|
||||
#define _SIMC_EDEADLOCK 56
|
||||
#define _SIMC_EBFONT 57
|
||||
#define _SIMC_ENOSTR 60
|
||||
#define _SIMC_ENODATA 61
|
||||
#define _SIMC_ETIME 62
|
||||
#define _SIMC_ENOSR 63
|
||||
#define _SIMC_ENONET 64
|
||||
#define _SIMC_ENOPKG 65
|
||||
#define _SIMC_EREMOTE 66
|
||||
#define _SIMC_ENOLINK 67
|
||||
#define _SIMC_EADV 68
|
||||
#define _SIMC_ESRMNT 69
|
||||
#define _SIMC_ECOMM 70
|
||||
#define _SIMC_EPROTO 71
|
||||
#define _SIMC_EMULTIHOP 74
|
||||
#define _SIMC_ELBIN 75
|
||||
#define _SIMC_EDOTDOT 76
|
||||
#define _SIMC_EBADMSG 77
|
||||
#define _SIMC_EFTYPE 79
|
||||
#define _SIMC_ENOTUNIQ 80
|
||||
#define _SIMC_EBADFD 81
|
||||
#define _SIMC_EREMCHG 82
|
||||
#define _SIMC_ELIBACC 83
|
||||
#define _SIMC_ELIBBAD 84
|
||||
#define _SIMC_ELIBSCN 85
|
||||
#define _SIMC_ELIBMAX 86
|
||||
#define _SIMC_ELIBEXEC 87
|
||||
#define _SIMC_ENOSYS 88
|
||||
#define _SIMC_ENMFILE 89
|
||||
#define _SIMC_ENOTEMPTY 90
|
||||
#define _SIMC_ENAMETOOLONG 91
|
||||
#define _SIMC_ELOOP 92
|
||||
#define _SIMC_EOPNOTSUPP 95
|
||||
#define _SIMC_EPFNOSUPPORT 96
|
||||
#define _SIMC_ECONNRESET 104
|
||||
#define _SIMC_ENOBUFS 105
|
||||
#define _SIMC_EAFNOSUPPORT 106
|
||||
#define _SIMC_EPROTOTYPE 107
|
||||
#define _SIMC_ENOTSOCK 108
|
||||
#define _SIMC_ENOPROTOOPT 109
|
||||
#define _SIMC_ESHUTDOWN 110
|
||||
#define _SIMC_ECONNREFUSED 111
|
||||
#define _SIMC_EADDRINUSE 112
|
||||
#define _SIMC_ECONNABORTED 113
|
||||
#define _SIMC_ENETUNREACH 114
|
||||
#define _SIMC_ENETDOWN 115
|
||||
#define _SIMC_ETIMEDOUT 116
|
||||
#define _SIMC_EHOSTDOWN 117
|
||||
#define _SIMC_EHOSTUNREACH 118
|
||||
#define _SIMC_EINPROGRESS 119
|
||||
#define _SIMC_EALREADY 120
|
||||
#define _SIMC_EDESTADDRREQ 121
|
||||
#define _SIMC_EMSGSIZE 122
|
||||
#define _SIMC_EPROTONOSUPPORT 123
|
||||
#define _SIMC_ESOCKTNOSUPPORT 124
|
||||
#define _SIMC_EADDRNOTAVAIL 125
|
||||
#define _SIMC_ENETRESET 126
|
||||
#define _SIMC_EISCONN 127
|
||||
#define _SIMC_ENOTCONN 128
|
||||
#define _SIMC_ETOOMANYREFS 129
|
||||
#define _SIMC_EPROCLIM 130
|
||||
#define _SIMC_EUSERS 131
|
||||
#define _SIMC_EDQUOT 132
|
||||
#define _SIMC_ESTALE 133
|
||||
#define _SIMC_ENOTSUP 134
|
||||
#define _SIMC_ENOMEDIUM 135
|
||||
#define _SIMC_ENOSHARE 136
|
||||
#define _SIMC_ECASECLASH 137
|
||||
#define _SIMC_EILSEQ 138
|
||||
#define _SIMC_EOVERFLOW 139
|
||||
|
||||
#endif /* ! _SIMCALL_ERRNO_H */
|
||||
+21
@@ -0,0 +1,21 @@
|
||||
/* File control operations for Xtensa ISS semihosting. */
|
||||
|
||||
/* Copyright (c) 2003 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
These coded instructions, statements, and computer programs are the
|
||||
copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
third parties in any manner, medium, or form, in whole or in part, without
|
||||
the prior written consent of Tensilica Inc. */
|
||||
|
||||
#ifndef _SIMCALL_FCNTL_H
|
||||
#define _SIMCALL_FCNTL_H
|
||||
|
||||
#define _SIMC_O_APPEND 0x0008
|
||||
#define _SIMC_O_NONBLOCK 0x0080
|
||||
#define _SIMC_O_CREAT 0x0100
|
||||
#define _SIMC_O_TRUNC 0x0200
|
||||
#define _SIMC_O_EXCL 0x0400
|
||||
#define _SIMC_O_TEXT 0x4000
|
||||
#define _SIMC_O_BINARY 0x8000
|
||||
|
||||
#endif /* ! _SIMCALL_FCNTL_H */
|
||||
Executable
+189
@@ -0,0 +1,189 @@
|
||||
/*
|
||||
* simcall.h - Simulator call numbers
|
||||
*
|
||||
* Software that runs on a simulated Xtensa processor using
|
||||
* the instruction set simulator (ISS) can invoke simulator
|
||||
* services using the SIMCALL instruction. The a2 register
|
||||
* is set prior to executing SIMCALL to a "simcall number",
|
||||
* indicating which service to invoke. This file defines the
|
||||
* simcall numbers defined and/or supported by the Xtensa ISS.
|
||||
*
|
||||
* IMPORTANT NOTE: These numbers are highly subject to change!
|
||||
*
|
||||
* Copyright (c) 2002-2007 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
#ifndef SIMCALL_INCLUDED
|
||||
#define SIMCALL_INCLUDED
|
||||
|
||||
/*
|
||||
* System call like services offered by the simulator host.
|
||||
* These are modeled after the Linux 2.4 kernel system calls
|
||||
* for Xtensa processors. However not all system calls and
|
||||
* not all functionality of a given system call are implemented,
|
||||
* or necessarily have well defined or equivalent semantics in
|
||||
* the context of a simulation (as opposed to a Unix kernel).
|
||||
*
|
||||
* These services behave largely as if they had been invoked
|
||||
* as a task in the simulator host's operating system
|
||||
* (eg. files accessed are those of the simulator host).
|
||||
* However, these SIMCALLs model a virtual operating system
|
||||
* so that various definitions, bit assignments etc
|
||||
* (eg. open mode bits, errno values, etc) are independent
|
||||
* of the host operating system used to run the simulation.
|
||||
* Rather these definitions are specific to the Xtensa ISS.
|
||||
* This way Xtensa ISA code written to use these SIMCALLs
|
||||
* can (in principle) be simulated on any host.
|
||||
*
|
||||
* Up to 6 parameters are passed in registers a3 to a8
|
||||
* (note the 6th parameter isn't passed on the stack,
|
||||
* unlike windowed function calling conventions).
|
||||
* The return value is in a2. A negative value in the
|
||||
* range -4096 to -1 indicates a negated error code to be
|
||||
* reported in errno with a return value of -1, otherwise
|
||||
* the value in a2 is returned as is.
|
||||
*/
|
||||
|
||||
/* These #defines need to match what's in Xtensa/OS/vxworks/xtiss/simcalls.c */
|
||||
|
||||
#define SYS_nop 0 /* n/a - setup; used to flush register windows */
|
||||
#define SYS_exit 1 /*x*/
|
||||
#define SYS_fork 2
|
||||
#define SYS_read 3 /*x*/
|
||||
#define SYS_write 4 /*x*/
|
||||
#define SYS_open 5 /*x*/
|
||||
#define SYS_close 6 /*x*/
|
||||
#define SYS_rename 7 /*x 38 - waitpid */
|
||||
#define SYS_creat 8 /*x*/
|
||||
#define SYS_link 9 /*x (not implemented on WIN32) */
|
||||
#define SYS_unlink 10 /*x*/
|
||||
#define SYS_execv 11 /* n/a - execve */
|
||||
#define SYS_execve 12 /* 11 - chdir */
|
||||
#define SYS_pipe 13 /* 42 - time */
|
||||
#define SYS_stat 14 /* 106 - mknod */
|
||||
#define SYS_chmod 15
|
||||
#define SYS_chown 16 /* 202 - lchown */
|
||||
#define SYS_utime 17 /* 30 - break */
|
||||
#define SYS_wait 18 /* n/a - oldstat */
|
||||
#define SYS_lseek 19 /*x*/
|
||||
#define SYS_getpid 20
|
||||
#define SYS_isatty 21 /* n/a - mount */
|
||||
#define SYS_fstat 22 /* 108 - oldumount */
|
||||
#define SYS_time 23 /* 13 - setuid */
|
||||
#define SYS_gettimeofday 24 /*x 78 - getuid (not implemented on WIN32) */
|
||||
#define SYS_times 25 /*X 43 - stime (Xtensa-specific implementation) */
|
||||
#define SYS_socket 26
|
||||
#define SYS_sendto 27
|
||||
#define SYS_recvfrom 28
|
||||
#define SYS_select_one 29 /* not compitible select, one file descriptor at the time */
|
||||
#define SYS_bind 30
|
||||
#define SYS_ioctl 31
|
||||
|
||||
/*
|
||||
* Other...
|
||||
*/
|
||||
#define SYS_iss_argc 1000 /* returns value of argc */
|
||||
#define SYS_iss_argv_size 1001 /* bytes needed for argv & arg strings */
|
||||
#define SYS_iss_set_argv 1002 /* saves argv & arg strings at given addr */
|
||||
|
||||
#define SYS_memset 1004 /* fill a range of memory (fast) */
|
||||
|
||||
/*
|
||||
* SIMCALLs for the ferret memory debugger. All are invoked by
|
||||
* libferret.a ... ( Xtensa/Target-Libs/ferret )
|
||||
*/
|
||||
#define SYS_ferret 1010
|
||||
#define SYS_malloc 1011
|
||||
#define SYS_free 1012
|
||||
#define SYS_more_heap 1013
|
||||
#define SYS_no_heap 1014
|
||||
#define SYS_enter_ferret 1015
|
||||
#define SYS_leave_ferret 1016
|
||||
|
||||
/*
|
||||
* SIMCALLs for ISS client commands
|
||||
*/
|
||||
#define SYS_profile_enable 1020
|
||||
#define SYS_profile_disable 1021
|
||||
#define SYS_trace_level 1022
|
||||
#define SYS_client_command 1023
|
||||
|
||||
/*
|
||||
* SIMCALL for simulation mode switching
|
||||
*/
|
||||
#define SYS_sim_mode_switch 1030
|
||||
|
||||
/*
|
||||
* SIMCALLs for XTMP/XTSC event notify and core stall
|
||||
*/
|
||||
#define SYS_event_fire 1040
|
||||
#define SYS_event_stall 1041
|
||||
|
||||
/*
|
||||
* SIMCALLs for callbacks registered in XTMP/XTSC
|
||||
*/
|
||||
#define SYS_callback_first 100
|
||||
#define SYS_callback_last 999
|
||||
|
||||
/*
|
||||
* User defined simcall
|
||||
*/
|
||||
#define SYS_user_simcall 100
|
||||
|
||||
#define SYS_xmpa_errinfo 200
|
||||
#define SYS_xmpa_proc_status 201
|
||||
#define SYS_xmpa_proc_start 202
|
||||
#define SYS_xmpa_proc_stop 203
|
||||
#define SYS_xmpa_proc_mem_read 204
|
||||
#define SYS_xmpa_proc_mem_write 205
|
||||
#define SYS_xmpa_proc_mem_fill 206
|
||||
#define SYS_xmpa_proc_reg_read 207
|
||||
#define SYS_xmpa_proc_reg_write 208
|
||||
|
||||
|
||||
/*
|
||||
* Extra SIMCALLs for GDB:
|
||||
*/
|
||||
#define SYS_gdb_break -1 /* invoked by XTOS on user exceptions if EPC points
|
||||
to a break.n/break, regardless of cause! */
|
||||
#define SYS_xmon_out -2 /* invoked by XMON: ... */
|
||||
#define SYS_xmon_in -3 /* invoked by XMON: ... */
|
||||
#define SYS_xmon_flush -4 /* invoked by XMON: ... */
|
||||
#define SYS_gdb_abort -5 /* invoked by XTOS in _xtos_panic() */
|
||||
#define SYS_gdb_illegal_inst -6 /* invoked by XTOS for illegal instructions (too deeply) */
|
||||
#define SYS_xmon_init -7 /* invoked by XMON: ... */
|
||||
#define SYS_gdb_enter_sktloop -8 /* invoked by XTOS on debug exceptions */
|
||||
#define SYS_unhandled_kernel_exc -9 /* invoked by XTOS for unhandled kernel exceptions */
|
||||
#define SYS_unhandled_user_exc -10 /* invoked by XTOS for unhandled user exceptions */
|
||||
#define SYS_unhandled_double_exc -11 /* invoked by XTOS for unhandled double exceptions */
|
||||
#define SYS_unhandled_highpri_interrupt -12 /* invoked by XTOS for unhandled high-priority interrupts */
|
||||
#define SYS_xmon_close -13 /* invoked by XMON: ... */
|
||||
|
||||
/*
|
||||
* SIMCALLs for vxWorks xtiss BSP:
|
||||
*/
|
||||
#define SYS_setup_ppp_pipes -83
|
||||
#define SYS_log_msg -84
|
||||
|
||||
/*
|
||||
* SYS_select_one specifiers
|
||||
*/
|
||||
#define XTISS_SELECT_ONE_READ 1
|
||||
#define XTISS_SELECT_ONE_WRITE 2
|
||||
#define XTISS_SELECT_ONE_EXCEPT 3
|
||||
|
||||
/*
|
||||
* SIMCALL for client calling arbitrary code in a client plug in.
|
||||
* see clients/xcc_instr to see how this works.
|
||||
*/
|
||||
|
||||
#define SYS_client 0xC0DECAFE
|
||||
|
||||
|
||||
|
||||
#endif /* !SIMCALL_INCLUDED */
|
||||
Executable
+143
@@ -0,0 +1,143 @@
|
||||
/*
|
||||
* Xtensa Special Register symbolic names
|
||||
*/
|
||||
|
||||
/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/specreg.h#2 $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2005-2011 Tensilica Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef XTENSA_SPECREG_H
|
||||
#define XTENSA_SPECREG_H
|
||||
|
||||
/* Special registers: */
|
||||
#define LBEG 0
|
||||
#define LEND 1
|
||||
#define LCOUNT 2
|
||||
#define SAR 3
|
||||
#define BR 4
|
||||
#define LITBASE 5
|
||||
#define SCOMPARE1 12
|
||||
#define ACCLO 16
|
||||
#define ACCHI 17
|
||||
#define MR_0 32
|
||||
#define MR_1 33
|
||||
#define MR_2 34
|
||||
#define MR_3 35
|
||||
#define PREFCTL 40
|
||||
#define WINDOWBASE 72
|
||||
#define WINDOWSTART 73
|
||||
#define PTEVADDR 83
|
||||
#define RASID 90
|
||||
#define ITLBCFG 91
|
||||
#define DTLBCFG 92
|
||||
#define IBREAKENABLE 96
|
||||
#define MEMCTL 97
|
||||
#define CACHEATTR 98
|
||||
#define ATOMCTL 99
|
||||
#define DDR 104
|
||||
#define MECR 110
|
||||
#define IBREAKA_0 128
|
||||
#define IBREAKA_1 129
|
||||
#define DBREAKA_0 144
|
||||
#define DBREAKA_1 145
|
||||
#define DBREAKC_0 160
|
||||
#define DBREAKC_1 161
|
||||
#define CONFIGID0 176
|
||||
#define EPC_1 177
|
||||
#define EPC_2 178
|
||||
#define EPC_3 179
|
||||
#define EPC_4 180
|
||||
#define EPC_5 181
|
||||
#define EPC_6 182
|
||||
#define EPC_7 183
|
||||
#define DEPC 192
|
||||
#define EPS_2 194
|
||||
#define EPS_3 195
|
||||
#define EPS_4 196
|
||||
#define EPS_5 197
|
||||
#define EPS_6 198
|
||||
#define EPS_7 199
|
||||
#define CONFIGID1 208
|
||||
#define EXCSAVE_1 209
|
||||
#define EXCSAVE_2 210
|
||||
#define EXCSAVE_3 211
|
||||
#define EXCSAVE_4 212
|
||||
#define EXCSAVE_5 213
|
||||
#define EXCSAVE_6 214
|
||||
#define EXCSAVE_7 215
|
||||
#define CPENABLE 224
|
||||
#define INTERRUPT 226
|
||||
#define INTREAD INTERRUPT /* alternate name for backward compatibility */
|
||||
#define INTSET INTERRUPT /* alternate name for backward compatibility */
|
||||
#define INTCLEAR 227
|
||||
#define INTENABLE 228
|
||||
#define PS 230
|
||||
#define VECBASE 231
|
||||
#define EXCCAUSE 232
|
||||
#define DEBUGCAUSE 233
|
||||
#define CCOUNT 234
|
||||
#define PRID 235
|
||||
#define ICOUNT 236
|
||||
#define ICOUNTLEVEL 237
|
||||
#define EXCVADDR 238
|
||||
#define CCOMPARE_0 240
|
||||
#define CCOMPARE_1 241
|
||||
#define CCOMPARE_2 242
|
||||
#define MISC_REG_0 244
|
||||
#define MISC_REG_1 245
|
||||
#define MISC_REG_2 246
|
||||
#define MISC_REG_3 247
|
||||
|
||||
/* Special cases (bases of special register series): */
|
||||
#define MR 32
|
||||
#define IBREAKA 128
|
||||
#define DBREAKA 144
|
||||
#define DBREAKC 160
|
||||
#define EPC 176
|
||||
#define EPS 192
|
||||
#define EXCSAVE 208
|
||||
#define CCOMPARE 240
|
||||
#define MISC_REG 244
|
||||
|
||||
/* Tensilica-defined user registers: */
|
||||
#if 0
|
||||
/*#define ... 21..24 */ /* (545CK) */
|
||||
/*#define ... 140..143 */ /* (545CK) */
|
||||
#define EXPSTATE 230 /* Diamond */
|
||||
#define THREADPTR 231 /* threadptr option */
|
||||
#define FCR 232 /* FPU */
|
||||
#define FSR 233 /* FPU */
|
||||
#define AE_OVF_SAR 240 /* HiFi2 */
|
||||
#define AE_BITHEAD 241 /* HiFi2 */
|
||||
#define AE_TS_FTS_BU_BP 242 /* HiFi2 */
|
||||
#define AE_SD_NO 243 /* HiFi2 */
|
||||
#define VSAR 240 /* VectraLX */
|
||||
#define ROUND_LO 242 /* VectraLX */
|
||||
#define ROUND_HI 243 /* VectraLX */
|
||||
#define CBEGIN 246 /* VectraLX */
|
||||
#define CEND 247 /* VectraLX */
|
||||
#endif
|
||||
|
||||
#endif /* XTENSA_SPECREG_H */
|
||||
|
||||
@@ -0,0 +1,96 @@
|
||||
/* Definitions for the xt_DFP_assist TIE package */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_DFP_assist_HEADER
|
||||
#define _XTENSA_xt_DFP_assist_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#ifdef __XCC__
|
||||
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
|
||||
/*
|
||||
* The following prototypes describe intrinsic functions
|
||||
* corresponding to TIE instructions. Some TIE instructions
|
||||
* may produce multiple results (designated as "out" operands
|
||||
* in the iclass section) or may have operands used as both
|
||||
* inputs and outputs (designated as "inout"). However, the C
|
||||
* and C++ languages do not provide syntax that can express
|
||||
* the in/out/inout constraints of TIE intrinsics.
|
||||
* Nevertheless, the compiler understands these constraints
|
||||
* and will check that the intrinsic functions are used
|
||||
* correctly. To improve the readability of these prototypes,
|
||||
* the "out" and "inout" parameters are marked accordingly
|
||||
* with comments.
|
||||
*/
|
||||
|
||||
extern void _TIE_xt_DFP_assist_F64ITER(unsigned arr /*inout*/, unsigned ars, unsigned art, immediate oper, immediate noshift);
|
||||
extern unsigned _TIE_xt_DFP_assist_F64RND(unsigned ars, unsigned art, immediate mode);
|
||||
extern void _TIE_xt_DFP_assist_F64ADDC(unsigned art /*inout*/, unsigned ars, immediate immZ, immediate immC);
|
||||
extern void _TIE_xt_DFP_assist_F64SUBC(unsigned art /*inout*/, unsigned ars, immediate immZ, immediate immC);
|
||||
extern unsigned _TIE_xt_DFP_assist_F64SIG(unsigned ars);
|
||||
extern unsigned _TIE_xt_DFP_assist_F64CMPL(unsigned ars, unsigned art);
|
||||
extern unsigned _TIE_xt_DFP_assist_F64CMPH(unsigned ars, unsigned art, immediate oper);
|
||||
extern unsigned _TIE_xt_DFP_assist_F64NORM(unsigned ars, unsigned art, immediate mode);
|
||||
extern unsigned _TIE_xt_DFP_assist_F64SEXP(unsigned ars, unsigned art);
|
||||
extern unsigned _TIE_xt_DFP_assist_RF64R(immediate hilo);
|
||||
extern void _TIE_xt_DFP_assist_WF64R(unsigned ars, unsigned art, immediate hilo);
|
||||
extern unsigned _TIE_xt_DFP_assist_RUR_F64R_LO(void);
|
||||
extern unsigned _TIE_xt_DFP_assist_RUR_F64R_HI(void);
|
||||
extern void _TIE_xt_DFP_assist_WUR_F64R_LO(unsigned art);
|
||||
extern void _TIE_xt_DFP_assist_WUR_F64R_HI(unsigned art);
|
||||
extern unsigned _TIE_xt_DFP_assist_RUR_F64S(void);
|
||||
extern void _TIE_xt_DFP_assist_WUR_F64S(unsigned art);
|
||||
#define F64ITER _TIE_xt_DFP_assist_F64ITER
|
||||
#define F64RND _TIE_xt_DFP_assist_F64RND
|
||||
#define F64ADDC _TIE_xt_DFP_assist_F64ADDC
|
||||
#define F64SUBC _TIE_xt_DFP_assist_F64SUBC
|
||||
#define F64SIG _TIE_xt_DFP_assist_F64SIG
|
||||
#define F64CMPL _TIE_xt_DFP_assist_F64CMPL
|
||||
#define F64CMPH _TIE_xt_DFP_assist_F64CMPH
|
||||
#define F64NORM _TIE_xt_DFP_assist_F64NORM
|
||||
#define F64SEXP _TIE_xt_DFP_assist_F64SEXP
|
||||
#define RF64R _TIE_xt_DFP_assist_RF64R
|
||||
#define WF64R _TIE_xt_DFP_assist_WF64R
|
||||
#define RUR_F64R_LO _TIE_xt_DFP_assist_RUR_F64R_LO
|
||||
#define RF64R_LO _TIE_xt_DFP_assist_RUR_F64R_LO
|
||||
#define RUR234 _TIE_xt_DFP_assist_RUR_F64R_LO
|
||||
#define RUR_F64R_HI _TIE_xt_DFP_assist_RUR_F64R_HI
|
||||
#define RF64R_HI _TIE_xt_DFP_assist_RUR_F64R_HI
|
||||
#define RUR235 _TIE_xt_DFP_assist_RUR_F64R_HI
|
||||
#define WUR_F64R_LO _TIE_xt_DFP_assist_WUR_F64R_LO
|
||||
#define WF64R_LO _TIE_xt_DFP_assist_WUR_F64R_LO
|
||||
#define WUR234 _TIE_xt_DFP_assist_WUR_F64R_LO
|
||||
#define WUR_F64R_HI _TIE_xt_DFP_assist_WUR_F64R_HI
|
||||
#define WF64R_HI _TIE_xt_DFP_assist_WUR_F64R_HI
|
||||
#define WUR235 _TIE_xt_DFP_assist_WUR_F64R_HI
|
||||
#define RUR_F64S _TIE_xt_DFP_assist_RUR_F64S
|
||||
#define RF64S _TIE_xt_DFP_assist_RUR_F64S
|
||||
#define RUR236 _TIE_xt_DFP_assist_RUR_F64S
|
||||
#define WUR_F64S _TIE_xt_DFP_assist_WUR_F64S
|
||||
#define WF64S _TIE_xt_DFP_assist_WUR_F64S
|
||||
#define WUR236 _TIE_xt_DFP_assist_WUR_F64S
|
||||
|
||||
#ifndef RUR
|
||||
#define RUR(NUM) RUR##NUM()
|
||||
#endif
|
||||
|
||||
#ifndef WUR
|
||||
#define WUR(VAL, NUM) WUR##NUM(VAL)
|
||||
#endif
|
||||
|
||||
#endif /* __XCC__ */
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
|
||||
#endif /* !_XTENSA_xt_DFP_assist_HEADER */
|
||||
@@ -0,0 +1,197 @@
|
||||
/* Definitions for the xt_FP TIE package */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_FP_HEADER
|
||||
#define _XTENSA_xt_FP_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#ifdef __XCC__
|
||||
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
#include <xtensa/tie/xt_booleans.h>
|
||||
typedef float _TIE_xt_FP_xtfloat;
|
||||
typedef _TIE_xt_FP_xtfloat xtfloat;
|
||||
|
||||
/*
|
||||
* The following prototypes describe intrinsic functions
|
||||
* corresponding to TIE instructions. Some TIE instructions
|
||||
* may produce multiple results (designated as "out" operands
|
||||
* in the iclass section) or may have operands used as both
|
||||
* inputs and outputs (designated as "inout"). However, the C
|
||||
* and C++ languages do not provide syntax that can express
|
||||
* the in/out/inout constraints of TIE intrinsics.
|
||||
* Nevertheless, the compiler understands these constraints
|
||||
* and will check that the intrinsic functions are used
|
||||
* correctly. To improve the readability of these prototypes,
|
||||
* the "out" and "inout" parameters are marked accordingly
|
||||
* with comments.
|
||||
*/
|
||||
|
||||
extern unsigned _TIE_xt_FP_RUR_FCR(void);
|
||||
extern void _TIE_xt_FP_WUR_FCR(unsigned v);
|
||||
extern unsigned _TIE_xt_FP_RUR_FSR(void);
|
||||
extern void _TIE_xt_FP_WUR_FSR(unsigned v);
|
||||
extern xtfloat _TIE_xt_FP_xtfloat_loadi(const xtfloat * p, immediate imm8x4);
|
||||
extern void _TIE_xt_FP_xtfloat_storei(xtfloat t, xtfloat * p, immediate imm8x4);
|
||||
extern void _TIE_xt_FP_xtfloat_loadip(xtfloat t /*out*/, const xtfloat * p /*inout*/, immediate imm8x4);
|
||||
extern void _TIE_xt_FP_xtfloat_storeip(xtfloat t, xtfloat * p /*inout*/, immediate imm8x4);
|
||||
extern xtfloat _TIE_xt_FP_xtfloat_loadx(const xtfloat * p, int imm8x4);
|
||||
extern void _TIE_xt_FP_xtfloat_storex(xtfloat t, xtfloat * p, int imm8x4);
|
||||
extern void _TIE_xt_FP_xtfloat_loadxp(xtfloat t /*out*/, const xtfloat * p /*inout*/, int imm8x4);
|
||||
extern void _TIE_xt_FP_xtfloat_storexp(xtfloat t, xtfloat * p /*inout*/, int imm8x4);
|
||||
extern xtfloat _TIE_xt_FP_xtfloat_move(xtfloat r);
|
||||
extern int _TIE_xt_FP_ROUND_S(xtfloat s, immediate t);
|
||||
extern int _TIE_xt_FP_TRUNC_S(xtfloat s, immediate t);
|
||||
extern unsigned _TIE_xt_FP_UTRUNC_S(xtfloat s, immediate t);
|
||||
extern int _TIE_xt_FP_FLOOR_S(xtfloat s, immediate t);
|
||||
extern int _TIE_xt_FP_CEIL_S(xtfloat s, immediate t);
|
||||
extern xtfloat _TIE_xt_FP_LSI(const xtfloat * p, immediate imm8x4);
|
||||
extern void _TIE_xt_FP_SSI(xtfloat t, xtfloat * p, immediate imm8x4);
|
||||
extern void _TIE_xt_FP_LSIP(xtfloat t /*out*/, const xtfloat * p /*inout*/, immediate imm8x4);
|
||||
extern void _TIE_xt_FP_SSIP(xtfloat t, xtfloat * p /*inout*/, immediate imm8x4);
|
||||
extern xtfloat _TIE_xt_FP_LSX(const xtfloat * p, int imm8x4);
|
||||
extern void _TIE_xt_FP_SSX(xtfloat t, xtfloat * p, int imm8x4);
|
||||
extern void _TIE_xt_FP_LSXP(xtfloat t /*out*/, const xtfloat * p /*inout*/, int imm8x4);
|
||||
extern void _TIE_xt_FP_SSXP(xtfloat t, xtfloat * p /*inout*/, int imm8x4);
|
||||
extern xtfloat _TIE_xt_FP_ABS_S(xtfloat s);
|
||||
extern xtfloat _TIE_xt_FP_NEG_S(xtfloat s);
|
||||
extern xtfloat _TIE_xt_FP_MOV_S(xtfloat s);
|
||||
extern void _TIE_xt_FP_MOVEQZ_S(xtfloat r /*inout*/, xtfloat s, int t);
|
||||
extern void _TIE_xt_FP_MOVNEZ_S(xtfloat r /*inout*/, xtfloat s, int t);
|
||||
extern void _TIE_xt_FP_MOVLTZ_S(xtfloat r /*inout*/, xtfloat s, int t);
|
||||
extern void _TIE_xt_FP_MOVGEZ_S(xtfloat r /*inout*/, xtfloat s, int t);
|
||||
extern void _TIE_xt_FP_MOVF_S(xtfloat r /*inout*/, xtfloat s, xtbool t);
|
||||
extern void _TIE_xt_FP_MOVT_S(xtfloat r /*inout*/, xtfloat s, xtbool t);
|
||||
extern unsigned _TIE_xt_FP_RFR(xtfloat s);
|
||||
extern xtfloat _TIE_xt_FP_WFR(unsigned s);
|
||||
extern xtfloat _TIE_xt_FP_FLOAT_S(int s, immediate t);
|
||||
extern xtfloat _TIE_xt_FP_UFLOAT_S(unsigned s, immediate t);
|
||||
extern xtbool _TIE_xt_FP_OEQ_S(xtfloat s, xtfloat t);
|
||||
extern xtbool _TIE_xt_FP_OLE_S(xtfloat s, xtfloat t);
|
||||
extern xtbool _TIE_xt_FP_OLT_S(xtfloat s, xtfloat t);
|
||||
extern xtbool _TIE_xt_FP_UEQ_S(xtfloat s, xtfloat t);
|
||||
extern xtbool _TIE_xt_FP_ULE_S(xtfloat s, xtfloat t);
|
||||
extern xtbool _TIE_xt_FP_ULT_S(xtfloat s, xtfloat t);
|
||||
extern xtbool _TIE_xt_FP_UN_S(xtfloat s, xtfloat t);
|
||||
extern xtfloat _TIE_xt_FP_ADD_S(xtfloat s, xtfloat t);
|
||||
extern xtfloat _TIE_xt_FP_SUB_S(xtfloat s, xtfloat t);
|
||||
extern xtfloat _TIE_xt_FP_MUL_S(xtfloat s, xtfloat t);
|
||||
extern void _TIE_xt_FP_MADD_S(xtfloat r /*inout*/, xtfloat s, xtfloat t);
|
||||
extern void _TIE_xt_FP_MSUB_S(xtfloat r /*inout*/, xtfloat s, xtfloat t);
|
||||
extern xtfloat _TIE_xt_FP_RECIP0_S(xtfloat s);
|
||||
extern xtfloat _TIE_xt_FP_DIV0_S(xtfloat s);
|
||||
extern xtfloat _TIE_xt_FP_NEXP01_S(xtfloat s);
|
||||
extern xtfloat _TIE_xt_FP_CONST_S(immediate s);
|
||||
extern void _TIE_xt_FP_MKDADJ_S(xtfloat r /*inout*/, xtfloat s);
|
||||
extern xtfloat _TIE_xt_FP_MKSADJ_S(xtfloat s);
|
||||
extern void _TIE_xt_FP_ADDEXPM_S(xtfloat r /*inout*/, xtfloat s);
|
||||
extern void _TIE_xt_FP_ADDEXP_S(xtfloat r /*inout*/, xtfloat s);
|
||||
extern void _TIE_xt_FP_DIVN_S(xtfloat r /*inout*/, xtfloat s, xtfloat t);
|
||||
extern xtfloat _TIE_xt_FP_RSQRT0_S(xtfloat s);
|
||||
extern xtfloat _TIE_xt_FP_SQRT0_S(xtfloat s);
|
||||
extern void _TIE_xt_FP_MADDN_S(xtfloat r /*inout*/, xtfloat s, xtfloat t);
|
||||
extern xtfloat _TIE_xt_FP_DIV_S(xtfloat s, xtfloat t);
|
||||
extern xtfloat _TIE_xt_FP_SQRT_S(xtfloat s);
|
||||
extern xtfloat _TIE_xt_FP_RECIP_S(xtfloat s);
|
||||
extern xtfloat _TIE_xt_FP_RSQRT_S(xtfloat s);
|
||||
extern xtfloat _TIE_xt_FP_FSQRT_S(xtfloat s);
|
||||
#define XT_RUR_FCR _TIE_xt_FP_RUR_FCR
|
||||
#define RFCR _TIE_xt_FP_RUR_FCR
|
||||
#define RUR232 _TIE_xt_FP_RUR_FCR
|
||||
#define XT_WUR_FCR _TIE_xt_FP_WUR_FCR
|
||||
#define WFCR _TIE_xt_FP_WUR_FCR
|
||||
#define WUR232 _TIE_xt_FP_WUR_FCR
|
||||
#define XT_RUR_FSR _TIE_xt_FP_RUR_FSR
|
||||
#define RFSR _TIE_xt_FP_RUR_FSR
|
||||
#define RUR233 _TIE_xt_FP_RUR_FSR
|
||||
#define XT_WUR_FSR _TIE_xt_FP_WUR_FSR
|
||||
#define WFSR _TIE_xt_FP_WUR_FSR
|
||||
#define WUR233 _TIE_xt_FP_WUR_FSR
|
||||
#define XT_xtfloat_loadi _TIE_xt_FP_xtfloat_loadi
|
||||
#define XT_xtfloat_storei _TIE_xt_FP_xtfloat_storei
|
||||
#define XT_xtfloat_loadip _TIE_xt_FP_xtfloat_loadip
|
||||
#define XT_xtfloat_storeip _TIE_xt_FP_xtfloat_storeip
|
||||
#define XT_xtfloat_loadx _TIE_xt_FP_xtfloat_loadx
|
||||
#define XT_xtfloat_storex _TIE_xt_FP_xtfloat_storex
|
||||
#define XT_xtfloat_loadxp _TIE_xt_FP_xtfloat_loadxp
|
||||
#define XT_xtfloat_storexp _TIE_xt_FP_xtfloat_storexp
|
||||
#define XT_xtfloat_move _TIE_xt_FP_xtfloat_move
|
||||
#define XT_ROUND_S _TIE_xt_FP_ROUND_S
|
||||
#define XT_TRUNC_S _TIE_xt_FP_TRUNC_S
|
||||
#define XT_UTRUNC_S _TIE_xt_FP_UTRUNC_S
|
||||
#define XT_FLOOR_S _TIE_xt_FP_FLOOR_S
|
||||
#define XT_CEIL_S _TIE_xt_FP_CEIL_S
|
||||
#define XT_LSI _TIE_xt_FP_LSI
|
||||
#define XT_SSI _TIE_xt_FP_SSI
|
||||
#define XT_LSIP _TIE_xt_FP_LSIP
|
||||
#define XT_SSIP _TIE_xt_FP_SSIP
|
||||
#define XT_LSX _TIE_xt_FP_LSX
|
||||
#define XT_SSX _TIE_xt_FP_SSX
|
||||
#define XT_LSXP _TIE_xt_FP_LSXP
|
||||
#define XT_SSXP _TIE_xt_FP_SSXP
|
||||
#define XT_ABS_S _TIE_xt_FP_ABS_S
|
||||
#define XT_NEG_S _TIE_xt_FP_NEG_S
|
||||
#define XT_MOV_S _TIE_xt_FP_MOV_S
|
||||
#define XT_MOVEQZ_S _TIE_xt_FP_MOVEQZ_S
|
||||
#define XT_MOVNEZ_S _TIE_xt_FP_MOVNEZ_S
|
||||
#define XT_MOVLTZ_S _TIE_xt_FP_MOVLTZ_S
|
||||
#define XT_MOVGEZ_S _TIE_xt_FP_MOVGEZ_S
|
||||
#define XT_MOVF_S _TIE_xt_FP_MOVF_S
|
||||
#define XT_MOVT_S _TIE_xt_FP_MOVT_S
|
||||
#define XT_RFR _TIE_xt_FP_RFR
|
||||
#define XT_WFR _TIE_xt_FP_WFR
|
||||
#define XT_FLOAT_S _TIE_xt_FP_FLOAT_S
|
||||
#define XT_UFLOAT_S _TIE_xt_FP_UFLOAT_S
|
||||
#define XT_OEQ_S _TIE_xt_FP_OEQ_S
|
||||
#define XT_OLE_S _TIE_xt_FP_OLE_S
|
||||
#define XT_OLT_S _TIE_xt_FP_OLT_S
|
||||
#define XT_UEQ_S _TIE_xt_FP_UEQ_S
|
||||
#define XT_ULE_S _TIE_xt_FP_ULE_S
|
||||
#define XT_ULT_S _TIE_xt_FP_ULT_S
|
||||
#define XT_UN_S _TIE_xt_FP_UN_S
|
||||
#define XT_ADD_S _TIE_xt_FP_ADD_S
|
||||
#define XT_SUB_S _TIE_xt_FP_SUB_S
|
||||
#define XT_MUL_S _TIE_xt_FP_MUL_S
|
||||
#define XT_MADD_S _TIE_xt_FP_MADD_S
|
||||
#define XT_MSUB_S _TIE_xt_FP_MSUB_S
|
||||
#define XT_RECIP0_S _TIE_xt_FP_RECIP0_S
|
||||
#define XT_DIV0_S _TIE_xt_FP_DIV0_S
|
||||
#define XT_NEXP01_S _TIE_xt_FP_NEXP01_S
|
||||
#define XT_CONST_S _TIE_xt_FP_CONST_S
|
||||
#define XT_MKDADJ_S _TIE_xt_FP_MKDADJ_S
|
||||
#define XT_MKSADJ_S _TIE_xt_FP_MKSADJ_S
|
||||
#define XT_ADDEXPM_S _TIE_xt_FP_ADDEXPM_S
|
||||
#define XT_ADDEXP_S _TIE_xt_FP_ADDEXP_S
|
||||
#define XT_DIVN_S _TIE_xt_FP_DIVN_S
|
||||
#define XT_RSQRT0_S _TIE_xt_FP_RSQRT0_S
|
||||
#define XT_SQRT0_S _TIE_xt_FP_SQRT0_S
|
||||
#define XT_MADDN_S _TIE_xt_FP_MADDN_S
|
||||
#define XT_DIV_S _TIE_xt_FP_DIV_S
|
||||
#define XT_SQRT_S _TIE_xt_FP_SQRT_S
|
||||
#define XT_RECIP_S _TIE_xt_FP_RECIP_S
|
||||
#define XT_RSQRT_S _TIE_xt_FP_RSQRT_S
|
||||
#define XT_FSQRT_S _TIE_xt_FP_FSQRT_S
|
||||
|
||||
#ifndef RUR
|
||||
#define RUR(NUM) RUR##NUM()
|
||||
#endif
|
||||
|
||||
#ifndef WUR
|
||||
#define WUR(VAL, NUM) WUR##NUM(VAL)
|
||||
#endif
|
||||
|
||||
#endif /* __XCC__ */
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
|
||||
#endif /* !_XTENSA_xt_FP_HEADER */
|
||||
@@ -0,0 +1,239 @@
|
||||
/* Definitions for the xt_MAC16 TIE package */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_MAC16_HEADER
|
||||
#define _XTENSA_xt_MAC16_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#ifdef __XCC__
|
||||
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
#include <xtensa/tie/xt_mul.h>
|
||||
|
||||
/*
|
||||
* The following prototypes describe intrinsic functions
|
||||
* corresponding to TIE instructions. Some TIE instructions
|
||||
* may produce multiple results (designated as "out" operands
|
||||
* in the iclass section) or may have operands used as both
|
||||
* inputs and outputs (designated as "inout"). However, the C
|
||||
* and C++ languages do not provide syntax that can express
|
||||
* the in/out/inout constraints of TIE intrinsics.
|
||||
* Nevertheless, the compiler understands these constraints
|
||||
* and will check that the intrinsic functions are used
|
||||
* correctly. To improve the readability of these prototypes,
|
||||
* the "out" and "inout" parameters are marked accordingly
|
||||
* with comments.
|
||||
*/
|
||||
|
||||
extern void _TIE_xt_MAC16_UMUL_AA_HH(unsigned ars, unsigned art);
|
||||
extern void _TIE_xt_MAC16_UMUL_AA_LH(unsigned ars, unsigned art);
|
||||
extern void _TIE_xt_MAC16_UMUL_AA_HL(unsigned ars, unsigned art);
|
||||
extern void _TIE_xt_MAC16_UMUL_AA_LL(unsigned ars, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MUL_AA_HH(unsigned ars, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MUL_AA_LH(unsigned ars, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MUL_AA_HL(unsigned ars, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MUL_AA_LL(unsigned ars, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MUL_AD_HH(unsigned ars, immediate my);
|
||||
extern void _TIE_xt_MAC16_MUL_AD_LH(unsigned ars, immediate my);
|
||||
extern void _TIE_xt_MAC16_MUL_AD_HL(unsigned ars, immediate my);
|
||||
extern void _TIE_xt_MAC16_MUL_AD_LL(unsigned ars, immediate my);
|
||||
extern void _TIE_xt_MAC16_MUL_DA_HH(immediate mx, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MUL_DA_LH(immediate mx, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MUL_DA_HL(immediate mx, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MUL_DA_LL(immediate mx, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MUL_DD_HH(immediate mx, immediate my);
|
||||
extern void _TIE_xt_MAC16_MUL_DD_LH(immediate mx, immediate my);
|
||||
extern void _TIE_xt_MAC16_MUL_DD_HL(immediate mx, immediate my);
|
||||
extern void _TIE_xt_MAC16_MUL_DD_LL(immediate mx, immediate my);
|
||||
extern void _TIE_xt_MAC16_MULS_AA_HH(unsigned ars, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MULS_AA_LH(unsigned ars, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MULS_AA_HL(unsigned ars, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MULS_AA_LL(unsigned ars, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MULA_AA_HH(unsigned ars, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MULA_AA_LH(unsigned ars, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MULA_AA_HL(unsigned ars, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MULA_AA_LL(unsigned ars, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MULS_AD_HH(unsigned ars, immediate my);
|
||||
extern void _TIE_xt_MAC16_MULS_AD_LH(unsigned ars, immediate my);
|
||||
extern void _TIE_xt_MAC16_MULS_AD_HL(unsigned ars, immediate my);
|
||||
extern void _TIE_xt_MAC16_MULS_AD_LL(unsigned ars, immediate my);
|
||||
extern void _TIE_xt_MAC16_MULA_AD_HH(unsigned ars, immediate my);
|
||||
extern void _TIE_xt_MAC16_MULA_AD_LH(unsigned ars, immediate my);
|
||||
extern void _TIE_xt_MAC16_MULA_AD_HL(unsigned ars, immediate my);
|
||||
extern void _TIE_xt_MAC16_MULA_AD_LL(unsigned ars, immediate my);
|
||||
extern void _TIE_xt_MAC16_MULS_DA_HH(immediate mx, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MULS_DA_LH(immediate mx, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MULS_DA_HL(immediate mx, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MULS_DA_LL(immediate mx, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MULA_DA_HH(immediate mx, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MULA_DA_LH(immediate mx, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MULA_DA_HL(immediate mx, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MULA_DA_LL(immediate mx, unsigned art);
|
||||
extern void _TIE_xt_MAC16_MULS_DD_HH(immediate mx, immediate my);
|
||||
extern void _TIE_xt_MAC16_MULS_DD_LH(immediate mx, immediate my);
|
||||
extern void _TIE_xt_MAC16_MULS_DD_HL(immediate mx, immediate my);
|
||||
extern void _TIE_xt_MAC16_MULS_DD_LL(immediate mx, immediate my);
|
||||
extern void _TIE_xt_MAC16_MULA_DD_HH(immediate mx, immediate my);
|
||||
extern void _TIE_xt_MAC16_MULA_DD_LH(immediate mx, immediate my);
|
||||
extern void _TIE_xt_MAC16_MULA_DD_HL(immediate mx, immediate my);
|
||||
extern void _TIE_xt_MAC16_MULA_DD_LL(immediate mx, immediate my);
|
||||
extern unsigned _TIE_xt_MAC16_RSR_M0(void);
|
||||
extern void _TIE_xt_MAC16_WSR_M0(unsigned art);
|
||||
extern void _TIE_xt_MAC16_XSR_M0(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_MAC16_RSR_M1(void);
|
||||
extern void _TIE_xt_MAC16_WSR_M1(unsigned art);
|
||||
extern void _TIE_xt_MAC16_XSR_M1(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_MAC16_RSR_M2(void);
|
||||
extern void _TIE_xt_MAC16_WSR_M2(unsigned art);
|
||||
extern void _TIE_xt_MAC16_XSR_M2(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_MAC16_RSR_M3(void);
|
||||
extern void _TIE_xt_MAC16_WSR_M3(unsigned art);
|
||||
extern void _TIE_xt_MAC16_XSR_M3(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_MAC16_RSR_ACCLO(void);
|
||||
extern void _TIE_xt_MAC16_WSR_ACCLO(unsigned art);
|
||||
extern void _TIE_xt_MAC16_XSR_ACCLO(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_MAC16_RSR_ACCHI(void);
|
||||
extern void _TIE_xt_MAC16_WSR_ACCHI(unsigned art);
|
||||
extern void _TIE_xt_MAC16_XSR_ACCHI(unsigned art /*inout*/);
|
||||
extern void _TIE_xt_MAC16_MULA_DA_LL_LDDEC(immediate w, const short * s /*inout*/, immediate x, int t);
|
||||
extern void _TIE_xt_MAC16_MULA_DA_LL_LDINC(immediate w, const short * s /*inout*/, immediate x, int t);
|
||||
extern void _TIE_xt_MAC16_MULA_DA_HL_LDDEC(immediate w, const short * s /*inout*/, immediate x, int t);
|
||||
extern void _TIE_xt_MAC16_MULA_DA_HL_LDINC(immediate w, const short * s /*inout*/, immediate x, int t);
|
||||
extern void _TIE_xt_MAC16_MULA_DA_LH_LDDEC(immediate w, const short * s /*inout*/, immediate x, int t);
|
||||
extern void _TIE_xt_MAC16_MULA_DA_LH_LDINC(immediate w, const short * s /*inout*/, immediate x, int t);
|
||||
extern void _TIE_xt_MAC16_MULA_DA_HH_LDDEC(immediate w, const short * s /*inout*/, immediate x, int t);
|
||||
extern void _TIE_xt_MAC16_MULA_DA_HH_LDINC(immediate w, const short * s /*inout*/, immediate x, int t);
|
||||
extern void _TIE_xt_MAC16_MULA_DD_LL_LDDEC(immediate w, const short * s /*inout*/, immediate x, immediate y);
|
||||
extern void _TIE_xt_MAC16_MULA_DD_LL_LDINC(immediate w, const short * s /*inout*/, immediate x, immediate y);
|
||||
extern void _TIE_xt_MAC16_MULA_DD_HL_LDDEC(immediate w, const short * s /*inout*/, immediate x, immediate y);
|
||||
extern void _TIE_xt_MAC16_MULA_DD_HL_LDINC(immediate w, const short * s /*inout*/, immediate x, immediate y);
|
||||
extern void _TIE_xt_MAC16_MULA_DD_LH_LDDEC(immediate w, const short * s /*inout*/, immediate x, immediate y);
|
||||
extern void _TIE_xt_MAC16_MULA_DD_LH_LDINC(immediate w, const short * s /*inout*/, immediate x, immediate y);
|
||||
extern void _TIE_xt_MAC16_MULA_DD_HH_LDDEC(immediate w, const short * s /*inout*/, immediate x, immediate y);
|
||||
extern void _TIE_xt_MAC16_MULA_DD_HH_LDINC(immediate w, const short * s /*inout*/, immediate x, immediate y);
|
||||
extern void _TIE_xt_MAC16_LDDEC(immediate w, const short * p /*inout*/);
|
||||
extern void _TIE_xt_MAC16_ULDDEC(immediate w, const unsigned short * p /*inout*/);
|
||||
extern void _TIE_xt_MAC16_SLDDEC(immediate w, const short * p /*inout*/);
|
||||
extern void _TIE_xt_MAC16_LDINC(immediate w, const short * p /*inout*/);
|
||||
extern void _TIE_xt_MAC16_ULDINC(immediate w, const unsigned short * p /*inout*/);
|
||||
extern void _TIE_xt_MAC16_SLDINC(immediate w, const short * p /*inout*/);
|
||||
extern int _TIE_xt_MAC16_RSR16(void);
|
||||
extern void _TIE_xt_MAC16_WSR16(int t);
|
||||
extern void _TIE_xt_MAC16_XSR16(int t /*inout*/);
|
||||
extern int _TIE_xt_MAC16_RSR17(void);
|
||||
extern void _TIE_xt_MAC16_WSR17(int t);
|
||||
extern void _TIE_xt_MAC16_XSR17(int t /*inout*/);
|
||||
#define XT_UMUL_AA_HH _TIE_xt_MAC16_UMUL_AA_HH
|
||||
#define XT_UMUL_AA_LH _TIE_xt_MAC16_UMUL_AA_LH
|
||||
#define XT_UMUL_AA_HL _TIE_xt_MAC16_UMUL_AA_HL
|
||||
#define XT_UMUL_AA_LL _TIE_xt_MAC16_UMUL_AA_LL
|
||||
#define XT_MUL_AA_HH _TIE_xt_MAC16_MUL_AA_HH
|
||||
#define XT_MUL_AA_LH _TIE_xt_MAC16_MUL_AA_LH
|
||||
#define XT_MUL_AA_HL _TIE_xt_MAC16_MUL_AA_HL
|
||||
#define XT_MUL_AA_LL _TIE_xt_MAC16_MUL_AA_LL
|
||||
#define XT_MUL_AD_HH _TIE_xt_MAC16_MUL_AD_HH
|
||||
#define XT_MUL_AD_LH _TIE_xt_MAC16_MUL_AD_LH
|
||||
#define XT_MUL_AD_HL _TIE_xt_MAC16_MUL_AD_HL
|
||||
#define XT_MUL_AD_LL _TIE_xt_MAC16_MUL_AD_LL
|
||||
#define XT_MUL_DA_HH _TIE_xt_MAC16_MUL_DA_HH
|
||||
#define XT_MUL_DA_LH _TIE_xt_MAC16_MUL_DA_LH
|
||||
#define XT_MUL_DA_HL _TIE_xt_MAC16_MUL_DA_HL
|
||||
#define XT_MUL_DA_LL _TIE_xt_MAC16_MUL_DA_LL
|
||||
#define XT_MUL_DD_HH _TIE_xt_MAC16_MUL_DD_HH
|
||||
#define XT_MUL_DD_LH _TIE_xt_MAC16_MUL_DD_LH
|
||||
#define XT_MUL_DD_HL _TIE_xt_MAC16_MUL_DD_HL
|
||||
#define XT_MUL_DD_LL _TIE_xt_MAC16_MUL_DD_LL
|
||||
#define XT_MULS_AA_HH _TIE_xt_MAC16_MULS_AA_HH
|
||||
#define XT_MULS_AA_LH _TIE_xt_MAC16_MULS_AA_LH
|
||||
#define XT_MULS_AA_HL _TIE_xt_MAC16_MULS_AA_HL
|
||||
#define XT_MULS_AA_LL _TIE_xt_MAC16_MULS_AA_LL
|
||||
#define XT_MULA_AA_HH _TIE_xt_MAC16_MULA_AA_HH
|
||||
#define XT_MULA_AA_LH _TIE_xt_MAC16_MULA_AA_LH
|
||||
#define XT_MULA_AA_HL _TIE_xt_MAC16_MULA_AA_HL
|
||||
#define XT_MULA_AA_LL _TIE_xt_MAC16_MULA_AA_LL
|
||||
#define XT_MULS_AD_HH _TIE_xt_MAC16_MULS_AD_HH
|
||||
#define XT_MULS_AD_LH _TIE_xt_MAC16_MULS_AD_LH
|
||||
#define XT_MULS_AD_HL _TIE_xt_MAC16_MULS_AD_HL
|
||||
#define XT_MULS_AD_LL _TIE_xt_MAC16_MULS_AD_LL
|
||||
#define XT_MULA_AD_HH _TIE_xt_MAC16_MULA_AD_HH
|
||||
#define XT_MULA_AD_LH _TIE_xt_MAC16_MULA_AD_LH
|
||||
#define XT_MULA_AD_HL _TIE_xt_MAC16_MULA_AD_HL
|
||||
#define XT_MULA_AD_LL _TIE_xt_MAC16_MULA_AD_LL
|
||||
#define XT_MULS_DA_HH _TIE_xt_MAC16_MULS_DA_HH
|
||||
#define XT_MULS_DA_LH _TIE_xt_MAC16_MULS_DA_LH
|
||||
#define XT_MULS_DA_HL _TIE_xt_MAC16_MULS_DA_HL
|
||||
#define XT_MULS_DA_LL _TIE_xt_MAC16_MULS_DA_LL
|
||||
#define XT_MULA_DA_HH _TIE_xt_MAC16_MULA_DA_HH
|
||||
#define XT_MULA_DA_LH _TIE_xt_MAC16_MULA_DA_LH
|
||||
#define XT_MULA_DA_HL _TIE_xt_MAC16_MULA_DA_HL
|
||||
#define XT_MULA_DA_LL _TIE_xt_MAC16_MULA_DA_LL
|
||||
#define XT_MULS_DD_HH _TIE_xt_MAC16_MULS_DD_HH
|
||||
#define XT_MULS_DD_LH _TIE_xt_MAC16_MULS_DD_LH
|
||||
#define XT_MULS_DD_HL _TIE_xt_MAC16_MULS_DD_HL
|
||||
#define XT_MULS_DD_LL _TIE_xt_MAC16_MULS_DD_LL
|
||||
#define XT_MULA_DD_HH _TIE_xt_MAC16_MULA_DD_HH
|
||||
#define XT_MULA_DD_LH _TIE_xt_MAC16_MULA_DD_LH
|
||||
#define XT_MULA_DD_HL _TIE_xt_MAC16_MULA_DD_HL
|
||||
#define XT_MULA_DD_LL _TIE_xt_MAC16_MULA_DD_LL
|
||||
#define XT_RSR_M0 _TIE_xt_MAC16_RSR_M0
|
||||
#define XT_WSR_M0 _TIE_xt_MAC16_WSR_M0
|
||||
#define XT_XSR_M0 _TIE_xt_MAC16_XSR_M0
|
||||
#define XT_RSR_M1 _TIE_xt_MAC16_RSR_M1
|
||||
#define XT_WSR_M1 _TIE_xt_MAC16_WSR_M1
|
||||
#define XT_XSR_M1 _TIE_xt_MAC16_XSR_M1
|
||||
#define XT_RSR_M2 _TIE_xt_MAC16_RSR_M2
|
||||
#define XT_WSR_M2 _TIE_xt_MAC16_WSR_M2
|
||||
#define XT_XSR_M2 _TIE_xt_MAC16_XSR_M2
|
||||
#define XT_RSR_M3 _TIE_xt_MAC16_RSR_M3
|
||||
#define XT_WSR_M3 _TIE_xt_MAC16_WSR_M3
|
||||
#define XT_XSR_M3 _TIE_xt_MAC16_XSR_M3
|
||||
#define XT_RSR_ACCLO _TIE_xt_MAC16_RSR_ACCLO
|
||||
#define XT_WSR_ACCLO _TIE_xt_MAC16_WSR_ACCLO
|
||||
#define XT_XSR_ACCLO _TIE_xt_MAC16_XSR_ACCLO
|
||||
#define XT_RSR_ACCHI _TIE_xt_MAC16_RSR_ACCHI
|
||||
#define XT_WSR_ACCHI _TIE_xt_MAC16_WSR_ACCHI
|
||||
#define XT_XSR_ACCHI _TIE_xt_MAC16_XSR_ACCHI
|
||||
#define XT_MULA_DA_LL_LDDEC _TIE_xt_MAC16_MULA_DA_LL_LDDEC
|
||||
#define XT_MULA_DA_LL_LDINC _TIE_xt_MAC16_MULA_DA_LL_LDINC
|
||||
#define XT_MULA_DA_HL_LDDEC _TIE_xt_MAC16_MULA_DA_HL_LDDEC
|
||||
#define XT_MULA_DA_HL_LDINC _TIE_xt_MAC16_MULA_DA_HL_LDINC
|
||||
#define XT_MULA_DA_LH_LDDEC _TIE_xt_MAC16_MULA_DA_LH_LDDEC
|
||||
#define XT_MULA_DA_LH_LDINC _TIE_xt_MAC16_MULA_DA_LH_LDINC
|
||||
#define XT_MULA_DA_HH_LDDEC _TIE_xt_MAC16_MULA_DA_HH_LDDEC
|
||||
#define XT_MULA_DA_HH_LDINC _TIE_xt_MAC16_MULA_DA_HH_LDINC
|
||||
#define XT_MULA_DD_LL_LDDEC _TIE_xt_MAC16_MULA_DD_LL_LDDEC
|
||||
#define XT_MULA_DD_LL_LDINC _TIE_xt_MAC16_MULA_DD_LL_LDINC
|
||||
#define XT_MULA_DD_HL_LDDEC _TIE_xt_MAC16_MULA_DD_HL_LDDEC
|
||||
#define XT_MULA_DD_HL_LDINC _TIE_xt_MAC16_MULA_DD_HL_LDINC
|
||||
#define XT_MULA_DD_LH_LDDEC _TIE_xt_MAC16_MULA_DD_LH_LDDEC
|
||||
#define XT_MULA_DD_LH_LDINC _TIE_xt_MAC16_MULA_DD_LH_LDINC
|
||||
#define XT_MULA_DD_HH_LDDEC _TIE_xt_MAC16_MULA_DD_HH_LDDEC
|
||||
#define XT_MULA_DD_HH_LDINC _TIE_xt_MAC16_MULA_DD_HH_LDINC
|
||||
#define XT_LDDEC _TIE_xt_MAC16_LDDEC
|
||||
#define XT_ULDDEC _TIE_xt_MAC16_ULDDEC
|
||||
#define XT_SLDDEC _TIE_xt_MAC16_SLDDEC
|
||||
#define XT_LDINC _TIE_xt_MAC16_LDINC
|
||||
#define XT_ULDINC _TIE_xt_MAC16_ULDINC
|
||||
#define XT_SLDINC _TIE_xt_MAC16_SLDINC
|
||||
#define XT_RSR16 _TIE_xt_MAC16_RSR16
|
||||
#define XT_WSR16 _TIE_xt_MAC16_WSR16
|
||||
#define XT_XSR16 _TIE_xt_MAC16_XSR16
|
||||
#define XT_RSR17 _TIE_xt_MAC16_RSR17
|
||||
#define XT_WSR17 _TIE_xt_MAC16_WSR17
|
||||
#define XT_XSR17 _TIE_xt_MAC16_XSR17
|
||||
|
||||
#endif /* __XCC__ */
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
|
||||
#endif /* !_XTENSA_xt_MAC16_HEADER */
|
||||
@@ -0,0 +1,24 @@
|
||||
/* Definitions for the 32-bit Integer Multiply Option. */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2009 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* NOTE: This file exists only for backward compatibility with RB-200X.x
|
||||
and earlier Xtensa releases. Starting with RC-2009.0 you should use
|
||||
<xtensa/tie/xt_mul.h>. */
|
||||
|
||||
#ifndef _XTENSA_xt_MUL32_HEADER
|
||||
#define _XTENSA_xt_MUL32_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
|
||||
#include <xtensa/tie/xt_mul.h>
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
#endif /* !_XTENSA_xt_MUL32_HEADER */
|
||||
@@ -0,0 +1,69 @@
|
||||
/* Definitions for the xt_booleans TIE package */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_booleans_HEADER
|
||||
#define _XTENSA_xt_booleans_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#ifdef __XCC__
|
||||
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
typedef _TIE_xtbool xtbool;
|
||||
typedef _TIE_xtbool2 xtbool2;
|
||||
typedef _TIE_xtbool4 xtbool4;
|
||||
typedef _TIE_xtbool8 xtbool8;
|
||||
typedef _TIE_xtbool16 xtbool16;
|
||||
|
||||
/*
|
||||
* The following prototypes describe intrinsic functions
|
||||
* corresponding to TIE instructions. Some TIE instructions
|
||||
* may produce multiple results (designated as "out" operands
|
||||
* in the iclass section) or may have operands used as both
|
||||
* inputs and outputs (designated as "inout"). However, the C
|
||||
* and C++ languages do not provide syntax that can express
|
||||
* the in/out/inout constraints of TIE intrinsics.
|
||||
* Nevertheless, the compiler understands these constraints
|
||||
* and will check that the intrinsic functions are used
|
||||
* correctly. To improve the readability of these prototypes,
|
||||
* the "out" and "inout" parameters are marked accordingly
|
||||
* with comments.
|
||||
*/
|
||||
|
||||
extern xtbool _TIE_xt_booleans_XORB(xtbool bs, xtbool bt);
|
||||
extern xtbool _TIE_xt_booleans_ORBC(xtbool bs, xtbool bt);
|
||||
extern xtbool _TIE_xt_booleans_ORB(xtbool bs, xtbool bt);
|
||||
extern xtbool _TIE_xt_booleans_ANDBC(xtbool bs, xtbool bt);
|
||||
extern xtbool _TIE_xt_booleans_ANDB(xtbool bs, xtbool bt);
|
||||
extern xtbool _TIE_xt_booleans_ALL4(xtbool4 bs4);
|
||||
extern xtbool _TIE_xt_booleans_ANY4(xtbool4 bs4);
|
||||
extern xtbool _TIE_xt_booleans_ALL8(xtbool8 bs8);
|
||||
extern xtbool _TIE_xt_booleans_ANY8(xtbool8 bs8);
|
||||
extern void _TIE_xt_booleans_MOVT(unsigned arr /*inout*/, unsigned ars, xtbool bt);
|
||||
extern void _TIE_xt_booleans_MOVF(unsigned arr /*inout*/, unsigned ars, xtbool bt);
|
||||
#define XT_XORB _TIE_xt_booleans_XORB
|
||||
#define XT_ORBC _TIE_xt_booleans_ORBC
|
||||
#define XT_ORB _TIE_xt_booleans_ORB
|
||||
#define XT_ANDBC _TIE_xt_booleans_ANDBC
|
||||
#define XT_ANDB _TIE_xt_booleans_ANDB
|
||||
#define XT_ALL4 _TIE_xt_booleans_ALL4
|
||||
#define XT_ANY4 _TIE_xt_booleans_ANY4
|
||||
#define XT_ALL8 _TIE_xt_booleans_ALL8
|
||||
#define XT_ANY8 _TIE_xt_booleans_ANY8
|
||||
#define XT_MOVT _TIE_xt_booleans_MOVT
|
||||
#define XT_MOVF _TIE_xt_booleans_MOVF
|
||||
|
||||
#endif /* __XCC__ */
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
|
||||
#endif /* !_XTENSA_xt_booleans_HEADER */
|
||||
@@ -0,0 +1,48 @@
|
||||
/* Definitions for the xt_coprocessors TIE package */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_coprocessors_HEADER
|
||||
#define _XTENSA_xt_coprocessors_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#ifdef __XCC__
|
||||
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
|
||||
/*
|
||||
* The following prototypes describe intrinsic functions
|
||||
* corresponding to TIE instructions. Some TIE instructions
|
||||
* may produce multiple results (designated as "out" operands
|
||||
* in the iclass section) or may have operands used as both
|
||||
* inputs and outputs (designated as "inout"). However, the C
|
||||
* and C++ languages do not provide syntax that can express
|
||||
* the in/out/inout constraints of TIE intrinsics.
|
||||
* Nevertheless, the compiler understands these constraints
|
||||
* and will check that the intrinsic functions are used
|
||||
* correctly. To improve the readability of these prototypes,
|
||||
* the "out" and "inout" parameters are marked accordingly
|
||||
* with comments.
|
||||
*/
|
||||
|
||||
extern unsigned _TIE_xt_coprocessors_RSR_CPENABLE(void);
|
||||
extern void _TIE_xt_coprocessors_WSR_CPENABLE(unsigned art);
|
||||
extern void _TIE_xt_coprocessors_XSR_CPENABLE(unsigned art /*inout*/);
|
||||
#define XT_RSR_CPENABLE _TIE_xt_coprocessors_RSR_CPENABLE
|
||||
#define XT_WSR_CPENABLE _TIE_xt_coprocessors_WSR_CPENABLE
|
||||
#define XT_XSR_CPENABLE _TIE_xt_coprocessors_XSR_CPENABLE
|
||||
|
||||
#endif /* __XCC__ */
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
|
||||
#endif /* !_XTENSA_xt_coprocessors_HEADER */
|
||||
@@ -0,0 +1,395 @@
|
||||
/* Definitions for the xt_core TIE package */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_core_HEADER
|
||||
#define _XTENSA_xt_core_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#ifdef __XCC__
|
||||
|
||||
|
||||
/*
|
||||
* The following prototypes describe intrinsic functions
|
||||
* corresponding to TIE instructions. Some TIE instructions
|
||||
* may produce multiple results (designated as "out" operands
|
||||
* in the iclass section) or may have operands used as both
|
||||
* inputs and outputs (designated as "inout"). However, the C
|
||||
* and C++ languages do not provide syntax that can express
|
||||
* the in/out/inout constraints of TIE intrinsics.
|
||||
* Nevertheless, the compiler understands these constraints
|
||||
* and will check that the intrinsic functions are used
|
||||
* correctly. To improve the readability of these prototypes,
|
||||
* the "out" and "inout" parameters are marked accordingly
|
||||
* with comments.
|
||||
*/
|
||||
|
||||
extern void _TIE_xt_core_ILL(void);
|
||||
extern void _TIE_xt_core_NOP(void);
|
||||
extern void _TIE_xt_core_SIMCALL(void);
|
||||
extern void _TIE_xt_core_MEMW(void);
|
||||
extern void _TIE_xt_core_EXTW(void);
|
||||
extern void _TIE_xt_core_ISYNC(void);
|
||||
extern void _TIE_xt_core_DSYNC(void);
|
||||
extern void _TIE_xt_core_ESYNC(void);
|
||||
extern void _TIE_xt_core_RSYNC(void);
|
||||
extern unsigned _TIE_xt_core_RSR_LBEG(void);
|
||||
extern void _TIE_xt_core_WSR_LBEG(unsigned art);
|
||||
extern void _TIE_xt_core_XSR_LBEG(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_CONFIGID0(void);
|
||||
extern void _TIE_xt_core_WSR_CONFIGID0(unsigned art);
|
||||
extern unsigned _TIE_xt_core_RSR_CONFIGID1(void);
|
||||
extern unsigned _TIE_xt_core_RUR_THREADPTR(void);
|
||||
extern void _TIE_xt_core_WUR_THREADPTR(unsigned v);
|
||||
extern unsigned _TIE_xt_core_uint32_loadi(const unsigned * p, immediate o);
|
||||
extern void _TIE_xt_core_uint32_storei(unsigned c, unsigned * p, immediate o);
|
||||
extern unsigned _TIE_xt_core_uint32_move(unsigned b);
|
||||
extern int _TIE_xt_core_ADDI(int s, immediate i);
|
||||
extern int _TIE_xt_core_OR(int s, int t);
|
||||
extern int _TIE_xt_core_L32I(const int * p, immediate i);
|
||||
extern void _TIE_xt_core_S32I(int r, int * p, immediate i);
|
||||
extern void _TIE_xt_core_S32NB(int r, int * p, immediate i);
|
||||
extern unsigned char _TIE_xt_core_L8UI(const unsigned char * p, immediate i);
|
||||
extern void _TIE_xt_core_S8I(signed char r, signed char * p, immediate i);
|
||||
extern unsigned short _TIE_xt_core_L16UI(const unsigned short * p, immediate i);
|
||||
extern short _TIE_xt_core_L16SI(const short * p, immediate i);
|
||||
extern void _TIE_xt_core_S16I(short r, short * p, immediate i);
|
||||
extern int _TIE_xt_core_ADDMI(int s, immediate i);
|
||||
extern int _TIE_xt_core_ADD(int s, int t);
|
||||
extern int _TIE_xt_core_ADDX2(int s, int t);
|
||||
extern int _TIE_xt_core_ADDX4(int s, int t);
|
||||
extern int _TIE_xt_core_ADDX8(int s, int t);
|
||||
extern int _TIE_xt_core_SUB(int s, int t);
|
||||
extern int _TIE_xt_core_SUBX2(int s, int t);
|
||||
extern int _TIE_xt_core_SUBX4(int s, int t);
|
||||
extern int _TIE_xt_core_SUBX8(int s, int t);
|
||||
extern int _TIE_xt_core_AND(int s, int t);
|
||||
extern int _TIE_xt_core_XOR(int s, int t);
|
||||
extern unsigned _TIE_xt_core_EXTUI(unsigned t, immediate i, immediate o);
|
||||
extern int _TIE_xt_core_MOVI(immediate i);
|
||||
extern void _TIE_xt_core_MOVEQZ(int r /*inout*/, int s, int t);
|
||||
extern void _TIE_xt_core_MOVNEZ(int r /*inout*/, int s, int t);
|
||||
extern void _TIE_xt_core_MOVLTZ(int r /*inout*/, int s, int t);
|
||||
extern void _TIE_xt_core_MOVGEZ(int r /*inout*/, int s, int t);
|
||||
extern int _TIE_xt_core_NEG(int t);
|
||||
extern int _TIE_xt_core_ABS(int t);
|
||||
extern void _TIE_xt_core_SSR(int s);
|
||||
extern void _TIE_xt_core_SSL(int s);
|
||||
extern void _TIE_xt_core_SSA8L(int s);
|
||||
extern void _TIE_xt_core_SSA8B(int s);
|
||||
extern void _TIE_xt_core_SSAI(immediate i);
|
||||
extern int _TIE_xt_core_SLL(int s);
|
||||
extern int _TIE_xt_core_SRC(int s, int t);
|
||||
extern unsigned _TIE_xt_core_SRL(unsigned t);
|
||||
extern int _TIE_xt_core_SRA(int t);
|
||||
extern int _TIE_xt_core_SLLI(int s, immediate i);
|
||||
extern int _TIE_xt_core_SRAI(int t, immediate i);
|
||||
extern unsigned _TIE_xt_core_SRLI(unsigned t, immediate i);
|
||||
extern int _TIE_xt_core_SSAI_SRC(int src1, int src2, immediate amount);
|
||||
extern int _TIE_xt_core_SSR_SRC(int src1, int src2, int amount);
|
||||
extern int _TIE_xt_core_WSR_SAR_SRC(int src1, int src2, int amount);
|
||||
extern int _TIE_xt_core_SSR_SRA(int src, int amount);
|
||||
extern unsigned _TIE_xt_core_SSR_SRL(unsigned src, int amount);
|
||||
extern int _TIE_xt_core_SSL_SLL(int src, int amount);
|
||||
extern int _TIE_xt_core_RSIL(immediate t);
|
||||
extern int _TIE_xt_core_RSR_LEND(void);
|
||||
extern void _TIE_xt_core_WSR_LEND(int t);
|
||||
extern void _TIE_xt_core_XSR_LEND(int t /*inout*/);
|
||||
extern int _TIE_xt_core_RSR_LCOUNT(void);
|
||||
extern void _TIE_xt_core_WSR_LCOUNT(int t);
|
||||
extern void _TIE_xt_core_XSR_LCOUNT(int t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_SAR(void);
|
||||
extern void _TIE_xt_core_WSR_SAR(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_SAR(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_MEMCTL(void);
|
||||
extern void _TIE_xt_core_WSR_MEMCTL(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_MEMCTL(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_LITBASE(void);
|
||||
extern void _TIE_xt_core_WSR_LITBASE(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_LITBASE(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_PS(void);
|
||||
extern void _TIE_xt_core_WSR_PS(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_PS(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EPC1(void);
|
||||
extern void _TIE_xt_core_WSR_EPC1(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EPC1(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EXCSAVE1(void);
|
||||
extern void _TIE_xt_core_WSR_EXCSAVE1(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EXCSAVE1(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EPC2(void);
|
||||
extern void _TIE_xt_core_WSR_EPC2(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EPC2(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EXCSAVE2(void);
|
||||
extern void _TIE_xt_core_WSR_EXCSAVE2(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EXCSAVE2(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EPC3(void);
|
||||
extern void _TIE_xt_core_WSR_EPC3(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EPC3(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EXCSAVE3(void);
|
||||
extern void _TIE_xt_core_WSR_EXCSAVE3(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EXCSAVE3(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EPC4(void);
|
||||
extern void _TIE_xt_core_WSR_EPC4(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EPC4(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EXCSAVE4(void);
|
||||
extern void _TIE_xt_core_WSR_EXCSAVE4(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EXCSAVE4(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EPC5(void);
|
||||
extern void _TIE_xt_core_WSR_EPC5(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EPC5(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EXCSAVE5(void);
|
||||
extern void _TIE_xt_core_WSR_EXCSAVE5(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EXCSAVE5(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EPC6(void);
|
||||
extern void _TIE_xt_core_WSR_EPC6(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EPC6(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EXCSAVE6(void);
|
||||
extern void _TIE_xt_core_WSR_EXCSAVE6(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EXCSAVE6(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EPC7(void);
|
||||
extern void _TIE_xt_core_WSR_EPC7(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EPC7(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EXCSAVE7(void);
|
||||
extern void _TIE_xt_core_WSR_EXCSAVE7(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EXCSAVE7(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_VECBASE(void);
|
||||
extern void _TIE_xt_core_WSR_VECBASE(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_VECBASE(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EPS2(void);
|
||||
extern void _TIE_xt_core_WSR_EPS2(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EPS2(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EPS3(void);
|
||||
extern void _TIE_xt_core_WSR_EPS3(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EPS3(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EPS4(void);
|
||||
extern void _TIE_xt_core_WSR_EPS4(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EPS4(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EPS5(void);
|
||||
extern void _TIE_xt_core_WSR_EPS5(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EPS5(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EPS6(void);
|
||||
extern void _TIE_xt_core_WSR_EPS6(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EPS6(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EPS7(void);
|
||||
extern void _TIE_xt_core_WSR_EPS7(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EPS7(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EXCCAUSE(void);
|
||||
extern void _TIE_xt_core_WSR_EXCCAUSE(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EXCCAUSE(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_EXCVADDR(void);
|
||||
extern void _TIE_xt_core_WSR_EXCVADDR(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_EXCVADDR(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_DEPC(void);
|
||||
extern void _TIE_xt_core_WSR_DEPC(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_DEPC(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_MISC0(void);
|
||||
extern void _TIE_xt_core_WSR_MISC0(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_MISC0(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_MISC1(void);
|
||||
extern void _TIE_xt_core_WSR_MISC1(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_MISC1(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_MISC2(void);
|
||||
extern void _TIE_xt_core_WSR_MISC2(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_MISC2(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_core_RSR_MISC3(void);
|
||||
extern void _TIE_xt_core_WSR_MISC3(unsigned t);
|
||||
extern void _TIE_xt_core_XSR_MISC3(unsigned t /*inout*/);
|
||||
extern int _TIE_xt_core_RSR_PRID(void);
|
||||
#define XT_ILL _TIE_xt_core_ILL
|
||||
#define XT_NOP _TIE_xt_core_NOP
|
||||
#define XT_SIMCALL _TIE_xt_core_SIMCALL
|
||||
#define XT_MEMW _TIE_xt_core_MEMW
|
||||
#define XT_EXTW _TIE_xt_core_EXTW
|
||||
#define XT_ISYNC _TIE_xt_core_ISYNC
|
||||
#define XT_DSYNC _TIE_xt_core_DSYNC
|
||||
#define XT_ESYNC _TIE_xt_core_ESYNC
|
||||
#define XT_RSYNC _TIE_xt_core_RSYNC
|
||||
#define XT_RSR_LBEG _TIE_xt_core_RSR_LBEG
|
||||
#define XT_WSR_LBEG _TIE_xt_core_WSR_LBEG
|
||||
#define XT_XSR_LBEG _TIE_xt_core_XSR_LBEG
|
||||
#define XT_RSR_CONFIGID0 _TIE_xt_core_RSR_CONFIGID0
|
||||
#define XT_WSR_CONFIGID0 _TIE_xt_core_WSR_CONFIGID0
|
||||
#define XT_RSR_CONFIGID1 _TIE_xt_core_RSR_CONFIGID1
|
||||
#define XT_RUR_THREADPTR _TIE_xt_core_RUR_THREADPTR
|
||||
#define RTHREADPTR _TIE_xt_core_RUR_THREADPTR
|
||||
#define RUR231 _TIE_xt_core_RUR_THREADPTR
|
||||
#define XT_WUR_THREADPTR _TIE_xt_core_WUR_THREADPTR
|
||||
#define WTHREADPTR _TIE_xt_core_WUR_THREADPTR
|
||||
#define WUR231 _TIE_xt_core_WUR_THREADPTR
|
||||
#define XT_uint32_loadi _TIE_xt_core_uint32_loadi
|
||||
#define XT_uint32_storei _TIE_xt_core_uint32_storei
|
||||
#define XT_uint32_move _TIE_xt_core_uint32_move
|
||||
#define XT_ADDI _TIE_xt_core_ADDI
|
||||
#define XT_OR _TIE_xt_core_OR
|
||||
#define XT_L32I _TIE_xt_core_L32I
|
||||
#define XT_S32I _TIE_xt_core_S32I
|
||||
#define XT_S32NB _TIE_xt_core_S32NB
|
||||
#define XT_L8UI _TIE_xt_core_L8UI
|
||||
#define XT_S8I _TIE_xt_core_S8I
|
||||
#define XT_L16UI _TIE_xt_core_L16UI
|
||||
#define XT_L16SI _TIE_xt_core_L16SI
|
||||
#define XT_S16I _TIE_xt_core_S16I
|
||||
#define XT_ADDMI _TIE_xt_core_ADDMI
|
||||
#define XT_ADD _TIE_xt_core_ADD
|
||||
#define XT_ADDX2 _TIE_xt_core_ADDX2
|
||||
#define XT_ADDX4 _TIE_xt_core_ADDX4
|
||||
#define XT_ADDX8 _TIE_xt_core_ADDX8
|
||||
#define XT_SUB _TIE_xt_core_SUB
|
||||
#define XT_SUBX2 _TIE_xt_core_SUBX2
|
||||
#define XT_SUBX4 _TIE_xt_core_SUBX4
|
||||
#define XT_SUBX8 _TIE_xt_core_SUBX8
|
||||
#define XT_AND _TIE_xt_core_AND
|
||||
#define XT_XOR _TIE_xt_core_XOR
|
||||
#define XT_EXTUI _TIE_xt_core_EXTUI
|
||||
#define XT_MOVI _TIE_xt_core_MOVI
|
||||
#define XT_MOVEQZ _TIE_xt_core_MOVEQZ
|
||||
#define XT_MOVNEZ _TIE_xt_core_MOVNEZ
|
||||
#define XT_MOVLTZ _TIE_xt_core_MOVLTZ
|
||||
#define XT_MOVGEZ _TIE_xt_core_MOVGEZ
|
||||
#define XT_NEG _TIE_xt_core_NEG
|
||||
#define XT_ABS _TIE_xt_core_ABS
|
||||
#define XT_SSR _TIE_xt_core_SSR
|
||||
#define XT_SSL _TIE_xt_core_SSL
|
||||
#define XT_SSA8L _TIE_xt_core_SSA8L
|
||||
#define XT_SSA8B _TIE_xt_core_SSA8B
|
||||
#define XT_SSAI _TIE_xt_core_SSAI
|
||||
#define XT_SLL _TIE_xt_core_SLL
|
||||
#define XT_SRC _TIE_xt_core_SRC
|
||||
#define XT_SRL _TIE_xt_core_SRL
|
||||
#define XT_SRA _TIE_xt_core_SRA
|
||||
#define XT_SLLI _TIE_xt_core_SLLI
|
||||
#define XT_SRAI _TIE_xt_core_SRAI
|
||||
#define XT_SRLI _TIE_xt_core_SRLI
|
||||
#define XT_SSAI_SRC _TIE_xt_core_SSAI_SRC
|
||||
#define XT_SSR_SRC _TIE_xt_core_SSR_SRC
|
||||
#define XT_WSR_SAR_SRC _TIE_xt_core_WSR_SAR_SRC
|
||||
#define XT_SSR_SRA _TIE_xt_core_SSR_SRA
|
||||
#define XT_SSR_SRL _TIE_xt_core_SSR_SRL
|
||||
#define XT_SSL_SLL _TIE_xt_core_SSL_SLL
|
||||
#define XT_RSIL _TIE_xt_core_RSIL
|
||||
#define XT_RSR_LEND _TIE_xt_core_RSR_LEND
|
||||
#define XT_WSR_LEND _TIE_xt_core_WSR_LEND
|
||||
#define XT_XSR_LEND _TIE_xt_core_XSR_LEND
|
||||
#define XT_RSR_LCOUNT _TIE_xt_core_RSR_LCOUNT
|
||||
#define XT_WSR_LCOUNT _TIE_xt_core_WSR_LCOUNT
|
||||
#define XT_XSR_LCOUNT _TIE_xt_core_XSR_LCOUNT
|
||||
#define XT_RSR_SAR _TIE_xt_core_RSR_SAR
|
||||
#define XT_WSR_SAR _TIE_xt_core_WSR_SAR
|
||||
#define XT_XSR_SAR _TIE_xt_core_XSR_SAR
|
||||
#define XT_RSR_MEMCTL _TIE_xt_core_RSR_MEMCTL
|
||||
#define XT_WSR_MEMCTL _TIE_xt_core_WSR_MEMCTL
|
||||
#define XT_XSR_MEMCTL _TIE_xt_core_XSR_MEMCTL
|
||||
#define XT_RSR_LITBASE _TIE_xt_core_RSR_LITBASE
|
||||
#define XT_WSR_LITBASE _TIE_xt_core_WSR_LITBASE
|
||||
#define XT_XSR_LITBASE _TIE_xt_core_XSR_LITBASE
|
||||
#define XT_RSR_PS _TIE_xt_core_RSR_PS
|
||||
#define XT_WSR_PS _TIE_xt_core_WSR_PS
|
||||
#define XT_XSR_PS _TIE_xt_core_XSR_PS
|
||||
#define XT_RSR_EPC1 _TIE_xt_core_RSR_EPC1
|
||||
#define XT_WSR_EPC1 _TIE_xt_core_WSR_EPC1
|
||||
#define XT_XSR_EPC1 _TIE_xt_core_XSR_EPC1
|
||||
#define XT_RSR_EXCSAVE1 _TIE_xt_core_RSR_EXCSAVE1
|
||||
#define XT_WSR_EXCSAVE1 _TIE_xt_core_WSR_EXCSAVE1
|
||||
#define XT_XSR_EXCSAVE1 _TIE_xt_core_XSR_EXCSAVE1
|
||||
#define XT_RSR_EPC2 _TIE_xt_core_RSR_EPC2
|
||||
#define XT_WSR_EPC2 _TIE_xt_core_WSR_EPC2
|
||||
#define XT_XSR_EPC2 _TIE_xt_core_XSR_EPC2
|
||||
#define XT_RSR_EXCSAVE2 _TIE_xt_core_RSR_EXCSAVE2
|
||||
#define XT_WSR_EXCSAVE2 _TIE_xt_core_WSR_EXCSAVE2
|
||||
#define XT_XSR_EXCSAVE2 _TIE_xt_core_XSR_EXCSAVE2
|
||||
#define XT_RSR_EPC3 _TIE_xt_core_RSR_EPC3
|
||||
#define XT_WSR_EPC3 _TIE_xt_core_WSR_EPC3
|
||||
#define XT_XSR_EPC3 _TIE_xt_core_XSR_EPC3
|
||||
#define XT_RSR_EXCSAVE3 _TIE_xt_core_RSR_EXCSAVE3
|
||||
#define XT_WSR_EXCSAVE3 _TIE_xt_core_WSR_EXCSAVE3
|
||||
#define XT_XSR_EXCSAVE3 _TIE_xt_core_XSR_EXCSAVE3
|
||||
#define XT_RSR_EPC4 _TIE_xt_core_RSR_EPC4
|
||||
#define XT_WSR_EPC4 _TIE_xt_core_WSR_EPC4
|
||||
#define XT_XSR_EPC4 _TIE_xt_core_XSR_EPC4
|
||||
#define XT_RSR_EXCSAVE4 _TIE_xt_core_RSR_EXCSAVE4
|
||||
#define XT_WSR_EXCSAVE4 _TIE_xt_core_WSR_EXCSAVE4
|
||||
#define XT_XSR_EXCSAVE4 _TIE_xt_core_XSR_EXCSAVE4
|
||||
#define XT_RSR_EPC5 _TIE_xt_core_RSR_EPC5
|
||||
#define XT_WSR_EPC5 _TIE_xt_core_WSR_EPC5
|
||||
#define XT_XSR_EPC5 _TIE_xt_core_XSR_EPC5
|
||||
#define XT_RSR_EXCSAVE5 _TIE_xt_core_RSR_EXCSAVE5
|
||||
#define XT_WSR_EXCSAVE5 _TIE_xt_core_WSR_EXCSAVE5
|
||||
#define XT_XSR_EXCSAVE5 _TIE_xt_core_XSR_EXCSAVE5
|
||||
#define XT_RSR_EPC6 _TIE_xt_core_RSR_EPC6
|
||||
#define XT_WSR_EPC6 _TIE_xt_core_WSR_EPC6
|
||||
#define XT_XSR_EPC6 _TIE_xt_core_XSR_EPC6
|
||||
#define XT_RSR_EXCSAVE6 _TIE_xt_core_RSR_EXCSAVE6
|
||||
#define XT_WSR_EXCSAVE6 _TIE_xt_core_WSR_EXCSAVE6
|
||||
#define XT_XSR_EXCSAVE6 _TIE_xt_core_XSR_EXCSAVE6
|
||||
#define XT_RSR_EPC7 _TIE_xt_core_RSR_EPC7
|
||||
#define XT_WSR_EPC7 _TIE_xt_core_WSR_EPC7
|
||||
#define XT_XSR_EPC7 _TIE_xt_core_XSR_EPC7
|
||||
#define XT_RSR_EXCSAVE7 _TIE_xt_core_RSR_EXCSAVE7
|
||||
#define XT_WSR_EXCSAVE7 _TIE_xt_core_WSR_EXCSAVE7
|
||||
#define XT_XSR_EXCSAVE7 _TIE_xt_core_XSR_EXCSAVE7
|
||||
#define XT_RSR_VECBASE _TIE_xt_core_RSR_VECBASE
|
||||
#define XT_WSR_VECBASE _TIE_xt_core_WSR_VECBASE
|
||||
#define XT_XSR_VECBASE _TIE_xt_core_XSR_VECBASE
|
||||
#define XT_RSR_EPS2 _TIE_xt_core_RSR_EPS2
|
||||
#define XT_WSR_EPS2 _TIE_xt_core_WSR_EPS2
|
||||
#define XT_XSR_EPS2 _TIE_xt_core_XSR_EPS2
|
||||
#define XT_RSR_EPS3 _TIE_xt_core_RSR_EPS3
|
||||
#define XT_WSR_EPS3 _TIE_xt_core_WSR_EPS3
|
||||
#define XT_XSR_EPS3 _TIE_xt_core_XSR_EPS3
|
||||
#define XT_RSR_EPS4 _TIE_xt_core_RSR_EPS4
|
||||
#define XT_WSR_EPS4 _TIE_xt_core_WSR_EPS4
|
||||
#define XT_XSR_EPS4 _TIE_xt_core_XSR_EPS4
|
||||
#define XT_RSR_EPS5 _TIE_xt_core_RSR_EPS5
|
||||
#define XT_WSR_EPS5 _TIE_xt_core_WSR_EPS5
|
||||
#define XT_XSR_EPS5 _TIE_xt_core_XSR_EPS5
|
||||
#define XT_RSR_EPS6 _TIE_xt_core_RSR_EPS6
|
||||
#define XT_WSR_EPS6 _TIE_xt_core_WSR_EPS6
|
||||
#define XT_XSR_EPS6 _TIE_xt_core_XSR_EPS6
|
||||
#define XT_RSR_EPS7 _TIE_xt_core_RSR_EPS7
|
||||
#define XT_WSR_EPS7 _TIE_xt_core_WSR_EPS7
|
||||
#define XT_XSR_EPS7 _TIE_xt_core_XSR_EPS7
|
||||
#define XT_RSR_EXCCAUSE _TIE_xt_core_RSR_EXCCAUSE
|
||||
#define XT_WSR_EXCCAUSE _TIE_xt_core_WSR_EXCCAUSE
|
||||
#define XT_XSR_EXCCAUSE _TIE_xt_core_XSR_EXCCAUSE
|
||||
#define XT_RSR_EXCVADDR _TIE_xt_core_RSR_EXCVADDR
|
||||
#define XT_WSR_EXCVADDR _TIE_xt_core_WSR_EXCVADDR
|
||||
#define XT_XSR_EXCVADDR _TIE_xt_core_XSR_EXCVADDR
|
||||
#define XT_RSR_DEPC _TIE_xt_core_RSR_DEPC
|
||||
#define XT_WSR_DEPC _TIE_xt_core_WSR_DEPC
|
||||
#define XT_XSR_DEPC _TIE_xt_core_XSR_DEPC
|
||||
#define XT_RSR_MISC0 _TIE_xt_core_RSR_MISC0
|
||||
#define XT_WSR_MISC0 _TIE_xt_core_WSR_MISC0
|
||||
#define XT_XSR_MISC0 _TIE_xt_core_XSR_MISC0
|
||||
#define XT_RSR_MISC1 _TIE_xt_core_RSR_MISC1
|
||||
#define XT_WSR_MISC1 _TIE_xt_core_WSR_MISC1
|
||||
#define XT_XSR_MISC1 _TIE_xt_core_XSR_MISC1
|
||||
#define XT_RSR_MISC2 _TIE_xt_core_RSR_MISC2
|
||||
#define XT_WSR_MISC2 _TIE_xt_core_WSR_MISC2
|
||||
#define XT_XSR_MISC2 _TIE_xt_core_XSR_MISC2
|
||||
#define XT_RSR_MISC3 _TIE_xt_core_RSR_MISC3
|
||||
#define XT_WSR_MISC3 _TIE_xt_core_WSR_MISC3
|
||||
#define XT_XSR_MISC3 _TIE_xt_core_XSR_MISC3
|
||||
#define XT_RSR_PRID _TIE_xt_core_RSR_PRID
|
||||
|
||||
#ifndef RUR
|
||||
#define RUR(NUM) RUR##NUM()
|
||||
#endif
|
||||
|
||||
#ifndef WUR
|
||||
#define WUR(VAL, NUM) WUR##NUM(VAL)
|
||||
#endif
|
||||
|
||||
#endif /* __XCC__ */
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
|
||||
#endif /* !_XTENSA_xt_core_HEADER */
|
||||
@@ -0,0 +1,116 @@
|
||||
/* Definitions for the xt_debug TIE package */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_debug_HEADER
|
||||
#define _XTENSA_xt_debug_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#ifdef __XCC__
|
||||
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
|
||||
/*
|
||||
* The following prototypes describe intrinsic functions
|
||||
* corresponding to TIE instructions. Some TIE instructions
|
||||
* may produce multiple results (designated as "out" operands
|
||||
* in the iclass section) or may have operands used as both
|
||||
* inputs and outputs (designated as "inout"). However, the C
|
||||
* and C++ languages do not provide syntax that can express
|
||||
* the in/out/inout constraints of TIE intrinsics.
|
||||
* Nevertheless, the compiler understands these constraints
|
||||
* and will check that the intrinsic functions are used
|
||||
* correctly. To improve the readability of these prototypes,
|
||||
* the "out" and "inout" parameters are marked accordingly
|
||||
* with comments.
|
||||
*/
|
||||
|
||||
extern void _TIE_xt_debug_BREAK(immediate imms, immediate immt);
|
||||
extern void _TIE_xt_debug_BREAK_N(immediate imms);
|
||||
extern unsigned _TIE_xt_debug_RSR_DBREAKA0(void);
|
||||
extern void _TIE_xt_debug_WSR_DBREAKA0(unsigned art);
|
||||
extern void _TIE_xt_debug_XSR_DBREAKA0(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_debug_RSR_DBREAKC0(void);
|
||||
extern void _TIE_xt_debug_WSR_DBREAKC0(unsigned art);
|
||||
extern void _TIE_xt_debug_XSR_DBREAKC0(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_debug_RSR_DBREAKA1(void);
|
||||
extern void _TIE_xt_debug_WSR_DBREAKA1(unsigned art);
|
||||
extern void _TIE_xt_debug_XSR_DBREAKA1(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_debug_RSR_DBREAKC1(void);
|
||||
extern void _TIE_xt_debug_WSR_DBREAKC1(unsigned art);
|
||||
extern void _TIE_xt_debug_XSR_DBREAKC1(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_debug_RSR_IBREAKA0(void);
|
||||
extern void _TIE_xt_debug_WSR_IBREAKA0(unsigned art);
|
||||
extern void _TIE_xt_debug_XSR_IBREAKA0(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_debug_RSR_IBREAKA1(void);
|
||||
extern void _TIE_xt_debug_WSR_IBREAKA1(unsigned art);
|
||||
extern void _TIE_xt_debug_XSR_IBREAKA1(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_debug_RSR_IBREAKENABLE(void);
|
||||
extern void _TIE_xt_debug_WSR_IBREAKENABLE(unsigned art);
|
||||
extern void _TIE_xt_debug_XSR_IBREAKENABLE(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_debug_RSR_DEBUGCAUSE(void);
|
||||
extern void _TIE_xt_debug_WSR_DEBUGCAUSE(unsigned art);
|
||||
extern void _TIE_xt_debug_XSR_DEBUGCAUSE(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_debug_RSR_ICOUNT(void);
|
||||
extern void _TIE_xt_debug_WSR_ICOUNT(unsigned art);
|
||||
extern void _TIE_xt_debug_XSR_ICOUNT(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_debug_RSR_ICOUNTLEVEL(void);
|
||||
extern void _TIE_xt_debug_WSR_ICOUNTLEVEL(unsigned art);
|
||||
extern void _TIE_xt_debug_XSR_ICOUNTLEVEL(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_debug_RSR_DDR(void);
|
||||
extern void _TIE_xt_debug_WSR_DDR(unsigned art);
|
||||
extern void _TIE_xt_debug_XSR_DDR(unsigned art /*inout*/);
|
||||
extern void _TIE_xt_debug_LDDR32_P(const void * ars /*inout*/);
|
||||
extern void _TIE_xt_debug_SDDR32_P(void * ars /*inout*/);
|
||||
#define XT_BREAK _TIE_xt_debug_BREAK
|
||||
#define XT_BREAK_N _TIE_xt_debug_BREAK_N
|
||||
#define XT_RSR_DBREAKA0 _TIE_xt_debug_RSR_DBREAKA0
|
||||
#define XT_WSR_DBREAKA0 _TIE_xt_debug_WSR_DBREAKA0
|
||||
#define XT_XSR_DBREAKA0 _TIE_xt_debug_XSR_DBREAKA0
|
||||
#define XT_RSR_DBREAKC0 _TIE_xt_debug_RSR_DBREAKC0
|
||||
#define XT_WSR_DBREAKC0 _TIE_xt_debug_WSR_DBREAKC0
|
||||
#define XT_XSR_DBREAKC0 _TIE_xt_debug_XSR_DBREAKC0
|
||||
#define XT_RSR_DBREAKA1 _TIE_xt_debug_RSR_DBREAKA1
|
||||
#define XT_WSR_DBREAKA1 _TIE_xt_debug_WSR_DBREAKA1
|
||||
#define XT_XSR_DBREAKA1 _TIE_xt_debug_XSR_DBREAKA1
|
||||
#define XT_RSR_DBREAKC1 _TIE_xt_debug_RSR_DBREAKC1
|
||||
#define XT_WSR_DBREAKC1 _TIE_xt_debug_WSR_DBREAKC1
|
||||
#define XT_XSR_DBREAKC1 _TIE_xt_debug_XSR_DBREAKC1
|
||||
#define XT_RSR_IBREAKA0 _TIE_xt_debug_RSR_IBREAKA0
|
||||
#define XT_WSR_IBREAKA0 _TIE_xt_debug_WSR_IBREAKA0
|
||||
#define XT_XSR_IBREAKA0 _TIE_xt_debug_XSR_IBREAKA0
|
||||
#define XT_RSR_IBREAKA1 _TIE_xt_debug_RSR_IBREAKA1
|
||||
#define XT_WSR_IBREAKA1 _TIE_xt_debug_WSR_IBREAKA1
|
||||
#define XT_XSR_IBREAKA1 _TIE_xt_debug_XSR_IBREAKA1
|
||||
#define XT_RSR_IBREAKENABLE _TIE_xt_debug_RSR_IBREAKENABLE
|
||||
#define XT_WSR_IBREAKENABLE _TIE_xt_debug_WSR_IBREAKENABLE
|
||||
#define XT_XSR_IBREAKENABLE _TIE_xt_debug_XSR_IBREAKENABLE
|
||||
#define XT_RSR_DEBUGCAUSE _TIE_xt_debug_RSR_DEBUGCAUSE
|
||||
#define XT_WSR_DEBUGCAUSE _TIE_xt_debug_WSR_DEBUGCAUSE
|
||||
#define XT_XSR_DEBUGCAUSE _TIE_xt_debug_XSR_DEBUGCAUSE
|
||||
#define XT_RSR_ICOUNT _TIE_xt_debug_RSR_ICOUNT
|
||||
#define XT_WSR_ICOUNT _TIE_xt_debug_WSR_ICOUNT
|
||||
#define XT_XSR_ICOUNT _TIE_xt_debug_XSR_ICOUNT
|
||||
#define XT_RSR_ICOUNTLEVEL _TIE_xt_debug_RSR_ICOUNTLEVEL
|
||||
#define XT_WSR_ICOUNTLEVEL _TIE_xt_debug_WSR_ICOUNTLEVEL
|
||||
#define XT_XSR_ICOUNTLEVEL _TIE_xt_debug_XSR_ICOUNTLEVEL
|
||||
#define XT_RSR_DDR _TIE_xt_debug_RSR_DDR
|
||||
#define XT_WSR_DDR _TIE_xt_debug_WSR_DDR
|
||||
#define XT_XSR_DDR _TIE_xt_debug_XSR_DDR
|
||||
#define XT_LDDR32_P _TIE_xt_debug_LDDR32_P
|
||||
#define XT_SDDR32_P _TIE_xt_debug_SDDR32_P
|
||||
|
||||
#endif /* __XCC__ */
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
|
||||
#endif /* !_XTENSA_xt_debug_HEADER */
|
||||
@@ -0,0 +1,58 @@
|
||||
/* Definitions for the xt_density TIE package */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_density_HEADER
|
||||
#define _XTENSA_xt_density_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#ifdef __XCC__
|
||||
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
|
||||
/*
|
||||
* The following prototypes describe intrinsic functions
|
||||
* corresponding to TIE instructions. Some TIE instructions
|
||||
* may produce multiple results (designated as "out" operands
|
||||
* in the iclass section) or may have operands used as both
|
||||
* inputs and outputs (designated as "inout"). However, the C
|
||||
* and C++ languages do not provide syntax that can express
|
||||
* the in/out/inout constraints of TIE intrinsics.
|
||||
* Nevertheless, the compiler understands these constraints
|
||||
* and will check that the intrinsic functions are used
|
||||
* correctly. To improve the readability of these prototypes,
|
||||
* the "out" and "inout" parameters are marked accordingly
|
||||
* with comments.
|
||||
*/
|
||||
|
||||
extern void _TIE_xt_density_ILL_N(void);
|
||||
extern void _TIE_xt_density_NOP_N(void);
|
||||
extern int _TIE_xt_density_L32I_N(const int * p, immediate i);
|
||||
extern void _TIE_xt_density_S32I_N(int t, int * p, immediate i);
|
||||
extern int _TIE_xt_density_ADD_N(int s, int t);
|
||||
extern int _TIE_xt_density_ADDI_N(int s, immediate i);
|
||||
extern int _TIE_xt_density_MOV_N(int s);
|
||||
extern int _TIE_xt_density_MOVI_N(immediate i);
|
||||
#define XT_ILL_N _TIE_xt_density_ILL_N
|
||||
#define XT_NOP_N _TIE_xt_density_NOP_N
|
||||
#define XT_L32I_N _TIE_xt_density_L32I_N
|
||||
#define XT_S32I_N _TIE_xt_density_S32I_N
|
||||
#define XT_ADD_N _TIE_xt_density_ADD_N
|
||||
#define XT_ADDI_N _TIE_xt_density_ADDI_N
|
||||
#define XT_MOV_N _TIE_xt_density_MOV_N
|
||||
#define XT_MOVI_N _TIE_xt_density_MOVI_N
|
||||
|
||||
#endif /* __XCC__ */
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
|
||||
#endif /* !_XTENSA_xt_density_HEADER */
|
||||
@@ -0,0 +1,45 @@
|
||||
/* Definitions for the xt_exceptions TIE package */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_exceptions_HEADER
|
||||
#define _XTENSA_xt_exceptions_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#ifdef __XCC__
|
||||
|
||||
|
||||
/*
|
||||
* The following prototypes describe intrinsic functions
|
||||
* corresponding to TIE instructions. Some TIE instructions
|
||||
* may produce multiple results (designated as "out" operands
|
||||
* in the iclass section) or may have operands used as both
|
||||
* inputs and outputs (designated as "inout"). However, the C
|
||||
* and C++ languages do not provide syntax that can express
|
||||
* the in/out/inout constraints of TIE intrinsics.
|
||||
* Nevertheless, the compiler understands these constraints
|
||||
* and will check that the intrinsic functions are used
|
||||
* correctly. To improve the readability of these prototypes,
|
||||
* the "out" and "inout" parameters are marked accordingly
|
||||
* with comments.
|
||||
*/
|
||||
|
||||
extern void _TIE_xt_exceptions_EXCW(void);
|
||||
extern void _TIE_xt_exceptions_SYSCALL(void);
|
||||
#define XT_EXCW _TIE_xt_exceptions_EXCW
|
||||
#define XT_SYSCALL _TIE_xt_exceptions_SYSCALL
|
||||
|
||||
#endif /* __XCC__ */
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
|
||||
#endif /* !_XTENSA_xt_exceptions_HEADER */
|
||||
@@ -0,0 +1,46 @@
|
||||
/* Definitions for the xt_externalregisters TIE package */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_externalregisters_HEADER
|
||||
#define _XTENSA_xt_externalregisters_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#ifdef __XCC__
|
||||
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
|
||||
/*
|
||||
* The following prototypes describe intrinsic functions
|
||||
* corresponding to TIE instructions. Some TIE instructions
|
||||
* may produce multiple results (designated as "out" operands
|
||||
* in the iclass section) or may have operands used as both
|
||||
* inputs and outputs (designated as "inout"). However, the C
|
||||
* and C++ languages do not provide syntax that can express
|
||||
* the in/out/inout constraints of TIE intrinsics.
|
||||
* Nevertheless, the compiler understands these constraints
|
||||
* and will check that the intrinsic functions are used
|
||||
* correctly. To improve the readability of these prototypes,
|
||||
* the "out" and "inout" parameters are marked accordingly
|
||||
* with comments.
|
||||
*/
|
||||
|
||||
extern unsigned _TIE_xt_externalregisters_RER(unsigned ars);
|
||||
extern void _TIE_xt_externalregisters_WER(unsigned art, unsigned ars);
|
||||
#define XT_RER _TIE_xt_externalregisters_RER
|
||||
#define XT_WER _TIE_xt_externalregisters_WER
|
||||
|
||||
#endif /* __XCC__ */
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
|
||||
#endif /* !_XTENSA_xt_externalregisters_HEADER */
|
||||
@@ -0,0 +1,50 @@
|
||||
/* Definitions for the xt_integerdivide TIE package */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_integerdivide_HEADER
|
||||
#define _XTENSA_xt_integerdivide_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#ifdef __XCC__
|
||||
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
|
||||
/*
|
||||
* The following prototypes describe intrinsic functions
|
||||
* corresponding to TIE instructions. Some TIE instructions
|
||||
* may produce multiple results (designated as "out" operands
|
||||
* in the iclass section) or may have operands used as both
|
||||
* inputs and outputs (designated as "inout"). However, the C
|
||||
* and C++ languages do not provide syntax that can express
|
||||
* the in/out/inout constraints of TIE intrinsics.
|
||||
* Nevertheless, the compiler understands these constraints
|
||||
* and will check that the intrinsic functions are used
|
||||
* correctly. To improve the readability of these prototypes,
|
||||
* the "out" and "inout" parameters are marked accordingly
|
||||
* with comments.
|
||||
*/
|
||||
|
||||
extern unsigned _TIE_xt_integerdivide_REMS(unsigned ars, unsigned art);
|
||||
extern unsigned _TIE_xt_integerdivide_REMU(unsigned ars, unsigned art);
|
||||
extern unsigned _TIE_xt_integerdivide_QUOS(unsigned ars, unsigned art);
|
||||
extern unsigned _TIE_xt_integerdivide_QUOU(unsigned ars, unsigned art);
|
||||
#define XT_REMS _TIE_xt_integerdivide_REMS
|
||||
#define XT_REMU _TIE_xt_integerdivide_REMU
|
||||
#define XT_QUOS _TIE_xt_integerdivide_QUOS
|
||||
#define XT_QUOU _TIE_xt_integerdivide_QUOU
|
||||
|
||||
#endif /* __XCC__ */
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
|
||||
#endif /* !_XTENSA_xt_integerdivide_HEADER */
|
||||
@@ -0,0 +1,56 @@
|
||||
/* Definitions for the xt_interrupt TIE package */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_interrupt_HEADER
|
||||
#define _XTENSA_xt_interrupt_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#ifdef __XCC__
|
||||
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
|
||||
/*
|
||||
* The following prototypes describe intrinsic functions
|
||||
* corresponding to TIE instructions. Some TIE instructions
|
||||
* may produce multiple results (designated as "out" operands
|
||||
* in the iclass section) or may have operands used as both
|
||||
* inputs and outputs (designated as "inout"). However, the C
|
||||
* and C++ languages do not provide syntax that can express
|
||||
* the in/out/inout constraints of TIE intrinsics.
|
||||
* Nevertheless, the compiler understands these constraints
|
||||
* and will check that the intrinsic functions are used
|
||||
* correctly. To improve the readability of these prototypes,
|
||||
* the "out" and "inout" parameters are marked accordingly
|
||||
* with comments.
|
||||
*/
|
||||
|
||||
extern void _TIE_xt_interrupt_WAITI(immediate s);
|
||||
extern unsigned _TIE_xt_interrupt_RSR_INTERRUPT(void);
|
||||
extern void _TIE_xt_interrupt_WSR_INTSET(unsigned art);
|
||||
extern void _TIE_xt_interrupt_WSR_INTCLEAR(unsigned art);
|
||||
extern unsigned _TIE_xt_interrupt_RSR_INTENABLE(void);
|
||||
extern void _TIE_xt_interrupt_WSR_INTENABLE(unsigned art);
|
||||
extern void _TIE_xt_interrupt_XSR_INTENABLE(unsigned art /*inout*/);
|
||||
#define XT_WAITI _TIE_xt_interrupt_WAITI
|
||||
#define XT_RSR_INTERRUPT _TIE_xt_interrupt_RSR_INTERRUPT
|
||||
#define XT_WSR_INTSET _TIE_xt_interrupt_WSR_INTSET
|
||||
#define XT_WSR_INTCLEAR _TIE_xt_interrupt_WSR_INTCLEAR
|
||||
#define XT_RSR_INTENABLE _TIE_xt_interrupt_RSR_INTENABLE
|
||||
#define XT_WSR_INTENABLE _TIE_xt_interrupt_WSR_INTENABLE
|
||||
#define XT_XSR_INTENABLE _TIE_xt_interrupt_XSR_INTENABLE
|
||||
|
||||
#endif /* __XCC__ */
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
|
||||
#endif /* !_XTENSA_xt_interrupt_HEADER */
|
||||
@@ -0,0 +1,66 @@
|
||||
/* Definitions for the xt_ioports TIE package */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_ioports_HEADER
|
||||
#define _XTENSA_xt_ioports_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#ifdef __XCC__
|
||||
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
|
||||
/*
|
||||
* The following prototypes describe intrinsic functions
|
||||
* corresponding to TIE instructions. Some TIE instructions
|
||||
* may produce multiple results (designated as "out" operands
|
||||
* in the iclass section) or may have operands used as both
|
||||
* inputs and outputs (designated as "inout"). However, the C
|
||||
* and C++ languages do not provide syntax that can express
|
||||
* the in/out/inout constraints of TIE intrinsics.
|
||||
* Nevertheless, the compiler understands these constraints
|
||||
* and will check that the intrinsic functions are used
|
||||
* correctly. To improve the readability of these prototypes,
|
||||
* the "out" and "inout" parameters are marked accordingly
|
||||
* with comments.
|
||||
*/
|
||||
|
||||
extern unsigned _TIE_xt_ioports_READ_IMPWIRE(void);
|
||||
extern void _TIE_xt_ioports_SETB_EXPSTATE(immediate bitindex);
|
||||
extern void _TIE_xt_ioports_CLRB_EXPSTATE(immediate bitindex);
|
||||
extern void _TIE_xt_ioports_WRMSK_EXPSTATE(unsigned art, unsigned ars);
|
||||
extern unsigned _TIE_xt_ioports_RUR_EXPSTATE(void);
|
||||
extern void _TIE_xt_ioports_WUR_EXPSTATE(unsigned v);
|
||||
#define READ_IMPWIRE _TIE_xt_ioports_READ_IMPWIRE
|
||||
#define SETB_EXPSTATE _TIE_xt_ioports_SETB_EXPSTATE
|
||||
#define CLRB_EXPSTATE _TIE_xt_ioports_CLRB_EXPSTATE
|
||||
#define WRMSK_EXPSTATE _TIE_xt_ioports_WRMSK_EXPSTATE
|
||||
#define RUR_EXPSTATE _TIE_xt_ioports_RUR_EXPSTATE
|
||||
#define REXPSTATE _TIE_xt_ioports_RUR_EXPSTATE
|
||||
#define RUR230 _TIE_xt_ioports_RUR_EXPSTATE
|
||||
#define WUR_EXPSTATE _TIE_xt_ioports_WUR_EXPSTATE
|
||||
#define WEXPSTATE _TIE_xt_ioports_WUR_EXPSTATE
|
||||
#define WUR230 _TIE_xt_ioports_WUR_EXPSTATE
|
||||
|
||||
#ifndef RUR
|
||||
#define RUR(NUM) RUR##NUM()
|
||||
#endif
|
||||
|
||||
#ifndef WUR
|
||||
#define WUR(VAL, NUM) WUR##NUM(VAL)
|
||||
#endif
|
||||
|
||||
#endif /* __XCC__ */
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
|
||||
#endif /* !_XTENSA_xt_ioports_HEADER */
|
||||
@@ -0,0 +1,58 @@
|
||||
/* Definitions for the xt_misc TIE package */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_misc_HEADER
|
||||
#define _XTENSA_xt_misc_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#ifdef __XCC__
|
||||
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
|
||||
/*
|
||||
* The following prototypes describe intrinsic functions
|
||||
* corresponding to TIE instructions. Some TIE instructions
|
||||
* may produce multiple results (designated as "out" operands
|
||||
* in the iclass section) or may have operands used as both
|
||||
* inputs and outputs (designated as "inout"). However, the C
|
||||
* and C++ languages do not provide syntax that can express
|
||||
* the in/out/inout constraints of TIE intrinsics.
|
||||
* Nevertheless, the compiler understands these constraints
|
||||
* and will check that the intrinsic functions are used
|
||||
* correctly. To improve the readability of these prototypes,
|
||||
* the "out" and "inout" parameters are marked accordingly
|
||||
* with comments.
|
||||
*/
|
||||
|
||||
extern int _TIE_xt_misc_CLAMPS(int s, immediate i);
|
||||
extern int _TIE_xt_misc_MIN(int s, int t);
|
||||
extern int _TIE_xt_misc_MAX(int s, int t);
|
||||
extern unsigned _TIE_xt_misc_MINU(unsigned s, unsigned t);
|
||||
extern unsigned _TIE_xt_misc_MAXU(unsigned s, unsigned t);
|
||||
extern int _TIE_xt_misc_NSA(int s);
|
||||
extern unsigned _TIE_xt_misc_NSAU(unsigned s);
|
||||
extern int _TIE_xt_misc_SEXT(int s, immediate i);
|
||||
#define XT_CLAMPS _TIE_xt_misc_CLAMPS
|
||||
#define XT_MIN _TIE_xt_misc_MIN
|
||||
#define XT_MAX _TIE_xt_misc_MAX
|
||||
#define XT_MINU _TIE_xt_misc_MINU
|
||||
#define XT_MAXU _TIE_xt_misc_MAXU
|
||||
#define XT_NSA _TIE_xt_misc_NSA
|
||||
#define XT_NSAU _TIE_xt_misc_NSAU
|
||||
#define XT_SEXT _TIE_xt_misc_SEXT
|
||||
|
||||
#endif /* __XCC__ */
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
|
||||
#endif /* !_XTENSA_xt_misc_HEADER */
|
||||
@@ -0,0 +1,62 @@
|
||||
/* Definitions for the xt_mmu TIE package */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_mmu_HEADER
|
||||
#define _XTENSA_xt_mmu_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#ifdef __XCC__
|
||||
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
|
||||
/*
|
||||
* The following prototypes describe intrinsic functions
|
||||
* corresponding to TIE instructions. Some TIE instructions
|
||||
* may produce multiple results (designated as "out" operands
|
||||
* in the iclass section) or may have operands used as both
|
||||
* inputs and outputs (designated as "inout"). However, the C
|
||||
* and C++ languages do not provide syntax that can express
|
||||
* the in/out/inout constraints of TIE intrinsics.
|
||||
* Nevertheless, the compiler understands these constraints
|
||||
* and will check that the intrinsic functions are used
|
||||
* correctly. To improve the readability of these prototypes,
|
||||
* the "out" and "inout" parameters are marked accordingly
|
||||
* with comments.
|
||||
*/
|
||||
|
||||
extern void _TIE_xt_mmu_IDTLB(unsigned ars);
|
||||
extern unsigned _TIE_xt_mmu_RDTLB1(unsigned ars);
|
||||
extern unsigned _TIE_xt_mmu_RDTLB0(unsigned ars);
|
||||
extern unsigned _TIE_xt_mmu_PDTLB(unsigned ars);
|
||||
extern void _TIE_xt_mmu_WDTLB(unsigned art, unsigned ars);
|
||||
extern void _TIE_xt_mmu_IITLB(unsigned ars);
|
||||
extern unsigned _TIE_xt_mmu_RITLB1(unsigned ars);
|
||||
extern unsigned _TIE_xt_mmu_RITLB0(unsigned ars);
|
||||
extern unsigned _TIE_xt_mmu_PITLB(unsigned ars);
|
||||
extern void _TIE_xt_mmu_WITLB(unsigned art, unsigned ars);
|
||||
#define XT_IDTLB _TIE_xt_mmu_IDTLB
|
||||
#define XT_RDTLB1 _TIE_xt_mmu_RDTLB1
|
||||
#define XT_RDTLB0 _TIE_xt_mmu_RDTLB0
|
||||
#define XT_PDTLB _TIE_xt_mmu_PDTLB
|
||||
#define XT_WDTLB _TIE_xt_mmu_WDTLB
|
||||
#define XT_IITLB _TIE_xt_mmu_IITLB
|
||||
#define XT_RITLB1 _TIE_xt_mmu_RITLB1
|
||||
#define XT_RITLB0 _TIE_xt_mmu_RITLB0
|
||||
#define XT_PITLB _TIE_xt_mmu_PITLB
|
||||
#define XT_WITLB _TIE_xt_mmu_WITLB
|
||||
|
||||
#endif /* __XCC__ */
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
|
||||
#endif /* !_XTENSA_xt_mmu_HEADER */
|
||||
@@ -0,0 +1,52 @@
|
||||
/* Definitions for the xt_mul TIE package */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_mul_HEADER
|
||||
#define _XTENSA_xt_mul_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#ifdef __XCC__
|
||||
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
|
||||
/*
|
||||
* The following prototypes describe intrinsic functions
|
||||
* corresponding to TIE instructions. Some TIE instructions
|
||||
* may produce multiple results (designated as "out" operands
|
||||
* in the iclass section) or may have operands used as both
|
||||
* inputs and outputs (designated as "inout"). However, the C
|
||||
* and C++ languages do not provide syntax that can express
|
||||
* the in/out/inout constraints of TIE intrinsics.
|
||||
* Nevertheless, the compiler understands these constraints
|
||||
* and will check that the intrinsic functions are used
|
||||
* correctly. To improve the readability of these prototypes,
|
||||
* the "out" and "inout" parameters are marked accordingly
|
||||
* with comments.
|
||||
*/
|
||||
|
||||
extern int _TIE_xt_mul_MUL16S(short s, short t);
|
||||
extern unsigned _TIE_xt_mul_MUL16U(unsigned short s, unsigned short t);
|
||||
extern int _TIE_xt_mul_MULL(int s, int t);
|
||||
extern unsigned _TIE_xt_mul_MULUH(unsigned s, unsigned t);
|
||||
extern int _TIE_xt_mul_MULSH(int s, int t);
|
||||
#define XT_MUL16S _TIE_xt_mul_MUL16S
|
||||
#define XT_MUL16U _TIE_xt_mul_MUL16U
|
||||
#define XT_MULL _TIE_xt_mul_MULL
|
||||
#define XT_MULUH _TIE_xt_mul_MULUH
|
||||
#define XT_MULSH _TIE_xt_mul_MULSH
|
||||
|
||||
#endif /* __XCC__ */
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
|
||||
#endif /* !_XTENSA_xt_mul_HEADER */
|
||||
@@ -0,0 +1,64 @@
|
||||
/* Definitions for the xt_regwin TIE package */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_regwin_HEADER
|
||||
#define _XTENSA_xt_regwin_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#ifdef __XCC__
|
||||
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
|
||||
/*
|
||||
* The following prototypes describe intrinsic functions
|
||||
* corresponding to TIE instructions. Some TIE instructions
|
||||
* may produce multiple results (designated as "out" operands
|
||||
* in the iclass section) or may have operands used as both
|
||||
* inputs and outputs (designated as "inout"). However, the C
|
||||
* and C++ languages do not provide syntax that can express
|
||||
* the in/out/inout constraints of TIE intrinsics.
|
||||
* Nevertheless, the compiler understands these constraints
|
||||
* and will check that the intrinsic functions are used
|
||||
* correctly. To improve the readability of these prototypes,
|
||||
* the "out" and "inout" parameters are marked accordingly
|
||||
* with comments.
|
||||
*/
|
||||
|
||||
extern void _TIE_xt_regwin_ENTRY(unsigned ars /*inout*/, immediate uimm12x8);
|
||||
extern void _TIE_xt_regwin_ROTW(immediate simm4);
|
||||
extern int _TIE_xt_regwin_MOVSP(int s);
|
||||
extern int _TIE_xt_regwin_L32E(const int * s, immediate o);
|
||||
extern void _TIE_xt_regwin_S32E(int t, int * s, immediate o);
|
||||
extern unsigned _TIE_xt_regwin_RSR_WINDOWBASE(void);
|
||||
extern void _TIE_xt_regwin_WSR_WINDOWBASE(unsigned t);
|
||||
extern void _TIE_xt_regwin_XSR_WINDOWBASE(unsigned t /*inout*/);
|
||||
extern unsigned _TIE_xt_regwin_RSR_WINDOWSTART(void);
|
||||
extern void _TIE_xt_regwin_WSR_WINDOWSTART(unsigned t);
|
||||
extern void _TIE_xt_regwin_XSR_WINDOWSTART(unsigned t /*inout*/);
|
||||
#define XT_ENTRY _TIE_xt_regwin_ENTRY
|
||||
#define XT_ROTW _TIE_xt_regwin_ROTW
|
||||
#define XT_MOVSP _TIE_xt_regwin_MOVSP
|
||||
#define XT_L32E _TIE_xt_regwin_L32E
|
||||
#define XT_S32E _TIE_xt_regwin_S32E
|
||||
#define XT_RSR_WINDOWBASE _TIE_xt_regwin_RSR_WINDOWBASE
|
||||
#define XT_WSR_WINDOWBASE _TIE_xt_regwin_WSR_WINDOWBASE
|
||||
#define XT_XSR_WINDOWBASE _TIE_xt_regwin_XSR_WINDOWBASE
|
||||
#define XT_RSR_WINDOWSTART _TIE_xt_regwin_RSR_WINDOWSTART
|
||||
#define XT_WSR_WINDOWSTART _TIE_xt_regwin_WSR_WINDOWSTART
|
||||
#define XT_XSR_WINDOWSTART _TIE_xt_regwin_XSR_WINDOWSTART
|
||||
|
||||
#endif /* __XCC__ */
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
|
||||
#endif /* !_XTENSA_xt_regwin_HEADER */
|
||||
@@ -0,0 +1,22 @@
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_scmpr_h_HEADER
|
||||
#define _XTENSA_xt_scmpr_h_HEADER
|
||||
|
||||
|
||||
/* Header includes start */
|
||||
|
||||
|
||||
/* Header includes end */
|
||||
|
||||
#endif /* !_XTENSA_xt_scmpr_h_HEADER */
|
||||
@@ -0,0 +1,60 @@
|
||||
/* Definitions for the xt_sync TIE package */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_sync_HEADER
|
||||
#define _XTENSA_xt_sync_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#ifdef __XCC__
|
||||
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
|
||||
/*
|
||||
* The following prototypes describe intrinsic functions
|
||||
* corresponding to TIE instructions. Some TIE instructions
|
||||
* may produce multiple results (designated as "out" operands
|
||||
* in the iclass section) or may have operands used as both
|
||||
* inputs and outputs (designated as "inout"). However, the C
|
||||
* and C++ languages do not provide syntax that can express
|
||||
* the in/out/inout constraints of TIE intrinsics.
|
||||
* Nevertheless, the compiler understands these constraints
|
||||
* and will check that the intrinsic functions are used
|
||||
* correctly. To improve the readability of these prototypes,
|
||||
* the "out" and "inout" parameters are marked accordingly
|
||||
* with comments.
|
||||
*/
|
||||
|
||||
extern unsigned _TIE_xt_sync_RSR_SCOMPARE1(void);
|
||||
extern void _TIE_xt_sync_WSR_SCOMPARE1(unsigned art);
|
||||
extern void _TIE_xt_sync_XSR_SCOMPARE1(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_sync_RSR_ATOMCTL(void);
|
||||
extern void _TIE_xt_sync_WSR_ATOMCTL(unsigned art);
|
||||
extern void _TIE_xt_sync_XSR_ATOMCTL(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_sync_L32AI(const unsigned * p, immediate o);
|
||||
extern void _TIE_xt_sync_S32RI(unsigned c, unsigned * p, immediate o);
|
||||
extern void _TIE_xt_sync_S32C1I(unsigned c /*inout*/, const unsigned * p, immediate o);
|
||||
#define XT_RSR_SCOMPARE1 _TIE_xt_sync_RSR_SCOMPARE1
|
||||
#define XT_WSR_SCOMPARE1 _TIE_xt_sync_WSR_SCOMPARE1
|
||||
#define XT_XSR_SCOMPARE1 _TIE_xt_sync_XSR_SCOMPARE1
|
||||
#define XT_RSR_ATOMCTL _TIE_xt_sync_RSR_ATOMCTL
|
||||
#define XT_WSR_ATOMCTL _TIE_xt_sync_WSR_ATOMCTL
|
||||
#define XT_XSR_ATOMCTL _TIE_xt_sync_XSR_ATOMCTL
|
||||
#define XT_L32AI _TIE_xt_sync_L32AI
|
||||
#define XT_S32RI _TIE_xt_sync_S32RI
|
||||
#define XT_S32C1I _TIE_xt_sync_S32C1I
|
||||
|
||||
#endif /* __XCC__ */
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
|
||||
#endif /* !_XTENSA_xt_sync_HEADER */
|
||||
@@ -0,0 +1,66 @@
|
||||
/* Definitions for the xt_timer TIE package */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_timer_HEADER
|
||||
#define _XTENSA_xt_timer_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#ifdef __XCC__
|
||||
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
|
||||
/*
|
||||
* The following prototypes describe intrinsic functions
|
||||
* corresponding to TIE instructions. Some TIE instructions
|
||||
* may produce multiple results (designated as "out" operands
|
||||
* in the iclass section) or may have operands used as both
|
||||
* inputs and outputs (designated as "inout"). However, the C
|
||||
* and C++ languages do not provide syntax that can express
|
||||
* the in/out/inout constraints of TIE intrinsics.
|
||||
* Nevertheless, the compiler understands these constraints
|
||||
* and will check that the intrinsic functions are used
|
||||
* correctly. To improve the readability of these prototypes,
|
||||
* the "out" and "inout" parameters are marked accordingly
|
||||
* with comments.
|
||||
*/
|
||||
|
||||
extern unsigned _TIE_xt_timer_RSR_CCOUNT(void);
|
||||
extern void _TIE_xt_timer_WSR_CCOUNT(unsigned art);
|
||||
extern void _TIE_xt_timer_XSR_CCOUNT(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_timer_RSR_CCOMPARE0(void);
|
||||
extern void _TIE_xt_timer_WSR_CCOMPARE0(unsigned art);
|
||||
extern void _TIE_xt_timer_XSR_CCOMPARE0(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_timer_RSR_CCOMPARE1(void);
|
||||
extern void _TIE_xt_timer_WSR_CCOMPARE1(unsigned art);
|
||||
extern void _TIE_xt_timer_XSR_CCOMPARE1(unsigned art /*inout*/);
|
||||
extern unsigned _TIE_xt_timer_RSR_CCOMPARE2(void);
|
||||
extern void _TIE_xt_timer_WSR_CCOMPARE2(unsigned art);
|
||||
extern void _TIE_xt_timer_XSR_CCOMPARE2(unsigned art /*inout*/);
|
||||
#define XT_RSR_CCOUNT _TIE_xt_timer_RSR_CCOUNT
|
||||
#define XT_WSR_CCOUNT _TIE_xt_timer_WSR_CCOUNT
|
||||
#define XT_XSR_CCOUNT _TIE_xt_timer_XSR_CCOUNT
|
||||
#define XT_RSR_CCOMPARE0 _TIE_xt_timer_RSR_CCOMPARE0
|
||||
#define XT_WSR_CCOMPARE0 _TIE_xt_timer_WSR_CCOMPARE0
|
||||
#define XT_XSR_CCOMPARE0 _TIE_xt_timer_XSR_CCOMPARE0
|
||||
#define XT_RSR_CCOMPARE1 _TIE_xt_timer_RSR_CCOMPARE1
|
||||
#define XT_WSR_CCOMPARE1 _TIE_xt_timer_WSR_CCOMPARE1
|
||||
#define XT_XSR_CCOMPARE1 _TIE_xt_timer_XSR_CCOMPARE1
|
||||
#define XT_RSR_CCOMPARE2 _TIE_xt_timer_RSR_CCOMPARE2
|
||||
#define XT_WSR_CCOMPARE2 _TIE_xt_timer_WSR_CCOMPARE2
|
||||
#define XT_XSR_CCOMPARE2 _TIE_xt_timer_XSR_CCOMPARE2
|
||||
|
||||
#endif /* __XCC__ */
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
|
||||
#endif /* !_XTENSA_xt_timer_HEADER */
|
||||
@@ -0,0 +1,44 @@
|
||||
/* Definitions for the xt_trace TIE package */
|
||||
|
||||
/*
|
||||
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* Do not modify. This is automatically generated.*/
|
||||
|
||||
#ifndef _XTENSA_xt_trace_HEADER
|
||||
#define _XTENSA_xt_trace_HEADER
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#ifdef __XCC__
|
||||
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
|
||||
/*
|
||||
* The following prototypes describe intrinsic functions
|
||||
* corresponding to TIE instructions. Some TIE instructions
|
||||
* may produce multiple results (designated as "out" operands
|
||||
* in the iclass section) or may have operands used as both
|
||||
* inputs and outputs (designated as "inout"). However, the C
|
||||
* and C++ languages do not provide syntax that can express
|
||||
* the in/out/inout constraints of TIE intrinsics.
|
||||
* Nevertheless, the compiler understands these constraints
|
||||
* and will check that the intrinsic functions are used
|
||||
* correctly. To improve the readability of these prototypes,
|
||||
* the "out" and "inout" parameters are marked accordingly
|
||||
* with comments.
|
||||
*/
|
||||
|
||||
extern void _TIE_xt_trace_WSR_MMID(unsigned art);
|
||||
#define XT_WSR_MMID _TIE_xt_trace_WSR_MMID
|
||||
|
||||
#endif /* __XCC__ */
|
||||
|
||||
#endif /* __XTENSA__ */
|
||||
|
||||
#endif /* !_XTENSA_xt_trace_HEADER */
|
||||
Executable
+93
@@ -0,0 +1,93 @@
|
||||
/* Misc TRAX API function definitions.
|
||||
|
||||
Copyright (c) 2007-2012 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef _TRAX_API_H_
|
||||
#define _TRAX_API_H_
|
||||
|
||||
#include <xtensa-isa.h>
|
||||
#include <xtensa-params.h>
|
||||
#include "tpack.h"
|
||||
#include "traxreg.h"
|
||||
|
||||
#include "xdm-regs.h"
|
||||
|
||||
/* Flags for trax_stop(): */
|
||||
#define TRAX_STOP_HALT 0x0001 /* halt immediately, don't wait for post-stop-trigger capture */
|
||||
#define TRAX_STOP_QUIET 0x0002 /* don't display informative messages */
|
||||
|
||||
|
||||
/*
|
||||
* Describes a TRAX channel (based on tpack).
|
||||
*/
|
||||
typedef struct {
|
||||
tpack_channel chan; /* channel structure header */
|
||||
/* Per TRAX unit information: */
|
||||
int trax_version; /* TRAX_ID_VER(id), one of TRAX_VER_xxx macros */
|
||||
unsigned long trax_tram_size; /* size of trace RAM in bytes */
|
||||
int trax_erratum10; /* set if TRAX 1.0 erratum workarounds needed */
|
||||
int trax_erratum20; /* set if TRAX 2.0 erratum workaround needed (PR 22161)*/
|
||||
int trax_erratum20_size;
|
||||
int trax_has_busy; /* has trace-busy feature */
|
||||
int trax_has_atb; /* has ATB feature */
|
||||
/*FIXME: add various features: coresight regs (don't call it that), APB, ATB, TRAM, ... */
|
||||
} trax_channel;
|
||||
|
||||
|
||||
/* Prototypes: */
|
||||
|
||||
/* TRAX Protocol API: */
|
||||
extern int trax_read_register(tpack_channel *tchan, int regno, unsigned *value);
|
||||
extern int trax_write_register(tpack_channel *tchan, int regno, unsigned value);
|
||||
extern int trax_read_memory(tpack_channel *tchan, int address, int size, unsigned char *pdata);
|
||||
extern int trax_fill_memory(tpack_channel *tchan, int address, int size, tpack_u32 pattern);
|
||||
extern int trax_enumerate_devices(tpack_channel *tchan, int * buf, int * size);
|
||||
|
||||
/* TRAX Network API: */
|
||||
extern unsigned long trax_ram_size(tpack_channel *traxchan);
|
||||
extern unsigned long trax_ram_size_addr(tpack_channel *traxchan);
|
||||
extern int trax_create_tracefile(tpack_channel *traxchan, int size, unsigned char * data,
|
||||
char *filename, int hflags, const char *toolver);
|
||||
extern int trax_memaccess_safe(tpack_channel *traxchan, const char *what);
|
||||
extern int trax_start(tpack_channel *traxchan, int flags);
|
||||
extern int trax_stop(tpack_channel *traxchan, int flags);
|
||||
extern int trax_halt(tpack_channel *traxchan, int flags);
|
||||
extern int trax_save(tpack_channel *traxchan, char *filename, int flags, const char *toolver, int erratum);
|
||||
|
||||
/* TRAX Misc API (no network dependencies): */
|
||||
int trax_fixed_hw(unsigned * regs);
|
||||
extern int trax_display_id(unsigned id, const char *prefix);
|
||||
extern int trax_display_summary(unsigned id,
|
||||
unsigned status,
|
||||
unsigned control,
|
||||
unsigned address,
|
||||
unsigned delay,
|
||||
unsigned trigger,
|
||||
unsigned match,
|
||||
unsigned startaddr,
|
||||
unsigned endaddr,
|
||||
const char *prefix);
|
||||
|
||||
/* Other: */
|
||||
|
||||
#endif /* _TRAX_API_H_ */
|
||||
|
||||
+144
@@ -0,0 +1,144 @@
|
||||
/* Definitions for Xtensa processor config info needed for TRAX.
|
||||
|
||||
Copyright (c) 2005-2011 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef TRAX_CORE_CONFIG_H
|
||||
#define TRAX_CORE_CONFIG_H
|
||||
|
||||
#include "xtensa-params.h"
|
||||
|
||||
/*
|
||||
* Vector Enumerations.
|
||||
*/
|
||||
|
||||
/* These must match the LX2.0 and later traceport spec: */
|
||||
#define VEC_NO_VECTOR 0
|
||||
#define VEC_FIRST VEC_RESET /* first valid vector */
|
||||
#define VEC_RESET 1
|
||||
#define VEC_DEBUG 2
|
||||
#define VEC_NMI 3
|
||||
#define VEC_USER 4
|
||||
#define VEC_KERNEL 5
|
||||
#define VEC_DOUBLE 6
|
||||
#define VEC_MEMERR 7
|
||||
#define VEC_RESERVED8 8
|
||||
#define VEC_RESERVED9 9
|
||||
#define VEC_WINO4 10
|
||||
#define VEC_WINU4 11
|
||||
#define VEC_WINO8 12
|
||||
#define VEC_WINU8 13
|
||||
#define VEC_WINO12 14
|
||||
#define VEC_WINU12 15
|
||||
#define VEC_INTLEVEL2 16
|
||||
#define VEC_INTLEVEL3 17
|
||||
#define VEC_INTLEVEL4 18
|
||||
#define VEC_INTLEVEL5 19
|
||||
#define VEC_INTLEVEL6 20
|
||||
/* These are internal, i.e. don't appear like this on traceport: */
|
||||
#define VEC_DEBUG_OCD 21
|
||||
#define VEC_UNKNOWN 22
|
||||
/* Enumerations 23 through 31 are also reserved, but putting */
|
||||
/* placeholders here seems wasteful and unnecessary. */
|
||||
#define VEC_COUNT 23
|
||||
|
||||
/* Other branch (change-of-PC-flow) type encodings;
|
||||
* if PC changes due to an exception or interrupt vector,
|
||||
* one of the VEC_* values above is used, otherwise
|
||||
* (or if it's unknown whether it's due to an exception/interrupt)
|
||||
* one of the following is used: */
|
||||
|
||||
#define BRANCH_IS_VEC(n) ((n) < VEC_COUNT) /* is known to be except/interrupt? */
|
||||
#define BRANCH_OR_VEC 24 /* unknown type of branch (branch/exception/interrupt/etc) */
|
||||
#define BRANCH_UNKNOWN 25 /* unknown type of branch (anything but except/interrupt) */
|
||||
#define BRANCH_UNKNOWN_ERR 26 /* like BRANCH_UNKNOWN with known error (non-branch instr) */
|
||||
#define BRANCH_LOOPBACK 28 /* zero-overhead loopback (from LEND to LBEG) */
|
||||
#define BRANCH_CONDTAKEN 29 /* conditional branch taken (or LOOP{NEZ,GTZ} loop skip) */
|
||||
#define BRANCH_JUMP 30 /* jump (unconditional branch, i.e. J or JX) */
|
||||
#define BRANCH_IS_CALL(n) (((n) & ~3) == 32) /* is a function call? */
|
||||
#define BRANCH_CALL0 32 /* non-windowed function call (CALL0, CALLX0) */
|
||||
#define BRANCH_CALL4 33 /* windowed function call (CALL4, CALLX4) */
|
||||
#define BRANCH_CALL8 34 /* windowed function call (CALL8, CALLX8) */
|
||||
#define BRANCH_CALL12 35 /* windowed function call (CALL12, CALLX12) */
|
||||
#define BRANCH_IS_RETURN(n) ((n) >= 36) /* is any kind of return? */
|
||||
#define BRANCH_IS_CALLRETURN(n) (((n) & ~1) == 36) /* is a function return? */
|
||||
#define BRANCH_RET 36 /* non-windowed function return (RET or RET.N) */
|
||||
#define BRANCH_RETW 37 /* windowed function return (RETW or RETW.N) */
|
||||
#define BRANCH_IS_EIRETURN(n) ((n) >= 38) /* is an except/inter. return? */
|
||||
#define BRANCH_RFE 38 /* RFE or RFUE */
|
||||
#define BRANCH_RFDE 39 /* RFDE */
|
||||
#define BRANCH_RFWO 40 /* RFWO */
|
||||
#define BRANCH_RFWU 41 /* RFWU */
|
||||
#define BRANCH_RFI_2 42 /* RFI 2 */
|
||||
#define BRANCH_RFI_3 43 /* RFI 3 */
|
||||
#define BRANCH_RFI_4 44 /* RFI 4 */
|
||||
#define BRANCH_RFI_5 45 /* RFI 5 */
|
||||
#define BRANCH_RFI_6 46 /* RFI 6 */
|
||||
#define BRANCH_RFI_NMI 47 /* RFI NMILEVEL */
|
||||
#define BRANCH_RFI_DEBUG 48 /* RFI DEBUGLEVEL */
|
||||
#define BRANCH_RFME 49 /* RFME */
|
||||
#define BRANCH_COUNT 50 /* (number of defined BRANCH_xxx values) */
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
unsigned vaddr;
|
||||
unsigned vaddr2; /* for static vectors only (reloc vectors option) */
|
||||
int is_configured;
|
||||
} trax_vector_t;
|
||||
|
||||
|
||||
/*
|
||||
* This structure describes those portion of a Tensilica processor's
|
||||
* configuration that are useful for trace.
|
||||
*/
|
||||
typedef struct {
|
||||
char ** isa_dlls;
|
||||
char * core_name; /* (XPG core name, not necessarily same as XTENSA_CORE) */
|
||||
int big_endian; /* 0 = little-endian, 1 = big-endian */
|
||||
int has_loops; /* 1 = zero overhead loops configured */
|
||||
int has_autorefill; /* 1 = TLB autorefill (MMU) configured */
|
||||
unsigned max_instr_size; /* in bytes (eg. 3, 4, 8, ...) */
|
||||
unsigned int_level_max; /* number of interrupt levels configured (without NMI) */
|
||||
int debug_level; /* debug intlevel, 0 if debug not configured */
|
||||
int nmi_level; /* NMI intlevel, 0 if NMI not configured */
|
||||
unsigned targethw_min; /* min. targeted hardware version (XTENSA_HWVERSION_<rel>) */
|
||||
unsigned targethw_max; /* max. targeted hardware version (XTENSA_HWVERSION_<rel>) */
|
||||
int reloc_vectors; /* 0 = fixed vectors, 1 = relocatable vectors */
|
||||
int statvec_select; /* 0 = stat vec base 0, 1 = stat vec base 1 (SW default) */
|
||||
int vecbase_align; /* number of bits to align VECBASE (32 - bits in VECBASE) */
|
||||
unsigned statvec_base0; /* static vector base 0 */
|
||||
unsigned statvec_base1; /* static vector base 1 */
|
||||
unsigned vecbase_reset; /* reset value of VECBASE */
|
||||
trax_vector_t vectors[VEC_COUNT]; /* all vectors... */
|
||||
} trax_core_config_t;
|
||||
|
||||
|
||||
/* Globals: */
|
||||
//extern const char * const trax_vector_short_names[/*VEC_COUNT*/]; // nobody uses this one
|
||||
extern const char * const trax_vector_names[/*VEC_COUNT*/];
|
||||
|
||||
/* Prototypes: */
|
||||
extern int trax_read_params (trax_core_config_t *c, xtensa_params p);
|
||||
extern int trax_vector_from_address(trax_core_config_t *config, unsigned long vaddr, unsigned long *vecbases);
|
||||
|
||||
#endif /* TRAX_CORE_CONFIG_H */
|
||||
|
||||
Executable
+91
@@ -0,0 +1,91 @@
|
||||
/* This file contains functions that are hidden from the user. These are
|
||||
* protocol specific functions used to read and write TRAX registers
|
||||
* and the trace memory
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012-2013 Tensilica Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef _TRAX_PROTO_H
|
||||
#define _TRAX_PROTO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Function to read register
|
||||
*
|
||||
* regno : The register number to be read (not ERI addressed)
|
||||
* data : Location where the read value is kept
|
||||
*
|
||||
* returns : 0 if successful, -1 if unsuccessful
|
||||
*/
|
||||
int trax_read_register_eri (int regno, unsigned *data);
|
||||
|
||||
/* Function to write a value into a register
|
||||
*
|
||||
* regno : The register number to be written (not ERI addressed)
|
||||
* value : The value to be written at that register location
|
||||
*
|
||||
* returns : 0 if successful, -1 if unsuccessful
|
||||
*/
|
||||
int trax_write_register_eri (int regno, unsigned value);
|
||||
|
||||
/* Function to read memory
|
||||
*
|
||||
* address : Address of the TraceRAM memory, each location has a word
|
||||
* len : Amount of memory in bytes, to be read
|
||||
* data : buffer in which the read memory is stored
|
||||
* final_address: Next address to be read in the following call to this
|
||||
* function (trace save mechanism)
|
||||
*
|
||||
* returns : 0 if successful, -1 if unsuccessful
|
||||
*/
|
||||
int trax_read_memory_eri (unsigned address, int len, int *data,
|
||||
unsigned *final_address);
|
||||
|
||||
/* Function to write a value to the memory address
|
||||
*
|
||||
* address : Address of the TraceRAM memory
|
||||
* value : The value to be written inside that location
|
||||
*
|
||||
* returns : 0 if successful, -1 if unsuccessful
|
||||
*/
|
||||
int trax_write_memory_eri (int address, unsigned value);
|
||||
|
||||
/* Function to write to a subfield of the register.
|
||||
* Called by set and show parameter functions.
|
||||
*
|
||||
* regno : Register number
|
||||
* regmask : Mask in order to toggle appropriate bits
|
||||
* value : Value to be written in the masked location
|
||||
*
|
||||
* returns : 0 if successful, -1 if unsuccessful
|
||||
*/
|
||||
int trax_write_register_field_eri (int regno, unsigned regmask,
|
||||
unsigned value);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Executable
+63
@@ -0,0 +1,63 @@
|
||||
/* This file contains utility functions that can be used for polling TRAX
|
||||
* or executing higher level save functionality
|
||||
* It assumes that print subroutines and file I/O routines are available
|
||||
* on the system
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012-2013 Tensilica Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _TRAX_UTIL_H
|
||||
#define _TRAX_UTIL_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* User can use this function if he wants to generate a tracefile output.
|
||||
* Internally it calls trax_get_trace in a loop until it realizes that
|
||||
* the entire trace has been read.
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* filename : user specified output trace file name. If the file does not
|
||||
* exist, it would create the new file, else would append to it
|
||||
*
|
||||
* returns : 0 if successful, -1 if unsuccessful
|
||||
*/
|
||||
int trax_save (trax_context *context, char *filename);
|
||||
|
||||
/* Displays a brief machine readable status.
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* returns : 0 if successful, -1 if unsuccessful
|
||||
*/
|
||||
int trax_poll (trax_context *context);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Executable
+409
@@ -0,0 +1,409 @@
|
||||
/* Header file for TRAX control Library */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012-2013 Tensilica Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _TRAX_H
|
||||
#define _TRAX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define TRAX_STOP_HALT 0x0001
|
||||
#define TRAX_STOP_QUIET 0x0002
|
||||
|
||||
/* Flag values to indicate if the user wanted to reverse the pcstop
|
||||
* parameters */
|
||||
#define TRAX_PCSTOP_REVERSE 0x0001
|
||||
#define TRAX_PCSTOP_NO_REVERSE 0x0000
|
||||
|
||||
/* Indicating whether postsize should be in terms of bytes, instructions
|
||||
* or percentage of trace size captured */
|
||||
#define TRAX_POSTSIZE_BYTES 0x0000
|
||||
#define TRAX_POSTSIZE_INSTR 0x0001
|
||||
#define TRAX_POSTSIZE_PERCENT 0x0002
|
||||
|
||||
/* Size of the header inside the trace file */
|
||||
#define TRAX_HEADER_SIZE 256
|
||||
|
||||
/* Minimum size between start and end addresses */
|
||||
#define TRAX_MIN_TRACEMEM 64
|
||||
|
||||
/* For basic debugging */
|
||||
#define DEBUG 0
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#define ffs(i) __builtin_ffs(i)
|
||||
|
||||
/* Data structures */
|
||||
|
||||
/* Represents the context of the TRAX unit and the current TRAX session.
|
||||
* To be used by set and show function calls to set and show appropriate
|
||||
* parameters of appropriate TRAX unit.
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
int trax_version; /* TRAX PC version information */
|
||||
unsigned long trax_tram_size; /* If trace RAM is present,size of it */
|
||||
int hflags; /* Flags that can be used to debug,
|
||||
print info, etc. */
|
||||
int address_read_last; /* During saving of the trace, this
|
||||
indicates the address from which
|
||||
the current trace reading must
|
||||
resume */
|
||||
unsigned long bytes_read; /* bytes read uptil now */
|
||||
unsigned long total_memlen; /* Total bytes to be read based on the
|
||||
trace collected in the trace RAM */
|
||||
bool get_trace_started; /* indicates that the first chunk of
|
||||
bytes (which include the header) has
|
||||
been read */
|
||||
} trax_context;
|
||||
|
||||
|
||||
/* -----------------------TRAX Initialization ------------------------------*/
|
||||
|
||||
/* Initializing the trax context. Reads registers and sets values for version,
|
||||
* trace RAM size, total memory length, etc. Most of the other values are
|
||||
* initialized to their default case.
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
*
|
||||
* returns : 0 if successful, -1 if unsuccessful, -2 if ram_size if
|
||||
* incorrect
|
||||
*/
|
||||
int trax_context_init_eri (trax_context *context);
|
||||
|
||||
/* -----------------Starting/Stopping TRAX session -------------------------*/
|
||||
|
||||
/* Start tracing with current parameter setting. If tracing is already in
|
||||
* progress, an error is reported. Otherwise, tracing starts and any unsaved
|
||||
* contents of the TraceRAM is discarded
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* returns : 0 if successful, 1 if trace is already active,
|
||||
* -1 if unsuccessful
|
||||
*/
|
||||
int trax_start (trax_context *context);
|
||||
|
||||
/* This command initiates a stop trigger or halts a trace session based of the
|
||||
* value of the flag parameter passed. In case stop trigger is initiated, any
|
||||
* selected post-stop-trigger capture proceeds normally.
|
||||
* If trace capture was not in progress, or a stop was already triggered, the
|
||||
* return value indicates appropriately.
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* flags : To differentiate between stopping trace without any
|
||||
* post-size-trigger capture (trax_halt) or with that.
|
||||
* A zero value would stop the trace based on trigger and a
|
||||
* value of one would halt it
|
||||
*
|
||||
* returns : 0 if successful, 1 if already stopped, -1 if unsuccessful
|
||||
*/
|
||||
int trax_stop_halt (trax_context *context, int flags);
|
||||
|
||||
/* Resets the TRAX parameters to their default values which would internally
|
||||
* involve resetting the TRAX registers. To invoke another trace session or
|
||||
* reset the current tracing mechanism, this function needs to be called as
|
||||
* it resets parameters of the context that deal with tracing information
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
*
|
||||
* returns : 0 if successful, -1 if unsuccessful
|
||||
*/
|
||||
int trax_reset (trax_context *context);
|
||||
|
||||
/* ---------------Set/Get several TRAX parameters --------------------------*/
|
||||
|
||||
/* Sets the start address and end address (word aligned) of the trace in the
|
||||
* TraceRAM. Care must be taken to ensure that the difference between the
|
||||
* start and the end addresses is atleast TRAX_MIN_TRACEMEM bytes. If not,
|
||||
* the values are reset to default, which is 0 for startaddr and
|
||||
* traceRAM_words -1 for endaddr
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* startaddr : value to which the start address must be set. Can be
|
||||
* any value between 0 - (traceRAM_words - 1)
|
||||
* endaddr : value to which the end address must be set. Can be any value
|
||||
* between 0 - (traceRAM_words - 1)
|
||||
*
|
||||
* returns : 0 if successful, -1 if unsuccessful, -2 if the difference
|
||||
* between the start and end addresses is less than
|
||||
* TRAX_MIN_TRACEMEM bytes or if they are passed incorrect
|
||||
* values, -3 if memory shared option is not configured, in
|
||||
* which case, start and end addresses are set to default
|
||||
* values instead of those passed by the user
|
||||
*/
|
||||
int trax_set_ram_boundaries (trax_context *context, unsigned startaddr,
|
||||
unsigned endaddr);
|
||||
|
||||
/* Shows the start address and end address(word aligned) of the trace in the
|
||||
* TraceRAM. If incorrect, the startaddress and the endaddress values are
|
||||
* set to default, i.e. 0 for startaddr and traceRAM_words - 1 for endaddr
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* startaddr : pointer to value which will contain the start address
|
||||
* endaddr : pointer to value which will contain the end address
|
||||
*
|
||||
* returns : 0 if successful, -1 if unsuccessful
|
||||
*
|
||||
*/
|
||||
int trax_get_ram_boundaries (trax_context *context, unsigned *startaddr,
|
||||
unsigned *endaddr);
|
||||
|
||||
/* Selects stop trigger via cross-trigger input
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* value : 0 = off (reset value), 1 = on
|
||||
*
|
||||
* returns : 0 if successful, -1 if unsuccessful
|
||||
*/
|
||||
int trax_set_ctistop (trax_context *context, unsigned value);
|
||||
|
||||
/* Shows if stop-trigger via cross-trigger input is off or on
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* returns : 0 if off, 1 if on, -1 if unsuccessful
|
||||
*/
|
||||
int trax_get_ctistop (trax_context *context);
|
||||
|
||||
/* Selects stop trigger via processor-trigger input
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* value : 0 = off (reset value), 1 = on
|
||||
*
|
||||
* returns : 0 if successful, -1 if unsuccessful
|
||||
*/
|
||||
int trax_set_ptistop (trax_context *context, unsigned value);
|
||||
|
||||
/* Shows if stop trigger visa processor-trigger input is off or on
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* returns : 0 if off, 1 if on, -1 if unsuccessful
|
||||
*/
|
||||
int trax_get_ptistop (trax_context *context);
|
||||
|
||||
/* Reports cross trigger output state
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* returns : 0 if CTO bit is reset, 1 if CTO bit is set
|
||||
*/
|
||||
int trax_get_cto (trax_context *context);
|
||||
|
||||
/* Reports processor trigger output state
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* returns : 0 if PTO bit is reset, 1 if PTO bit is set
|
||||
*/
|
||||
int trax_get_pto (trax_context *context);
|
||||
|
||||
/* Selects condition that asserts cross trigger output
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* option : 0 = off(reset value)/1 = ontrig/2 = onhalt
|
||||
*
|
||||
* returns : 0 if successful, -1 if unsuccessful
|
||||
*/
|
||||
int trax_set_ctowhen (trax_context *context, int option);
|
||||
|
||||
/* Shows condition that asserted cross trigger output. It can be
|
||||
* any of: ontrig or onhalt or even off
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
*
|
||||
* returns : 0 if off, 1 if ontrig, 2 if onhalt, -1 if unsuccessful
|
||||
*/
|
||||
int trax_get_ctowhen (trax_context *context);
|
||||
|
||||
/* Selects condition that asserts processor trigger output
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* option : 0 = off(reset value)/1 = ontrig/2 = onhalt
|
||||
*
|
||||
* returns : 0 if successful, -1 if unsuccessful
|
||||
*/
|
||||
int trax_set_ptowhen (trax_context *context, int option);
|
||||
|
||||
|
||||
/* Shows condition that asserted processor trigger output. It can be
|
||||
* any of: ontrig or onhalt or even off
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* returns : 0 if off, 1 if ontrig, 2 if onhalt, -1 if unsuccessful
|
||||
*/
|
||||
int trax_get_ptowhen (trax_context *context);
|
||||
|
||||
/* Selects the trace synchronization message period.
|
||||
* If ATEN enabled, we cannot allow syncper to be off, set it to reset value.
|
||||
* Also, if no trace RAM, and ATEN enabled, set syncper to be reset value
|
||||
* i.e. 256. A value of 1 i.e. on indicates that internally the message
|
||||
* frequency is set to an optimal value. This option should be preferred
|
||||
* if the user is not sure what message frequency option to set for the
|
||||
* trace session.
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* option : 0 = off, 1 = on, -1 = auto, 8, 16, 32, 64, 128,
|
||||
* 256 (reset value)
|
||||
*
|
||||
* returns : 0 if successful, -1 if unsuccessful, -2 if incorrect
|
||||
* arguments
|
||||
*/
|
||||
int trax_set_syncper (trax_context *context, int option);
|
||||
|
||||
/* Shows trace synchronization message period. Can be one of:
|
||||
* off, on, auto, 8, 16, 32, 64, 128, 256 (reset value)
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* returns : value of sync period, 0 if off, -1 if unsuccessful
|
||||
*/
|
||||
int trax_get_syncper (trax_context *context);
|
||||
|
||||
/* Selects stop trigger via PC match. Specifies the address or
|
||||
* address range to match against program counter. Trace stops when the
|
||||
* processor executes an instruction matching the specified address
|
||||
* or range.
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* index : indicates the number of stop trigger (currently there is
|
||||
* only one i.e. index = 0)
|
||||
* startaddress : start range of the address at which the stop trigger
|
||||
* should be activated
|
||||
* enaddress : end range of the address at which the stop trigger should
|
||||
* be activated
|
||||
* flags : If non-zero, this inverts the range. i.e. trace stops
|
||||
* when the processor executes an instruction that does not
|
||||
* match the specified address or range
|
||||
*
|
||||
* returns : 0 if successful, -1 if unsuccessful, -2 if incorrect
|
||||
* arguments (unaligned)
|
||||
*
|
||||
* Note : For the current version of TRAX library, the endaddress and
|
||||
* startaddress can differ by at most 31 bytes and the total
|
||||
* range i.e. (endaddress - startaddress + 1) has to be a power
|
||||
* of two
|
||||
*/
|
||||
int trax_set_pcstop (trax_context *context, int index, unsigned long startaddress,
|
||||
unsigned long endaddress, int flags);
|
||||
|
||||
/* Shows the stop trigger via PC match
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* index : container of information about the number of stop triggers
|
||||
* startaddress : container of start range of stop trigger
|
||||
* endaddress : container of end range of stop trigger
|
||||
* flags : container of information whcih indicates whether the
|
||||
* pc stop range is inverted or not.
|
||||
*
|
||||
* returns : 0 if successful, -1 if unsuccessful
|
||||
*/
|
||||
int trax_get_pcstop (trax_context *context, int *index,
|
||||
unsigned long *startaddress,
|
||||
unsigned long *endaddress, int *flags);
|
||||
|
||||
/* This function is used to set the amount of trace to be captured past
|
||||
* the stop trigger.
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* count_unit : contains the count of units (instructions or bytes) to be
|
||||
* captured post trigger. If 0, it implies that this is off
|
||||
* unit : unit of measuring the count. 0 is bytes, 1 is instructions
|
||||
* 2 is percentage of trace
|
||||
*
|
||||
* returns : 0 if successful, -1 if unsuccessful, -2 if incorrect
|
||||
* arguments
|
||||
*
|
||||
*/
|
||||
int trax_set_postsize (trax_context *context, int count_unit, int unit);
|
||||
|
||||
/* This function shows the amount of TraceRAM in terms of the number of
|
||||
* instructions or bytes, captured post the stop trigger
|
||||
*
|
||||
* context : pointer to structure which contains information about the
|
||||
* current TRAX session
|
||||
* count_unit : will contain the count of units(instructions or bytes) post
|
||||
* trigger
|
||||
* unit : will contain information about the events that are counted
|
||||
* 0 implies that the traceRAM words consumed are counted and
|
||||
* 1 implies that the target processor instructions executed and
|
||||
* excpetions/interrupts taken are counted
|
||||
*
|
||||
* returns : 0 if postsize was got successfully, -1 if unsuccessful
|
||||
*/
|
||||
int trax_get_postsize (trax_context *context, int *count_unit, int *unit);
|
||||
|
||||
/* -------------------------- TRAX save routines ---------------------------*/
|
||||
|
||||
/* This function should be called by the user to return a chunk of
|
||||
* bytes in buf. It can be a lower layer function of save, or can be
|
||||
* called by the user explicitly. If bytes_actually_read contains a 0
|
||||
* after a call to this function has been made, it implies that the entire
|
||||
* trace has been read successfully.
|
||||
*
|
||||
* context : pointer to structure which contains information about
|
||||
* the current TRAX session
|
||||
* buf : Buffer that is allocated by the user, all the trace
|
||||
* data read would be put in this buffer, which can then
|
||||
* be used to generate a tracefile.
|
||||
* The first TRAX_HEADER_SIZE of the buffer will always
|
||||
* contain the header information.
|
||||
* bytes_to_be_read : Indicates the bytes the user wants to read. The first
|
||||
* invocation would need this parameter to be
|
||||
* TRAX_HEADER_SIZE at least.
|
||||
*
|
||||
* returns : bytes actually read during the call to this function.
|
||||
* 0 implies that all the bytes in the trace have been
|
||||
* read, -1 if unsuccessful read/write of
|
||||
* registers or memory, -2 if trace was active while
|
||||
* this function was called, -3 if user enters
|
||||
* bytes_to_be_read < TRAX_HEADER_SIZE in the first
|
||||
* pass
|
||||
*/
|
||||
int trax_get_trace (trax_context *context, void *buf,
|
||||
int bytes_to_be_read);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TRAX_H */
|
||||
Executable
+62
@@ -0,0 +1,62 @@
|
||||
/* TRAX file header definition.
|
||||
|
||||
Copyright (c) 2007-2012 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
|
||||
#define TRAX_FHEAD_MAGIC "TRAXdmp"
|
||||
#define TRAX_FHEAD_VERSION 1
|
||||
|
||||
/* Header flags: */
|
||||
#define TRAX_FHEADF_OCD_ENABLED 0x00000001 /* set if OCD was enabled while capturing trace */
|
||||
#define TRAX_FHEADF_TESTDUMP 0x00000002 /* set if is a test file
|
||||
(from 'memsave' instead of 'save') */
|
||||
#define TRAX_FHEADF_OCD_ENABLED_WHILE_EXIT 0x00000004 /* set if OCD was enabled while capturing trace and
|
||||
we were exiting the OCD mode */
|
||||
|
||||
/* Header at the start of a TRAX dump file. */
|
||||
typedef struct {
|
||||
char magic[8]; /* 00: "TRAXdmp\0" (TRAX_FHEAD_MAGIC) */
|
||||
char endianness; /* 08: 0=little-endian, 1=big-endian */
|
||||
char version; /* 09: TRAX_FHEAD_VERSION */
|
||||
char reserved0[2]; /* 0A: ... */
|
||||
unsigned filesize; /* 0C: size of the trace file, including this header */
|
||||
unsigned trace_ofs; /* 10: start of trace output, byte offset from start of header */
|
||||
unsigned trace_size; /* 14: size of trace output in bytes */
|
||||
unsigned dumptime; /* 18: date/time of capture save (secs since 1970-01-01), 0 if unknown */
|
||||
unsigned flags; /* 1C: misc flags (TRAX_FHEAD_F_xxx) */
|
||||
char username[16]; /* 20: user doing the capture/save (up to 15 chars) */
|
||||
char toolver[24]; /* 30: tool + version used for capture/save (up to 23 chars) */
|
||||
char reserved2[40]; /* 48: (reserved - could be hostname used for dump (up to 39 chars)) */
|
||||
unsigned configid[2]; /* 70: processor ConfigID values, 0 if unknown */
|
||||
unsigned ts_freq; /* 78: timestamp frequency, 0 if not specified */
|
||||
unsigned reserved3; /* 7C: (reserved) */
|
||||
unsigned id; /* 80: TRAX registers at time of save (0 if not read) */
|
||||
unsigned control;
|
||||
unsigned status;
|
||||
unsigned reserved4; /* Data register (should not be read) */
|
||||
unsigned address;
|
||||
unsigned trigger;
|
||||
unsigned match;
|
||||
unsigned delay;
|
||||
unsigned trax_regs[24]; /*100: (total size) -- dummy allocation (FIXME) */
|
||||
} trax_file_header;
|
||||
|
||||
Executable
+199
@@ -0,0 +1,199 @@
|
||||
/* TRAX register definitions
|
||||
|
||||
Copyright (c) 2006-2012 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef _TRAX_REGISTERS_H_
|
||||
#define _TRAX_REGISTERS_H_
|
||||
|
||||
#define SHOW 1
|
||||
#define HIDE 0
|
||||
|
||||
#define RO 0
|
||||
#define RW 1
|
||||
|
||||
/* TRAX Register Numbers (from possible range of 0..127) */
|
||||
#if 0
|
||||
#define TRAXREG_ID 0
|
||||
#define TRAXREG_CONTROL 1
|
||||
#define TRAXREG_STATUS 2
|
||||
#define TRAXREG_DATA 3
|
||||
#define TRAXREG_ADDRESS 4
|
||||
#define TRAXREG_TRIGGER 5
|
||||
#define TRAXREG_MATCH 6
|
||||
#define TRAXREG_DELAY 7
|
||||
#define TRAXREG_STARTADDR 8
|
||||
#define TRAXREG_ENDADDR 9
|
||||
/* Internal use only (unpublished): */
|
||||
#define TRAXREG_P4CHANGE 16
|
||||
#define TRAXREG_P4REV 17
|
||||
#define TRAXREG_P4DATE 18
|
||||
#define TRAXREG_P4TIME 19
|
||||
#define TRAXREG_PDSTATUS 20
|
||||
#define TRAXREG_PDDATA 21
|
||||
#define TRAXREG_STOP_PC 22
|
||||
#define TRAXREG_STOP_ICNT 23
|
||||
#define TRAXREG_MSG_STATUS 24
|
||||
#define TRAXREG_FSM_STATUS 25
|
||||
#define TRAXREG_IB_STATUS 26
|
||||
#define TRAXREG_MAX 27
|
||||
#define TRAXREG_ITCTRL 96
|
||||
#endif
|
||||
/* The registers above match the NAR addresses. So, their values are used for NAR access */
|
||||
|
||||
/* TRAX Register Fields */
|
||||
|
||||
/* TRAX ID register fields: */
|
||||
#define TRAX_ID_PRODNO 0xf0000000 /* product number (0=TRAX) */
|
||||
#define TRAX_ID_PRODOPT 0x0f000000 /* product options */
|
||||
#define TRAX_ID_MIW64 0x08000000 /* opt: instruction width */
|
||||
#define TRAX_ID_AMTRAX 0x04000000 /* opt: collection of options,
|
||||
internal (VER_2_0 or later)*/
|
||||
#define TRAX_ID_MAJVER(id) (((id) >> 20) & 0x0f)
|
||||
#define TRAX_ID_MINVER(id) (((id) >> 17) & 0x07)
|
||||
#define TRAX_ID_VER(id) ((TRAX_ID_MAJVER(id)<<4)|TRAX_ID_MINVER(id))
|
||||
#define TRAX_ID_STDCFG 0x00010000 /* standard config */
|
||||
#define TRAX_ID_CFGID 0x0000ffff /* TRAX configuration ID */
|
||||
#define TRAX_ID_MEMSHARED 0x00001000 /* Memshared option in TRAX */
|
||||
#define TRAX_ID_FROM_VER(ver) ((((ver) & 0xf0) << 16) | (((ver) & 0x7) << 17))
|
||||
/* Other TRAX ID register macros: */
|
||||
/* TRAX versions of interest (TRAX_ID_VER(), ie. MAJVER*16 + MINVER): */
|
||||
#define TRAX_VER_1_0 0x10 /* RA */
|
||||
#define TRAX_VER_1_1 0x11 /* RB thru RC-2010.1 */
|
||||
#define TRAX_VER_2_0 0x20 /* RC-2010.2, RD-2010.0,
|
||||
RD-2011.1 */
|
||||
#define TRAX_VER_2_1 0x21 /* RC-2011.3 / RD-2011.2 and
|
||||
later */
|
||||
#define TRAX_VER_3_0 0x30 /* RE-2012.0 */
|
||||
#define TRAX_VER_3_1 0x31 /* RE-2012.1 */
|
||||
#define TRAX_VER_HUAWEI_3 TRAX_VER_3_0 /* For Huawei, PRs: 25223, 25224
|
||||
, 24880 */
|
||||
|
||||
|
||||
/* TRAX version 1.0 requires a couple software workarounds: */
|
||||
#define TRAX_ID_1_0_ERRATUM(id) (TRAX_ID_VER(id) == TRAX_VER_1_0)
|
||||
/* TRAX version 2.0 requires software workaround for PR 22161: */
|
||||
#define TRAX_ID_MEMSZ_ERRATUM(id) (TRAX_ID_VER(id) == TRAX_VER_2_0)
|
||||
|
||||
/* TRAX Control register fields: */
|
||||
#define TRAX_CONTROL_TREN 0x00000001
|
||||
#define TRAX_CONTROL_TRSTP 0x00000002
|
||||
#define TRAX_CONTROL_PCMEN 0x00000004
|
||||
#define TRAX_CONTROL_PTIEN 0x00000010
|
||||
#define TRAX_CONTROL_CTIEN 0x00000020
|
||||
#define TRAX_CONTROL_TMEN 0x00000080 /* 2.0+ */
|
||||
#define TRAX_CONTROL_CNTU 0x00000200
|
||||
#define TRAX_CONTROL_BIEN 0x00000400
|
||||
#define TRAX_CONTROL_BOEN 0x00000800
|
||||
#define TRAX_CONTROL_TSEN 0x00000800
|
||||
#define TRAX_CONTROL_SMPER 0x00007000
|
||||
#define TRAX_CONTROL_SMPER_SHIFT 12
|
||||
#define TRAX_CONTROL_PTOWT 0x00010000
|
||||
#define TRAX_CONTROL_CTOWT 0x00020000
|
||||
#define TRAX_CONTROL_PTOWS 0x00100000
|
||||
#define TRAX_CONTROL_CTOWS 0x00200000
|
||||
#define TRAX_CONTROL_ATID 0x7F000000 /* 2.0+, amtrax */
|
||||
#define TRAX_CONTROL_ATID_SHIFT 24
|
||||
#define TRAX_CONTROL_ATEN 0x80000000 /* 2.0+, amtrax */
|
||||
|
||||
#define TRAX_CONTROL_PTOWS_ER 0x00020000 /* For 3.0 */
|
||||
#define TRAX_CONTROL_CTOWT_ER 0x00100000 /* For 3.0 */
|
||||
|
||||
#define TRAX_CONTROL_ITCTO 0x00400000 /* For 3.0 */
|
||||
#define TRAX_CONTROL_ITCTIA 0x00800000 /* For 3.0 */
|
||||
#define TRAX_CONTROL_ITATV 0x01000000 /* For 3.0 */
|
||||
|
||||
|
||||
/* TRAX Status register fields: */
|
||||
#define TRAX_STATUS_TRACT 0x00000001
|
||||
#define TRAX_STATUS_TRIG 0x00000002
|
||||
#define TRAX_STATUS_PCMTG 0x00000004
|
||||
#define TRAX_STATUS_BUSY 0x00000008 /* ER ??? */
|
||||
#define TRAX_STATUS_PTITG 0x00000010
|
||||
#define TRAX_STATUS_CTITG 0x00000020
|
||||
#define TRAX_STATUS_MEMSZ 0x00001F00
|
||||
#define TRAX_STATUS_MEMSZ_SHIFT 8
|
||||
#define TRAX_STATUS_PTO 0x00010000
|
||||
#define TRAX_STATUS_CTO 0x00020000
|
||||
|
||||
#define TRAX_STATUS_ITCTOA 0x00400000 /* For 3.0 */
|
||||
#define TRAX_STATUS_ITCTI 0x00800000 /* For 3.0 */
|
||||
#define TRAX_STATUS_ITATR 0x01000000 /* For 3.0 */
|
||||
|
||||
|
||||
/* TRAX Address register fields: */
|
||||
#define TRAX_ADDRESS_TWSAT 0x80000000
|
||||
#define TRAX_ADDRESS_TWSAT_SHIFT 31
|
||||
#define TRAX_ADDRESS_TOTALMASK 0x00FFFFFF
|
||||
// !!! VUakiVU. added for new TRAX:
|
||||
#define TRAX_ADDRESS_WRAPCNT 0x7FE00000 /* version ???... */
|
||||
#define TRAX_ADDRESS_WRAP_SHIFT 21
|
||||
|
||||
/* TRAX PCMatch register fields: */
|
||||
#define TRAX_PCMATCH_PCML 0x0000001F
|
||||
#define TRAX_PCMATCH_PCML_SHIFT 0
|
||||
#define TRAX_PCMATCH_PCMS 0x80000000
|
||||
|
||||
/* Compute trace ram buffer size (in bytes) from status register: */
|
||||
#define TRAX_MEM_SIZE(status) (1L << (((status) & TRAX_STATUS_MEMSZ) >> TRAX_STATUS_MEMSZ_SHIFT))
|
||||
|
||||
#if 0
|
||||
/* Describes a field within a register: */
|
||||
typedef struct {
|
||||
const char* name;
|
||||
// unsigned width;
|
||||
// unsigned shift;
|
||||
char width;
|
||||
char shift;
|
||||
char visible; /* 0 = internal use only, 1 = shown */
|
||||
char reserved;
|
||||
} trax_regfield_t;
|
||||
#endif
|
||||
|
||||
/* Describes a TRAX register: */
|
||||
typedef struct {
|
||||
const char* name;
|
||||
unsigned id;
|
||||
char width;
|
||||
char visible;
|
||||
char writable;
|
||||
char reserved;
|
||||
//const trax_regfield_t * fieldset;
|
||||
} trax_regdef_t;
|
||||
|
||||
|
||||
extern const trax_regdef_t trax_reglist[];
|
||||
extern const signed char trax_readable_regs[];
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Prototypes: */
|
||||
extern int trax_find_reg(char * regname, char **errmsg);
|
||||
extern const char * trax_regname(int regno);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TRAX_REGISTERS_H_ */
|
||||
|
||||
+69
@@ -0,0 +1,69 @@
|
||||
/*******************************************************************************
|
||||
Copyright (c) 2006-2013 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
These coded instructions, statements, and computer programs are the
|
||||
copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
third parties in any manner, medium, or form, in whole or in part, without
|
||||
the prior written consent of Tensilica Inc.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
uart-16550-board.h Board-specific UART info on these boards:
|
||||
Avnet AV60 (XT-AV60)
|
||||
Avnet AV110 (XT-AV110)
|
||||
Avnet AV200 (XT-AV200)
|
||||
Xilinx ML605 (XT-ML605)
|
||||
Xilinx KC705 (XT-KC705)
|
||||
|
||||
Interface between board-independent driver and board-specific header.
|
||||
|
||||
This is used by a board-independent 16550 UART driver to obtain board-specific
|
||||
information about 1 instance of the 16550 UART on the board, such as the device
|
||||
register base address and spacing (a function of how the address lines are
|
||||
connected on the board) and the frequency of the UART clock. The driver does
|
||||
not refer directly to the board-specific header, which therefore is not
|
||||
constrained to use macro names consistent with other boards.
|
||||
|
||||
!! Must not contain any board-specific macro names (only UART specific). !!
|
||||
|
||||
Included at compile-time via an include path specific to the board.
|
||||
|
||||
These boards contain a single 16550 UART implemented on the FPGA.
|
||||
Their clock frequency comes from the board's core clock (not its own crystal)
|
||||
which depends on the core config so is not a constant. Obtained via the BSP.
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _UART_16550_BOARD_H
|
||||
#define _UART_16550_BOARD_H
|
||||
|
||||
#include <xtensa/xtbsp.h> /* BSP API */
|
||||
#include <xtensa/board.h> /* Board info */
|
||||
|
||||
|
||||
/* Base address of UART's registers. */
|
||||
#ifdef UART16550_VADDR
|
||||
#define UART_16550_REGBASE UART16550_VADDR
|
||||
#endif
|
||||
|
||||
/*
|
||||
The UART's registers are connected at word addresses on these boards.
|
||||
Each byte-wide register appears as the least-significant-byte (LSB) of the
|
||||
word regardless of the endianness of the processor.
|
||||
*/
|
||||
#define UART_16550_REGSPACING 4
|
||||
typedef unsigned uart16550_reg_t;
|
||||
|
||||
/* UART Clock Frequency in Hz */
|
||||
#define UART_16550_XTAL_FREQ xtbsp_clock_freq_hz()
|
||||
|
||||
/* UART Interrupt Number */
|
||||
#ifdef UART16550_INTNUM
|
||||
#define UART_16550_INTNUM UART16550_INTNUM
|
||||
#endif
|
||||
|
||||
|
||||
/* Include generic information shared by all boards that use this device. */
|
||||
#include <xtensa/uart-16550.h>
|
||||
|
||||
#endif /* _UART_16550_BOARD_H */
|
||||
|
||||
Executable
+152
@@ -0,0 +1,152 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Copyright (c) 2006-2007 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
uart-16550.h Generic definitions for National Semiconductor 16550 UART
|
||||
|
||||
This is used by board-support-packages with one or more 16550 compatible UARTs.
|
||||
A BSP provides a base address for each instance of a 16550 UART on the board.
|
||||
|
||||
Note that a 16552 DUART (Dual UART) is simply two instances of a 16550 UART.
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _UART_16550_H_
|
||||
#define _UART_16550_H_
|
||||
|
||||
/* C interface to UART registers. */
|
||||
struct uart_dev_s {
|
||||
union {
|
||||
uart16550_reg_t rxb; /* DLAB=0: receive buffer, read-only */
|
||||
uart16550_reg_t txb; /* DLAB=0: transmit buffer, write-only */
|
||||
uart16550_reg_t dll; /* DLAB=1: divisor, LS byte latch */
|
||||
} w0;
|
||||
union {
|
||||
uart16550_reg_t ier; /* DLAB=0: interrupt-enable register */
|
||||
uart16550_reg_t dlm; /* DLAB=1: divisor, MS byte latch */
|
||||
} w1;
|
||||
|
||||
union {
|
||||
uart16550_reg_t isr; /* DLAB=0: interrupt status register, read-only */
|
||||
uart16550_reg_t fcr; /* DLAB=0: FIFO control register, write-only */
|
||||
uart16550_reg_t afr; /* DLAB=1: alternate function register */
|
||||
} w2;
|
||||
|
||||
uart16550_reg_t lcr; /* line control-register, write-only */
|
||||
uart16550_reg_t mcr; /* modem control-regsiter, write-only */
|
||||
uart16550_reg_t lsr; /* line status register, read-only */
|
||||
uart16550_reg_t msr; /* modem status register, read-only */
|
||||
uart16550_reg_t scr; /* scratch regsiter, read/write */
|
||||
};
|
||||
|
||||
|
||||
#define _RXB(u) ((u)->w0.rxb)
|
||||
#define _TXB(u) ((u)->w0.txb)
|
||||
#define _DLL(u) ((u)->w0.dll)
|
||||
#define _IER(u) ((u)->w1.ier)
|
||||
#define _DLM(u) ((u)->w1.dlm)
|
||||
#define _ISR(u) ((u)->w2.isr)
|
||||
#define _FCR(u) ((u)->w2.fcr)
|
||||
#define _AFR(u) ((u)->w2.afr)
|
||||
#define _LCR(u) ((u)->lcr)
|
||||
#define _MCR(u) ((u)->mcr)
|
||||
#define _LSR(u) ((u)->lsr)
|
||||
#define _MSR(u) ((u)->msr)
|
||||
#define _SCR(u) ((u)->scr)
|
||||
|
||||
typedef volatile struct uart_dev_s uart_dev_t;
|
||||
|
||||
/* IER bits */
|
||||
#define RCVR_DATA_REG_INTENABLE 0x01
|
||||
#define XMIT_HOLD_REG_INTENABLE 0x02
|
||||
#define RCVR_STATUS_INTENABLE 0x04
|
||||
#define MODEM_STATUS_INTENABLE 0x08
|
||||
|
||||
/* FCR bits */
|
||||
#define _FIFO_ENABLE 0x01
|
||||
#define RCVR_FIFO_RESET 0x02
|
||||
#define XMIT_FIFO_RESET 0x04
|
||||
#define DMA_MODE_SELECT 0x08
|
||||
#define RCVR_TRIGGER_LSB 0x40
|
||||
#define RCVR_TRIGGER_MSB 0x80
|
||||
|
||||
/* AFR bits */
|
||||
#define AFR_CONC_WRITE 0x01
|
||||
#define AFR_BAUDOUT_SEL 0x02
|
||||
#define AFR_RXRDY_SEL 0x04
|
||||
|
||||
/* ISR bits */
|
||||
#define INT_STATUS(r) ((r)&1)
|
||||
#define INT_PRIORITY(r) (((r)>>1)&0x7)
|
||||
|
||||
/* LCR bits */
|
||||
#define WORD_LENGTH(n) (((n)-5)&0x3)
|
||||
#define STOP_BIT_ENABLE 0x04
|
||||
#define PARITY_ENABLE 0x08
|
||||
#define EVEN_PARITY 0x10
|
||||
#define FORCE_PARITY 0x20
|
||||
#define XMIT_BREAK 0x40
|
||||
#define DLAB_ENABLE 0x80
|
||||
|
||||
/* MCR bits */
|
||||
#define _DTR 0x01
|
||||
#define _RTS 0x02
|
||||
#define _OP1 0x04
|
||||
#define _OP2 0x08
|
||||
#define LOOP_BACK 0x10
|
||||
|
||||
/* LSR Bits */
|
||||
#define RCVR_DATA_READY 0x01
|
||||
#define OVERRUN_ERROR 0x02
|
||||
#define PARITY_ERROR 0x04
|
||||
#define FRAMING_ERROR 0x08
|
||||
#define BREAK_INTERRUPT 0x10
|
||||
#define XMIT_HOLD_EMPTY 0x20
|
||||
#define XMIT_EMPTY 0x40
|
||||
#define FIFO_ERROR 0x80
|
||||
#define RCVR_READY(u) (_LSR(u)&RCVR_DATA_READY)
|
||||
#define XMIT_READY(u) (_LSR(u)&XMIT_HOLD_EMPTY)
|
||||
|
||||
/* MSR bits */
|
||||
#define _RDR 0x01
|
||||
#define DELTA_DSR 0x02
|
||||
#define DELTA_RI 0x04
|
||||
#define DELTA_CD 0x08
|
||||
#define _CTS 0x10
|
||||
#define _DSR 0x20
|
||||
#define _RI 0x40
|
||||
#define _CD 0x80
|
||||
|
||||
|
||||
/* Compute 16-bit divisor for baudrate generator, with rounding: */
|
||||
#define UART_DIVISOR(clock,baud) (((clock)/16 + (baud)/2)/(baud))
|
||||
|
||||
/* Prototypes of driver functions */
|
||||
extern void uart16550_init( uart_dev_t *u, unsigned baud, unsigned ndata,
|
||||
unsigned parity, unsigned nstop );
|
||||
extern void uart16550_out( uart_dev_t *u, char c );
|
||||
extern char uart16550_in( uart_dev_t *u );
|
||||
extern unsigned uart16550_measure_sys_clk( uart_dev_t *u );
|
||||
|
||||
#endif /* _UART_16550_H_ */
|
||||
Executable
+276
@@ -0,0 +1,276 @@
|
||||
/* Customer ID=11656; Build=0x5f626; Copyright (c) 2005-2014 by Cadence Design Systems, Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of
|
||||
* Cadence Design Systems, Inc. They may not be modified, copied, reproduced,
|
||||
* distributed, or disclosed to third parties in any manner, medium, or form,
|
||||
* in whole or in part, without the prior written consent of Cadence Design
|
||||
* Systems Inc.
|
||||
*/
|
||||
#ifndef __UDMA_H__
|
||||
#define __UDMA_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Size of the uDMA descriptor */
|
||||
#define UDMA_DESC_STRUCT_SIZE 32
|
||||
|
||||
/* Request attribute is a bit vector passed to the udma functions - udma_copy,
|
||||
* udma_2d_copy, udma_add_descs.
|
||||
* Bit 0 : 1 - trigger an interrupt when done, else do nothing
|
||||
* Bit 1 : 0 - retry the failed request; abort after programmer specified
|
||||
* number of retries. Defaults to abort with no retries.
|
||||
* 1 - abort the failed request (after retries) and all pending requests
|
||||
*/
|
||||
#define UDMA_DONE_INTERRUPT 0x1
|
||||
#define UDMA_ERROR_ABORT 0x0
|
||||
#define UDMA_ERROR_ABORT_ALL 0x2
|
||||
|
||||
/* Enum representing various udma error conditions, udma status, and
|
||||
* return values
|
||||
*/
|
||||
typedef enum {
|
||||
UDMA_OK = 0,
|
||||
UDMA_ERROR_QUEUE_FULL = 1,
|
||||
UDMA_ERROR_BAD_DESC = 2,
|
||||
UDMA_ERROR_DRAM_CROSSING = 3,
|
||||
UDMA_ERROR_PIF_ADDR_BUS = 4,
|
||||
UDMA_ERROR_PIF_DATA_BUS = 5,
|
||||
UDMA_REQ_PENDING = 6,
|
||||
UDMA_REQ_DONE = 7,
|
||||
UDMA_ERROR_BAD_REQUEST = 8,
|
||||
UDMA_ERROR_INVALID_ARG = 11,
|
||||
UDMA_ERROR_INIT = 12,
|
||||
UDMA_ERROR_INTERNAL = -1
|
||||
} udma_status_t;
|
||||
|
||||
#ifndef __UDMA_INTERNAL_H__
|
||||
/* Opaque structure describing a uDMA descriptor */
|
||||
struct udma_desc_struct {
|
||||
char _[UDMA_DESC_STRUCT_SIZE];
|
||||
} __attribute__ ((aligned (UDMA_DESC_STRUCT_SIZE)));
|
||||
#endif
|
||||
|
||||
typedef struct udma_desc_struct udma_desc_t;
|
||||
|
||||
/* Initialize the udma control structure, the uDMA registers with
|
||||
* the descriptor queue addresses, and the uDMA sync and error interrupt
|
||||
* handler. This function needs to be invoked prior to using the uDMA.
|
||||
*
|
||||
* xmp_udma_sync_intr : Processor interrupt number to flag udma done
|
||||
* xmp_udma_error_intr : Processor interrupt number to flag udma error
|
||||
*
|
||||
* Returns UDMA_ERROR_INIT if there was an error during initialization else
|
||||
* returns UDMA_OK.
|
||||
*/
|
||||
extern udma_status_t
|
||||
udma_init(uint32_t xmp_udma_sync_intr, uint32_t xmp_udma_error_intr);
|
||||
|
||||
/* Performs a copy of a linear block of size bytes from the src
|
||||
* to the dest address. If the call returns UDMA_OK, status is set to
|
||||
* UDMA_REQ_PENDING or UDMA_REQ_DONE. If there is a dma error, the error code,
|
||||
* which could be one of UDMA_ERROR_BAD_DESC, UDMA_ERROR_DRAM_CROSSING,
|
||||
* UDMA_ERROR_PIF_ADDR_BUS, UDMA_ERROR_PIF_DATA_BUS is returned in the status.
|
||||
* Status is set to UDMA_REQ_DONE if the dma completes normally.
|
||||
* On completion, the callback function is invoked with the callback_data
|
||||
* and status as parameters. Note, the callback is always invoked even if
|
||||
* there is a dma error.
|
||||
*
|
||||
* src : src address of the copy
|
||||
* dest : dest address of the copy
|
||||
* size : number of bytes to copy
|
||||
* callback_data : optional data to be passed to callback_func
|
||||
* callback_func : optional callback after copy is done
|
||||
* request_attr : attribute defining how to process this request
|
||||
* (see description of the request attribute in top of udma.h)
|
||||
* status : track status of the copy; this gets also passed
|
||||
* as the second argument to the callback_func
|
||||
*
|
||||
* Returns UDMA_ERROR_QUEUE_FULL if no more requests can be added, else
|
||||
* returns UDMA_OK.
|
||||
*/
|
||||
extern udma_status_t
|
||||
udma_copy(void *dest,
|
||||
void *src,
|
||||
size_t size,
|
||||
void *callback_data,
|
||||
void (*callback_func)(void *, udma_status_t *status),
|
||||
uint32_t request_attr,
|
||||
udma_status_t *status);
|
||||
|
||||
/* Performs a copy of a 2D block of data from the src to the dest
|
||||
* address. If the call returns UDMA_OK, status is set to UDMA_REQ_PENDING or
|
||||
* UDMA_REQ_DONE. If there is a dma error, the error code,
|
||||
* which could be one of UDMA_ERROR_BAD_DESC, UDMA_ERROR_DRAM_CROSSING,
|
||||
* UDMA_ERROR_PIF_ADDR_BUS, UDMA_ERROR_PIF_DATA_BUS is returned in the status.
|
||||
* Status is set to UDMA_REQ_DONE if the dma completes normally.
|
||||
* On completion, the callback function is invoked with the callback_data
|
||||
* and status as parameters. Note, the callback is always invoked even if
|
||||
* there is a dma error.
|
||||
*
|
||||
* src : src address of the copy
|
||||
* dest : dest address of the copy
|
||||
* row_size : number of bytes per row to copy
|
||||
* num_rows : number of rows to copy
|
||||
* src_pitch : src pitch
|
||||
* dest_pitch : dest pitch
|
||||
* callback_data : optional data to be passed to callback_func
|
||||
* callback_func : optional callback after copy is done
|
||||
* request_attr : attribute defining how to process this request
|
||||
* (see description of the request attribute in top of udma.h)
|
||||
* status : track status of the copy; this gets also passed
|
||||
* as the second argument to the callback_func
|
||||
*
|
||||
* Returns UDMA_ERROR_QUEUE_FULL if no more requests can be added, else
|
||||
* returns UDMA_OK.
|
||||
*/
|
||||
extern udma_status_t
|
||||
udma_2d_copy(void *dest,
|
||||
void *src,
|
||||
size_t row_size,
|
||||
uint32_t num_rows,
|
||||
uint32_t src_pitch,
|
||||
uint32_t dest_pitch,
|
||||
void *callback_data,
|
||||
void (*callback_func)(void *, udma_status_t *status),
|
||||
uint32_t request_attr,
|
||||
udma_status_t *status);
|
||||
|
||||
/* Process requests that are done. Any callbacks associated
|
||||
* with the completed requests gets invoked. If there are any errors,
|
||||
* the error request is (and any pending request based on the request attribute)
|
||||
* cancelled and the error code is returned in the status associated with
|
||||
* all such cancelled requests. Callbacks associated with the cancelled
|
||||
* requests are also invoked. If all requests terminate normally, the status
|
||||
* of the completed requests are set to UDMA_REQ_DONE.
|
||||
*
|
||||
* Returns void
|
||||
*/
|
||||
extern void
|
||||
udma_process_requests();
|
||||
|
||||
/* Sets the udma max PIF block size
|
||||
*
|
||||
* max_block_size : max block size to be set
|
||||
*
|
||||
* Returns UDMA_ERROR_INVALID_ARG if block_size is > 3, else returns UDMA_OK
|
||||
*/
|
||||
udma_status_t
|
||||
udma_set_max_block_size(uint32_t block_size);
|
||||
|
||||
/* Sets the udma max outstanding PIF requests
|
||||
*
|
||||
* max_outstanding : max outstanding PIF requests
|
||||
*
|
||||
* Returns UDMA_ERROR_INVALID_ARG if max_outstanding is not between 1 and 16
|
||||
* else returns UDMA_OK
|
||||
*/
|
||||
udma_status_t
|
||||
udma_set_max_outstanding(uint32_t max_outstanding);
|
||||
|
||||
/* Initialize a uDMA descriptor using the copy parameters. The descriptor
|
||||
* is then queued separately using udma_add_desc
|
||||
*
|
||||
* src : src address of the copy
|
||||
* dest : dest address of the copy
|
||||
* row_size : number of bytes per row to copy
|
||||
* num_rows : number of rows to copy
|
||||
* src_pitch : src pitch
|
||||
* dest_pitch : dest pitch
|
||||
* notify_with_interrupt : If 1, interrupt when dma is done with this descriptor
|
||||
* if 0, do nothing, else undefined
|
||||
*
|
||||
* Returns void
|
||||
*/
|
||||
extern void
|
||||
udma_set_desc(void *src,
|
||||
void *dest,
|
||||
size_t row_size,
|
||||
uint32_t num_rows,
|
||||
uint32_t src_pitch,
|
||||
uint32_t dest_pitch,
|
||||
uint32_t notify_with_interrupt,
|
||||
udma_desc_t *desc);
|
||||
|
||||
/* Add multiple uDMA descriptors to the descriptor queue. If the call returns
|
||||
* UDMA_OK, the status is set to UDMA_REQ_PENDING or UDMA_REQ_DONE.
|
||||
* If there is a dma error, the error code, which could be one of
|
||||
* UDMA_ERROR_BAD_DESC, UDMA_ERROR_DRAM_CROSSING, UDMA_ERROR_PIF_ADDR_BUS,
|
||||
* UDMA_ERROR_PIF_DATA_BUS is returned in the status. Status is set
|
||||
* to UDMA_REQ_DONE, if the dma completes normally.
|
||||
* On completion, the callback function is invoked with the callback_data
|
||||
* and status as parameters. Note, the callback is always invoked even if
|
||||
* there is a dma error.
|
||||
*
|
||||
* desc : descriptors to be added
|
||||
* num_desc : number of descriptors to be added
|
||||
* callback_data : optional data to be passed to callback_func
|
||||
* callback_func : optional callback after copy is done
|
||||
* request_attr : attribute defining how to process this request
|
||||
* (see description of the request attribute in top of udma.h)
|
||||
* Note, bit 0 (for enabling interrupt) is ignored in this call.
|
||||
* To interrupt on dma completion, set the
|
||||
* notify_with_interrupt parameter when creating descriptors
|
||||
* using udma_set_desc.
|
||||
* status : track status of the copy; this gets also passed
|
||||
* as the second argument to the callback_func
|
||||
*
|
||||
* Returns UDMA_ERROR_QUEUE_FULL if no more descriptors can be added,
|
||||
* UDMA_ERROR_INVALID_ARG if num_descs == 0, else return UDMA_OK
|
||||
*/
|
||||
udma_status_t
|
||||
udma_add_descs(udma_desc_t *descs,
|
||||
uint32_t num_descs,
|
||||
void *callback_data,
|
||||
void (*callback_func)(void *, udma_status_t *status),
|
||||
uint32_t request_attr,
|
||||
udma_status_t *status);
|
||||
|
||||
/* Wait for udma copy request to complete. Could spin wait or goto waiti
|
||||
* based on the sleep_wait parameter. Once the request is done, the callback
|
||||
* associated with this request and any prior completed requests are handled.
|
||||
* Error code, if any, is returned in the status s, else s is set to
|
||||
* UDMA_REQ_DONE.
|
||||
*
|
||||
* s : status to wait for
|
||||
* sleep_wait : sleep wait if true, else spin waits
|
||||
*
|
||||
* Returns void
|
||||
*/
|
||||
extern void
|
||||
udma_wait_request(volatile udma_status_t *s, uint32_t sleep_wait);
|
||||
|
||||
/* Inlined function to set the src, dest address of the descriptor
|
||||
*
|
||||
* src : src address of the uDMA
|
||||
* dest : dest address of the uDMA
|
||||
* desc : descriptor to be modified
|
||||
*
|
||||
* Returns void
|
||||
*/
|
||||
void static inline
|
||||
udma_set_desc_addrs(void *src, void *dest, udma_desc_t *desc) {
|
||||
uint32_t *d = (uint32_t *)desc;
|
||||
*d = (uintptr_t)src;
|
||||
*(d+1) = (uintptr_t)dest;
|
||||
}
|
||||
|
||||
/* Sets the number of retries for a failed dma request
|
||||
*
|
||||
* max_retries : max number of retries
|
||||
*
|
||||
* Sets the max number of retries for a failed dma request. The default is 0,
|
||||
* i.e, no retries
|
||||
*/
|
||||
void
|
||||
udma_set_max_retries(uint32_t max_retries);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __UDMA_H__ */
|
||||
Executable
+530
@@ -0,0 +1,530 @@
|
||||
/* xdm-regs.h - Common register and related definitions for the XDM
|
||||
(Xtensa Debug Module) */
|
||||
|
||||
/* Copyright (c) 2011-2012 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
|
||||
#ifndef _XDM_REGS_H_
|
||||
#define _XDM_REGS_H_
|
||||
|
||||
/* NOTE: This header file is included by C, assembler, and other sources.
|
||||
So any C-specific or asm-specific content must be appropriately #ifdef'd. */
|
||||
|
||||
|
||||
/*
|
||||
* XDM registers can be accessed using APB, ERI, or JTAG (via NAR).
|
||||
* Address offsets for APB and ERI are the same, and for JTAG
|
||||
* is different (due to the limited 7-bit NAR addressing).
|
||||
*
|
||||
* Here, we first provide the constants as APB / ERI address offsets.
|
||||
* This is necessary for assembler code (which accesses XDM via ERI),
|
||||
* because complex conversion macros between the two address maps
|
||||
* don't work in the assembler.
|
||||
* Conversion macros are used to convert these to/from JTAG (NAR),
|
||||
* addresses, for software using JTAG.
|
||||
*/
|
||||
/* FIXME: maybe provide only MISC+CS registers here, and leave specific
|
||||
subsystem registers in separate headers? eg. for TRAX, PERF, OCD */
|
||||
|
||||
/* XDM_.... ERI addr [NAR addr] Description...... */
|
||||
|
||||
/* TRAX */
|
||||
#define XDM_TRAX_ID 0x0000 /*[0x00] ID */
|
||||
#define XDM_TRAX_CONTROL 0x0004 /*[0x01] Control */
|
||||
#define XDM_TRAX_STATUS 0x0008 /*[0x02] Status */
|
||||
#define XDM_TRAX_DATA 0x000C /*[0x03] Data */
|
||||
#define XDM_TRAX_ADDRESS 0x0010 /*[0x04] Address */
|
||||
#define XDM_TRAX_TRIGGER 0x0014 /*[0x05] Stop PC */
|
||||
#define XDM_TRAX_MATCH 0x0018 /*[0x06] Stop PC Range */
|
||||
#define XDM_TRAX_DELAY 0x001C /*[0x07] Post Stop Trigger Capture Size */
|
||||
#define XDM_TRAX_STARTADDR 0x0020 /*[0x08] Trace Memory Start */
|
||||
#define XDM_TRAX_ENDADDR 0x0024 /*[0x09] Trace Memory End */
|
||||
#define XDM_TRAX_DEBUGPC 0x003C /*[0x0F] Debug PC */
|
||||
#define XDM_TRAX_P4CHANGE 0x0040 /*[0x10] X */
|
||||
#define XDM_TRAX_TIME0 0x0040 /*[0x10] First Time Register */
|
||||
#define XDM_TRAX_P4REV 0x0044 /*[0x11] X */
|
||||
#define XDM_TRAX_TIME1 0x0044 /*[0x11] Second Time Register */
|
||||
#define XDM_TRAX_P4DATE 0x0048 /*[0x12] X */
|
||||
#define XDM_TRAX_INTTIME_MAX 0x0048 /*[0x12] maximal Value of Timestamp IntTime */
|
||||
#define XDM_TRAX_P4TIME 0x004C /*[0x13] X */
|
||||
#define XDM_TRAX_PDSTATUS 0x0050 /*[0x14] Sample of PDebugStatus */
|
||||
#define XDM_TRAX_PDDATA 0x0054 /*[0x15] Sample of PDebugData */
|
||||
#define XDM_TRAX_STOP_PC 0x0058 /*[0x16] X */
|
||||
#define XDM_TRAX_STOP_ICNT 0x005C /*[0x16] X */
|
||||
#define XDM_TRAX_MSG_STATUS 0x0060 /*[0x17] X */
|
||||
#define XDM_TRAX_FSM_STATUS 0x0064 /*[0x18] X */
|
||||
#define XDM_TRAX_IB_STATUS 0x0068 /*[0x19] X */
|
||||
#define XDM_TRAX_STOPCNT 0x006C /*[0x1A] X */
|
||||
|
||||
/* Performance Monitoring Counters */
|
||||
#define XDM_PERF_PMG 0x1000 /*[0x20] perf. mon. global control register */
|
||||
#define XDM_PERF_INTPC 0x1010 /*[0x24] perf. mon. interrupt PC */
|
||||
#define XDM_PERF_PM0 0x1080 /*[0x28] perf. mon. counter 0 value */
|
||||
#define XDM_PERF_PM1 0x1084 /*[0x29] perf. mon. counter 1 value */
|
||||
#define XDM_PERF_PM2 0x1088 /*[0x2A] perf. mon. counter 2 value */
|
||||
#define XDM_PERF_PM3 0x108C /*[0x2B] perf. mon. counter 3 value */
|
||||
#define XDM_PERF_PM4 0x1090 /*[0x2C] perf. mon. counter 4 value */
|
||||
#define XDM_PERF_PM5 0x1094 /*[0x2D] perf. mon. counter 5 value */
|
||||
#define XDM_PERF_PM6 0x1098 /*[0x2E] perf. mon. counter 6 value */
|
||||
#define XDM_PERF_PM7 0x109C /*[0x2F] perf. mon. counter 7 value */
|
||||
#define XDM_PERF_PM(n) (0x1080+((n)<<2)) /* perfmon cnt n=0..7 value */
|
||||
#define XDM_PERF_PMCTRL0 0x1100 /*[0x30] perf. mon. counter 0 control */
|
||||
#define XDM_PERF_PMCTRL1 0x1104 /*[0x31] perf. mon. counter 1 control */
|
||||
#define XDM_PERF_PMCTRL2 0x1108 /*[0x32] perf. mon. counter 2 control */
|
||||
#define XDM_PERF_PMCTRL3 0x110C /*[0x33] perf. mon. counter 3 control */
|
||||
#define XDM_PERF_PMCTRL4 0x1110 /*[0x34] perf. mon. counter 4 control */
|
||||
#define XDM_PERF_PMCTRL5 0x1114 /*[0x35] perf. mon. counter 5 control */
|
||||
#define XDM_PERF_PMCTRL6 0x1118 /*[0x36] perf. mon. counter 6 control */
|
||||
#define XDM_PERF_PMCTRL7 0x111C /*[0x37] perf. mon. counter 7 control */
|
||||
#define XDM_PERF_PMCTRL(n) (0x1100+((n)<<2)) /* perfmon cnt n=0..7 control */
|
||||
#define XDM_PERF_PMSTAT0 0x1180 /*[0x38] perf. mon. counter 0 status */
|
||||
#define XDM_PERF_PMSTAT1 0x1184 /*[0x39] perf. mon. counter 1 status */
|
||||
#define XDM_PERF_PMSTAT2 0x1188 /*[0x3A] perf. mon. counter 2 status */
|
||||
#define XDM_PERF_PMSTAT3 0x118C /*[0x3B] perf. mon. counter 3 status */
|
||||
#define XDM_PERF_PMSTAT4 0x1190 /*[0x3C] perf. mon. counter 4 status */
|
||||
#define XDM_PERF_PMSTAT5 0x1194 /*[0x3D] perf. mon. counter 5 status */
|
||||
#define XDM_PERF_PMSTAT6 0x1198 /*[0x3E] perf. mon. counter 6 status */
|
||||
#define XDM_PERF_PMSTAT7 0x119C /*[0x3F] perf. mon. counter 7 status */
|
||||
#define XDM_PERF_PMSTAT(n) (0x1180+((n)<<2)) /* perfmon cnt n=0..7 status */
|
||||
|
||||
/* On-Chip-Debug (OCD) */
|
||||
#define XDM_OCD_ID 0x2000 /*[0x40] ID register */
|
||||
#define XDM_OCD_DCR_CLR 0x2008 /*[0x42] Debug Control reg clear */
|
||||
#define XDM_OCD_DCR_SET 0x200C /*[0x43] Debug Control reg set */
|
||||
#define XDM_OCD_DSR 0x2010 /*[0x44] Debug Status reg */
|
||||
#define XDM_OCD_DDR 0x2014 /*[0x45] Debug Data reg */
|
||||
#define XDM_OCD_DDREXEC 0x2018 /*[0x46] Debug Data reg + execute-DIR */
|
||||
#define XDM_OCD_DIR0EXEC 0x201C /*[0x47] Debug Instruction reg, word 0 + execute-DIR */
|
||||
#define XDM_OCD_DIR0 0x2020 /*[0x48] Debug Instruction reg, word 1 */
|
||||
#define XDM_OCD_DIR1 0x2024 /*[0x49] Debug Instruction reg, word 2 */
|
||||
#define XDM_OCD_DIR2 0x2028 /*[0x4A] Debug Instruction reg, word 3 */
|
||||
#define XDM_OCD_DIR3 0x202C /*[0x49] Debug Instruction reg, word 4 */
|
||||
#define XDM_OCD_DIR4 0x2030 /*[0x4C] Debug Instruction reg, word 5 */
|
||||
#define XDM_OCD_DIR5 0x2034 /*[0x4D] Debug Instruction reg, word 5 */
|
||||
#define XDM_OCD_DIR6 0x2038 /*[0x4E] Debug Instruction reg, word 6 */
|
||||
#define XDM_OCD_DIR7 0x203C /*[0x4F] Debug Instruction reg, word 7 */
|
||||
|
||||
/* Miscellaneous Registers */
|
||||
#define XDM_MISC_PWRCTL 0x3020 /*[0x58] Power and Reset Control */
|
||||
#define XDM_MISC_PWRSTAT 0x3024 /*[0x59] Power and Reset Status */
|
||||
#define XDM_MISC_ERISTAT 0x3028 /*[0x5A] ERI Transaction Status */
|
||||
#define XDM_MISC_DATETIME 0x3034 /*[0x5D] [INTERNAL] Timestamps of build */
|
||||
#define XDM_MISC_UBID 0x3038 /*[0x5E] [INTERNAL] Build Unique ID */
|
||||
#define XDM_MISC_CID 0x303C /*[0x5F] [INTERNAL] Customer ID */
|
||||
|
||||
/* CoreSight compatibility */
|
||||
#define XDM_CS_ITCTRL 0x3F00 /*[0x60] InTegration Mode control reg */
|
||||
#define XDM_CS_CLAIMSET 0x3FA0 /*[0x68] Claim Tag Set reg */
|
||||
#define XDM_CS_CLAIMCLR 0x3FA4 /*[0x69] Claim Tag Clear reg */
|
||||
#define XDM_CS_LOCK_ACCESS 0x3FB0 /*[0x6B] Lock Access (writing 0xC5ACCE55 unlocks) */
|
||||
#define XDM_CS_LOCK_STATUS 0x3FB4 /*[0x6D] Lock Status */
|
||||
#define XDM_CS_AUTH_STATUS 0x3FB8 /*[0x6E] Authentication Status */
|
||||
#define XDM_CS_DEV_ID 0x3FC8 /*[0x72] Device ID */
|
||||
#define XDM_CS_DEV_TYPE 0x3FCC /*[0x73] Device Type */
|
||||
#define XDM_CS_PER_ID4 0x3FD0 /*[0x74] Peripheral ID reg byte 4 */
|
||||
#define XDM_CS_PER_ID5 0x3FD4 /*[0x75] Peripheral ID reg byte 5 */
|
||||
#define XDM_CS_PER_ID6 0x3FD8 /*[0x76] Peripheral ID reg byte 6 */
|
||||
#define XDM_CS_PER_ID7 0x3FDC /*[0x77] Peripheral ID reg byte 7 */
|
||||
#define XDM_CS_PER_ID0 0x3FE0 /*[0x78] Peripheral ID reg byte 0 */
|
||||
#define XDM_CS_PER_ID1 0x3FE4 /*[0x79] Peripheral ID reg byte 1 */
|
||||
#define XDM_CS_PER_ID2 0x3FE8 /*[0x7A] Peripheral ID reg byte 2 */
|
||||
#define XDM_CS_PER_ID3 0x3FEC /*[0x7B] Peripheral ID reg byte 3 */
|
||||
#define XDM_CS_COMP_ID0 0x3FF0 /*[0x7C] Component ID reg byte 0 */
|
||||
#define XDM_CS_COMP_ID1 0x3FF4 /*[0x7D] Component ID reg byte 1 */
|
||||
#define XDM_CS_COMP_ID2 0x3FF8 /*[0x7E] Component ID reg byte 2 */
|
||||
#define XDM_CS_COMP_ID3 0x3FFC /*[0x7F] Component ID reg byte 3 */
|
||||
|
||||
#define CS_PER_ID0 0x00000003
|
||||
#define CS_PER_ID1 0x00000021
|
||||
#define CS_PER_ID2 0x0000000f
|
||||
#define CS_PER_ID3 0x00000000
|
||||
#define CS_PER_ID4 0x00000024
|
||||
|
||||
#define CS_COMP_ID0 0x0000000d
|
||||
#define CS_COMP_ID1 0x00000090
|
||||
#define CS_COMP_ID2 0x00000005
|
||||
#define CS_COMP_ID3 0x000000b1
|
||||
|
||||
#define CS_DEV_TYPE 0x00000015
|
||||
|
||||
#define XTENSA_IDCODE 0x120034e5 // FIXME (upper bits not spec. out but BE is !)
|
||||
#define XTENSA_MFC_ID (XTENSA_IDCODE & 0xFFF)
|
||||
#define CS_DEV_ID XTENSA_IDCODE
|
||||
|
||||
#define NXS_OCD_REG(val) ((val >= 0x40) && (val <= 0x5F))
|
||||
#define NXS_TRAX_REG(val) val <= 0x3F
|
||||
|
||||
#define ERI_TRAX_REG(val) ((val & 0xFFFF) < 0x1000)
|
||||
#define ERI_OCD_REG(val) ((val & 0xFFFF) >= 0x2000) && ((val & 0xFFFF) < 0x4000))
|
||||
|
||||
/* Convert above 14-bit ERI/APB address/offset to 7-bit NAR address: */
|
||||
#define _XDM_ERI_TO_NAR(a) ( ((a)&0x3F80)==0x0000 ? (((a)>>2) & 0x1F) \
|
||||
: ((a)&0x3E00)==0x1000 ? (0x20 | (((a)>>2) & 7) | (((a)>>4) & 0x18)) \
|
||||
: ((a)&0x3FC0)==0x2000 ? (0x40 | (((a)>>2) & 0xF)) \
|
||||
: ((a)&0x3FE0)==0x3020 ? (0x50 | (((a)>>2) & 0xF)) \
|
||||
: ((a)&0x3FFC)==0x3F00 ? 0x60 \
|
||||
: ((a)&0x3F80)==0x3F80 ? (0x60 | (((a)>>2) & 0x1F)) \
|
||||
: -1 )
|
||||
|
||||
#define XDM_ERI_TO_NAR(a) _XDM_ERI_TO_NAR(a & 0xFFFF)
|
||||
|
||||
/* Convert 7-bit NAR address back to ERI/APB address/offset: */
|
||||
#define _XDM_NAR_TO_APB(a) ((a) <= 0x1f ? ((a) << 2) \
|
||||
:(a) >= 0x20 && (a) <= 0x3F ? (0x1000 | (((a)& 7) << 2) | (((a)&0x18)<<4)) \
|
||||
:(a) >= 0x40 && (a) <= 0x4F ? (0x2000 | (((a)&0xF) << 2)) \
|
||||
:(a) >= 0x58 && (a) <= 0x5F ? (0x3000 | (((a)&0xF) << 2)) \
|
||||
:(a) == 0x60 ? (0x3F00) \
|
||||
:(a) >= 0x68 && (a) <= 0x7F ? (0x3F80 | (((a)&0x1F) << 2)) \
|
||||
: -1)
|
||||
|
||||
#define XDM_NAR_TO_APB(a) _XDM_NAR_TO_APB((a & 0xFFFF))
|
||||
#define XDM_NAR_TO_ERI(a) _XDM_NAR_TO_APB((a & 0xFFFF)) | 0x000000
|
||||
|
||||
/* Convert APB to ERI address */
|
||||
#define XDM_APB_TO_ERI(a) ((a) | (0x100000))
|
||||
#define XDM_ERI_TO_APB(a) ((a) & (0x0FFFFF))
|
||||
|
||||
/*********** Bit definitions within some of the above registers ***********/
|
||||
#define OCD_ID_LSDDRP 0x01000000
|
||||
#define OCD_ID_LSDDRP_SHIFT 24
|
||||
#define OCD_ID_ENDIANESS 0x00000001
|
||||
#define OCD_ID_ENDIANESS_SHIFT 0
|
||||
#define OCD_ID_PSO 0x0000000C
|
||||
#define OCD_ID_PSO_SHIFT 2
|
||||
#define OCD_ID_TRACEPORT 0x00000080
|
||||
#define OCD_ID_TRACEPORT_SHIFT 7
|
||||
|
||||
/* Power Status register. NOTE: different bit positions in JTAG vs. ERI/APB !! */
|
||||
/* ERI/APB: */
|
||||
#define PWRSTAT_CORE_DOMAIN_ON 0x00000001 /* set if core is powered on */
|
||||
#define PWRSTAT_CORE_DOMAIN_ON_SHIFT 0
|
||||
#define PWRSTAT_WAKEUP_RESET 0x00000002 /* [ERI only] 0=cold start, 1=PSO wakeup */
|
||||
#define PWRSTAT_WAKEUP_RESET_SHIFT 1
|
||||
#define PWRSTAT_CACHES_LOST_POWER 0x00000004 /* [ERI only] set if caches (/localmems?) lost power */
|
||||
/* FIXME: does this include local memories? */
|
||||
#define PWRSTAT_CACHES_LOST_POWER_SHIFT 2
|
||||
#define PWRSTAT_CORE_STILL_NEEDED 0x00000010 /* set if others keeping core awake */
|
||||
#define PWRSTAT_CORE_STILL_NEEDED_SHIFT 4
|
||||
#define PWRSTAT_MEM_DOMAIN_ON 0x00000100 /* set if memory domain is powered on */
|
||||
#define PWRSTAT_MEM_DOMAIN_ON_SHIFT 8
|
||||
#define PWRSTAT_DEBUG_DOMAIN_ON 0x00001000 /* set if debug domain is powered on */
|
||||
#define PWRSTAT_DEBUG_DOMAIN_ON_SHIFT 12
|
||||
#define PWRSTAT_ALL_ON PWRSTAT_CORE_DOMAIN_ON | PWRSTAT_MEM_DOMAIN_ON | PWRSTAT_DEBUG_DOMAIN_ON
|
||||
#define PWRSTAT_CORE_WAS_RESET 0x00010000 /* [APB only] set if core got reset */
|
||||
#define PWRSTAT_CORE_WAS_RESET_SHIFT 16
|
||||
#define PWRSTAT_DEBUG_WAS_RESET 0x10000000 /* set if debug module got reset */
|
||||
#define PWRSTAT_DEBUG_WAS_RESET_SHIFT 28
|
||||
/* JTAG: */
|
||||
#define J_PWRSTAT_CORE_DOMAIN_ON 0x01 /* set if core is powered on */
|
||||
#define J_PWRSTAT_MEM_DOMAIN_ON 0x02 /* set if memory domain is powered on */
|
||||
#define J_PWRSTAT_DEBUG_DOMAIN_ON 0x04 /* set if debug domain is powered on */
|
||||
#define J_PWRSTAT_ALL_ON J_PWRSTAT_CORE_DOMAIN_ON | J_PWRSTAT_MEM_DOMAIN_ON | J_PWRSTAT_DEBUG_DOMAIN_ON
|
||||
#define J_PWRSTAT_CORE_STILL_NEEDED 0x08 /* set if others keeping core awake */
|
||||
#define J_PWRSTAT_CORE_WAS_RESET 0x10 /* set if core got reset */
|
||||
#define J_PWRSTAT_DEBUG_WAS_RESET 0x40 /* set if debug module got reset */
|
||||
|
||||
/* Power Control register. NOTE: different bit positions in JTAG vs. ERI/APB !! */
|
||||
/* ERI/APB: */
|
||||
#define PWRCTL_CORE_SHUTOFF 0x00000001 /* [ERI only] core wants to shut off on WAITI */
|
||||
#define PWRCTL_CORE_SHUTOFF_SHIFT 0
|
||||
#define PWRCTL_CORE_WAKEUP 0x00000001 /* [APB only] set to force core to stay powered on */
|
||||
#define PWRCTL_CORE_WAKEUP_SHIFT 0
|
||||
#define PWRCTL_MEM_WAKEUP 0x00000100 /* set to force memory domain to stay powered on */
|
||||
#define PWRCTL_MEM_WAKEUP_SHIFT 8
|
||||
#define PWRCTL_DEBUG_WAKEUP 0x00001000 /* set to force debug domain to stay powered on */
|
||||
#define PWRCTL_DEBUG_WAKEUP_SHIFT 12
|
||||
#define PWRCTL_ALL_ON PWRCTL_CORE_WAKEUP | PWRCTL_MEM_WAKEUP | PWRCTL_DEBUG_WAKEUP
|
||||
#define PWRCTL_CORE_RESET 0x00010000 /* [APB only] set to assert core reset */
|
||||
#define PWRCTL_CORE_RESET_SHIFT 16
|
||||
#define PWRCTL_DEBUG_RESET 0x10000000 /* set to assert debug module reset */
|
||||
#define PWRCTL_DEBUG_RESET_SHIFT 28
|
||||
/* JTAG: */
|
||||
#define J_PWRCTL_CORE_WAKEUP 0x01 /* set to force core to stay powered on */
|
||||
#define J_PWRCTL_MEM_WAKEUP 0x02 /* set to force memory domain to stay powered on */
|
||||
#define J_PWRCTL_DEBUG_WAKEUP 0x04 /* set to force debug domain to stay powered on */
|
||||
#define J_DEBUG_USE 0x80 /* */
|
||||
#define J_PWRCTL_ALL_ON J_DEBUG_USE | J_PWRCTL_CORE_WAKEUP | J_PWRCTL_MEM_WAKEUP | J_PWRCTL_DEBUG_WAKEUP
|
||||
#define J_PWRCTL_DEBUG_ON J_DEBUG_USE | J_PWRCTL_DEBUG_WAKEUP
|
||||
#define J_PWRCTL_CORE_RESET 0x10 /* set to assert core reset */
|
||||
#define J_PWRCTL_DEBUG_RESET 0x40 /* set to assert debug module reset */
|
||||
|
||||
#define J_PWRCTL_WRITE_MASK 0xFF
|
||||
#define J_PWRSTAT_WRITE_MASK 0xFF
|
||||
|
||||
#define PWRCTL_WRITE_MASK ~0
|
||||
#define PWRSTAT_WRITE_MASK ~0
|
||||
|
||||
/************ The following are only relevant for JTAG, so perhaps belong in OCD only **************/
|
||||
|
||||
/* XDM 5-bit JTAG Instruction Register (IR) values: */
|
||||
#define XDM_IR_PWRCTL 0x08 /* select 8-bit Power/Reset Control (PRC) */
|
||||
#define XDM_IR_PWRSTAT 0x09 /* select 8-bit Power/Reset Status (PRS) */
|
||||
#define XDM_IR_NAR_SEL 0x1c /* select altern. 8-bit NAR / 32-bit NDR (Nexus-style) */
|
||||
#define XDM_IR_NDR_SEL 0x1d /* select altern. 32-bit NDR / 8-bit NAR
|
||||
(FIXME - functionality not yet in HW) */
|
||||
#define XDM_IR_IDCODE 0x1e /* select 32-bit JTAG IDCODE */
|
||||
#define XDM_IR_BYPASS 0x1f /* select 1-bit bypass */
|
||||
|
||||
#define XDM_IR_WIDTH 5 /* width of IR for Xtensa TAP */
|
||||
|
||||
/* NAR register bits: */
|
||||
#define XDM_NAR_WRITE 0x01
|
||||
#define XDM_NAR_ADDR_MASK 0xFE
|
||||
#define XDM_NAR_ADDR_SHIFT 1
|
||||
|
||||
#define XDM_NAR_BUSY 0x02
|
||||
#define XDM_NAR_ERROR 0x01
|
||||
|
||||
#define NEXUS_DIR_READ 0x00
|
||||
#define NEXUS_DIR_WRITE 0x01
|
||||
|
||||
/************ Define DCR register bits **************/
|
||||
|
||||
#define DCR_ENABLEOCD 0x0000001
|
||||
#define DCR_ENABLEOCD_SHIFT 0
|
||||
#define DCR_DEBUG_INT 0x0000002
|
||||
#define DCR_DEBUG_INT_SHIFT 1
|
||||
#define DCR_DEBUG_OVERRIDE 0x0000004
|
||||
#define DCR_DEBUG_OVERRIDE_SHIFT 2
|
||||
#define DCR_DEBUG_INTERCEPT 0x0000008
|
||||
#define DCR_DEBUG_INTERCEPT_SHIFT 3
|
||||
#define DCR_MASK_NMI 0x0000020
|
||||
#define DCR_MASK_NMI_SHIFT 5
|
||||
#define DCR_STEP_ENABLE 0x0000040
|
||||
#define DCR_STEP_ENABLE_SHIFT 6
|
||||
#define DCR_BREAK_IN_EN 0x0010000
|
||||
#define DCR_BREAK_IN_EN_SHIFT 16
|
||||
#define DCR_BREAK_OUT_EN 0x0020000
|
||||
#define DCR_BREAK_OUT_EN_SHIFT 17
|
||||
#define DCR_DEBUG_INT_EN 0x0040000
|
||||
#define DCR_DEBUG_INT_EN_SHIFT 18
|
||||
#define DCR_DBG_SW_ACTIVE 0x0100000
|
||||
#define DCR_DBG_SW_ACTIVE_SHIFT 20
|
||||
#define DCR_STALL_IN_EN 0x0200000
|
||||
#define DCR_STALL_IN_EN_SHIFT 21
|
||||
#define DCR_DEBUG_OUT_EN 0x0400000
|
||||
#define DCR_DEBUG_OUT_EN_SHIFT 22
|
||||
#define DCR_BREAK_OUT_ITO 0x1000000
|
||||
#define DCR_STALL_OUT_ITO 0x2000000
|
||||
#define DCR_STALL_OUT_ITO_SHIFT 25
|
||||
|
||||
/************ Define DSR register bits **************/
|
||||
|
||||
#define DOSR_EXECDONE_ER 0x01
|
||||
#define DOSR_EXECDONE_SHIFT 0
|
||||
#define DOSR_EXCEPTION_ER 0x02
|
||||
#define DOSR_EXCEPTION_SHIFT 1
|
||||
#define DOSR_BUSY 0x04
|
||||
#define DOSR_BUSY_SHIFT 2
|
||||
#define DOSR_OVERRUN 0x08
|
||||
#define DOSR_OVERRUN_SHIFT 3
|
||||
#define DOSR_INOCDMODE_ER 0x10
|
||||
#define DOSR_INOCDMODE_SHIFT 4
|
||||
#define DOSR_CORE_WROTE_DDR_ER 0x400
|
||||
#define DOSR_CORE_WROTE_DDR_SHIFT 10
|
||||
#define DOSR_CORE_READ_DDR_ER 0x800
|
||||
#define DOSR_CORE_READ_DDR_SHIFT 11
|
||||
#define DOSR_HOST_WROTE_DDR_ER 0x4000
|
||||
#define DOSR_HOST_WROTE_DDR_SHIFT 14
|
||||
#define DOSR_HOST_READ_DDR_ER 0x8000
|
||||
#define DOSR_HOST_READ_DDR_SHIFT 15
|
||||
|
||||
#define DOSR_DEBUG_PEND_BIN 0x10000
|
||||
#define DOSR_DEBUG_PEND_HOST 0x20000
|
||||
#define DOSR_DEBUG_PEND_TRAX 0x40000
|
||||
#define DOSR_DEBUG_BIN 0x100000
|
||||
#define DOSR_DEBUG_HOST 0x200000
|
||||
#define DOSR_DEBUG_TRAX 0x400000
|
||||
#define DOSR_DEBUG_PEND_BIN_SHIFT 16
|
||||
#define DOSR_DEBUG_PEND_HOST_SHIFT 17
|
||||
#define DOSR_DEBUG_PEND_TRAX_SHIFT 18
|
||||
#define DOSR_DEBUG_BREAKIN 0x0100000
|
||||
#define DOSR_DEBUG_BREAKIN_SHIFT 20
|
||||
#define DOSR_DEBUG_HOST_SHIFT 21
|
||||
#define DOSR_DEBUG_TRAX_SHIFT 22
|
||||
|
||||
#define DOSR_DEBUG_STALL 0x1000000
|
||||
#define DOSR_DEBUG_STALL_SHIFT 24
|
||||
|
||||
#define DOSR_CORE_ON 0x40000000
|
||||
#define DOSR_CORE_ON_SHIFT 30
|
||||
#define DOSR_DEBUG_ON 0x80000000
|
||||
#define DOSR_DEBUG_ON_SHIFT 31
|
||||
|
||||
/********** Performance monitor registers bits **********/
|
||||
|
||||
#define PERF_PMG_ENABLE 0x00000001 /* global enable bit */
|
||||
#define PERF_PMG_ENABLE_SHIFT 0
|
||||
|
||||
#define PERF_PMCTRL_INT_ENABLE 0x00000001 /* assert interrupt on overflow */
|
||||
#define PERF_PMCTRL_INT_ENABLE_SHIFT 0
|
||||
#define PERF_PMCTRL_KRNLCNT 0x00000008 /* ignore TRACELEVEL */
|
||||
#define PERF_PMCTRL_KRNLCNT_SHIFT 3
|
||||
#define PERF_PMCTRL_TRACELEVEL 0x000000F0 /* count when CINTLEVEL <= TRACELEVEL */
|
||||
#define PERF_PMCTRL_TRACELEVEL_SHIFT 4
|
||||
#define PERF_PMCTRL_SELECT 0x00001F00 /* events group selector */
|
||||
#define PERF_PMCTRL_SELECT_SHIFT 8
|
||||
#define PERF_PMCTRL_MASK 0xFFFF0000 /* events mask */
|
||||
#define PERF_PMCTRL_MASK_SHIFT 16
|
||||
|
||||
#define PERF_PMSTAT_OVERFLOW 0x00000001 /* counter overflowed */
|
||||
#define PERF_PMSTAT_OVERFLOW_SHIFT 0
|
||||
#define PERF_PMSTAT_INT 0x00000010 /* interrupt asserted */
|
||||
#define PERF_PMSTAT_INT_SHIFT 4
|
||||
|
||||
#if defined (USE_XDM_REGNAME) || defined (USE_DAP_REGNAME)
|
||||
/* Describes XDM register: */
|
||||
typedef struct {
|
||||
int reg;
|
||||
char* name;
|
||||
} regdef_t;
|
||||
|
||||
/*char* regname(regdef_t* list, int regno)
|
||||
{
|
||||
unsigned i;
|
||||
for(i = 0 ; i < (sizeof(list) / sizeof(regdef_t)); i++){
|
||||
if(list[i].reg == regno)
|
||||
return list[i].name;
|
||||
}
|
||||
return "???";
|
||||
}*/
|
||||
|
||||
/*
|
||||
* Returns the name of the specified XDM register number,
|
||||
* or simply "???" if the register number is not recognized.
|
||||
* FIXME - requires -1 as the last entry - change to compare the name to ???
|
||||
* or even better, make the code above to work.
|
||||
*/
|
||||
static char * regname(regdef_t* list, int reg)
|
||||
{
|
||||
int i = 0;
|
||||
while (list[i].reg != -1){
|
||||
if (list[i].reg == reg)
|
||||
break;
|
||||
i++;
|
||||
}
|
||||
return list[i].name;
|
||||
}
|
||||
|
||||
#if defined (USE_XDM_REGNAME)
|
||||
regdef_t xdm_reglist[] =
|
||||
{
|
||||
{XDM_TRAX_ID ,"TRAX_ID" },
|
||||
{XDM_TRAX_CONTROL ,"CONTROL" },
|
||||
{XDM_TRAX_STATUS ,"STATUS" },
|
||||
{XDM_TRAX_DATA ,"DATA" },
|
||||
{XDM_TRAX_ADDRESS ,"ADDRESS" },
|
||||
{XDM_TRAX_TRIGGER ,"TRIGGER PC" },
|
||||
{XDM_TRAX_MATCH ,"PC MATCH" },
|
||||
{XDM_TRAX_DELAY ,"DELAY CNT." },
|
||||
{XDM_TRAX_STARTADDR ,"START ADDRESS"},
|
||||
{XDM_TRAX_ENDADDR ,"END ADDRESS" },
|
||||
{XDM_TRAX_DEBUGPC ,"DEBUG PC" },
|
||||
{XDM_TRAX_P4CHANGE ,"P4 CHANGE" },
|
||||
{XDM_TRAX_P4REV ,"P4 REV." },
|
||||
{XDM_TRAX_P4DATE ,"P4 DATE" },
|
||||
{XDM_TRAX_P4TIME ,"P4 TIME" },
|
||||
{XDM_TRAX_PDSTATUS ,"PD STATUS" },
|
||||
{XDM_TRAX_PDDATA ,"PD DATA" },
|
||||
{XDM_TRAX_STOP_PC ,"STOP PC" },
|
||||
{XDM_TRAX_STOP_ICNT ,"STOP ICNT" },
|
||||
{XDM_TRAX_MSG_STATUS ,"MSG STAT." },
|
||||
{XDM_TRAX_FSM_STATUS ,"FSM STAT." },
|
||||
{XDM_TRAX_IB_STATUS ,"IB STAT." },
|
||||
|
||||
{XDM_OCD_ID ,"OCD_ID" },
|
||||
{XDM_OCD_DCR_CLR ,"DCR_CLR" },
|
||||
{XDM_OCD_DCR_SET ,"DCR_SET" },
|
||||
{XDM_OCD_DSR ,"DOSR" },
|
||||
{XDM_OCD_DDR ,"DDR" },
|
||||
{XDM_OCD_DDREXEC ,"DDREXEC" },
|
||||
{XDM_OCD_DIR0EXEC ,"DIR0EXEC"},
|
||||
{XDM_OCD_DIR0 ,"DIR0" },
|
||||
{XDM_OCD_DIR1 ,"DIR1" },
|
||||
{XDM_OCD_DIR2 ,"DIR2" },
|
||||
{XDM_OCD_DIR3 ,"DIR3" },
|
||||
{XDM_OCD_DIR4 ,"DIR4" },
|
||||
{XDM_OCD_DIR5 ,"DIR5" },
|
||||
{XDM_OCD_DIR6 ,"DIR6" },
|
||||
{XDM_OCD_DIR7 ,"DIR7" },
|
||||
|
||||
{XDM_PERF_PMG ,"PMG" },
|
||||
{XDM_PERF_INTPC ,"INTPC" },
|
||||
{XDM_PERF_PM0 ,"PM0 " },
|
||||
{XDM_PERF_PM1 ,"PM1 " },
|
||||
{XDM_PERF_PM2 ,"PM2 " },
|
||||
{XDM_PERF_PM3 ,"PM3 " },
|
||||
{XDM_PERF_PM4 ,"PM4 " },
|
||||
{XDM_PERF_PM5 ,"PM5 " },
|
||||
{XDM_PERF_PM6 ,"PM6 " },
|
||||
{XDM_PERF_PM7 ,"PM7 " },
|
||||
{XDM_PERF_PMCTRL0 ,"PMCTRL0"},
|
||||
{XDM_PERF_PMCTRL1 ,"PMCTRL1"},
|
||||
{XDM_PERF_PMCTRL2 ,"PMCTRL2"},
|
||||
{XDM_PERF_PMCTRL3 ,"PMCTRL3"},
|
||||
{XDM_PERF_PMCTRL4 ,"PMCTRL4"},
|
||||
{XDM_PERF_PMCTRL5 ,"PMCTRL5"},
|
||||
{XDM_PERF_PMCTRL6 ,"PMCTRL6"},
|
||||
{XDM_PERF_PMCTRL7 ,"PMCTRL7"},
|
||||
{XDM_PERF_PMSTAT0 ,"PMSTAT0"},
|
||||
{XDM_PERF_PMSTAT1 ,"PMSTAT1"},
|
||||
{XDM_PERF_PMSTAT2 ,"PMSTAT2"},
|
||||
{XDM_PERF_PMSTAT3 ,"PMSTAT3"},
|
||||
{XDM_PERF_PMSTAT4 ,"PMSTAT4"},
|
||||
{XDM_PERF_PMSTAT5 ,"PMSTAT5"},
|
||||
{XDM_PERF_PMSTAT6 ,"PMSTAT6"},
|
||||
{XDM_PERF_PMSTAT7 ,"PMSTAT7"},
|
||||
|
||||
{XDM_MISC_PWRCTL ,"PWRCTL" },
|
||||
{XDM_MISC_PWRSTAT ,"PWRSTAT" },
|
||||
{XDM_MISC_ERISTAT ,"ERISTAT" },
|
||||
{XDM_MISC_DATETIME ,"DATETIME"},
|
||||
{XDM_MISC_UBID ,"UBID" },
|
||||
{XDM_MISC_CID ,"CID" },
|
||||
|
||||
{XDM_CS_ITCTRL ,"ITCTRL" },
|
||||
{XDM_CS_CLAIMSET ,"CLAIMSET" },
|
||||
{XDM_CS_CLAIMCLR ,"CLAIMCLR" },
|
||||
{XDM_CS_LOCK_ACCESS ,"LOCK_ACCESS"},
|
||||
{XDM_CS_LOCK_STATUS ,"LOCK_STATUS"},
|
||||
{XDM_CS_AUTH_STATUS ,"AUTH_STATUS"},
|
||||
{XDM_CS_DEV_ID ,"DEV_ID" },
|
||||
{XDM_CS_DEV_TYPE ,"DEV_TYPE" },
|
||||
{XDM_CS_PER_ID4 ,"PER_ID4" },
|
||||
{XDM_CS_PER_ID5 ,"PER_ID5" },
|
||||
{XDM_CS_PER_ID6 ,"PER_ID6" },
|
||||
{XDM_CS_PER_ID7 ,"PER_ID7" },
|
||||
{XDM_CS_PER_ID0 ,"PER_ID0" },
|
||||
{XDM_CS_PER_ID1 ,"PER_ID1" },
|
||||
{XDM_CS_PER_ID2 ,"PER_ID2" },
|
||||
{XDM_CS_PER_ID3 ,"PER_ID3" },
|
||||
{XDM_CS_COMP_ID0 ,"COMP_ID0" },
|
||||
{XDM_CS_COMP_ID1 ,"COMP_ID1" },
|
||||
{XDM_CS_COMP_ID2 ,"COMP_ID2" },
|
||||
{XDM_CS_COMP_ID3 ,"COMP_ID3" },
|
||||
{-1 ,"???" },
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* _XDM_REGS_H_ */
|
||||
Executable
+97
@@ -0,0 +1,97 @@
|
||||
/* xmon.h - XMON definitions
|
||||
*
|
||||
* $Id: //depot/rel/Eaglenest/Xtensa/OS/xmon/xmon.h#3 $
|
||||
*
|
||||
* Copyright (c) 2001-2013 Tensilica Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef __H_XMON
|
||||
#define __H_XMON
|
||||
|
||||
/* Default GDB packet size */
|
||||
#define GDB_PKT_SIZE 4096
|
||||
|
||||
/*XMON signals */
|
||||
#define XMON_SIGINT 2 /*target was interrupted */
|
||||
#define XMON_SIGILL 4 /*illegal instruction */
|
||||
#define XMON_SIGTRAP 5 /*general exception */
|
||||
#define XMON_SIGSEGV 11 /*page faults */
|
||||
|
||||
|
||||
/* Type of log message from XMON to the application */
|
||||
typedef enum {
|
||||
XMON_LOG,
|
||||
XMON_TRACE,
|
||||
XMON_ERR,
|
||||
XMON_APP,
|
||||
XMON_GDB
|
||||
} xmon_log_t;
|
||||
|
||||
/* Return value type for xmon_proc() (see below) */
|
||||
typedef enum {
|
||||
XMON_GDB_PEND,
|
||||
XMON_GDB_PKT,
|
||||
XMON_NOT_GDB
|
||||
} xmon_gdb_pkt_t;
|
||||
|
||||
#ifdef _cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* THE FOLLOWING ROUTINES ARE USED BY USER
|
||||
*/
|
||||
extern int _xmon_init(char* gdbBuf, int gdbPktSize,
|
||||
void(*xlog)(xmon_log_t type, const char* str));
|
||||
//Initialize GDB communication and logging to the main app.
|
||||
//For the logging to work, xlog function needs to be provided.
|
||||
//gdbBuf - pointer to a buffer XMON can use to comm. with GDB
|
||||
//gdbPktSize - Size of the allocated buffer for GDB communication.
|
||||
//xlog - logger handle.
|
||||
|
||||
|
||||
extern void _xmon_close(void);
|
||||
//Main application can detach from xmon at any time
|
||||
|
||||
|
||||
extern xmon_gdb_pkt_t _xmon_proc(char);
|
||||
// Give character to XMON to check if GDB message
|
||||
// Application is supposed to accumulate all the
|
||||
// character in case the recognition fails and chars
|
||||
// have to be sent to the original handler
|
||||
// Return: XMON_GDB_PEND - send me more chars
|
||||
// XMON_GDB_PKT - GDB message confirmed, C) not
|
||||
// XMON_NOT_GDB - not GDB message
|
||||
|
||||
|
||||
/*
|
||||
* THE FOLLOWING ROUTINES NEED TO BE PROVIDED BY USER
|
||||
*/
|
||||
extern int _xmon_in(); // wait for character from GDB
|
||||
extern void _xmon_out(char); // output a character to GDB
|
||||
extern int _xmon_flush(void); // flush output characters
|
||||
|
||||
#ifdef _cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
+789
@@ -0,0 +1,789 @@
|
||||
/* Customer ID=11656; Build=0x5f626; Copyright (c) 2008-2009 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
These coded instructions, statements, and computer programs are the
|
||||
copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
third parties in any manner, medium, or form, in whole or in part, without
|
||||
the prior written consent of Tensilica Inc. */
|
||||
|
||||
#ifndef _XMP_LIBRARY_H
|
||||
#define _XMP_LIBRARY_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <xtensa/config/core-isa.h>
|
||||
#include <xtensa/config/core.h>
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
#if XCHAL_HAVE_RELEASE_SYNC
|
||||
#include <xtensa/tie/xt_sync.h>
|
||||
#endif
|
||||
#if XCHAL_HAVE_EXTERN_REGS
|
||||
#include <xtensa/xtensa-xer.h>
|
||||
#endif
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#include "xtensa/system/mpsystem.h"
|
||||
|
||||
/*
|
||||
W A R N I N G:
|
||||
|
||||
xmp library clients should treat all data structures in this file
|
||||
as opaque. They are only public to enable users to declare them
|
||||
statically.
|
||||
*/
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------------
|
||||
When using XMP on cache-incoherent systems, these macros are helpful
|
||||
to ensure that you are not reading stale data, and to ensure that
|
||||
the data you write makes it all the way back to main memory.
|
||||
*/
|
||||
|
||||
#if !XCHAL_DCACHE_IS_COHERENT
|
||||
#define XMP_WRITE_BACK_ELEMENT(x) xthal_dcache_region_writeback((void *)x, sizeof(*x))
|
||||
#define XMP_INVALIDATE_ELEMENT(x) xthal_dcache_region_invalidate((void *)x, sizeof(*x))
|
||||
#define XMP_WRITE_BACK_INVALIDATE_ELEMENT(x) xthal_dcache_region_writeback_inv((void *)x, sizeof(*x))
|
||||
#define XMP_WRITE_BACK_ARRAY(x) xthal_dcache_region_writeback((void *)x, sizeof(x))
|
||||
#define XMP_INVALIDATE_ARRAY(x) xthal_dcache_region_invalidate((void *)x, sizeof(x))
|
||||
#define XMP_WRITE_BACK_INVALIDATE_ARRAY(x) xthal_dcache_region_writeback_inv((void *)x, sizeof(x))
|
||||
#define XMP_WRITE_BACK_ARRAY_ELEMENTS(x, num_elements) xthal_dcache_region_writeback((void *)x, sizeof(*x) * num_elements)
|
||||
#define XMP_INVALIDATE_ARRAY_ELEMENTS(x, num_elements) xthal_dcache_region_invalidate((void *)x, sizeof(*x) * num_elements)
|
||||
#define XMP_WRITE_BACK_INVALIDATE_ARRAY_ELEMENTS(x, num_elements) xthal_dcache_region_writeback_inv((void *)x, sizeof(*x) * num_elements)
|
||||
#else
|
||||
#define XMP_WRITE_BACK_ELEMENT(x)
|
||||
#define XMP_INVALIDATE_ELEMENT(x)
|
||||
#define XMP_WRITE_BACK_INVALIDATE_ELEMENT(x)
|
||||
#define XMP_WRITE_BACK_ARRAY(x)
|
||||
#define XMP_INVALIDATE_ARRAY(x)
|
||||
#define XMP_WRITE_BACK_INVALIDATE_ARRAY(x)
|
||||
#define XMP_WRITE_BACK_ARRAY_ELEMENTS(x, num_elements)
|
||||
#define XMP_INVALIDATE_ARRAY_ELEMENTS(x, num_elements)
|
||||
#define XMP_WRITE_BACK_INVALIDATE_ARRAY_ELEMENTS(x, num_elements)
|
||||
#endif
|
||||
|
||||
/* -------------------------------------------------------------------------
|
||||
Initialization, error codes, constants and house-keeping
|
||||
|
||||
Every core should call xmp_init with the number of cores in the
|
||||
system.
|
||||
|
||||
xmp_init should be called before you use any global synchronization
|
||||
primitive or shared data.
|
||||
|
||||
Further, before you use a dynamically allocated synchronization
|
||||
primitives, you need to both initialize it by calling the
|
||||
xmp_*_init function, and you need to have called xmp_init, which
|
||||
sets up interrupt handlers and interrupt routing.
|
||||
|
||||
The second parameter sets the interprocessor interrupt
|
||||
routing. Passing zero instructs the library to use the default
|
||||
routing, which will be suitable for most users.
|
||||
|
||||
*/
|
||||
|
||||
extern void xmp_init (int num_cores, unsigned int interrupt_routing);
|
||||
|
||||
|
||||
/* If you want finer-grained control than that provided by xmp_init,
|
||||
you can the functions below individually--however, this is more
|
||||
inconvenient and requires greater understanding of the library's
|
||||
internals. Don't use them directly unless you have a good reason.
|
||||
*/
|
||||
|
||||
extern void xmp_unpack_shared (void);
|
||||
extern void xmp_route_interrupts (unsigned int routing);
|
||||
|
||||
#if XCHAL_HAVE_MP_INTERRUPTS
|
||||
extern void xmp_enable_ipi_interrupts (void);
|
||||
|
||||
/* Turn off certain things enabled by xmp_init */
|
||||
extern void xmp_disable_ipi_interrupts (void);
|
||||
#endif
|
||||
|
||||
extern void xmp_end (void);
|
||||
|
||||
/* Only valid after xmp_init. */
|
||||
extern int xmp_num_cores (void);
|
||||
|
||||
/* How many cycles should a core wait before rechecking a
|
||||
synchronization variable? Higher values will reduce memory
|
||||
transactions, but will also result in higher latency in returning
|
||||
from synchronization.
|
||||
*/
|
||||
extern void xmp_spin_wait_set_cycles (unsigned int limit);
|
||||
|
||||
/* If you would prefer to provide your own spin wait function,
|
||||
to go to sleep, etc. Declare a function of this type, then call
|
||||
this function. */
|
||||
typedef void (*xmp_spin_wait_function_t)(void);
|
||||
extern void xmp_spin_wait_set_function (xmp_spin_wait_function_t func);
|
||||
extern void xmp_spin(void);
|
||||
|
||||
#define XMP_NO_OWNER 0x07
|
||||
#define XMP_MUTEX_DESTROYED 0xFE
|
||||
#define XMP_ERROR_FATAL 0xFD
|
||||
|
||||
#define XMP_MAX_CORES 0x4
|
||||
|
||||
|
||||
static inline unsigned int xmp_prid (void)
|
||||
{
|
||||
#if XCHAL_HAVE_PRID
|
||||
return XT_RSR_PRID() & 0xFF;
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------------
|
||||
Tracing
|
||||
|
||||
A core must set a trace_file if it wants any synchronization
|
||||
tracing to occur. Sharing file descriptors among cores is very
|
||||
messy, so don't do it. This, unfortunately, means that two cores
|
||||
contending for a mutex are not able to trace to the same file.
|
||||
|
||||
Any object (except the atomic integer) can have tracing off or on.
|
||||
*/
|
||||
|
||||
extern void xmp_set_trace_file (FILE * file);
|
||||
extern void xmp_trace (const char * fmt, ...);
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------------
|
||||
Memory Allocation Functions.
|
||||
|
||||
These do what you would expect, only from shared memory instead of
|
||||
private memory.
|
||||
*/
|
||||
|
||||
#if XCHAL_DCACHE_IS_COHERENT
|
||||
extern void * xmp_malloc (size_t size);
|
||||
extern void * xmp_calloc (size_t nmemb, size_t size);
|
||||
extern void xmp_free (void * ptr);
|
||||
#endif
|
||||
extern void * xmp_sbrk(int size);
|
||||
|
||||
/* -------------------------------------------------------------------------
|
||||
xmp_atomic_int_t
|
||||
|
||||
The most basic synchronization primitive in the xmp library.
|
||||
Atomic ints are sharable among processors, and even interrupt
|
||||
levels on the same processor. However, their semantics are fairly
|
||||
rudimentary. All other primitives are based on these, therefore,
|
||||
changing this implementation affects all other primitives.
|
||||
|
||||
*/
|
||||
|
||||
typedef unsigned int xmp_atomic_int_t;
|
||||
|
||||
static inline xmp_atomic_int_t
|
||||
xmp_coherent_l32ai(xmp_atomic_int_t * address)
|
||||
{
|
||||
XMP_INVALIDATE_ELEMENT (address);
|
||||
return XT_L32AI(address, 0);
|
||||
}
|
||||
|
||||
static inline void
|
||||
xmp_coherent_s32ri(xmp_atomic_int_t value, xmp_atomic_int_t * address)
|
||||
{
|
||||
XT_S32RI (value, address, 0);
|
||||
XMP_WRITE_BACK_ELEMENT (address);
|
||||
}
|
||||
|
||||
#define XMP_ATOMIC_INT_INITIALIZER(value) (value)
|
||||
|
||||
/* xmp_atomic_int_init - Initialize an int prior to use
|
||||
|
||||
Nonsynchronizing, Nonblocking
|
||||
|
||||
Usage:
|
||||
value - initial value
|
||||
integer - points to an uninitialized integer
|
||||
|
||||
On exit:
|
||||
initialized to given value
|
||||
|
||||
Errors: none
|
||||
*/
|
||||
|
||||
static inline void
|
||||
xmp_atomic_int_init (xmp_atomic_int_t * integer, int value)
|
||||
{
|
||||
xmp_coherent_s32ri (value, integer);
|
||||
}
|
||||
|
||||
|
||||
/* xmp_atomic_int_value - Read the value
|
||||
|
||||
Nonsynchronizing, Nonblocking
|
||||
|
||||
Usage:
|
||||
integer - points to an int
|
||||
|
||||
Returns:
|
||||
the value
|
||||
*/
|
||||
|
||||
static inline int
|
||||
xmp_atomic_int_value (xmp_atomic_int_t * integer)
|
||||
{
|
||||
return xmp_coherent_l32ai (integer);
|
||||
}
|
||||
|
||||
|
||||
/* xmp_atomic_int_conditional_increment - Conditionally increment integer
|
||||
|
||||
Synchronizing, nonblocking
|
||||
|
||||
Usage:
|
||||
integer - points to an initialized integer
|
||||
amount - how much to increment
|
||||
prev - believed value of the integer
|
||||
eg: prev = xmp_atomic_int_value (integer);
|
||||
success = xmp_atomic_int_increment (integer, 1, prev);
|
||||
|
||||
Returns: current value of integer - user should check if it matches
|
||||
the previous value of the integer. If it does, then the update
|
||||
was successful.
|
||||
|
||||
*/
|
||||
|
||||
#define USE_ASSEMBLY_IMPLEMENTATION 0
|
||||
|
||||
static inline int
|
||||
xmp_atomic_int_conditional_increment (xmp_atomic_int_t * integer, int amount, int prev)
|
||||
{
|
||||
int val;
|
||||
int saved;
|
||||
|
||||
#if USE_ASSEMBLY_IMPLEMENTATION
|
||||
/* %0 = prev
|
||||
%1 = saved
|
||||
%2 = atomic integer pointer
|
||||
%3 = amount
|
||||
*/
|
||||
|
||||
asm volatile ("wsr.scompare1 %0\n"
|
||||
"mov %1, %0\n"
|
||||
"add %0, %0, %3\n"
|
||||
"s32c1i %0, %2, 0\n"
|
||||
: "+&a" (prev), "+&a"(saved) : "a" (integer), "a" (amount));
|
||||
|
||||
return prev;
|
||||
|
||||
#else
|
||||
|
||||
XT_WSR_SCOMPARE1 (prev);
|
||||
val = prev + amount;
|
||||
saved = val;
|
||||
XT_S32C1I (val, integer, 0);
|
||||
|
||||
return val;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/* xmp_atomic_int_increment - Increment integer
|
||||
|
||||
Synchronizing, blocking
|
||||
|
||||
Usage:
|
||||
integer - points to an initialized integer
|
||||
amount - how much to increment
|
||||
|
||||
Returns: new value of integer
|
||||
|
||||
*/
|
||||
|
||||
static inline int
|
||||
xmp_atomic_int_increment (xmp_atomic_int_t * integer, int amount)
|
||||
{
|
||||
int val;
|
||||
int saved;
|
||||
#if USE_ASSEMBLY_IMPLEMENTATION
|
||||
/* %0 = val
|
||||
%1 = saved
|
||||
%2 = atomic integer pointer
|
||||
%3 = amount
|
||||
*/
|
||||
|
||||
asm volatile ("l32ai %0, %2, 0\n"
|
||||
"1:\n"
|
||||
"wsr.scompare1 %0\n"
|
||||
"mov %1, %0\n"
|
||||
"add %0, %0, %3\n"
|
||||
"s32c1i %0, %2, 0\n"
|
||||
"bne %0, %1, 1b\n"
|
||||
: "+&a" (val), "+&a"(saved) : "a" (integer), "a" (amount));
|
||||
#else
|
||||
/* Accurately naming "val" is tricky. Sometimes it will be what we
|
||||
want to be the new value, but sometimes it contains the value
|
||||
that is currently at the location. */
|
||||
|
||||
/* Load location's current value */
|
||||
val = xmp_coherent_l32ai (integer);
|
||||
|
||||
do {
|
||||
XT_WSR_SCOMPARE1 (val);
|
||||
saved = val;
|
||||
/* Change it to what we would like to store there--"new_val" */
|
||||
val = val + amount;
|
||||
/* Possibly store new_val, but reload location's current value no
|
||||
matter what. */
|
||||
XT_S32C1I (val, integer, 0);
|
||||
if (val != saved)
|
||||
xmp_spin();
|
||||
} while (val != saved);
|
||||
|
||||
#endif
|
||||
return val + amount;
|
||||
}
|
||||
|
||||
|
||||
/* xmp_atomic_int_conditional_set - Set the value of an atomic integer
|
||||
|
||||
Synchronizing, nonblocking
|
||||
|
||||
Usage:
|
||||
integer - points to an initialized integer
|
||||
from - believed value of the integer
|
||||
eg: prev = xmp_atomic_int_value (integer);
|
||||
success = xmp_atomic_int_conditional_set (integer, 1, prev);
|
||||
to - new value
|
||||
|
||||
Returns: current value of integer - user should check if it matches
|
||||
the previous value of the integer. If it does, then the update
|
||||
was successful.
|
||||
|
||||
*/
|
||||
|
||||
static inline int
|
||||
xmp_atomic_int_conditional_set (xmp_atomic_int_t * integer, int from, int to)
|
||||
{
|
||||
int val;
|
||||
|
||||
/* Don't even try to update if the integer's value isn't what we
|
||||
think it should be. This prevents acquiring this cache-line for
|
||||
writing and therefore prevents bus transactions when various
|
||||
cores contend. */
|
||||
val = xmp_coherent_l32ai(integer);
|
||||
if (val == from) {
|
||||
XT_WSR_SCOMPARE1 (from);
|
||||
val = to;
|
||||
/* Possibly store to, but reload location's current value no
|
||||
matter what. */
|
||||
XT_S32C1I (val, integer, 0);
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
|
||||
/* Macros to implement trivial spin locks. These are very primitive, but
|
||||
can be useful when you don't need the higher-overhead synchronization.
|
||||
|
||||
To use an xmp_atomic_int_t as a trivial spin lock, you should
|
||||
initialize it to zero first.
|
||||
*/
|
||||
|
||||
#define XMP_SIMPLE_SPINLOCK_ACQUIRE(atomic_int_ptr) \
|
||||
{ while (xmp_atomic_int_conditional_set (atomic_int_ptr, 0, xmp_prid() + 1) != 0) \
|
||||
xmp_spin(); }
|
||||
#define XMP_SIMPLE_SPINLOCK_RELEASE(atomic_int_ptr) \
|
||||
{ while (xmp_atomic_int_conditional_set (atomic_int_ptr, xmp_prid() + 1, 0) != xmp_prid() + 1) \
|
||||
xmp_spin(); }
|
||||
|
||||
#define XMP_SIMPLE_SPINLOCK_OWNER(atomic_int_ptr) (xmp_atomic_int_value(atomic_int_ptr) - 1)
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------------
|
||||
xmp_mutex_t - An even higher-level data structure to enforce
|
||||
mutual exclusion between cores. A core which waits on a mutex might
|
||||
sleep with a waiti and be interrupted by an interrupt.
|
||||
|
||||
Mutexes can be normal or recursive. For a normal mutex, a core
|
||||
attempting to acquire a mutex it already holds will result in
|
||||
deadlock. For a recursive mutex, a core will succeed in acquiring a
|
||||
mutex it already holds, and must release it as many times as it
|
||||
acquired it.
|
||||
|
||||
Mutexes are not sharable between interrupt levels--because
|
||||
ownership is tracked by core, not thread.
|
||||
|
||||
Like all xmp data structures, an object of type xmp_mutex_t
|
||||
should be treated by the programmer as opaque. They are only
|
||||
public in this header file to allow them to be declared statically.
|
||||
|
||||
For configurations with 16-byte cache lines, this has the most
|
||||
frequently used and changed data in the first line.
|
||||
|
||||
*/
|
||||
|
||||
#if XCHAL_DCACHE_IS_COHERENT
|
||||
typedef struct xmp_mutex_t {
|
||||
xmp_atomic_int_t qlock;
|
||||
unsigned int qhead;
|
||||
unsigned int qtail;
|
||||
unsigned char queue[XMP_MAX_CORES];
|
||||
unsigned short held;
|
||||
|
||||
unsigned char owner;
|
||||
unsigned char recursive : 1;
|
||||
unsigned char trace : 1;
|
||||
unsigned char system : 1;
|
||||
unsigned char unused : 5;
|
||||
const char * name;
|
||||
} xmp_mutex_t __attribute__ ((aligned (XMP_MAX_DCACHE_LINESIZE)));
|
||||
|
||||
|
||||
#define XMP_MUTEX_INITIALIZER(name) \
|
||||
{ 0, 0, -1, {XMP_NO_OWNER, XMP_NO_OWNER, XMP_NO_OWNER, XMP_NO_OWNER}, \
|
||||
0, XMP_NO_OWNER, XMP_MUTEX_FLAG_NORMAL, 0, 0, 0, name }
|
||||
|
||||
#define XMP_RECURSIVE_MUTEX_INITIALIZER(name) \
|
||||
{ 0, 0, -1, {XMP_NO_OWNER, XMP_NO_OWNER, XMP_NO_OWNER, XMP_NO_OWNER}, \
|
||||
0, XMP_NO_OWNER, XMP_MUTEX_FLAG_RECURSIVE, 0, 0, 0, name }
|
||||
|
||||
#define XMP_MUTEX_FLAG_NORMAL 0
|
||||
#define XMP_MUTEX_FLAG_RECURSIVE 1
|
||||
|
||||
#define XMP_MUTEX_ACQUIRE_FAILED -1
|
||||
#define XMP_MUTEX_ERROR_DESTROY_OWNED -2
|
||||
#define XMP_MUTEX_ERROR_NOT_OWNED -3
|
||||
#define XMP_MUTEX_ERROR_ALREADY_OWNED -4
|
||||
|
||||
/*
|
||||
xmp_mutex_init
|
||||
|
||||
Nonsynchronizing
|
||||
Nonblocking
|
||||
|
||||
Usage:
|
||||
mutex - points to an uninitialized mutex
|
||||
name - name if you want one, NULL if not.
|
||||
recursive - use recursive semantices
|
||||
|
||||
Returns
|
||||
zero on success (always succeeds)
|
||||
|
||||
*/
|
||||
|
||||
extern int xmp_mutex_init (xmp_mutex_t * mutex,
|
||||
const char * name,
|
||||
unsigned int recursive);
|
||||
|
||||
/*
|
||||
int xmp_mutex_destroy (xmp_mutex_t * mutex);
|
||||
|
||||
Synchronizing - will fail if mutex is held by anyone -- including
|
||||
current processor
|
||||
Nonblocking
|
||||
|
||||
Usage:
|
||||
mutex - points to a mutex
|
||||
|
||||
Returns
|
||||
zero on success
|
||||
non-zero if mutex is held
|
||||
*/
|
||||
|
||||
extern int xmp_mutex_destroy (xmp_mutex_t * mutex);
|
||||
|
||||
|
||||
/*
|
||||
xmp_mutex_lock -- Synchronizing
|
||||
xmp_mutex_trylock
|
||||
|
||||
Usage:
|
||||
mutex - points to a mutex
|
||||
|
||||
Returns
|
||||
zero on success
|
||||
*/
|
||||
|
||||
extern int xmp_mutex_lock (xmp_mutex_t * mutex);
|
||||
extern int xmp_mutex_trylock (xmp_mutex_t * mutex);
|
||||
|
||||
|
||||
/*
|
||||
xmp_mutex_unlock
|
||||
|
||||
Synchronizing
|
||||
Nonblocking
|
||||
|
||||
Usage:
|
||||
mutex - points to a mutex
|
||||
|
||||
Returns
|
||||
zero on success - mutex is released
|
||||
non-zero on failure - mutex is owned by another core
|
||||
- prid of processor that does own it
|
||||
note that by the time this function
|
||||
returns, the owner of the core may
|
||||
have changed.
|
||||
*/
|
||||
|
||||
extern int xmp_mutex_unlock (xmp_mutex_t * mutex);
|
||||
|
||||
|
||||
/*
|
||||
xmp_mutex_name
|
||||
|
||||
Nonsynchronizing
|
||||
Nonblocking
|
||||
|
||||
Usage:
|
||||
mutex - points to a mutex
|
||||
|
||||
Returns the name of the given mutex, which may be NULL.
|
||||
|
||||
*/
|
||||
|
||||
const char * xmp_mutex_name (const xmp_mutex_t * mutex);
|
||||
|
||||
|
||||
/*
|
||||
xmp_mutex_trace_on
|
||||
xmp_mutex_trace_off
|
||||
|
||||
Nonsynchronizing
|
||||
Nonblocking
|
||||
|
||||
Turn off and on tracing for the mutex.
|
||||
|
||||
These functions are only present in the debug version of the library.
|
||||
*/
|
||||
|
||||
extern void xmp_mutex_trace_on (xmp_mutex_t * mutex);
|
||||
extern void xmp_mutex_trace_off (xmp_mutex_t * mutex);
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------------
|
||||
xmp_condition_t
|
||||
|
||||
Condition Variables following Mesa semantics.
|
||||
|
||||
Condition variables are not sharable among interrupt levels.
|
||||
|
||||
*/
|
||||
|
||||
|
||||
typedef struct xmp_condition_t {
|
||||
unsigned int qhead;
|
||||
unsigned int qtail;
|
||||
unsigned char queue[XMP_MAX_CORES];
|
||||
unsigned int waiting[XMP_MAX_CORES];
|
||||
|
||||
unsigned char trace : 1;
|
||||
unsigned char unused : 7;
|
||||
const char * name;
|
||||
} xmp_condition_t __attribute__ ((aligned (XMP_MAX_DCACHE_LINESIZE)));
|
||||
|
||||
|
||||
#define XMP_CONDITION_INITIALIZER(name) \
|
||||
{ 0, -1, {XMP_NO_OWNER, XMP_NO_OWNER, XMP_NO_OWNER, XMP_NO_OWNER}, \
|
||||
{0, 0, 0, 0}, 0, 0, name}
|
||||
|
||||
|
||||
/* xmp_condition_init - Initialize a condition variable
|
||||
|
||||
Nonsynchronizing, Nonblocking
|
||||
|
||||
Usage:
|
||||
condition - pointer to an xmp_condition_t
|
||||
|
||||
On exit:
|
||||
condition initialized
|
||||
|
||||
Errors: none
|
||||
*/
|
||||
|
||||
extern int xmp_condition_init (xmp_condition_t * condition,
|
||||
const char * name);
|
||||
extern int xmp_condition_destroy (xmp_condition_t * condition);
|
||||
|
||||
|
||||
/* xmp_condition_wait - Wait for a condition variable
|
||||
|
||||
Synchronizing, blocking
|
||||
|
||||
Usage:
|
||||
condition - pointer to an xmp_condition_t
|
||||
mutex - pointer to an xmp_mutex_t already acquired by the calling
|
||||
process
|
||||
|
||||
Errors: if the mutex isn't held by this core
|
||||
*/
|
||||
|
||||
extern int xmp_condition_wait (xmp_condition_t * condition,
|
||||
xmp_mutex_t * mutex);
|
||||
|
||||
/* xmp_condition_signal
|
||||
|
||||
- Signal the first (if any) core waiting on a condition variable
|
||||
|
||||
You must hold the mutex you passed to xmp_condition_wait before
|
||||
calling this function.
|
||||
|
||||
Synchronizing, nonblocking
|
||||
|
||||
Usage:
|
||||
condition - pointer to an xmp_condition_t
|
||||
|
||||
Errors: none
|
||||
*/
|
||||
|
||||
extern int xmp_condition_signal (xmp_condition_t * condition);
|
||||
|
||||
|
||||
/* xmp_condition_broadcast
|
||||
|
||||
- Signal all cores waiting on a condition variable
|
||||
|
||||
Synchronizing, nonblocking
|
||||
|
||||
You must hold the mutex you passed to xmp_condition_wait before
|
||||
calling this function.
|
||||
|
||||
Usage:
|
||||
condition - pointer to an xmp_condition_t
|
||||
|
||||
Errors: none
|
||||
*/
|
||||
|
||||
extern int xmp_condition_broadcast (xmp_condition_t * condition);
|
||||
|
||||
|
||||
static inline const char * xmp_condition_name (const xmp_condition_t * condition)
|
||||
{
|
||||
return condition->name;
|
||||
}
|
||||
|
||||
/*
|
||||
xmp_condition_trace_on
|
||||
xmp_condition_trace_off
|
||||
|
||||
Nonsynchronizing
|
||||
Nonblocking
|
||||
|
||||
Turn off and on statistics and tracing for the condition. For
|
||||
tracing you must also set a trace file for the core.
|
||||
|
||||
These functions are only present in the debug-version of the library.
|
||||
*/
|
||||
|
||||
extern void xmp_condition_trace_on (xmp_condition_t * condition);
|
||||
extern void xmp_condition_trace_off (xmp_condition_t * condition);
|
||||
|
||||
#endif /* XCHAL_DCACHE_IS_COHERENT */
|
||||
|
||||
/* -------------------------------------------------------------------------
|
||||
xmp_barrier_t
|
||||
|
||||
Classic barriers that stop any core from continuing until a
|
||||
specified number of cores reach that point. Once the barrier allows
|
||||
cores through, the barrier is reset and will stop cores from
|
||||
progressing again.
|
||||
|
||||
Barriers are not sharable among interrupt levels.
|
||||
|
||||
*/
|
||||
|
||||
|
||||
typedef struct xmp_barrier_t
|
||||
{
|
||||
xmp_atomic_int_t count;
|
||||
xmp_atomic_int_t state;
|
||||
xmp_atomic_int_t sleeping;
|
||||
unsigned short num_cores;
|
||||
unsigned short trace : 1;
|
||||
unsigned short system : 1;
|
||||
const char * name;
|
||||
} xmp_barrier_t __attribute__ ((aligned (XMP_MAX_DCACHE_LINESIZE)));
|
||||
|
||||
#define XMP_BARRIER_INITIALIZER(number, name) \
|
||||
{ 0, 0, 0, number, 0, 0, name }
|
||||
|
||||
|
||||
/* xmp_barrier_init - Initialize a barrier
|
||||
|
||||
Nonsynchronizing, Nonblocking
|
||||
|
||||
Usage:
|
||||
barrier - pointer to an xmp_barrier_t
|
||||
num_cores - number of cores needed to arrive at the
|
||||
barrier before any are allowed through
|
||||
On exit:
|
||||
barrier initialized
|
||||
|
||||
Always returns zero.
|
||||
|
||||
Errors: none
|
||||
*/
|
||||
|
||||
extern int xmp_barrier_init (xmp_barrier_t * barrier, int num_cores,
|
||||
const char * name);
|
||||
|
||||
|
||||
/* xmp_barrier_wait - Wait on a barrier
|
||||
|
||||
Nonsynchronizing, Nonblocking
|
||||
|
||||
Usage:
|
||||
barrier - pointer to an xmp_barrier_t
|
||||
On exit:
|
||||
Enough cores (as determined at the barrier's initialization)
|
||||
have reached the barrier.
|
||||
|
||||
Errors: none
|
||||
*/
|
||||
|
||||
extern int xmp_barrier_wait (xmp_barrier_t * barrier);
|
||||
|
||||
|
||||
static inline const char * xmp_barrier_name (const xmp_barrier_t * barrier)
|
||||
{
|
||||
return barrier->name;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
xmp_barrier_trace_on
|
||||
xmp_barrier_trace_off
|
||||
|
||||
Nonsynchronizing
|
||||
Nonblocking
|
||||
|
||||
Turn on and off tracing for the barrier. For
|
||||
tracing you must also set a trace file for the core.
|
||||
|
||||
These functions are only present in the debug-version of the library.
|
||||
*/
|
||||
|
||||
extern void xmp_barrier_trace_on (xmp_barrier_t * barrier);
|
||||
extern void xmp_barrier_trace_off (xmp_barrier_t * barrier);
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------------
|
||||
Portions of the library that are internal, but belong here for
|
||||
convenience.
|
||||
*/
|
||||
|
||||
extern xmp_atomic_int_t _ResetSync;
|
||||
|
||||
static inline void
|
||||
xmp_initial_sync (int num_cores)
|
||||
{
|
||||
xmp_atomic_int_increment (&_ResetSync, 1);
|
||||
while (xmp_coherent_l32ai (&_ResetSync) != num_cores)
|
||||
xmp_spin ();
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _XMP_LIBRARY_H */
|
||||
Executable
+524
@@ -0,0 +1,524 @@
|
||||
/** @file */
|
||||
|
||||
// xos.h - XOS API interface and data structures visible to user code.
|
||||
|
||||
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining
|
||||
// a copy of this software and associated documentation files (the
|
||||
// "Software"), to deal in the Software without restriction, including
|
||||
// without limitation the rights to use, copy, modify, merge, publish,
|
||||
// distribute, sublicense, and/or sell copies of the Software, and to
|
||||
// permit persons to whom the Software is furnished to do so, subject to
|
||||
// the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
|
||||
#ifndef __XOS_H__
|
||||
#define __XOS_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#include "xos_types.h"
|
||||
|
||||
#include <xtensa/config/core.h>
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
#include <xtensa/tie/xt_core.h>
|
||||
#include <xtensa/tie/xt_interrupt.h>
|
||||
#endif
|
||||
|
||||
#include "xos_common.h"
|
||||
#include "xos_errors.h"
|
||||
#include "xos_regaccess.h"
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Convert x into a literal string.
|
||||
//-----------------------------------------------------------------------------
|
||||
#define _XOS_STR(x) __XOS_STR(x)
|
||||
#define __XOS_STR(x) #x
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// XOS version.
|
||||
//-----------------------------------------------------------------------------
|
||||
#define XOS_VERSION_MAJOR 1
|
||||
#define XOS_VERSION_MINOR 10
|
||||
#define XOS_VERSION_STRING "1.10" ///< XOS version string.
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Runtime error handling.
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Reports a fatal error and halts XOS operation, i.e. halts the system. This
|
||||
/// function will call a user-registered error handler (if one has been set)
|
||||
/// and then halt the system. The user handler may do system-specific things
|
||||
/// such as record the error reason in nonvolatile memory etc.
|
||||
///
|
||||
/// \param errcode Error code. May be any user defined value < 0.
|
||||
/// Values >=0 are reserved for use by the system.
|
||||
///
|
||||
/// \param errmsg Optional text string describing the error.
|
||||
///
|
||||
/// \return This function does not return.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
void
|
||||
xos_fatal_error(int32_t errcode, const char * errmsg);
|
||||
|
||||
|
||||
#if XOS_DEBUG
|
||||
|
||||
// Do not call directly.
|
||||
void
|
||||
xos_assert(const char * file, int32_t line);
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Check condition and fail if condition expression is false.
|
||||
/// In debug builds, an assertion failure will cause a fatal error to be
|
||||
/// reported. In non-debug builds, assertions are compiled out.
|
||||
///
|
||||
/// NOTE: Remember that any code in XOS_ASSERT() statements gets compiled out
|
||||
/// for non-debug builds.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
#define XOS_ASSERT(expr) if ((expr) == 0) xos_assert(__FILE__, __LINE__)
|
||||
|
||||
#else
|
||||
|
||||
#define XOS_ASSERT(expr)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Interrupt handler function pointer type.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
typedef void (XosIntFunc)(void * arg);
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Print handler function pointer type.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
typedef int32_t (XosPrintFunc)(void * arg, const char * fmt, ...);
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Fatal error handler function pointer type.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
typedef void (XosFatalErrFunc)(int32_t errcode, const char * errmsg);
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Exception handler function pointer type.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
typedef void (XosExcHandlerFunc)(XosExcFrame * frame);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Install a user defined exception handler for the specified exception type.
|
||||
/// This will override the default XOS exception handler. The handler is a C
|
||||
/// function that is passed one parameter -- a pointer to the exception frame.
|
||||
/// The exception frame is allocated on the stack of the thread that caused the
|
||||
/// exception, and contains saved state and exception information. For details
|
||||
/// of the exception frame see the structure XosExcFrame.
|
||||
///
|
||||
/// \param exc Exception type (number) to override. The exception
|
||||
/// numbers are enumerated in <xtensa/corebits.h>.
|
||||
///
|
||||
/// \param handler Pointer to handler function to be installed.
|
||||
/// To revert to the default handler, pass NULL.
|
||||
///
|
||||
/// \return Returns a pointer to previous handler installed, if any.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
XosExcHandlerFunc *
|
||||
xos_register_exception_handler(int32_t exc, XosExcHandlerFunc * handler);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Install a user defined fatal error handler. This function will be called if
|
||||
/// a fatal error is reported either by user code or by XOS itself. It will be
|
||||
/// passed the same arguments that are passed to xos_fatal_error().
|
||||
///
|
||||
/// The handler need not return. It should make minimal assumptions about the
|
||||
/// state of the system. In particular, it should not assume that further XOS
|
||||
/// system calls will succeed.
|
||||
///
|
||||
/// \param handler Pointer to handler function to be installed.
|
||||
///
|
||||
/// \return Returns a pointer to previous handler installed, if any.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
XosFatalErrFunc *
|
||||
xos_register_fatal_error_handler(XosFatalErrFunc * handler);
|
||||
|
||||
|
||||
#ifdef _XOS_INCLUDE_INTERNAL_
|
||||
# include "xos_internal.h"
|
||||
#endif
|
||||
|
||||
|
||||
#include "xos_thread.h"
|
||||
#include "xos_timer.h"
|
||||
#include "xos_cond.h"
|
||||
#include "xos_event.h"
|
||||
#include "xos_mutex.h"
|
||||
#include "xos_msgq.h"
|
||||
#include "xos_semaphore.h"
|
||||
#include "xos_stopwatch.h"
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Register a handler function to call when interrupt "num" occurs.
|
||||
///
|
||||
/// For level-triggered and timer interrupts, the handler function will have
|
||||
/// to clear the source of the interrupt before returning, to avoid infinitely
|
||||
/// retaking the interrupt. Edge-triggered and software interrupts are
|
||||
/// automatically cleared by the OS interrupt dispatcher (see xos_handlers.S).
|
||||
///
|
||||
/// \param num Xtensa internal interrupt number (0..31). To
|
||||
/// refer to a specific external interrupt number
|
||||
/// (BInterrupt pin), use HAL macro XCHAL_EXTINTx_NUM
|
||||
/// where 'x' is the external number.
|
||||
///
|
||||
/// \param handler Pointer to handler function.
|
||||
///
|
||||
/// \param arg Argument passed to handler.
|
||||
///
|
||||
/// \return Returns XOS_OK if successful, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_register_interrupt_handler(int32_t num, XosIntFunc * handler, void * arg);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Unregister a handler function for interrupt "num". If no handler was
|
||||
/// installed, this function will have no effect.
|
||||
///
|
||||
/// \param num Xtensa internal interrupt number (0..31). To
|
||||
/// refer to a specific external interrupt number
|
||||
/// (BInterrupt pin), use HAL macro XCHAL_EXTINTx_NUM
|
||||
/// where 'x' is the external number.
|
||||
///
|
||||
/// \return Returns XOS_OK if successful, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_unregister_interrupt_handler(int32_t num);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Register a high priority interrupt handler for interrupt level "level".
|
||||
///
|
||||
/// Unlike low and medium priority interrupt handlers, high priority handlers
|
||||
/// are not installed for a specific interrupt number, but for an interrupt
|
||||
/// level. The level must be above XCHAL_EXCM_LEVEL. The handler function must
|
||||
/// be written in assembly since C handlers are not supported for levels above
|
||||
/// XCHAL_EXCM_LEVEL. The handler function must preserve all registers except
|
||||
/// a0, and must return to the dispatcher via a "ret" instruction, not "rfi".
|
||||
///
|
||||
/// NOTE: This method of dispatch takes a few cycles of overhead. If you wish
|
||||
/// to save even these cycles, then you can define your own dispatch function
|
||||
/// to override the built-in dispatcher. See xos_handlers.S for more details.
|
||||
///
|
||||
/// \param level The interrupt level to be handled.
|
||||
///
|
||||
/// \param handler Pointer to handler function.
|
||||
///
|
||||
/// \return Returns XOS_OK if successful, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_register_hp_interrupt_handler(int32_t level, void * handler);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Enable a specific interrupt, by interrupt number.
|
||||
/// The state (enabled vs. disabled) of individual interrupts is global, i.e.
|
||||
/// not associated with any specific thread. Depending on system options and
|
||||
/// implementation, this state may be stored in one of two ways:
|
||||
/// - directly in the INTENABLE register, or
|
||||
/// - in a global variable (this is generally the case when INTENABLE is used
|
||||
/// not just to control what interrupts are enabled globally, but also for
|
||||
/// software interrupt prioritization within an interrupt level, effectively
|
||||
/// providing finer grained levels; in this case XOS takes care to update
|
||||
/// INTENABLE whenever either the global enabled-state variable or the
|
||||
/// per-thread fine-grained-level variable change).
|
||||
/// Thus it is best to never access the INTENABLE register directly.
|
||||
///
|
||||
/// To modify thread-specific interrupt priority level, use one of:
|
||||
/// - xos_set_int_pri_level()
|
||||
/// - xos_restore_int_pri_level()
|
||||
/// - xos_disable_interrupts()
|
||||
/// - xos_restore_interrupts()
|
||||
///
|
||||
/// NOTE: To refer to a specific external interrupt number (BInterrupt pin),
|
||||
/// use HAL macro XCHAL_EXTINTx_NUM where 'x' is the external interrupt
|
||||
/// number. For example, to enable external interrupt 3 (BInterrupt[3]),
|
||||
/// you can use:
|
||||
///
|
||||
/// xos_interrupt_enable( XCHAL_EXTINT3_NUM );
|
||||
///
|
||||
/// \param intnum Interrupt number to enable. Must range between 0-31.
|
||||
///
|
||||
/// \return Returns nothing.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
void
|
||||
xos_interrupt_enable(uint32_t intnum);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Disable a specific individual interrupt, by interrupt number.
|
||||
///
|
||||
/// This is the counterpart to xos_interrupt_enable(). See the description
|
||||
/// of xos_interrupt_enable() for further comments and notes.
|
||||
///
|
||||
/// \param intnum Interrupt number to disable. Must range between 0-31.
|
||||
///
|
||||
/// \return Returns nothing.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
void
|
||||
xos_interrupt_disable(uint32_t intnum);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Get the CPU's current interrupt priority level. Interrupts at or below this
|
||||
/// priority level are blocked.
|
||||
///
|
||||
/// \return Returns the current IPL, ranging from 0 to XCHAL_NUM_INTLEVELS.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
static inline uint32_t
|
||||
xos_get_int_pri_level(void)
|
||||
{
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
return XT_RSR_PS() & 0xF;
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Set the CPU's interrupt priority level to the specified level, but only if
|
||||
/// the current IPL is below the one requested. This function will never cause
|
||||
/// the interrupt priority level to be lowered from the current level.
|
||||
/// Call this function to block interrupts at or below the specified priority
|
||||
/// level.
|
||||
///
|
||||
/// When setting the IPL temporarily (such as in a critical section), call
|
||||
/// xos_set_int_pri_level(), execute the critical code section, and then call
|
||||
/// xos_restore_int_pri_level().
|
||||
///
|
||||
/// The interrupt priority level is part of the thread context, so it is saved
|
||||
/// and restored across context switches. To enable and disable individual
|
||||
/// interrupts globally, use the functions xos_interrupt_enable() and
|
||||
/// xos_interrupt_disable() instead.
|
||||
///
|
||||
/// NOTE: It is usually not required to disable interrupts at a level higher
|
||||
/// than that of the highest priority interrupt that interacts with the OS
|
||||
/// (i.e. calls into XOS such that threads may be woken / blocked /
|
||||
/// reprioritized / switched, or otherwise access XOS data structures).
|
||||
/// In XOS, that maximum level is XOS_MAX_OS_INTLEVEL, which defaults to
|
||||
/// XCHAL_EXCM_LEVEL. This may be modified by editing xos_params.h and
|
||||
/// rebuilding XOS.
|
||||
///
|
||||
/// \param level The new interrupt priority level (IPL).
|
||||
///
|
||||
/// \return Returns a value that can be used to restore the previous
|
||||
/// priority level by calling xos_restore_int_pri_level(). This
|
||||
/// value should be treated as opaque by application code, and
|
||||
/// should be passed unchanged to the restore function.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t
|
||||
xos_set_int_pri_level(uint32_t level)
|
||||
{
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
#pragma no_reorder
|
||||
uint32_t ps = XT_RSR_PS();
|
||||
|
||||
if (level > (ps & 0xF)) {
|
||||
level = (ps & ~0xF) | level;
|
||||
XT_WSR_PS(level);
|
||||
XT_RSYNC();
|
||||
}
|
||||
|
||||
return ps;
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Restores the CPU to a previously saved interrupt priority level. This level
|
||||
/// must have been obtained by calling xos_set_int_pri_level().
|
||||
///
|
||||
/// \param oldval Return value from xos_set_int_pri_level().
|
||||
///
|
||||
/// \return Returns nothing.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
__attribute__((always_inline))
|
||||
static inline void
|
||||
xos_restore_int_pri_level(const uint32_t oldval)
|
||||
{
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
#pragma no_reorder
|
||||
XT_WSR_PS(oldval);
|
||||
XT_RSYNC();
|
||||
#else
|
||||
// Nothing
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Disable all interrupts that can interact directly with the OS. This is a
|
||||
/// convenience function, shorthand for setting the IPL to XOS_MAX_OS_INTLEVEL.
|
||||
///
|
||||
/// Returns: A value that can be used to restore the previous priority level
|
||||
/// by calling xos_restore_interrupts(). This value should be treated as
|
||||
/// opaque by application code, and should be passed unchanged to the restore
|
||||
/// function.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
static inline uint32_t
|
||||
xos_disable_interrupts(void)
|
||||
{
|
||||
return xos_set_int_pri_level(XOS_MAX_OS_INTLEVEL);
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Restore the CPU's previously saved interrupt status. This is a convenience
|
||||
/// function, the counterpart to xos_disable_interrupts().
|
||||
///
|
||||
/// \return rval Return value from xos_disable_interrupts().
|
||||
///
|
||||
/// \return Returns nothing.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
static inline void
|
||||
xos_restore_interrupts(uint32_t rval)
|
||||
{
|
||||
xos_restore_int_pri_level(rval);
|
||||
}
|
||||
|
||||
|
||||
#ifdef _XOS_INCLUDE_INTERNAL_
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Enter an OS critical section, i.e. get exclusive access to OS critical
|
||||
// state and data structures. Code that manipulates the state of OS objects
|
||||
// or modifies internal OS state must call this function first, to ensure
|
||||
// that it has exclusive access. On a single-core system, this is equivalent
|
||||
// to blocking all interrupts that can interact directly with the OS, i.e.
|
||||
// all interrupts at or below XOS_MAX_OS_INTLEVEL. In a multi-core system
|
||||
// this is likely to be implemented differently to achieve the same effect.
|
||||
//
|
||||
// Returns: A value that is to be used to restore the state of the CPU when
|
||||
// exiting the critical section. This must be treated as opaque and passed
|
||||
// unmodified to xos_critical_exit().
|
||||
//
|
||||
// NOTE: This function is meant for use in OS code, not in applications.
|
||||
//-----------------------------------------------------------------------------
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t
|
||||
xos_critical_enter(void)
|
||||
{
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
// This function cannot be called by high-level interrupt handlers,
|
||||
// i.e. it can never be called with intlevel > XOS_MAX_OS_INTLEVEL.
|
||||
// So, we do not need to check current intlevel because we will not
|
||||
// ever be lowering it by setting it to XOS_MAX_OS_INTLEVEL.
|
||||
// NOTE: sync after RSIL not needed.
|
||||
return XT_RSIL(XOS_MAX_OS_INTLEVEL);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Exit an OS critical section and restore CPU state. See the documentation
|
||||
// for xos_critical_enter().
|
||||
//
|
||||
// cflags Return value from xos_critical_enter().
|
||||
// Must be treated as an opaque value.
|
||||
//
|
||||
// Returns: Nothing.
|
||||
//
|
||||
// NOTE: This function is meant for use in OS code, not in applications.
|
||||
//-----------------------------------------------------------------------------
|
||||
__attribute__((always_inline))
|
||||
static inline void
|
||||
xos_critical_exit(uint32_t cflags)
|
||||
{
|
||||
xos_restore_int_pri_level(cflags);
|
||||
}
|
||||
|
||||
#endif // _XOS_INCLUDE_INTERNAL_
|
||||
|
||||
|
||||
// This file uses things defined above
|
||||
#include "xos_syslog.h"
|
||||
|
||||
|
||||
// Misc
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Helper function to list all threads in system. Useful for debug.
|
||||
//-----------------------------------------------------------------------------
|
||||
void
|
||||
xos_display_threads(void * arg, XosPrintFunc * print_fn);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __XOS_H__
|
||||
|
||||
Executable
+362
@@ -0,0 +1,362 @@
|
||||
|
||||
// xos_common.h - Macros and definitions common to C and assembly code.
|
||||
|
||||
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining
|
||||
// a copy of this software and associated documentation files (the
|
||||
// "Software"), to deal in the Software without restriction, including
|
||||
// without limitation the rights to use, copy, modify, merge, publish,
|
||||
// distribute, sublicense, and/or sell copies of the Software, and to
|
||||
// permit persons to whom the Software is furnished to do so, subject to
|
||||
// the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
|
||||
#ifndef __XOS_COMMON_H__
|
||||
#define __XOS_COMMON_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#include <xtensa/corebits.h>
|
||||
#include <xtensa/config/system.h>
|
||||
#include <xtensa/config/tie.h>
|
||||
|
||||
#include "xos_params.h"
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Macros that help define structures for both C and assembler.
|
||||
// These are somewhat different from the XTOS version in xtruntime-frames.h.
|
||||
//-----------------------------------------------------------------------------
|
||||
#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
|
||||
|
||||
#define STRUCT_BEGIN .pushsection .text; .struct 0
|
||||
#define STRUCT_FIELD(ctype,size,asname,name) asname: .space size
|
||||
#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space (size)*(n)
|
||||
#define STRUCT_END(sname) sname##Size:; .popsection
|
||||
|
||||
#else
|
||||
|
||||
#define STRUCT_BEGIN typedef struct {
|
||||
#define STRUCT_FIELD(ctype,size,asname,name) ctype name;
|
||||
#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n];
|
||||
#define STRUCT_END(sname) } sname;
|
||||
|
||||
#endif //_ASMLANGUAGE || __ASSEMBLER__
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Offsets relative to xos_globals.
|
||||
//-----------------------------------------------------------------------------
|
||||
#define XOS_INTLEVEL_MASK 0 // offset to the level mask
|
||||
#define XOS_INTENABLE_MASK 4 // offset to the enable mask
|
||||
#define XOS_CURR_THREADPTR 8 // offset to the current thread ptr
|
||||
#define XOS_NEXT_THREADPTR 12 // offset to the next thread ptr
|
||||
#define XOS_INTERRUPT_TABLE 16 // offset to the interrupt table
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Offsets for xos_interrupt_table[] entries.
|
||||
//-----------------------------------------------------------------------------
|
||||
#define XOS_INTTAB_HANDLER (XOS_INTERRUPT_TABLE+0) // ofs to interrupt handler
|
||||
#define XOS_INTTAB_ARG (XOS_INTERRUPT_TABLE+4) // ofs to interrupt handler arg
|
||||
#define XOS_INTTAB_PS (XOS_INTERRUPT_TABLE+8) // (hwpri) PS for interrupt level
|
||||
#define XOS_INTTAB_LEVEL (XOS_INTERRUPT_TABLE+8) // (swpri) interrupt level (1..7)
|
||||
#define XOS_INTTAB_PRI (XOS_INTERRUPT_TABLE+9) // (swpri) interrupt priority (0..255)
|
||||
#define XOS_INTTAB_PRIMASK (XOS_INTERRUPT_TABLE+12) // (swpri) mask of higher pri. interrupts
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Exception/interrupt stack frame layout for a pre-empted thread
|
||||
// tcb->resume_fn == &xos_resume_preempted_thread).
|
||||
// Pointed to by thread->esf. Located just below thread's current stack ptr.
|
||||
// Thread's a1 == thread->esf + XosExcFrameSize.
|
||||
// NOTE: exception frame size is a multiple of 16.
|
||||
//-----------------------------------------------------------------------------
|
||||
STRUCT_BEGIN
|
||||
STRUCT_AFIELD(long,4,FRAME_AREG,areg, 12) // a4-a15 (offsets 0 thru 44)
|
||||
// (a1 is computed, a0,a2-a3 are in s32e range of a1)
|
||||
//#if XCHAL_HAVE_LOOPS
|
||||
STRUCT_FIELD (long,4,FRAME_LBEG,lbeg)
|
||||
STRUCT_FIELD (long,4,FRAME_LEND,lend)
|
||||
STRUCT_FIELD (long,4,FRAME_LCOUNT,lcount)
|
||||
//#endif
|
||||
//#if XCHAL_HAVE_MAC16
|
||||
STRUCT_FIELD (long,4,FRAME_ACCLO,acclo)
|
||||
STRUCT_FIELD (char,1,FRAME_ACCHI,acchi)
|
||||
//#endif
|
||||
STRUCT_FIELD (char,1,FRAME_SAR,sar)
|
||||
STRUCT_FIELD (short,2,FRAME_PAD0,pad0) // unused
|
||||
STRUCT_FIELD (long,4,FRAME_EXCCAUSE,exccause)
|
||||
STRUCT_FIELD (long,4,FRAME_EXCVADDR,excvaddr)
|
||||
STRUCT_FIELD (long,4,FRAME_PAD1,pad1) // unused -- pad to make multiple of 16 bytes
|
||||
STRUCT_FIELD (long,4,FRAME_PAD2,pad2)
|
||||
STRUCT_FIELD (long,4,FRAME_PS,ps) // (XOS_FRAME_SIZE-44) in S32E range of end
|
||||
STRUCT_FIELD (long,4,FRAME_PC,pc) // (XOS_FRAME_SIZE-40) in S32E range of end
|
||||
STRUCT_FIELD (long,4,FRAME_A0,a0)
|
||||
STRUCT_FIELD (long,4,FRAME_A2,a2) // (XOS_FRAME_SIZE-32) in S32E range of end
|
||||
STRUCT_FIELD (long,4,FRAME_A3,a3) // (XOS_FRAME_SIZE-28) in S32E range of end
|
||||
STRUCT_FIELD (long,4,FRAME_LEVELMASK,levelmask) //
|
||||
STRUCT_FIELD (long,4,FRAME_NESTCHAIN,nestchain) // nested C function call chain ptr
|
||||
// Caller's a0-a3 save area below SP. These fields MUST be the last ones in the
|
||||
// struct so that they are guaranteed to be just under the original SP (before
|
||||
// we allocate the exception frame).
|
||||
STRUCT_AFIELD (long,4,FRAME_CWINSAVE,cwinsave, 4) // (XOS_FRAME_SIZE-16)
|
||||
STRUCT_END(XosExcFrame) // NOTE: exception frame size is 128
|
||||
|
||||
#define FRAME_AR(x) (FRAME_AREG + x*4 - 16)
|
||||
|
||||
#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
|
||||
#define XOS_FRAME_SIZE XosExcFrameSize
|
||||
#else
|
||||
#define XOS_FRAME_SIZE sizeof(XosExcFrame)
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Stack frame layout for a cooperatively switched out thread
|
||||
// (tcb->resume_fn == &xos_resume_cooperative_thread).
|
||||
// Pointed to by thread->esf. This is a function frame.
|
||||
// Thread's a1 == thread->esf.
|
||||
//-----------------------------------------------------------------------------
|
||||
STRUCT_BEGIN
|
||||
STRUCT_FIELD (long,4,CFRAME_A0,a0) // return PC
|
||||
STRUCT_FIELD (long,4,CFRAME_LEVELMASK,levelmask)
|
||||
STRUCT_FIELD (long,4,CFRAME_PS,ps)
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
STRUCT_FIELD (long,4,CFRAME_PAD0,pad0)
|
||||
STRUCT_AFIELD(long,4,CFRAME_AREG,areg,4) // callee-saved regs a12-a15
|
||||
#endif
|
||||
STRUCT_END(XosCoopFrame)
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Offsets into thread control block (must match xos_thread.h !!)
|
||||
//-----------------------------------------------------------------------------
|
||||
#define TCB_RESUME_FN 12 // ptr to thread resume asm sequence
|
||||
#define TCB_STACK_ESF 16 // saved stack ptr (actually, ptr to ESF)
|
||||
#define TCB_TIE_SAVE 20 // ptr to TIE save area
|
||||
#define TCB_RETVALUE 24 // ptr to xos_block return value
|
||||
#define TCB_STACK_END 36 // ptr to end of stack (thread's initial stack ptr)
|
||||
#define TCB_STARTUP_ENTRY 40 // ptr to thread entry function
|
||||
#define TCB_STARTUP_ARG 44 // ptr to thread entry function's arg
|
||||
#define TCB_READY 48 // thread ready state (1 byte)
|
||||
#define TCB_CLIB_PTR 108 // thread C lib context pointer
|
||||
|
||||
#define TCB_RESUME_CCOUNT 116 // cycle count at last resume
|
||||
#define TCB_CYCLE_COUNT 120 // number of cycles consumed
|
||||
#define TCB_NORMAL_RESUMES 128 // number of cooperative/restart thread resumes
|
||||
#define TCB_PREEMPT_RESUMES 132 // number of pre-emptive thread resumes
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Coprocessor state handling:
|
||||
// The coprocessor state save area is allocated on the thread stack. The stack
|
||||
// must be sized appropriately. Threads that do not use coprocessors need not
|
||||
// allocate the storage area.
|
||||
//
|
||||
// Along with the save area for each coprocessor, two bitmasks with flags per
|
||||
// coprocessor (laid out as in the CPENABLE reg) help manage context switching
|
||||
// coprocessors as efficiently as possible:
|
||||
//
|
||||
// XT_CPENABLE
|
||||
// The contents of a non-running thread's CPENABLE register.
|
||||
// It represents the coprocessors owned (and whose state is still needed)
|
||||
// by the thread. When a thread is preempted, its CPENABLE is saved here.
|
||||
// When a thread solicits a context switch, its CPENABLE is cleared - the
|
||||
// compiler has saved the (caller-saved) coprocessor state if needed.
|
||||
// When a non-running thread loses ownership of a CP, its bit is cleared.
|
||||
// When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
|
||||
// Avoids coprocessor exceptions when no change of ownership is needed.
|
||||
//
|
||||
// XT_CPSTORED
|
||||
// A bitmask with the same layout as CPENABLE, a bit per coprocessor.
|
||||
// Indicates whether the state of each coprocessor is saved in the state
|
||||
// save area. When a thread enters the kernel, only the state of coprocs
|
||||
// still enabled in CPENABLE is saved. When the coprocessor exception
|
||||
// handler assigns ownership of a coprocessor to a thread, it restores
|
||||
// the saved state only if this bit is set, and clears this bit.
|
||||
//
|
||||
// XT_CP_CS_ST
|
||||
// A bitmask with the same layout as CPENABLE, a bit per co-processor.
|
||||
// Indicates whether callee-saved state is saved in the state save area.
|
||||
// Callee-saved state is saved by itself on a solicited context switch,
|
||||
// and restored when needed by the coprocessor exception handler.
|
||||
// Unsolicited switches will cause the entire coprocessor to be saved
|
||||
// when necessary.
|
||||
//
|
||||
// XT_NCP_ASA
|
||||
// Pointer to aligned save area for non-CP state. This is always filled
|
||||
// in, even if there is no non-CP state to be saved. If there is no state
|
||||
// to be saved then no space is actually allocated and this pointer is
|
||||
// not used.
|
||||
//
|
||||
// XT_CP_ASA
|
||||
// Pointer to aligned save area for coprocessor state. This is filled in
|
||||
// only if coprocessor state is to be saved for the thread. Allows it to be
|
||||
// aligned more than the overall save area (which might be stack-aligned
|
||||
// or TCB-aligned). Especially relevant for Xtensa cores configured with a
|
||||
// very large data path that requires alignment greater than 16 bytes (ABI
|
||||
// stack alignment).
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
|
||||
|
||||
// Offsets of each coprocessor save area within the 'aligned save area'.
|
||||
// The non-CP TIE state save area is at offset 0, so that it does not
|
||||
// move around if some or all coprocessors are not to be saved.
|
||||
|
||||
#define XT_NCP_SA 0
|
||||
#define XT_CP0_SA ALIGNUP(XCHAL_CP0_SA_ALIGN, XT_NCP_SA + XCHAL_NCP_SA_SIZE)
|
||||
#define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
|
||||
#define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
|
||||
#define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
|
||||
#define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
|
||||
#define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
|
||||
#define XT_CP6_SA ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
|
||||
#define XT_CP7_SA ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
|
||||
|
||||
#define XT_TOT_SA_SIZE ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE)
|
||||
#define XT_NCP_SA_SIZE XCHAL_NCP_SA_SIZE
|
||||
|
||||
// Offsets within the overall save area
|
||||
|
||||
#define XT_CPENABLE 0 // (2 bytes) coprocessors active for this thread
|
||||
#define XT_CPSTORED 2 // (2 bytes) coprocessors saved for this thread
|
||||
#define XT_CP_CS_ST 4 // (2 bytes) coprocessor callee-saved regs for this thread
|
||||
#define XT_NCP_ASA 8 // (4 bytes) ptr to aligned save area for nonCP state
|
||||
#define XT_CP_ASA 12 // (4 bytes) ptr to aligned save area for CP state
|
||||
|
||||
// Overall size allows for dynamic alignment, make sure multiple of 4 bytes.
|
||||
// XT_CP_SIZE - total space needed for all coprocessors + nonCP state + hdr
|
||||
// XT_NCP_SIZE - total space needed for nonCP state + hdr
|
||||
|
||||
#define XT_CP_SIZE ALIGNUP(4, (16 + XT_TOT_SA_SIZE + XCHAL_TOTAL_SA_ALIGN))
|
||||
#define XT_NCP_SIZE ALIGNUP(4, (16 + XT_NCP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN))
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Stack size computation.
|
||||
//
|
||||
// XOS_STACK_MIN_SIZE
|
||||
// The minimum recommended stack size for any XOS thread. If you want to
|
||||
// use a stack size smaller than this, you will have to verify that the
|
||||
// smaller size will work under all operating conditions.
|
||||
//
|
||||
// XOS_STACK_MIN_SIZE_NO_CP
|
||||
// The minimum recommended atack size for threads that will not use any
|
||||
// coprocessor resources. No coprocessor state will be saved/restored
|
||||
// for these threads. Non-CP TIE state will still be saved/restored.
|
||||
// These threads must be created with the flag XOS_THREAD_NO_CP.
|
||||
//
|
||||
// XOS_STACK_EXTRA
|
||||
// The amount of stack space used by the system to:
|
||||
// - save coprocessor state
|
||||
// - save non-coprocessor TIE state
|
||||
// - allocate an interrupt/exception frame
|
||||
//
|
||||
// XOS_STACK_EXTRA_NO_CP
|
||||
// The amount of stack space used by the system to:
|
||||
// - save non-coprocessor TIE state
|
||||
// - allocate an interrupt/exception frame
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
#define XOS_STACK_EXTRA (XOS_FRAME_SIZE + XT_CP_SIZE)
|
||||
#define XOS_STACK_EXTRA_NO_CP (XOS_FRAME_SIZE + XT_NCP_SIZE)
|
||||
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
#define XOS_STACK_MIN_SIZE (XOS_STACK_EXTRA + 0x180)
|
||||
#define XOS_STACK_MIN_SIZE_NO_CP (XOS_STACK_EXTRA_NO_CP + 0x180)
|
||||
#else
|
||||
#define XOS_STACK_MIN_SIZE (XOS_STACK_EXTRA + 0x200)
|
||||
#define XOS_STACK_MIN_SIZE_NO_CP (XOS_STACK_EXTRA_NO_CP + 0x200)
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Items related to C library thread safety.
|
||||
//-----------------------------------------------------------------------------
|
||||
#if XOS_OPT_THREAD_SAFE_CLIB
|
||||
|
||||
#if XSHAL_CLIB == XTHAL_CLIB_XCLIB
|
||||
#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
|
||||
#include <sys/reent.h>
|
||||
#endif
|
||||
#define CLIB_THREAD_STRUCT struct _reent xclib_reent
|
||||
#define GLOBAL_CLIB_PTR _reent_ptr
|
||||
#elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB
|
||||
#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
|
||||
#include <sys/reent.h>
|
||||
#endif
|
||||
#define CLIB_THREAD_STRUCT struct _reent newlib_reent
|
||||
#define GLOBAL_CLIB_PTR _impure_ptr
|
||||
#else
|
||||
#error The selected C runtime library is not thread safe.
|
||||
#endif
|
||||
|
||||
#endif // XOS_OPT_THREAD_SAFE_CLIB
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Check (MAX_OS_INTLEVEL,EXCM_LEVEL)
|
||||
//-----------------------------------------------------------------------------
|
||||
#if XOS_MAX_OS_INTLEVEL >= XCHAL_EXCM_LEVEL
|
||||
# define XOS_MAX_OSEXCM_LEVEL XOS_MAX_OS_INTLEVEL
|
||||
#else
|
||||
# warning "XOS_MAX_OS_INTLEVEL was set below XCHAL_EXCM_LEVEL: this was never tested"
|
||||
# define XOS_MAX_OSEXCM_LEVEL XCHAL_EXCM_LEVEL
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Detect if in interrupt context.
|
||||
//-----------------------------------------------------------------------------
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
#define INTERRUPT_CONTEXT ((XT_RSR_PS() & PS_UM) == 0)
|
||||
#else
|
||||
#define INTERRUPT_CONTEXT 0
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Xtensa tools version.
|
||||
//-----------------------------------------------------------------------------
|
||||
#if defined __XCC__
|
||||
#define XTTOOLS_VERSION (__XCC__ + __XCC_MINOR__)
|
||||
#else
|
||||
#define XTTOOLS_VERSION (0)
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Erratum workarounds.
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
// Erratum 487 fix is available in version RF.3 onwards and RG.2 onwards.
|
||||
#if ((__XCC__ == 11000) && (__XCC_MINOR__ >= 3)) || (XTTOOLS_VERSION >= 12002)
|
||||
#define HWERR_487_FIX hw_erratum_487_fix
|
||||
#else
|
||||
#define HWERR_487_FIX
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __XOS_COMMON_H__
|
||||
|
||||
Executable
+145
@@ -0,0 +1,145 @@
|
||||
/** @file */
|
||||
|
||||
// xos_cond.h - XOS condition variables API interface and data structures.
|
||||
|
||||
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining
|
||||
// a copy of this software and associated documentation files (the
|
||||
// "Software"), to deal in the Software without restriction, including
|
||||
// without limitation the rights to use, copy, modify, merge, publish,
|
||||
// distribute, sublicense, and/or sell copies of the Software, and to
|
||||
// permit persons to whom the Software is furnished to do so, subject to
|
||||
// the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
// NOTE: Do not include this file directly in your application. Including
|
||||
// xos.h will automatically include this file.
|
||||
|
||||
#ifndef __XOS_COND_H__
|
||||
#define __XOS_COND_H__
|
||||
|
||||
#include "xos_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Function pointer type for condition callbacks (defined in xos_thread.h)
|
||||
//
|
||||
// typedef int32_t (XosCondFunc)(void * arg, int32_t sig_value, XosThread * thread);
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Condition object.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
typedef struct XosCond {
|
||||
XosThreadQueue queue; ///< Queue of waiters.
|
||||
#if XOS_COND_DEBUG
|
||||
uint32_t sig; // Signature indicates valid object.
|
||||
#endif
|
||||
} XosCond;
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Initialize a condition object before first use. The object must be
|
||||
/// allocated by the caller.
|
||||
///
|
||||
/// \param cond Pointer to condition object.
|
||||
///
|
||||
/// \return Returns nothing.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
void
|
||||
xos_cond_create(XosCond * cond);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Destroy a condition object. Must have been previously created by calling
|
||||
/// xos_cond_create().
|
||||
///
|
||||
/// \param cond Pointer to condition object.
|
||||
///
|
||||
/// \return Returns nothing.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
void
|
||||
xos_cond_delete(XosCond * cond);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Wait on a condition: block until the condition is satisfied. The condition
|
||||
/// is satisfied when xos_cond_signal() is called on this condition *and* the
|
||||
/// condition callback function returns non-zero. If there is no callback
|
||||
/// function, then the condition is automatically satisfied.
|
||||
///
|
||||
/// The condition structure must have been initialized before first use by
|
||||
/// calling xos_cond_create().
|
||||
///
|
||||
/// \param cond Pointer to condition object.
|
||||
///
|
||||
/// \param cond_fn Pointer to a function, called by xos_cond_signal(),
|
||||
/// that should return non-zero if this thread is to
|
||||
/// be resumed. The function is invoked as:
|
||||
/// `(*cond_fn)(cond_arg, sig_value)`.
|
||||
///
|
||||
/// \param cond_arg Argument passed to cond_fn.
|
||||
///
|
||||
/// \return Returns the value passed to xos_cond_signal().
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_cond_wait(XosCond * cond, XosCondFunc * cond_fn, void * cond_arg);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Trigger the condition: wake all threads waiting on the condition, if their
|
||||
/// condition function evaluates to true (non-zero). If there is no condition
|
||||
/// function for a thread then it is automatically awakened.
|
||||
///
|
||||
/// The condition structure must have been initialized before first use by
|
||||
/// calling xos_cond_create().
|
||||
///
|
||||
/// \param cond Pointer to condition object.
|
||||
///
|
||||
/// \param sig_value Value passed to all waiters, returned by
|
||||
/// xos_cond_wait().
|
||||
///
|
||||
/// \return Returns the number of waiting threads that were resumed.
|
||||
///
|
||||
/// NOTE: Signaling a condition that has no waiters has no effect on it, and
|
||||
/// the signal is not remembered. Any thread that waits on it later must be
|
||||
/// woken by another call to xos_cond_signal().
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_cond_signal(XosCond * cond, int32_t sig_value);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __XOS_COND_H__
|
||||
|
||||
Executable
+107
@@ -0,0 +1,107 @@
|
||||
/** @file */
|
||||
|
||||
// xos_errors.h - XOS error codes.
|
||||
|
||||
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining
|
||||
// a copy of this software and associated documentation files (the
|
||||
// "Software"), to deal in the Software without restriction, including
|
||||
// without limitation the rights to use, copy, modify, merge, publish,
|
||||
// distribute, sublicense, and/or sell copies of the Software, and to
|
||||
// permit persons to whom the Software is furnished to do so, subject to
|
||||
// the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
// NOTE: Do not include this file directly in your application. Including
|
||||
// xos.h will automatically include this file.
|
||||
|
||||
|
||||
#ifndef __XOS_ERRORS_H__
|
||||
#define __XOS_ERRORS_H__
|
||||
|
||||
#include "xos_types.h"
|
||||
|
||||
|
||||
#define _XOS_ERR_FIRST (-65536)
|
||||
#define _XOS_ERR_LAST (-1)
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// List of XOS error codes. All error codes are negative integers, except for
|
||||
/// XOS_OK which is zero.
|
||||
/// XOS error codes occupy the range from -65536 up to -1.
|
||||
/// The function IS_XOS_ERRCODE() can be used to check if a value lies within
|
||||
/// the error code range.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
typedef enum xos_err_t {
|
||||
XOS_OK = 0,
|
||||
|
||||
XOS_ERR_NOT_FOUND = _XOS_ERR_FIRST, ///< Object not found
|
||||
XOS_ERR_INVALID_PARAMETER, ///< Function parameter is invalid
|
||||
XOS_ERR_LIMIT, ///< Limit exceeded
|
||||
XOS_ERR_NOT_OWNED, ///< Object not owned by caller
|
||||
XOS_ERR_MUTEX_LOCKED, ///< Mutex is already locked
|
||||
XOS_ERR_MUTEX_NOT_OWNED, ///< Mutex not owned by caller
|
||||
XOS_ERR_MUTEX_ALREADY_OWNED, ///< Mutex already owned by caller
|
||||
XOS_ERR_MUTEX_DELETE, ///< Mutex being waited on has been deleted
|
||||
XOS_ERR_COND_DELETE, ///< Condition being waited on has been deleted
|
||||
XOS_ERR_SEM_DELETE, ///< Semaphore being waited on has been deleted
|
||||
XOS_ERR_SEM_BUSY, ///< Semaphore is not available
|
||||
XOS_ERR_EVENT_DELETE, ///< Event being waited on has been deleted
|
||||
XOS_ERR_MSGQ_FULL, ///< Message queue is full
|
||||
XOS_ERR_MSGQ_EMPTY, ///< Message queue is empty
|
||||
XOS_ERR_MSGQ_DELETE, ///< Message queue being waited on has been deleted
|
||||
XOS_ERR_TIMER_DELETE, ///< Timer being waited on has been deleted
|
||||
XOS_ERR_CONTAINER_NOT_RTC, ///< Containing thread not of RTC type
|
||||
XOS_ERR_CONTAINER_NOT_SAME_PRI, ///< Containing thread not at same priority
|
||||
XOS_ERR_STACK_TOO_SMALL, ///< Thread stack is too small
|
||||
XOS_ERR_CONTAINER_ILLEGAL, ///< Illegal container thread
|
||||
XOS_ERR_ILLEGAL_OPERATION, ///< This operation is not allowed
|
||||
XOS_ERR_THREAD_EXITED, ///< The thread has already exited
|
||||
XOS_ERR_NO_TIMER, ///< No suitable timer found
|
||||
XOS_ERR_FEATURE_NOT_PRESENT, ///< This feature is disabled or not implemented
|
||||
XOS_ERR_TIMEOUT, ///< Wait timed out
|
||||
|
||||
XOS_ERR_UNHANDLED_INTERRUPT, ///< No handler for interrupt
|
||||
XOS_ERR_UNHANDLED_EXCEPTION, ///< No handler for exception
|
||||
XOS_ERR_INTERRUPT_CONTEXT, ///< Operation is illegal in interrupt context
|
||||
XOS_ERR_THREAD_BLOCKED, ///< Thread already blocked
|
||||
XOS_ERR_ASSERT_FAILED, ///< Runtime assertion failure
|
||||
XOS_ERR_CLIB_ERR, ///< Error in C library thread safety module
|
||||
XOS_ERR_INTERNAL_ERROR, ///< XOS internal error
|
||||
|
||||
XOS_ERR_LAST = _XOS_ERR_LAST,
|
||||
} xos_err_t;
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Check if a value is a valid XOS error code.
|
||||
///
|
||||
/// \param val Value to check
|
||||
///
|
||||
/// \return Returns nonzero if 'val' is in the XOS error code range.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
static inline int32_t
|
||||
IS_XOS_ERRCODE(xos_err_t val)
|
||||
{
|
||||
return ((val >= _XOS_ERR_FIRST) && (val <= _XOS_ERR_LAST));
|
||||
}
|
||||
|
||||
|
||||
#endif // __XOS_ERRORS_H__
|
||||
|
||||
Executable
+281
@@ -0,0 +1,281 @@
|
||||
/** @file */
|
||||
|
||||
// xos_event.h - XOS Event API interface and data structures.
|
||||
|
||||
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining
|
||||
// a copy of this software and associated documentation files (the
|
||||
// "Software"), to deal in the Software without restriction, including
|
||||
// without limitation the rights to use, copy, modify, merge, publish,
|
||||
// distribute, sublicense, and/or sell copies of the Software, and to
|
||||
// permit persons to whom the Software is furnished to do so, subject to
|
||||
// the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
// NOTE: Do not include this file directly in your application. Including
|
||||
// xos.h will automatically include this file.
|
||||
|
||||
#ifndef __XOS_EVENT_H__
|
||||
#define __XOS_EVENT_H__
|
||||
|
||||
#include "xos_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Defines.
|
||||
//-----------------------------------------------------------------------------
|
||||
#define XOS_EVENT_BITS_ALL 0xFFFFFFFF
|
||||
#define XOS_EVENT_BITS_NONE 0
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Event flags.
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Event object.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
typedef struct XosEvent {
|
||||
XosThreadQueue waitq; ///< Queue of waiters.
|
||||
uint32_t bits; ///< Event bits
|
||||
uint32_t mask; ///< Specifies which bits are valid
|
||||
uint16_t flags; ///< Properties.
|
||||
uint16_t pad; ///< Padding
|
||||
#if XOS_EVENT_DEBUG
|
||||
uint32_t sig; // Valid signature indicates inited.
|
||||
#endif
|
||||
} XosEvent;
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Initialize an event object before first use.
|
||||
///
|
||||
/// \param event Pointer to event object.
|
||||
///
|
||||
/// \param mask Mask of active bits. Only these bits can be signaled.
|
||||
///
|
||||
/// \param flags Creation flags (currently ignored, should be zero).
|
||||
///
|
||||
/// \return Returns nothing.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
void
|
||||
xos_event_create(XosEvent * event, uint32_t mask, uint32_t flags);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Destroy an event object. Must have been previously created by calling
|
||||
/// xos_event_create().
|
||||
///
|
||||
/// \param event Pointer to event object.
|
||||
///
|
||||
/// \return Returns nothing.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
void
|
||||
xos_event_delete(XosEvent * event);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Set the specified bits in the specified event. Propagates the bit states
|
||||
/// to all waiting threads and wakes them if needed.
|
||||
///
|
||||
/// \param event Pointer to event object.
|
||||
///
|
||||
/// \param bits Mask of bits to set. Bits not set in the mask
|
||||
/// will not be modified by this call. To set all
|
||||
/// the bits in the event, use the constant
|
||||
/// XOS_EVENT_BITS_ALL.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_event_set(XosEvent * event, uint32_t bits);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Clear the specified bits in the specified event. Propagates the bit states
|
||||
/// to all waiting threads and wakes them if needed.
|
||||
///
|
||||
/// \param event Pointer to event object.
|
||||
///
|
||||
/// \param bits Mask of bits to clear. Every bit that is set in
|
||||
/// the mask will be cleared from the event. Bits
|
||||
/// not set in the mask will not be modified by this
|
||||
/// call. To clear all the bits in an event use the
|
||||
/// constant XOS_EVENT_BITS_ALL.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_event_clear(XosEvent * event, uint32_t bits);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Clear and set the specified bits in the specified event. The two steps are
|
||||
/// combined into one update, so this is faster than calling xos_event_clear()
|
||||
/// and xos_event_set() separately. Only one update is sent out to waiting
|
||||
/// threads.
|
||||
///
|
||||
/// \param event Pointer to event object.
|
||||
///
|
||||
/// \param clr_bits Mask of bits to clear. The clear operation
|
||||
/// happens before the set operation.
|
||||
///
|
||||
/// \param set_bits Mask of bits to set.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_event_clear_and_set(XosEvent * event, uint32_t clr_bits, uint32_t set_bits);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Get the current state of the event object. This is a snapshot of the state
|
||||
/// of the event at this time.
|
||||
///
|
||||
/// \param event Pointer to event object.
|
||||
///
|
||||
/// \param pstate Pointer to a uint32_t variable where the state
|
||||
/// will be returned.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_event_get(XosEvent * event, uint32_t * pstate);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Wait until all the specified bits in the wait mask become set in the given
|
||||
/// event object.
|
||||
///
|
||||
/// \param event Pointer to event object.
|
||||
///
|
||||
/// \param bits Mask of bits to test.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_event_wait_all(XosEvent * event, uint32_t bits);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Wait until all the specified bits in the wait mask become set in the given
|
||||
/// event object, or the timeout expires.
|
||||
///
|
||||
/// \param event Pointer to event object.
|
||||
///
|
||||
/// \param bits Mask of bits to test.
|
||||
///
|
||||
/// \param to_cycles Timeout in cycles. Convert from time to cycles
|
||||
/// using the helper functions provided in xos_timer.
|
||||
/// A value of zero indicates no timeout.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, XOS_ERR_TIMEOUT on timeout, else
|
||||
/// error code.
|
||||
///
|
||||
/// NOTE: If XOS_OPT_WAIT_TIMEOUT is not enabled, then the timeout value is
|
||||
/// ignored, and no timeout will occur.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_event_wait_all_timeout(XosEvent * event, uint32_t bits, uint64_t to_cycles);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Wait until any of the specified bits in the wait mask become set in the
|
||||
/// given event object.
|
||||
///
|
||||
/// \param event Pointer to event object.
|
||||
///
|
||||
/// \param bits Mask of bits to test.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_event_wait_any(XosEvent * event, uint32_t bits);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Wait until any of the specified bits in the wait mask become set in the
|
||||
/// event object, or the timeout expires.
|
||||
///
|
||||
/// \param event Pointer to event object.
|
||||
///
|
||||
/// \param bits Mask of bits to test.
|
||||
///
|
||||
/// \param to_cycles Timeout in cycles. Convert from time to cycles
|
||||
/// using the helper functions provided in xos_timer.
|
||||
/// A value of zero indicates no timeout.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, XOS_ERR_TIMEOUT on timeout, else
|
||||
/// error code.
|
||||
///
|
||||
/// NOTE: If XOS_OPT_WAIT_TIMEOUT is not enabled, then the timeout value is
|
||||
/// ignored, and no timeout will occur.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_event_wait_any_timeout(XosEvent * event, uint32_t bits, uint64_t to_cycles);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Atomically set a specified group of bits, then wait for another specified
|
||||
/// group of bits to become set.
|
||||
///
|
||||
/// \param event Pointer to event object.
|
||||
///
|
||||
/// \param set_bits Group of bits to set.
|
||||
///
|
||||
/// \param wait_bits Group of bits to wait on. All the bits in the
|
||||
/// group will have to get set before the wait is
|
||||
/// satisfied.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_event_set_and_wait(XosEvent * event, uint32_t set_bits, uint32_t wait_bits);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __XOS_EVENT_H__
|
||||
|
||||
+120
@@ -0,0 +1,120 @@
|
||||
|
||||
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining
|
||||
// a copy of this software and associated documentation files (the
|
||||
// "Software"), to deal in the Software without restriction, including
|
||||
// without limitation the rights to use, copy, modify, merge, publish,
|
||||
// distribute, sublicense, and/or sell copies of the Software, and to
|
||||
// permit persons to whom the Software is furnished to do so, subject to
|
||||
// the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
|
||||
#ifndef __XOS_INTERNAL_H__
|
||||
#define __XOS_INTERNAL_H__
|
||||
|
||||
#if !defined(__XOS_H__) || !defined(_XOS_INCLUDE_INTERNAL_)
|
||||
#error "xos_internal.h must be included by defining _XOS_INCLUDE_INTERNAL_ before including xos.h"
|
||||
#endif
|
||||
|
||||
#include <xtensa/config/core.h>
|
||||
#include "xos_common.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
// Use this macro to suppress compiler warnings for unused variables.
|
||||
|
||||
#define UNUSED(x) (void)(x)
|
||||
|
||||
|
||||
#if XOS_DEBUG
|
||||
|
||||
#include <stdio.h>
|
||||
#include <xtensa/xtutil.h>
|
||||
# define DPRINTF printf
|
||||
|
||||
#else
|
||||
|
||||
# define DPRINTF(x...) do {} while(0)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Internal flags for thread creation.
|
||||
//-----------------------------------------------------------------------------
|
||||
#define XOS_THREAD_FAKE 0x8000 // Don't allocate stack (init and idle threads).
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Interrupt handler table entry. This structure defines one entry in the XOS
|
||||
// interrupt handler table.
|
||||
//-----------------------------------------------------------------------------
|
||||
typedef struct XosIntEntry {
|
||||
XosIntFunc * handler; // Pointer to handler function.
|
||||
void * arg; // Argument passed to handler function.
|
||||
#if XOS_OPT_INTERRUPT_SWPRI
|
||||
unsigned char level; // Interrupt level.
|
||||
unsigned char priority; // Interrupt priority.
|
||||
short reserved; // Reserved.
|
||||
unsigned int primask; // Mask of interrupts at higher priority.
|
||||
#else
|
||||
unsigned int ps; // Value of PS when running the handler.
|
||||
#endif
|
||||
} XosIntEntry;
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Extern variables.
|
||||
//-----------------------------------------------------------------------------
|
||||
extern unsigned xos_intlevel_mask;
|
||||
extern unsigned xos_intenable_mask;
|
||||
extern XosIntEntry xos_interrupt_table[XCHAL_NUM_INTERRUPTS];
|
||||
|
||||
extern uint32_t xos_clock_freq;
|
||||
extern uint32_t xos_tick_period;
|
||||
extern uint64_t xos_system_ticks;
|
||||
extern uint64_t xos_system_cycles;
|
||||
extern uint32_t xos_num_ctx_switches;
|
||||
|
||||
|
||||
/*
|
||||
|
||||
One thing I noticed is different between my initial idea of stack
|
||||
assignments to RTC threads, when comparing to interrupts, is that I
|
||||
expected each RTC thread priority to have its own stack, whereas
|
||||
interrupts of different priorities share an interrupt stack.
|
||||
|
||||
It's not really a difference in memory usage, because when assigning
|
||||
multiple priorities to a stack, you have to add-up worst-case for
|
||||
all priorities. One possible functional difference is that with
|
||||
separate stacks per priority, it's possible to dynamically change
|
||||
the priority of an RTC thread (while it's running). Not sure how
|
||||
valuable that might be -- changing priority is useful with priority
|
||||
inheritance, to avoid priority inversion, but I don't know how often
|
||||
an RTC thread might acquire a lock (it couldn't block on acquiring a
|
||||
lock in the usual sense -- it could get queued waiting and be restarted
|
||||
when it becomes available, or use try_lock instead of lock).
|
||||
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __XOS_INTERNAL_H__ */
|
||||
|
||||
Executable
+278
@@ -0,0 +1,278 @@
|
||||
/** @file */
|
||||
|
||||
// xos_msgq.h - XOS Message Queue API and data structures.
|
||||
|
||||
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining
|
||||
// a copy of this software and associated documentation files (the
|
||||
// "Software"), to deal in the Software without restriction, including
|
||||
// without limitation the rights to use, copy, modify, merge, publish,
|
||||
// distribute, sublicense, and/or sell copies of the Software, and to
|
||||
// permit persons to whom the Software is furnished to do so, subject to
|
||||
// the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
// NOTE: Do not include this file directly in your application. Including
|
||||
// xos.h will automatically include this file.
|
||||
|
||||
|
||||
#ifndef __XOS_MSGQ_H__
|
||||
#define __XOS_MSGQ_H__
|
||||
|
||||
#include "xos_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// XosMsgQueue is a multi-writer multi-reader message queue implementation.
|
||||
// It is completely thread-safe and can be used by interrupt handlers.
|
||||
// Interrupt handlers are guaranteed not to block when trying to send or
|
||||
// receive a message. Messages are copied into the queue. The queue contains
|
||||
// storage for a fixed number of messages defined at queue creation time.
|
||||
// Messages must be a multiple of 4 bytes long (padded if necessary) and the
|
||||
// message buffers must be 4-byte aligned.
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Message Queue flags.
|
||||
//-----------------------------------------------------------------------------
|
||||
#define XOS_MSGQ_WAIT_PRIORITY 0x0000 ///< Wake waiters in priority order (default)
|
||||
#define XOS_MSGQ_WAIT_FIFO 0x0001 ///< Wake waiters in FIFO order
|
||||
#define XOS_MSGQ_FULL 0x0002 // Queue is full
|
||||
#define XOS_MSGQ_DELETED 0x8000 // Queue is deleted
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// XosMsgQueue object.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
typedef struct XosMsgQueue {
|
||||
uint16_t flags; ///< queue flags
|
||||
uint16_t count; ///< # of messages queue can hold
|
||||
uint32_t msize; ///< message size in bytes
|
||||
uint16_t head; ///< write pointer
|
||||
uint16_t tail; ///< read pointer
|
||||
XosThreadQueue readq; ///< reader wait queue
|
||||
XosThreadQueue writeq; ///< writer wait queue
|
||||
#if XOS_MSGQ_DEBUG
|
||||
uint32_t sig; // debug signature
|
||||
#endif
|
||||
#if XOS_OPT_MSGQ_STATS
|
||||
uint32_t num_send; ///< # of messages put to queue
|
||||
uint32_t num_recv; ///< # of messages taken from queue
|
||||
uint32_t num_send_blks; ///< # of times thread blocked on send
|
||||
uint32_t num_recv_blks; ///< # of times thread blocked on recv
|
||||
#endif
|
||||
uint32_t msg[1]; ///< first word of message buffer
|
||||
} XosMsgQueue;
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Use these macros to statically or dynamically allocate a message queue.
|
||||
/// XOS_MSGQ_ALLOC allocates a static queue, while XOS_MSGQ_SIZE can be used
|
||||
/// to allocate memory via malloc() etc.
|
||||
///
|
||||
/// Static: this allocates a queue named "testq", containing 10 messages,
|
||||
/// each 16 bytes long.
|
||||
///
|
||||
/// XOS_MSGQ_ALLOC(testq, 10, 16);
|
||||
///
|
||||
/// Dynamic: this allocates a queue named "testq", containing 10 messages,
|
||||
/// each 16 bytes long.
|
||||
///
|
||||
/// XosMsgQueue * testq = malloc( XOS_MSGQ_SIZE(10, 16) );
|
||||
///
|
||||
/// \param name The queue name, i.e. the name of the pointer
|
||||
/// to the queue. Used as the queue handle in
|
||||
/// queue API calls.
|
||||
///
|
||||
/// \param num Number of messages to allocate in queue. Must be > 0.
|
||||
///
|
||||
/// \param size Message size in bytes. Must be > 0 and multiple of 4.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
#define XOS_MSGQ_ALLOC(name, num, size) \
|
||||
static uint8_t name ## _buf[ sizeof(XosMsgQueue) + ((num) * (size)) ]; \
|
||||
XosMsgQueue * name = (XosMsgQueue *) name ## _buf;
|
||||
|
||||
#define XOS_MSGQ_SIZE(num, size) \
|
||||
(sizeof(XosMsgQueue) + ((num) * (size)))
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Create the message queue object. Memory for the queue must be allocated by
|
||||
/// the caller, either statically or via dynamic allocation. See the macros
|
||||
/// XOS_MSGQ_ALLOC and XOS_MSGQ_SIZE for examples.
|
||||
///
|
||||
/// \param msgq Handle (pointer) to message queue.
|
||||
///
|
||||
/// \param num Number of messages allocated in queue. Must be > 0.
|
||||
///
|
||||
/// \param size Message size in bytes. Must be > 0 and multiple of 4.
|
||||
///
|
||||
/// \param flags Queue flags:
|
||||
/// - XOS_MSGQ_WAIT_FIFO - blocked threads will be
|
||||
/// woken in FIFO order.
|
||||
/// - XOS_MSGQ_WAIT_PRIORITY - blocked threads will
|
||||
/// be woken in priority order (default).
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_msgq_create(XosMsgQueue * msgq, uint16_t num, uint32_t size, uint16_t flags);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Destroys the specified queue. Any waiting threads are unblocked with an
|
||||
/// error return. Any messages in the queue will be lost.
|
||||
///
|
||||
/// \param msgq Pointer to message queue.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_msgq_delete(XosMsgQueue * msgq);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Put a message into the queue. The message contents are copied into the next
|
||||
/// available message slot. If no space is available, this function will block
|
||||
/// if called from a thread, but will return immediately if called from an
|
||||
/// interrupt handler.
|
||||
///
|
||||
/// \param msgq Pointer to message queue.
|
||||
///
|
||||
/// \param msg Pointer to message buffer.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_msgq_put(XosMsgQueue * msgq, const uint32_t * msg);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Put a message into the queue. The message contents are copied into the next
|
||||
/// available message slot. If no space is available, this function will block
|
||||
/// if called from a thread, but will return immediately if called from an
|
||||
/// interrupt handler. The thread will be unblocked when space frees up in the
|
||||
/// queue or the timeout expires.
|
||||
///
|
||||
/// \param msgq Pointer to message queue.
|
||||
///
|
||||
/// \param msg Pointer to message buffer.
|
||||
///
|
||||
/// \param to_cycles Timeout in cycles. Convert from time to cycles
|
||||
/// using the helper functions provided in xos_timer.
|
||||
/// A value of zero indicates no timeout.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, XOS_ERR_TIMEOUT on timeout, else error code.
|
||||
///
|
||||
/// NOTE: If XOS_OPT_WAIT_TIMEOUT is not enabled, then the timeout value is
|
||||
/// ignored, and no timeout will occur.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_msgq_put_timeout(XosMsgQueue * msgq, const uint32_t * msg, uint64_t to_cycles);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Get a message from the queue. The message contents are copied into the
|
||||
/// buffer that must be provided. If no message is available, this function
|
||||
/// will block if called from a thread, but will return immediately if called
|
||||
/// from an interrupt handler.
|
||||
///
|
||||
/// \param msgq Pointer to message queue.
|
||||
///
|
||||
/// \param msg Pointer to message buffer.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_msgq_get(XosMsgQueue * msgq, uint32_t * msg);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Get a message from the queue. The message contents are copied into the
|
||||
/// buffer that must be provided. If no message is available, this function
|
||||
/// will block if called from a thread, but will return immediately if called
|
||||
/// from an interrupt handler. The thread will be unblocked when a message
|
||||
/// arrives in the queue or the timeout expires.
|
||||
///
|
||||
/// \param msgq Pointer to message queue.
|
||||
///
|
||||
/// \param msg Pointer to message buffer.
|
||||
///
|
||||
/// \param to_cycles Timeout in cycles. Convert from time to cycles
|
||||
/// using the helper functions provided in xos_timer.
|
||||
/// A value of zero indicates no timeout.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, XOS_ERR_TIMEOUT on timeout, else error code.
|
||||
///
|
||||
/// NOTE: If XOS_OPT_WAIT_TIMEOUT is not enabled, then the timeout value is
|
||||
/// ignored, and no timeout will occur.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_msgq_get_timeout(XosMsgQueue * msgq, uint32_t * msg, uint64_t to_cycles);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Check if the queue is empty.
|
||||
///
|
||||
/// \param msgq Pointer to message queue.
|
||||
///
|
||||
/// \return Returns nonzero if queue is empty, zero if queue is not empty.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_msgq_empty(XosMsgQueue * msgq);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Check if the queue is full.
|
||||
///
|
||||
/// \param msgq Pointer to message queue.
|
||||
///
|
||||
/// \return Returns nonzero if queue is full, zero if queue is not full.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_msgq_full(XosMsgQueue * msgq);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __XOS_MSGQ_H__
|
||||
|
||||
Executable
+205
@@ -0,0 +1,205 @@
|
||||
/** @file */
|
||||
|
||||
// xos_mutex.h - XOS Mutex API interface and data structures.
|
||||
|
||||
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining
|
||||
// a copy of this software and associated documentation files (the
|
||||
// "Software"), to deal in the Software without restriction, including
|
||||
// without limitation the rights to use, copy, modify, merge, publish,
|
||||
// distribute, sublicense, and/or sell copies of the Software, and to
|
||||
// permit persons to whom the Software is furnished to do so, subject to
|
||||
// the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
// NOTE: Do not include this file directly in your application. Including
|
||||
// xos.h will automatically include this file.
|
||||
|
||||
#ifndef __XOS_MUTEX_H__
|
||||
#define __XOS_MUTEX_H__
|
||||
|
||||
#include "xos_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Mutex flags.
|
||||
//-----------------------------------------------------------------------------
|
||||
#define XOS_MUTEX_WAIT_PRIORITY 0x0000 ///< Wake waiters in priority order (default)
|
||||
#define XOS_MUTEX_WAIT_FIFO 0x0001 ///< Wake waiters in FIFO order
|
||||
#define XOS_MUTEX_PRIORITY_CLG 0x0004 // Use priority ceiling
|
||||
#define XOS_MUTEX_PRIORITY_INV 0x0008 // Protect against priority inversion
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// XosMutex object.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
typedef struct XosMutex {
|
||||
XosThread * owner; ///< Owning thread (null if unlocked).
|
||||
XosThreadQueue waitq; ///< Queue of waiters.
|
||||
uint32_t flags; ///< Properties.
|
||||
uint32_t priority;
|
||||
int32_t lock_count; ///< For recursive locking.
|
||||
#if XOS_MUTEX_DEBUG
|
||||
uint32_t sig; // Valid signature indicates inited.
|
||||
#endif
|
||||
} XosMutex;
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Initialize a mutex object before first use.
|
||||
///
|
||||
/// \param mutex Pointer to mutex object.
|
||||
///
|
||||
/// \param flags Creation flags:
|
||||
/// - XOS_MUTEX_WAIT_FIFO -- Queue waiting threads
|
||||
/// in fifo order.
|
||||
/// - XOS_MUTEX_WAIT_PRIORITY -- Queue waiting threads
|
||||
/// by priority. This is the default.
|
||||
/// - XOS_MUTEX_PRIORITY_CLG -- Use specified priority
|
||||
/// value as the mutex's priority ceiling. If the
|
||||
/// owning thread has a priority lower than the mutex's
|
||||
/// priority, then the thread will have its priority
|
||||
/// raised to the higher value as long as it owns the
|
||||
/// mutex.
|
||||
/// - XOS_MUTEX_PRIORITY_INV -- Protect against priority
|
||||
/// inversion. If there is a waiting thread with a
|
||||
/// higher priority than the current owner thread,
|
||||
/// then the owner thread's priority is raised to the
|
||||
/// higher value for as long as it owns the mutex.
|
||||
///
|
||||
/// \param priority Mutex's priority ceiling. This is used only if the
|
||||
/// XOS_MUTEX_PRIORITY_CLG flag is set.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
/// NOTE: XOS_MUTEX_PRIORITY_CLG and XOS_MUTEX_PRIORITY_INV are NOT supported
|
||||
/// in the current release. They will be supported in a future release.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_mutex_create(XosMutex * mutex, uint32_t flags, uint8_t priority);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Destroy a mutex object. Must have been previously initialized by calling
|
||||
/// xos_mutex_create().
|
||||
///
|
||||
/// \param mutex Pointer to mutex object.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_mutex_delete(XosMutex * mutex);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Take ownership of the mutex: block until the mutex is owned.
|
||||
/// The mutex must have been initialized.
|
||||
///
|
||||
/// \param mutex Pointer to mutex object.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_mutex_lock(XosMutex * mutex);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Take ownership of the mutex: block until the mutex is owned or the timeout
|
||||
/// expires. The mutex must have been initialized.
|
||||
///
|
||||
/// \param mutex Pointer to mutex object.
|
||||
///
|
||||
/// \param to_cycles Timeout in cycles. Convert from time to cycles
|
||||
/// using the helper functions provided in xos_timer.
|
||||
/// A value of zero indicates no timeout.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, XOS_ERR_TIMEOUT on timeout, else error code.
|
||||
///
|
||||
/// NOTE: If XOS_OPT_WAIT_TIMEOUT is not enabled, then the timeout value is
|
||||
/// ignored, and no timeout will occur.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_mutex_lock_timeout(XosMutex * mutex, uint64_t to_cycles);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Release ownership of the mutex. The mutex must have been initialized and
|
||||
/// must be owned by the calling thread.
|
||||
///
|
||||
/// \param mutex Pointer to mutex object.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_mutex_unlock(XosMutex * mutex);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Try to take ownership of the mutex, but do not block if the mutex is taken.
|
||||
/// Return immediately. The mutex must have been initialized.
|
||||
///
|
||||
/// \param mutex Pointer to mutex object.
|
||||
///
|
||||
/// \return Returns XOS_OK on success (mutex owned), else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_mutex_trylock(XosMutex * mutex);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Return the state of the mutex (locked or unlocked) but do not attempt to
|
||||
/// take ownership. The mutex must have been initialized.
|
||||
///
|
||||
/// \param mutex Pointer to mutex object.
|
||||
///
|
||||
/// \return Returns 0 if the mutex is unlocked, 1 if it is locked, -1 on error.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
static inline int32_t
|
||||
xos_mutex_test(XosMutex * mutex)
|
||||
{
|
||||
XOS_ASSERT(mutex);
|
||||
|
||||
if (mutex != XOS_NULL) {
|
||||
return (mutex->owner != XOS_NULL) ? 1 : 0;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __XOS_MUTEX_H__
|
||||
|
||||
Executable
+276
@@ -0,0 +1,276 @@
|
||||
/** @file */
|
||||
|
||||
// xos_params.h - user-settable compile time parameters for XOS.
|
||||
|
||||
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining
|
||||
// a copy of this software and associated documentation files (the
|
||||
// "Software"), to deal in the Software without restriction, including
|
||||
// without limitation the rights to use, copy, modify, merge, publish,
|
||||
// distribute, sublicense, and/or sell copies of the Software, and to
|
||||
// permit persons to whom the Software is furnished to do so, subject to
|
||||
// the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
|
||||
#ifndef __XOS_PARAMS_H__
|
||||
#define __XOS_PARAMS_H__
|
||||
|
||||
#include <xtensa/config/core.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Number of thread priority levels. At this time XOS supports a maximum of
|
||||
/// 32 priority levels (0 - 31).
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
#ifndef XOS_NUM_PRIORITY
|
||||
#define XOS_NUM_PRIORITY 16 // Default is 16
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Debug flags - Set to 1 to enable debug mode (and more verbose operation).
|
||||
/// Can be set individually, or define XOS_DEBUG_ALL to enable all of them.
|
||||
///
|
||||
/// - XOS_DEBUG -- Generic OS debug
|
||||
/// - XOS_COND_DEBUG -- Condition objects debug
|
||||
/// - XOS_EVENT_DEBUG -- Event objects debug
|
||||
/// - XOS_MSGQ_DEBUG -- Message queue debug
|
||||
/// - XOS_MUTEX_DEBUG -- Mutex objects debug
|
||||
/// - XOS_SEM_DEBUG -- Semaphore objects debug
|
||||
/// - XOS_THREAD_DEBUG -- Thread module debug
|
||||
/// - XOS_TIMER_DEBUG -- Timer module debug
|
||||
///
|
||||
/// WARNING: Enabling one or more of these flags will affect system performance
|
||||
/// and timing.
|
||||
///
|
||||
/// NOTE: Not all of these have been fully implemented.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
#if defined XOS_DEBUG_ALL
|
||||
|
||||
#define XOS_DEBUG 1
|
||||
#define XOS_THREAD_DEBUG 1
|
||||
#define XOS_TIMER_DEBUG 1
|
||||
#define XOS_COND_DEBUG 1
|
||||
#define XOS_MUTEX_DEBUG 1
|
||||
#define XOS_SEM_DEBUG 1
|
||||
#define XOS_EVENT_DEBUG 1
|
||||
#define XOS_MSGQ_DEBUG 1
|
||||
|
||||
#else
|
||||
|
||||
#ifndef XOS_DEBUG
|
||||
#define XOS_DEBUG 0
|
||||
#endif
|
||||
#ifndef XOS_THREAD_DEBUG
|
||||
#define XOS_THREAD_DEBUG 0
|
||||
#endif
|
||||
#ifndef XOS_TIMER_DEBUG
|
||||
#define XOS_TIMER_DEBUG 0
|
||||
#endif
|
||||
#ifndef XOS_COND_DEBUG
|
||||
#define XOS_COND_DEBUG 0
|
||||
#endif
|
||||
#ifndef XOS_MUTEX_DEBUG
|
||||
#define XOS_MUTEX_DEBUG 0
|
||||
#endif
|
||||
#ifndef XOS_SEM_DEBUG
|
||||
#define XOS_SEM_DEBUG 0
|
||||
#endif
|
||||
#ifndef XOS_EVENT_DEBUG
|
||||
#define XOS_EVENT_DEBUG 0
|
||||
#endif
|
||||
#ifndef XOS_MSGQ_DEBUG
|
||||
#define XOS_MSGQ_DEBUG 0
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Set this option to 1 to enable runtime statistics collection for XOS.
|
||||
/// NOTE: Enabling this option does have some impact on runtime performance
|
||||
/// and OS footprint.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
#ifndef XOS_OPT_STATS
|
||||
#define XOS_OPT_STATS 1
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Set this option to 1 to enable statistics tracking for message queues.
|
||||
/// enabling this will cause message queue objects to increase in size, and add
|
||||
/// some overhead to message queue processing.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
#ifndef XOS_OPT_MSGQ_STATS
|
||||
#define XOS_OPT_MSGQ_STATS 0
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Size of interrupt stack in bytes. Shared by all interrupt handlers. Must be
|
||||
/// sized to handle worst case nested interrupts. This is also used by the idle
|
||||
/// thread so must exist even if interrupts are not configured.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
#ifndef XOS_INT_STACK_SIZE
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
#define XOS_INT_STACK_SIZE 8192
|
||||
#else
|
||||
#define XOS_INT_STACK_SIZE 32
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Default maximum interrupt level at which XOS primitives may be called.
|
||||
/// It is the level at which interrupts are disabled by default.
|
||||
/// See also description of xos_set_int_pri_level().
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
#ifndef XOS_MAX_OS_INTLEVEL
|
||||
#define XOS_MAX_OS_INTLEVEL XCHAL_EXCM_LEVEL
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Set this to 1 to enable stack checking. The stack is filled with a pattern
|
||||
/// on thread creation, and the stack is checked at certain times during system
|
||||
/// operation.
|
||||
/// WARNING: Enabling this option can have some impact on runtime performance.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
#ifndef XOS_OPT_STACK_CHECK
|
||||
#if XOS_DEBUG
|
||||
#define XOS_OPT_STACK_CHECK 1
|
||||
#else
|
||||
#define XOS_OPT_STACK_CHECK 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Set XOS_CLOCK_FREQ to the system clock frequency if this is known ahead of
|
||||
/// time. Otherwise, call xos_set_clock_freq() to set it at run time.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
#ifndef XOS_CLOCK_FREQ
|
||||
#define XOS_CLOCK_FREQ 1000000
|
||||
#endif
|
||||
#define XOS_DEFAULT_CLOCK_FREQ XOS_CLOCK_FREQ
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Set this option to 1 to enable software prioritization of interrupts. The
|
||||
/// priority scheme applied is that a higher interrupt number at the same level
|
||||
/// will have higher priority.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
#ifndef XOS_OPT_INTERRUPT_SWPRI
|
||||
#define XOS_OPT_INTERRUPT_SWPRI 1
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Set this option to 1 to use the thread-safe version of the C runtime library.
|
||||
/// You may need to enable this if you call C library functions from multiple
|
||||
/// threads -- see the documentation for the relevant C library to determine if
|
||||
/// this is necessary. This option increases the size of the TCB.
|
||||
/// NOTE: At this time only the newlib and xclib libraries are supported for
|
||||
/// thread safety.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
#include <xtensa/config/system.h>
|
||||
|
||||
#ifndef XOS_OPT_THREAD_SAFE_CLIB
|
||||
|
||||
#if XSHAL_CLIB == XTHAL_CLIB_XCLIB
|
||||
#define XOS_OPT_THREAD_SAFE_CLIB 1
|
||||
#elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB
|
||||
#define XOS_OPT_THREAD_SAFE_CLIB 1
|
||||
#else
|
||||
#define XOS_OPT_THREAD_SAFE_CLIB 0
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Set this option to 1 to enable the wait timeout feature. This allows waits
|
||||
/// on waitable objects to expire after a specified timeout.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
#ifndef XOS_OPT_WAIT_TIMEOUT
|
||||
#define XOS_OPT_WAIT_TIMEOUT 1
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Set this option to 1 to enable threads waiting on timer objects. If this
|
||||
/// feature is not used, turning it off will make timer objects smaller, and
|
||||
/// reduce the time taken by timer expiry processing (by a small amount).
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
#ifndef XOS_OPT_TIMER_WAIT
|
||||
#define XOS_OPT_TIMER_WAIT 1
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Set this option to 1 to enable time-slicing between multiple threads at the
|
||||
/// same priority. If this option is enabled then on every timer tick the timer
|
||||
/// handler will switch out the current thread if there is another ready thread
|
||||
/// at the same priority, and allow the latter thread to run. Execution will be
|
||||
/// round robin switched among all the threads at the same priority.
|
||||
///
|
||||
/// Currently the time slice interval is fixed to be one timer tick.
|
||||
///
|
||||
/// This feature is most useful if fixed duration timer ticks are used.
|
||||
/// If dynamic ticking is enabled, then time slicing will work unpredictably
|
||||
/// because the interval between ticks will vary. In some cases it may be
|
||||
/// better to turn time slicing off.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
#ifndef XOS_OPT_TIME_SLICE
|
||||
#define XOS_OPT_TIME_SLICE 1
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __XOS_PARAMS_H__
|
||||
|
||||
+201
@@ -0,0 +1,201 @@
|
||||
|
||||
// xos_regaccess.h - Access routines for various processor special registers.
|
||||
|
||||
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining
|
||||
// a copy of this software and associated documentation files (the
|
||||
// "Software"), to deal in the Software without restriction, including
|
||||
// without limitation the rights to use, copy, modify, merge, publish,
|
||||
// distribute, sublicense, and/or sell copies of the Software, and to
|
||||
// permit persons to whom the Software is furnished to do so, subject to
|
||||
// the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
#ifndef __REGACCESS_H__
|
||||
#define __REGACCESS_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "xos_types.h"
|
||||
|
||||
#include <xtensa/config/core.h>
|
||||
|
||||
#if defined (__XCC__)
|
||||
#if XCHAL_HAVE_CCOUNT
|
||||
#include <xtensa/tie/xt_timer.h>
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Read CCOUNT register.
|
||||
//-----------------------------------------------------------------------------
|
||||
static __inline__ uint32_t xos_get_ccount(void)
|
||||
{
|
||||
#if XCHAL_HAVE_CCOUNT
|
||||
|
||||
#if defined (__XCC__)
|
||||
return XT_RSR_CCOUNT();
|
||||
#else
|
||||
uint32_t ccount;
|
||||
|
||||
__asm__ __volatile__ ( "rsr %0, ccount" : "=a" (ccount) );
|
||||
return ccount;
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
return 0;
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Read CCOMPARE0
|
||||
//-----------------------------------------------------------------------------
|
||||
static __inline__ uint32_t xos_get_ccompare0(void)
|
||||
{
|
||||
#if XCHAL_HAVE_CCOUNT
|
||||
|
||||
#if defined (__XCC__)
|
||||
return XT_RSR_CCOMPARE0();
|
||||
#else
|
||||
uint32_t ccompare0;
|
||||
|
||||
__asm__ __volatile__ ( "rsr %0, ccompare0" : "=a" (ccompare0));
|
||||
return ccompare0;
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
return 0;
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Read CCOMPARE1
|
||||
//-----------------------------------------------------------------------------
|
||||
#if (XCHAL_NUM_TIMERS > 1)
|
||||
static __inline__ uint32_t xos_get_ccompare1(void)
|
||||
{
|
||||
#if defined (__XCC__)
|
||||
return XT_RSR_CCOMPARE1();
|
||||
#else
|
||||
uint32_t ccompare1;
|
||||
|
||||
__asm__ __volatile__ ( "rsr %0, ccompare1" : "=a" (ccompare1));
|
||||
return ccompare1;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Read CCOMPARE2
|
||||
//-----------------------------------------------------------------------------
|
||||
#if (XCHAL_NUM_TIMERS > 2)
|
||||
static __inline__ uint32_t xos_get_ccompare2(void)
|
||||
{
|
||||
#if defined (__XCC__)
|
||||
return XT_RSR_CCOMPARE2();
|
||||
#else
|
||||
uint32_t ccompare2;
|
||||
|
||||
__asm__ __volatile__ ( "rsr %0, ccompare2" : "=a" (ccompare2));
|
||||
return ccompare2;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Write CCOMPARE0
|
||||
//-----------------------------------------------------------------------------
|
||||
static __inline__ void xos_set_ccompare0(uint32_t val)
|
||||
{
|
||||
#if XCHAL_HAVE_CCOUNT
|
||||
|
||||
#if defined (__XCC__)
|
||||
XT_WSR_CCOMPARE0(val);
|
||||
XT_ISYNC();
|
||||
#else
|
||||
__asm__ __volatile__ (
|
||||
"wsr %0, ccompare0\n"
|
||||
"isync"
|
||||
:
|
||||
: "a" (val)
|
||||
);
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
// Empty
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Write CCOMPARE1
|
||||
//-----------------------------------------------------------------------------
|
||||
#if (XCHAL_NUM_TIMERS > 1)
|
||||
static __inline__ void xos_set_ccompare1(uint32_t val)
|
||||
{
|
||||
#if defined (__XCC__)
|
||||
XT_WSR_CCOMPARE1(val);
|
||||
XT_ISYNC();
|
||||
#else
|
||||
__asm__ __volatile__ (
|
||||
"wsr %0, ccompare1\n"
|
||||
"isync"
|
||||
:
|
||||
: "a" (val)
|
||||
);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Write CCOMPARE2
|
||||
//-----------------------------------------------------------------------------
|
||||
#if (XCHAL_NUM_TIMERS > 2)
|
||||
static __inline__ void xos_set_ccompare2(uint32_t val)
|
||||
{
|
||||
#if defined (__XCC__)
|
||||
XT_WSR_CCOMPARE2(val);
|
||||
XT_ISYNC();
|
||||
#else
|
||||
__asm__ __volatile__ (
|
||||
"wsr %0, ccompare2\n"
|
||||
"isync"
|
||||
:
|
||||
: "a" (val)
|
||||
);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __REGACCESS_H__
|
||||
|
||||
+190
@@ -0,0 +1,190 @@
|
||||
/** @file */
|
||||
|
||||
// xos_semaphore.h - XOS Semaphore API interface and data structures.
|
||||
|
||||
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining
|
||||
// a copy of this software and associated documentation files (the
|
||||
// "Software"), to deal in the Software without restriction, including
|
||||
// without limitation the rights to use, copy, modify, merge, publish,
|
||||
// distribute, sublicense, and/or sell copies of the Software, and to
|
||||
// permit persons to whom the Software is furnished to do so, subject to
|
||||
// the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
// NOTE: Do not include this file directly in your application. Including
|
||||
// xos.h will automatically include this file.
|
||||
|
||||
#ifndef __XOS_SEMAPHORE_H__
|
||||
#define __XOS_SEMAPHORE_H__
|
||||
|
||||
#include "xos_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Semaphore flags.
|
||||
//-----------------------------------------------------------------------------
|
||||
#define XOS_SEM_WAIT_PRIORITY 0x0000 ///< Wake waiters in priority order (default)
|
||||
#define XOS_SEM_WAIT_FIFO 0x0001 ///< Wake waiters in FIFO order
|
||||
#define XOS_SEM_PRIORITY_INV 0x0004 // Protect against priority inversion
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// XosSem object.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
typedef struct XosSem {
|
||||
uint32_t count; ///< Current count
|
||||
XosThreadQueue waitq; ///< Queue of waiters.
|
||||
uint32_t flags; ///< Properties.
|
||||
#if XOS_SEM_DEBUG
|
||||
uint32_t sig; // Valid signature indicates inited.
|
||||
#endif
|
||||
} XosSem;
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Initialize a semaphore object before first use.
|
||||
///
|
||||
/// \param sem Pointer to semaphore object.
|
||||
///
|
||||
/// \param flags Creation flags:
|
||||
/// - XOS_SEM_WAIT_FIFO -- queue waiting threads in
|
||||
/// fifo order.
|
||||
/// - XOS_SEM_WAIT_PRIORITY -- queue waiting threads
|
||||
/// by priority. This is the default.
|
||||
/// - XOS_SEM_PRIORITY_INV -- protect against priority
|
||||
/// inversion.
|
||||
///
|
||||
/// \param initial_count Initial count for semaphore on creation.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
/// NOTE: XOS_SEM_PRIORITY_INV is NOT supported in the current release. It will
|
||||
/// be supported in a future release.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_sem_create(XosSem * sem, uint32_t flags, uint32_t initial_count);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Destroy a semaphore object. Must have been previously created by calling
|
||||
/// xos_sem_create().
|
||||
///
|
||||
/// \param sem Pointer to semaphore object.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_sem_delete(XosSem * sem);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Decrement the semaphore count: block until the decrement is possible.
|
||||
/// The semaphore must have been initialized.
|
||||
///
|
||||
/// \param sem Pointer to semaphore object.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_sem_get(XosSem * sem);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Decrement the semaphore count: block until the decrement is possible or
|
||||
/// the timeout expires. The semaphore must have been initialized.
|
||||
///
|
||||
/// \param sem Pointer to semaphore object.
|
||||
///
|
||||
/// \param to_cycles Timeout in cycles. Convert from time to cycles
|
||||
/// using the helper functions provided in xos_timer.
|
||||
/// A value of zero indicates no timeout.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, XOS_ERR_TIMEOUT on timeout, else error code.
|
||||
///
|
||||
/// NOTE: If XOS_OPT_WAIT_TIMEOUT is not enabled, then the timeout value is
|
||||
/// ignored, and no timeout will occur.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_sem_get_timeout(XosSem * sem, uint64_t to_cycles);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Increment the semaphore count. The semaphore must have been initialized.
|
||||
/// Remember that this action may wake up a waiting thread, and if that thread
|
||||
/// is higher priority then there will be an immediate context switch.
|
||||
///
|
||||
/// \param sem Pointer to semaphore object.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_sem_put(XosSem * sem);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Try to decrement the semaphore, but do not block if the semaphore count is
|
||||
/// zero. Return immediately. The semaphore must have been initialized.
|
||||
///
|
||||
/// \param sem Pointer to semaphore object.
|
||||
///
|
||||
/// \return Returns XOS_OK on success (semaphore decremented), else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_sem_tryget(XosSem * sem);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Return the count of the semaphore but do not attempt to decrement it.
|
||||
/// The semaphore must have been initialized.
|
||||
///
|
||||
/// \param sem Pointer to semaphore object.
|
||||
///
|
||||
/// \return Returns semaphore count, -1 on error.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
static inline int32_t
|
||||
xos_sem_test(XosSem * sem)
|
||||
{
|
||||
XOS_ASSERT(sem);
|
||||
|
||||
return sem ? sem->count : -1;
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __XOS_SEMAPHORE_H__
|
||||
|
||||
+175
@@ -0,0 +1,175 @@
|
||||
/** @file */
|
||||
|
||||
// xos_stopwatch.h - XOS Stopwatch objects and related API.
|
||||
|
||||
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining
|
||||
// a copy of this software and associated documentation files (the
|
||||
// "Software"), to deal in the Software without restriction, including
|
||||
// without limitation the rights to use, copy, modify, merge, publish,
|
||||
// distribute, sublicense, and/or sell copies of the Software, and to
|
||||
// permit persons to whom the Software is furnished to do so, subject to
|
||||
// the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
// NOTE: Do not include this file directly in your application. Including
|
||||
// xos.h will automatically include this file.
|
||||
|
||||
|
||||
#ifndef __XOS_STOPWATCH_H__
|
||||
#define __XOS_STOPWATCH_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "xos_types.h"
|
||||
#include "xos_params.h"
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// A stopwatch object can be used to track elapsed time and accumulate total
|
||||
// elapsed time over multiple execution periods. The stopwatch records the
|
||||
// time whenever its start function is called, and stops recording the time
|
||||
// when the stop function is called and updates its cumulative time counter.
|
||||
// The stopwatch keeps time in cycles. This can be converted to seconds etc.
|
||||
// by using the XOS conversion calls such as xos_cycles_to_secs().
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// XosStopwatch object.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
typedef struct XosStopwatch {
|
||||
uint64_t total; ///< Total accumulated cycle count
|
||||
uint64_t start; ///< Starting system cycle count
|
||||
uint16_t active; ///< Active flag (nonzero when active)
|
||||
} XosStopwatch;
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Initialize a stopwatch object.
|
||||
///
|
||||
/// \param sw Pointer to a stopwatch object.
|
||||
///
|
||||
/// \return Returns nothing.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
static inline void
|
||||
xos_stopwatch_init(XosStopwatch * sw)
|
||||
{
|
||||
sw->total = 0;
|
||||
sw->start = 0;
|
||||
sw->active = 0;
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Start a stopwatch. Starts cycle counting.
|
||||
/// Note that this does not necessarily start counting from zero. The current
|
||||
/// run (start-to-stop interval) will just get added to the accumulated count
|
||||
/// in the stopwatch if any.
|
||||
/// To reset the accumulated count, use xos_stopwatch_clear().
|
||||
///
|
||||
/// \param sw Pointer to a stopwatch object.
|
||||
///
|
||||
/// \return Returns nothing.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
static inline void
|
||||
xos_stopwatch_start(XosStopwatch * sw)
|
||||
{
|
||||
XOS_ASSERT(!sw->active);
|
||||
sw->active = 1;
|
||||
sw->start = xos_get_system_cycles();
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Stop a stopwatch. Stops cycle counting and updates total.
|
||||
///
|
||||
/// \param sw Pointer to a stopwatch object.
|
||||
///
|
||||
/// \return Returns nothing.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
static inline void
|
||||
xos_stopwatch_stop(XosStopwatch * sw)
|
||||
{
|
||||
XOS_ASSERT(sw->active);
|
||||
sw->active = 0;
|
||||
sw->total += xos_get_system_cycles() - sw->start;
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Get stopwatch accumulated count.
|
||||
///
|
||||
/// \param sw Pointer to a stopwatch object.
|
||||
///
|
||||
/// \return Returns the accumulated count.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
static inline uint64_t
|
||||
xos_stopwatch_count(XosStopwatch * sw)
|
||||
{
|
||||
return sw->total;
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Get elapsed time since stopwatch was started. If not started, returns zero.
|
||||
///
|
||||
/// \param sw Pointer to a stopwatch object.
|
||||
///
|
||||
/// \return Returns elapsed time in cycles.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
static inline uint64_t
|
||||
xos_stopwatch_elapsed(XosStopwatch * sw)
|
||||
{
|
||||
return sw->active ? xos_get_system_cycles() - sw->start : 0;
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Clears a stopwatch. Resets the accumulated count to zero, and deactivates
|
||||
/// it if active.
|
||||
///
|
||||
/// \param sw Pointer to a stopwatch object.
|
||||
///
|
||||
/// \return Returns nothing.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
static inline void
|
||||
xos_stopwatch_clear(XosStopwatch * sw)
|
||||
{
|
||||
xos_stopwatch_init(sw);
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __XOS_STOPWATCH_H__
|
||||
|
||||
Executable
+330
@@ -0,0 +1,330 @@
|
||||
/** @file */
|
||||
|
||||
// xos_syslog.h - XOS Event logging module.
|
||||
|
||||
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining
|
||||
// a copy of this software and associated documentation files (the
|
||||
// "Software"), to deal in the Software without restriction, including
|
||||
// without limitation the rights to use, copy, modify, merge, publish,
|
||||
// distribute, sublicense, and/or sell copies of the Software, and to
|
||||
// permit persons to whom the Software is furnished to do so, subject to
|
||||
// the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
// NOTE: Do not include this file directly in your application. Including
|
||||
// xos.h will automatically include this file.
|
||||
|
||||
|
||||
#ifndef __XOS_SYSLOG_H__
|
||||
#define __XOS_SYSLOG_H__
|
||||
|
||||
#include "xos_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// The XOS system log is an array of fixed size entries. The size of the log
|
||||
// is determined by the application, and memory for the log must be provided
|
||||
// at init time. Every time the log function is called, an entry is made in
|
||||
// the log and the next pointer advanced. When the log is full, it will wrap
|
||||
// around and start overwriting the oldest entries.
|
||||
// Logging can be done from C/C++ code as well as assembly code, and at any
|
||||
// interrupt level, even from high level interrupt handlers.
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Defines.
|
||||
//-----------------------------------------------------------------------------
|
||||
#define XOS_SYSLOG_ENABLED 0x0001
|
||||
|
||||
|
||||
///----------------------------------------------------------------------------
|
||||
///
|
||||
/// Use this macro to compute how much memory to allocate for the syslog.
|
||||
///
|
||||
///----------------------------------------------------------------------------
|
||||
#define XOS_SYSLOG_SIZE(num_entries) \
|
||||
( sizeof(XosSysLog) + ((num_entries - 1) * sizeof(XosSysLogEntry)) )
|
||||
|
||||
|
||||
///----------------------------------------------------------------------------
|
||||
///
|
||||
/// System log entry structure.
|
||||
///
|
||||
///----------------------------------------------------------------------------
|
||||
typedef struct XosSysLogEntry {
|
||||
uint32_t timestamp; ///< Timestamp in clock cycles
|
||||
uint32_t param1; ///< User defined value
|
||||
uint32_t param2; ///< User defined value
|
||||
struct XosSysLogEntry * next; ///< Link to next entry
|
||||
} XosSysLogEntry;
|
||||
|
||||
|
||||
///----------------------------------------------------------------------------
|
||||
///
|
||||
/// System log structure.
|
||||
///
|
||||
///----------------------------------------------------------------------------
|
||||
typedef struct XosSysLog {
|
||||
uint16_t flags; ///< Flags
|
||||
uint16_t size; ///< Number of entries
|
||||
XosSysLogEntry * next; ///< Next write position
|
||||
XosSysLogEntry entries[1]; ///< First entry
|
||||
} XosSysLog;
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Pointer to syslog area.
|
||||
//-----------------------------------------------------------------------------
|
||||
extern XosSysLog * xos_syslog;
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
///
|
||||
/// Initialize the syslog. Initializing the log also enables it. The system
|
||||
/// log always wraps around when full and overwrites the oldest entries.
|
||||
///
|
||||
/// \param log_mem Pointer to allocated memory for the log.
|
||||
///
|
||||
/// \param num_entries The number of entries that the log can contain.
|
||||
///
|
||||
/// \return Returns nothing.
|
||||
///
|
||||
//----------------------------------------------------------------------------
|
||||
static inline void
|
||||
xos_syslog_init(void * log_mem, uint16_t num_entries)
|
||||
{
|
||||
uint16_t i;
|
||||
|
||||
xos_syslog = (XosSysLog *) log_mem;
|
||||
xos_syslog->size = num_entries;
|
||||
xos_syslog->next = xos_syslog->entries;
|
||||
|
||||
for (i = 0; i < num_entries - 1; i++) {
|
||||
xos_syslog->entries[i].next = &(xos_syslog->entries[i+1]);
|
||||
xos_syslog->entries[i].timestamp = 0;
|
||||
}
|
||||
xos_syslog->entries[i].next = xos_syslog->entries;
|
||||
xos_syslog->entries[i].timestamp = 0;
|
||||
|
||||
xos_syslog->flags = XOS_SYSLOG_ENABLED;
|
||||
}
|
||||
|
||||
|
||||
///----------------------------------------------------------------------------
|
||||
///
|
||||
/// Reset the syslog. All entries made up to now are abandoned and the write
|
||||
/// pointer is set to the first entry location.
|
||||
///
|
||||
/// No parameters.
|
||||
///
|
||||
/// \return Returns nothing.
|
||||
///
|
||||
///----------------------------------------------------------------------------
|
||||
static inline void
|
||||
xos_syslog_clear()
|
||||
{
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
uint32_t ps = XT_RSIL(XCHAL_NUM_INTLEVELS);
|
||||
#endif
|
||||
|
||||
xos_syslog_init(xos_syslog, xos_syslog->size);
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
xos_restore_int_pri_level(ps);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
///----------------------------------------------------------------------------
|
||||
///
|
||||
/// Enable logging to the syslog. This function needs to be called only if
|
||||
/// logging had been previously disabled via xos_syslog_disable(), since
|
||||
/// initializing the syslog automatically enables it.
|
||||
///
|
||||
/// No parameters.
|
||||
///
|
||||
/// \return Returns nothing.
|
||||
///
|
||||
///----------------------------------------------------------------------------
|
||||
static inline void
|
||||
xos_syslog_enable()
|
||||
{
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
uint32_t ps = XT_RSIL(XCHAL_NUM_INTLEVELS);
|
||||
#endif
|
||||
|
||||
xos_syslog->flags |= XOS_SYSLOG_ENABLED;
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
xos_restore_int_pri_level(ps);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
///----------------------------------------------------------------------------
|
||||
///
|
||||
/// Disable logging to the syslog. It is sometimes useful to disable logging
|
||||
/// while the log is being examined or dumped.
|
||||
///
|
||||
/// No parameters.
|
||||
///
|
||||
/// \return Returns nothing.
|
||||
///
|
||||
///----------------------------------------------------------------------------
|
||||
static inline void
|
||||
xos_syslog_disable()
|
||||
{
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
uint32_t ps = XT_RSIL(XCHAL_NUM_INTLEVELS);
|
||||
#endif
|
||||
xos_syslog->flags &= ~XOS_SYSLOG_ENABLED;
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
xos_restore_int_pri_level(ps);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
///----------------------------------------------------------------------------
|
||||
///
|
||||
/// Write an entry into the syslog. This function does disable all interrupts
|
||||
/// since logging can be done from interrupt handlers as well. It will write
|
||||
/// into the log only if the log exists and is enabled.
|
||||
///
|
||||
/// \param param1 User defined value.
|
||||
///
|
||||
/// \param param2 User defined value.
|
||||
///
|
||||
/// \return Returns nothing.
|
||||
///
|
||||
///----------------------------------------------------------------------------
|
||||
static inline void
|
||||
xos_syslog_write(uint32_t param1, uint32_t param2)
|
||||
{
|
||||
if (xos_syslog != XOS_NULL) {
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
uint32_t ps = XT_RSIL(XCHAL_NUM_INTLEVELS);
|
||||
#endif
|
||||
|
||||
if ((xos_syslog->flags & XOS_SYSLOG_ENABLED) != 0) {
|
||||
XosSysLogEntry * next = xos_syslog->next;
|
||||
|
||||
next->timestamp = xos_get_ccount();
|
||||
next->param1 = param1;
|
||||
next->param2 = param2;
|
||||
|
||||
xos_syslog->next = next->next;
|
||||
}
|
||||
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
xos_restore_int_pri_level(ps);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
///----------------------------------------------------------------------------
|
||||
///
|
||||
/// Read the first (oldest) entry in the syslog. Will return an error if the
|
||||
/// log has not been created or is empty. Storage to copy the entry must be
|
||||
/// provided by the caller.
|
||||
///
|
||||
/// \param entry Pointer to storage where the entry data will be
|
||||
/// copied. This pointer must be passed to
|
||||
/// xos_syslog_get_next().
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
///----------------------------------------------------------------------------
|
||||
static inline int32_t
|
||||
xos_syslog_get_first(XosSysLogEntry * entry)
|
||||
{
|
||||
if (xos_syslog == XOS_NULL) {
|
||||
return XOS_ERR_NOT_FOUND;
|
||||
}
|
||||
|
||||
if (entry != XOS_NULL) {
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
uint32_t ps = XT_RSIL(XCHAL_NUM_INTLEVELS);
|
||||
#endif
|
||||
XosSysLogEntry * next = xos_syslog->next;
|
||||
|
||||
// 'next' should be pointing to the next entry to be overwritten, if we
|
||||
// have wrapped. This means it is the oldest entry. However if this entry
|
||||
// has a zero timestamp then we have not wrapped, in which case we must
|
||||
// look at the first entry in the list.
|
||||
if (next->timestamp == 0) {
|
||||
next = xos_syslog->entries;
|
||||
}
|
||||
|
||||
*entry = *next;
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
xos_restore_int_pri_level(ps);
|
||||
#endif
|
||||
return entry->timestamp ? XOS_OK : XOS_ERR_NOT_FOUND;
|
||||
}
|
||||
|
||||
return XOS_ERR_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
|
||||
///----------------------------------------------------------------------------
|
||||
///
|
||||
/// Get the next sequential entry from the syslog. This function must be called
|
||||
/// only after xos_syslog_get_first() has been called.
|
||||
///
|
||||
/// \param entry Pointer to storage where entry data will be copied.
|
||||
/// Must be the same pointer that was passed in the call
|
||||
/// to xos_syslog_get_first(), as it is used to keep track
|
||||
/// of the current position.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
///----------------------------------------------------------------------------
|
||||
static inline int32_t
|
||||
xos_syslog_get_next(XosSysLogEntry * entry)
|
||||
{
|
||||
if (entry != XOS_NULL) {
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
uint32_t ps = XT_RSIL(XCHAL_NUM_INTLEVELS);
|
||||
#endif
|
||||
XosSysLogEntry * next = entry->next;
|
||||
int32_t ret = XOS_OK;
|
||||
|
||||
// Make sure we're not pointing past the last entry.
|
||||
if ((next != XOS_NULL) && (next != xos_syslog->next) && (next->timestamp != 0)) {
|
||||
*entry = *next;
|
||||
}
|
||||
else {
|
||||
ret = XOS_ERR_NOT_FOUND;
|
||||
}
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
xos_restore_int_pri_level(ps);
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
||||
return XOS_ERR_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __XOS_SYSLOG_H__
|
||||
|
||||
Executable
+1086
File diff suppressed because it is too large
Load Diff
Executable
+592
@@ -0,0 +1,592 @@
|
||||
/** @file */
|
||||
|
||||
// xos_timer.h - XOS Timer API interface and data structures.
|
||||
|
||||
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining
|
||||
// a copy of this software and associated documentation files (the
|
||||
// "Software"), to deal in the Software without restriction, including
|
||||
// without limitation the rights to use, copy, modify, merge, publish,
|
||||
// distribute, sublicense, and/or sell copies of the Software, and to
|
||||
// permit persons to whom the Software is furnished to do so, subject to
|
||||
// the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
// NOTE: Do not include this file directly in your application. Including
|
||||
// xos.h will automatically include this file.
|
||||
|
||||
|
||||
#ifndef __XOS_TIMER_H__
|
||||
#define __XOS_TIMER_H__
|
||||
|
||||
#include "xos_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Function pointer type for timer callbacks.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
typedef void (XosTimerFunc)(void * arg);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Timer event structure. Used to track pending timer events.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
typedef struct XosTimer {
|
||||
struct XosTimer * next; ///< Pointer to next event in list.
|
||||
uint64_t when; ///< Time (clock cycles) at which to trigger.
|
||||
uint64_t delta; ///< Delta for next re-trigger, 0 if none.
|
||||
XosTimerFunc * fn; ///< Function to call when timer expires.
|
||||
void * arg; ///< Argument to pass to called function.
|
||||
bool active; ///< Set if active (in some list of events).
|
||||
#if XOS_OPT_TIMER_WAIT
|
||||
XosThreadQueue waitq; ///< Queue of threads waiting on this timer.
|
||||
#endif
|
||||
#if XOS_TIMER_DEBUG
|
||||
uint32_t signature;
|
||||
#endif
|
||||
} XosTimer;
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Extern declarations.
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
// System clock frequency in cycles per second.
|
||||
extern uint32_t xos_clock_freq;
|
||||
|
||||
|
||||
///@{
|
||||
//-----------------------------------------------------------------------------
|
||||
// Functions to convert from clock cycles to time units and vice versa.
|
||||
//
|
||||
// Note that these are integer conversions so for example a cycle count of less
|
||||
// than one second will convert to zero seconds.
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
/// Converts CPU cycles to time in seconds.
|
||||
///
|
||||
/// \param cycles Number of CPU cycles.
|
||||
///
|
||||
/// \return Equivalent number of seconds (truncated to integer).
|
||||
static inline uint64_t
|
||||
xos_cycles_to_secs(uint64_t cycles)
|
||||
{
|
||||
return cycles / xos_clock_freq;
|
||||
}
|
||||
|
||||
/// Converts CPU cycles to time in milliseconds.
|
||||
///
|
||||
/// \param cycles Number of CPU cycles.
|
||||
///
|
||||
/// \return Equivalent number of milliseconds (truncated to integer).
|
||||
static inline uint64_t
|
||||
xos_cycles_to_msecs(uint64_t cycles)
|
||||
{
|
||||
return (cycles * 1000) / xos_clock_freq;
|
||||
}
|
||||
|
||||
/// Converts CPU cycles to time in microseconds.
|
||||
///
|
||||
/// \param cycles Number of CPU cycles.
|
||||
///
|
||||
/// \return Equivalent number of microseconds (truncated to integer).
|
||||
static inline uint64_t
|
||||
xos_cycles_to_usecs(uint64_t cycles)
|
||||
{
|
||||
return (cycles * 1000000) / xos_clock_freq;
|
||||
}
|
||||
|
||||
/// Converts time in seconds to CPU cycle count.
|
||||
///
|
||||
/// \param secs Number of seconds.
|
||||
///
|
||||
/// \return Equivalent number of CPU cycles.
|
||||
static inline uint64_t
|
||||
xos_secs_to_cycles(uint64_t secs)
|
||||
{
|
||||
return secs * xos_clock_freq;
|
||||
}
|
||||
|
||||
/// Converts time in milliseconds to CPU cycle count.
|
||||
///
|
||||
/// \param msecs Number of milliseconds.
|
||||
///
|
||||
/// \return Equivalent number of CPU cycles.
|
||||
static inline uint64_t
|
||||
xos_msecs_to_cycles(uint64_t msecs)
|
||||
{
|
||||
return (msecs * xos_clock_freq) / 1000;
|
||||
}
|
||||
|
||||
/// Converts time in microseconds to CPU cycle count.
|
||||
///
|
||||
/// \param usecs Number of microseconds.
|
||||
///
|
||||
/// \return Equivalent number of CPU cycles.
|
||||
static inline uint64_t
|
||||
xos_usecs_to_cycles(uint64_t usecs)
|
||||
{
|
||||
return (usecs * xos_clock_freq) / 1000000;
|
||||
}
|
||||
///@}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Set system clock frequency. This is expected to be set only once, and only
|
||||
/// if the clock frequency is not known at compile time.
|
||||
///
|
||||
/// \param freq Frequency in cycles per second.
|
||||
///
|
||||
/// \return Returns nothing.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
static inline void
|
||||
xos_set_clock_freq(uint32_t freq)
|
||||
{
|
||||
xos_clock_freq = freq;
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Get current system clock frequency.
|
||||
///
|
||||
/// \return Returns current system clock frequency in cycles per second.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
static inline uint32_t
|
||||
xos_get_clock_freq()
|
||||
{
|
||||
return xos_clock_freq;
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Initialize timer support and start the system timer.
|
||||
/// This function must be called before calling any other timer function.
|
||||
///
|
||||
/// NOTE: The smaller the tick period, the more precisely delays can be
|
||||
/// specified using timers. However, we also need to make the tick period
|
||||
/// large enough to allow time both to execute the tick timer interrupt handler
|
||||
/// and for the application to make reasonable forward progress. If tick_period
|
||||
/// is too small, the timer interrupt may re-trigger before the timer interrupt
|
||||
/// handler has returned to the application, thus keeping the processor busy in
|
||||
/// constantly executing the timer interrupt handler without leaving any cycles
|
||||
/// for the application. Or, the application might get some cycles but only a
|
||||
/// fraction of what is spent in the timer interrupt handler, thus severely
|
||||
/// impacting application performance.
|
||||
///
|
||||
/// The exact number of cycles needed to execute the timer interrupt handler
|
||||
/// is not specified here. It depends on many factors (e.g. use of caches,
|
||||
/// various processor configuration options, etc) and can vary by orders of
|
||||
/// magnitude. Also note that the time to execute this handler is variable:
|
||||
/// when timers expire upon a given tick timer interrupt, their respective
|
||||
/// timer handler functions are called from within the interrupt handler.
|
||||
///
|
||||
/// \param timer_num Which Xtensa timer to use (0..2). This timer
|
||||
/// must exist and be configured at level 1 or at a
|
||||
/// medium-priority interrupt level (<=EXCM_LEVEL).
|
||||
/// If 'timer_num' is -1, then this function will
|
||||
/// automatically choose the highest priority timer
|
||||
/// that is suitable for use. This value will be
|
||||
/// passed to xos_system_timer_select().
|
||||
///
|
||||
/// \param tick_period Number of clock (CCOUNT) cycles between ticks.
|
||||
/// Must range between 0 and UINT32_MAX.
|
||||
/// Zero is used to specify dynamic tick (tickless)
|
||||
/// mode.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_start_system_timer(int32_t timer_num, uint32_t tick_period);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Get the timer number of the system timer. Useful mainly when XOS has been
|
||||
/// allowed to choose its own timer via xos_start_system_timer(). Not valid if
|
||||
/// called before the system timer has been started.
|
||||
///
|
||||
/// \return Returns one of XOS_SYS_TIMER_0, XOS_SYS_TIMER_1, XOS_SYS_TIMER_2
|
||||
/// or XOS_SYS_TIMER_EXTERNAL, or XOS_SYS_TIMER_NONE.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_get_system_timer_num(void);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Initialize timer object.
|
||||
///
|
||||
/// \param timer Pointer to timer event structure.
|
||||
///
|
||||
/// \return Returns nothing.
|
||||
///
|
||||
/// NOTE: This function should not be called on a timer object once it has
|
||||
/// been activated.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
void xos_timer_init(XosTimer * timer);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Flags for xos_timer_start().
|
||||
//-----------------------------------------------------------------------------
|
||||
#define XOS_TIMER_DELTA 0x0000
|
||||
#define XOS_TIMER_PERIODIC 0x0001
|
||||
#define XOS_TIMER_ABSOLUTE 0x0002
|
||||
#define XOS_TIMER_FROM_NOW 0x0000
|
||||
#define XOS_TIMER_FROM_LAST 0x0010
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Start the timer, and when the timer expires, call the specified function
|
||||
/// (invoke (*fn)(arg)). If the timer is periodic, it will be automatically
|
||||
/// restarted when it expires.
|
||||
///
|
||||
/// The specified timer event structure must have been initialized before
|
||||
/// first use by calling xos_timer_init().
|
||||
///
|
||||
/// The callback function will be called in an interrupt context. Hence it is
|
||||
/// NOT safe to use any coprocessors in the function, including the FPU. If a
|
||||
/// coprocessor must be used, then its state must be saved and restored across
|
||||
/// its use.
|
||||
///
|
||||
/// NOTE: If you are using the timer only to wait on (via xos_timer_wait())
|
||||
/// then it is not necessary to specify a callback function. You should pass
|
||||
/// NULL for the callback function and zero for the callback argument.
|
||||
///
|
||||
/// \param timer Pointer to timer event structure. Must have been
|
||||
/// initialized. May be active or not.
|
||||
///
|
||||
/// \param when When to call the function (see flags).
|
||||
///
|
||||
/// \param flags Set of option flags XOS_TIMER_* \n
|
||||
/// The following flags are mutually exclusive:
|
||||
/// - XOS_TIMER_DELTA -- when is number of cycles from
|
||||
/// [see below] (default)
|
||||
/// - XOS_TIMER_PERIODIC -- when is number of cycles
|
||||
/// from [see below], and timer continually
|
||||
/// re-triggers at that interval
|
||||
/// - XOS_TIMER_ABSOLUTE -- when is absolute value of
|
||||
/// cycle count \n
|
||||
/// \n
|
||||
/// The following flags are mutually exclusive:
|
||||
/// - XOS_TIMER_FROM_NOW -- *DELTA and *PERIODIC are
|
||||
/// relative to now (default)
|
||||
/// - XOS_TIMER_FROM_LAST -- *DELTA and *PERIODIC are
|
||||
/// relative to the timer event's last specified expiry
|
||||
/// time (usually in the future if active, in the past
|
||||
/// if not, absolute 0 if was never activated).
|
||||
///
|
||||
/// \param func Function to call (called in timer interrupt context).
|
||||
/// This argument is optional. Specify NULL if no function
|
||||
/// is to be called.
|
||||
///
|
||||
/// \param arg Argument passed to callback function. Only relevant if
|
||||
/// 'func' is not NULL.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_timer_start(XosTimer * timer,
|
||||
uint64_t when,
|
||||
uint32_t flags,
|
||||
XosTimerFunc * func,
|
||||
void * arg);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Stop the timer and remove it from the list of active timers. Has no effect
|
||||
/// if the timer is not active. Any waiting threads are woken up.
|
||||
///
|
||||
/// The timer structure must have been initialized at least once, else its
|
||||
/// contents are undefined and can lead to unpredictable results.
|
||||
///
|
||||
/// \param timer Pointer to timer object.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_timer_stop(XosTimer * timer);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Reset and restart the timer.
|
||||
///
|
||||
/// The timer is reset to go off at time "when" from now. If the timer was not
|
||||
/// active, it will be activated. If the timer was active, it will be restarted.
|
||||
/// If the timer is periodic, the period will be set to "when".
|
||||
/// The timer object must have been initialized at some point before this call.
|
||||
///
|
||||
/// \param timer Pointer to timer object.
|
||||
///
|
||||
/// \param when Number of cycles from now that the timer will expire.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_timer_restart(XosTimer * timer, uint64_t when);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Check if the timer is active. The timer is active if it has been started
|
||||
/// and not yet expired or canceled.
|
||||
///
|
||||
/// \param timer Pointer to timer object.
|
||||
///
|
||||
/// \return Returns non-zero if the timer is active, else zero.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
static inline int32_t
|
||||
xos_timer_is_active(XosTimer * timer)
|
||||
{
|
||||
return timer ? timer->active : 0;
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Get the repeat period for a periodic timer. For a one-shot timer this will
|
||||
/// return zero. The period is reported in system clock cycles.
|
||||
///
|
||||
/// \param timer Pointer to timer object.
|
||||
///
|
||||
/// \return Returns period in cycles, or zero for non-periodic timers.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
static inline uint64_t
|
||||
xos_timer_get_period(XosTimer * timer)
|
||||
{
|
||||
return timer ? timer->delta : 0;
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Set the repeat period for a periodic timer. The period must be specified
|
||||
/// in system clock cycles.
|
||||
///
|
||||
/// If the timer is active, the change in period does not take effect until
|
||||
/// the timer expires at least once after this call.
|
||||
/// Note that setting a period of zero will effectively turn a periodic timer
|
||||
/// into a one-shot timer. Similarly, a one-shot timer can be turned into a
|
||||
/// periodic timer.
|
||||
///
|
||||
/// \param timer Pointer to timer object.
|
||||
///
|
||||
/// \param period Repeat period in system clock cycles.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_timer_set_period(XosTimer * timer, uint64_t period);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Get the current system cycle count. This accounts for the periodic rollover
|
||||
/// of the 32-bit CCOUNT cycle counter and returns a 64-bit value.
|
||||
///
|
||||
/// \return Returns the current system cycle count.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
static inline uint64_t
|
||||
xos_get_system_cycles(void)
|
||||
{
|
||||
extern uint64_t xos_system_cycles;
|
||||
extern uint32_t xos_last_ccount;
|
||||
|
||||
// xos_last_ccount was updated when xos_system_cycles was last updated.
|
||||
// We need to add in the number of cycles elapsed since then.
|
||||
return xos_system_cycles + (xos_get_ccount() - xos_last_ccount);
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Put calling thread to sleep for at least the specified number of cycles.
|
||||
/// The actual number of cycles spent sleeping may be larger depending upon
|
||||
/// the granularity of the system timer. Once the specified time has elapsed
|
||||
/// the thread will be woken and made ready.
|
||||
///
|
||||
/// \param cycles Number of system clock cycles to sleep.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_thread_sleep(uint64_t cycles);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Put calling thread to sleep for at least the specified number of msec.
|
||||
/// The actual amount of time spent sleeping may be larger depending upon
|
||||
/// the granularity of the system timer. Once the specified time has elapsed
|
||||
/// the thread will be woken and made ready.
|
||||
///
|
||||
/// \return msecs The number of milliseconds to sleep.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
static inline int32_t
|
||||
xos_thread_sleep_msec(uint64_t msecs)
|
||||
{
|
||||
return xos_thread_sleep(xos_msecs_to_cycles(msecs));
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Put calling thread to sleep for at least the specified number of usec.
|
||||
/// The actual amount of time spent sleeping may be larger depending upon
|
||||
/// the granularity of the system timer. Once the specified time has elapsed
|
||||
/// the thread will be woken and made ready.
|
||||
///
|
||||
/// \return usecs The number of microseconds to sleep.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
static inline int32_t
|
||||
xos_thread_sleep_usec(uint64_t usecs)
|
||||
{
|
||||
return xos_thread_sleep(xos_usecs_to_cycles(usecs));
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Wait on a timer until it expires or is cancelled. The calling thread will
|
||||
/// be blocked. The timer must be active.
|
||||
/// NOTE: This operation is only available if XOS_OPT_TIMER_WAIT is set
|
||||
/// to 1 in the configuration options.
|
||||
///
|
||||
/// \param timer Pointer to timer object.
|
||||
///
|
||||
/// \return Returns XOS_OK on normal timeout, else an error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_timer_wait(XosTimer * timer);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// System timer control interface.
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Defines for system timer ID.
|
||||
//-----------------------------------------------------------------------------
|
||||
#define XOS_SYS_TIMER_0 0 ///< Internal timer 0
|
||||
#define XOS_SYS_TIMER_1 1 ///< Internal timer 1
|
||||
#define XOS_SYS_TIMER_2 2 ///< Internal timer 2
|
||||
#define XOS_SYS_TIMER_EXTERNAL -2 ///< External timer
|
||||
#define XOS_SYS_TIMER_NONE -1 ///< No system timer selected
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// This function handles XOS timer tick processing. It must be called by the
|
||||
/// timer interrupt handler on every timer interrupt. This function computes
|
||||
/// the time to the next tick and sets it up by calling xos_system_timer_set().
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
void
|
||||
xos_tick_handler(void);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Selects the timer to use. The selection may be one of the internal timers
|
||||
/// or an external timer. The default implementation selects an internal timer.
|
||||
/// This function can be overridden to provide custom timer processing or to
|
||||
/// support an external timer.
|
||||
///
|
||||
/// \param timer_num The internal timer number to select (0-2) or
|
||||
/// -1 to auto-select a timer. This parameter can
|
||||
/// be ignored by custom implementations that use
|
||||
/// an external timer.
|
||||
///
|
||||
/// \param psel Pointer to a location where the selected timer
|
||||
/// ID must be returned. The timer ID must be one
|
||||
/// of XOS_SYS_TIMER_0, XOS_SYS_TIMER_1, XOS_SYS_TIMER_2
|
||||
/// or XOS_SYS_TIMER_EXTERNAL.
|
||||
///
|
||||
/// \return Returns XOS_OK on success, else error code.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
int32_t
|
||||
xos_system_timer_select(int32_t timer_num, int32_t *psel);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Starts the system timer and sets up the first interrupt. This function can
|
||||
/// be overridden to provide custom timer processing or to support an external
|
||||
/// timer.
|
||||
///
|
||||
/// \param cycles The number of CPU cycles from now when the
|
||||
/// first interrupt must occur.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
void
|
||||
xos_system_timer_init(uint32_t cycles);
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// Sets the next trigger value of the system timer. The parameter 'cycles' is
|
||||
/// the number of CPU cycles from now when the interrupt must occur.
|
||||
/// This function can be overridden to provide custom timer processing or to
|
||||
/// support an external timer.
|
||||
///
|
||||
/// \param cycles The number of CPU cycles from now when the
|
||||
/// next interrupt must occur.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
void
|
||||
xos_system_timer_set(uint32_t cycles);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __XOS_TIMER_H__
|
||||
|
||||
Executable
+75
@@ -0,0 +1,75 @@
|
||||
/** @file */
|
||||
// xos_types.h - XOS type definitions.
|
||||
|
||||
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining
|
||||
// a copy of this software and associated documentation files (the
|
||||
// "Software"), to deal in the Software without restriction, including
|
||||
// without limitation the rights to use, copy, modify, merge, publish,
|
||||
// distribute, sublicense, and/or sell copies of the Software, and to
|
||||
// permit persons to whom the Software is furnished to do so, subject to
|
||||
// the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
// NOTE: Do not include this file directly in your application. Including
|
||||
// xos.h will automatically include this file.
|
||||
|
||||
|
||||
#ifndef __XOS_TYPES_H__
|
||||
#define __XOS_TYPES_H__
|
||||
|
||||
#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// The following are defined here because of the variations in the C libraries
|
||||
// that we need to work with.
|
||||
// - Not all of them have stdbool.h
|
||||
// - Not all of them define NULL as (void *)0
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// XOS define for NULL value. This makes the NULL value independent of the
|
||||
/// C library (not all of them define NULL the same way).
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
#define XOS_NULL ((void *)0)
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
///
|
||||
/// XOS definition of 'bool' type. Some C libraries do not support stdbool.h.
|
||||
///
|
||||
//-----------------------------------------------------------------------------
|
||||
#ifndef bool
|
||||
#define bool int8_t
|
||||
#define false 0 ///< XOS definition of 'false'
|
||||
#define true 1 ///< XOS definition of 'true'
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
|
||||
|
||||
#endif // __XOS_TYPES_H__
|
||||
|
||||
+283
@@ -0,0 +1,283 @@
|
||||
/*
|
||||
* Customer ID=11656; Build=0x5f626; Copyright (c) 2012 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef __XT_PERF_CONSTS_H__
|
||||
#define __XT_PERF_CONSTS_H__
|
||||
|
||||
/*
|
||||
* Performance monitor counter selectors
|
||||
*/
|
||||
|
||||
#define XTPERF_CNT_COMMITTED_INSN 0x8002 /* Instructions committed */
|
||||
#define XTPERF_CNT_BRANCH_PENALTY 0x8003 /* Branch penalty cycles */
|
||||
#define XTPERF_CNT_PIPELINE_INTERLOCKS 0x8004 /* Pipeline interlocks cycles */
|
||||
#define XTPERF_CNT_ICACHE_MISSES 0x8005 /* ICache misses penalty in cycles */
|
||||
#define XTPERF_CNT_DCACHE_MISSES 0x8006 /* DCache misses penalty in cycles */
|
||||
|
||||
#define XTPERF_CNT_CYCLES 0 /* Count cycles */
|
||||
#define XTPERF_CNT_OVERFLOW 1 /* Overflow of counter n-1 (assuming this is counter n) */
|
||||
#define XTPERF_CNT_INSN 2 /* Successfully completed instructions */
|
||||
#define XTPERF_CNT_D_STALL 3 /* Data-related GlobalStall cycles */
|
||||
#define XTPERF_CNT_I_STALL 4 /* Instruction-related and other GlobalStall cycles */
|
||||
#define XTPERF_CNT_EXR 5 /* Exceptions and pipeline replays */
|
||||
#define XTPERF_CNT_BUBBLES 6 /* Hold and other bubble cycles */
|
||||
#define XTPERF_CNT_I_TLB 7 /* Instruction TLB Accesses (per instruction retiring) */
|
||||
#define XTPERF_CNT_I_MEM 8 /* Instruction memory accesses (per instruction retiring) */
|
||||
#define XTPERF_CNT_D_TLB 9 /* Data TLB accesses */
|
||||
#define XTPERF_CNT_D_LOAD_U1 10 /* Data memory load instruction (load-store unit 1) */
|
||||
#define XTPERF_CNT_D_STORE_U1 11 /* Data memory store instruction (load-store unit 1) */
|
||||
#define XTPERF_CNT_D_ACCESS_U1 12 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 1) */
|
||||
#define XTPERF_CNT_D_LOAD_U2 13 /* Data memory load instruction (load-store unit 2) */
|
||||
#define XTPERF_CNT_D_STORE_U2 14 /* Data memory store instruction (load-store unit 2) */
|
||||
#define XTPERF_CNT_D_ACCESS_U2 15 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 2) */
|
||||
#define XTPERF_CNT_D_LOAD_U3 16 /* Data memory load instruction (load-store unit 3) */
|
||||
#define XTPERF_CNT_D_STORE_U3 17 /* Data memory store instruction (load-store unit 3) */
|
||||
#define XTPERF_CNT_D_ACCESS_U3 18 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 3) */
|
||||
#define XTPERF_CNT_MULTIPLE_LS 22 /* Multiple Load/Store */
|
||||
#define XTPERF_CNT_OUTBOUND_PIF 23 /* Outbound PIF transactions */
|
||||
#define XTPERF_CNT_INBOUND_PIF 24 /* Inbound PIF transactions */
|
||||
#define XTPERF_CNT_PREFETCH 26 /* Prefetch events */
|
||||
|
||||
|
||||
/*
|
||||
* Masks for each of the selector listed above
|
||||
*/
|
||||
|
||||
/* XTPERF_CNT_COMMITTED_INSN selector mask */
|
||||
|
||||
#define XTPERF_MASK_COMMITTED_INSN 0x0001
|
||||
|
||||
/* XTPERF_CNT_BRANCH_PENALTY selector mask */
|
||||
|
||||
#define XTPERF_MASK_BRANCH_PENALTY 0x0001
|
||||
|
||||
/* XTPERF_CNT_PIPELINE_INTERLOCKS selector mask */
|
||||
|
||||
#define XTPERF_MASK_PIPELINE_INTERLOCKS 0x0001
|
||||
|
||||
/* XTPERF_CNT_ICACHE_MISSES selector mask */
|
||||
|
||||
#define XTPERF_MASK_ICACHE_MISSES 0x0001
|
||||
|
||||
/* XTPERF_CNT_DCACHE_MISSES selector mask */
|
||||
|
||||
#define XTPERF_MASK_DCACHE_MISSES 0x0001
|
||||
|
||||
/* XTPERF_CNT_CYCLES selector mask */
|
||||
|
||||
#define XTPERF_MASK_CYCLES 0x0001
|
||||
|
||||
/* XTPERF_CNT_OVERFLOW selector mask */
|
||||
|
||||
#define XTPERF_MASK_OVERFLOW 0x0001
|
||||
|
||||
/*
|
||||
* XTPERF_CNT_INSN selector mask
|
||||
*/
|
||||
|
||||
#define XTPERF_MASK_INSN_ALL 0x8DFF
|
||||
|
||||
#define XTPERF_MASK_INSN_JX 0x0001 /* JX */
|
||||
#define XTPERF_MASK_INSN_CALLX 0x0002 /* CALLXn */
|
||||
#define XTPERF_MASK_INSN_RET 0x0004 /* call return i.e. RET, RETW */
|
||||
#define XTPERF_MASK_INSN_RF 0x0008 /* supervisor return i.e. RFDE, RFE, RFI, RFWO, RFWU */
|
||||
#define XTPERF_MASK_INSN_BRANCH_TAKEN 0x0010 /* Conditional branch taken, or loopgtz/loopnez skips loop */
|
||||
#define XTPERF_MASK_INSN_J 0x0020 /* J */
|
||||
#define XTPERF_MASK_INSN_CALL 0x0040 /* CALLn */
|
||||
#define XTPERF_MASK_INSN_BRANCH_NOT_TAKEN 0x0080 /* Conditional branch fall through (aka. not-taken branch) */
|
||||
#define XTPERF_MASK_INSN_LOOP_TAKEN 0x0100 /* Loop instr falls into loop (aka. taken loop) */
|
||||
#define XTPERF_MASK_INSN_LOOP_BEG 0x0400 /* Loopback taken to LBEG */
|
||||
#define XTPERF_MASK_INSN_LOOP_END 0x0800 /* Loopback falls through to LEND */
|
||||
#define XTPERF_MASK_INSN_NON_BRANCH 0x8000 /* Non-branch instruction (aka. non-CTI) */
|
||||
|
||||
/*
|
||||
* XTPERF_CNT_D_STALL selector mask
|
||||
*/
|
||||
|
||||
#define XTPERF_MASK_D_STALL_ALL 0x01FE
|
||||
|
||||
#define XTPERF_MASK_D_STALL_STORE_BUF_FULL 0x0002 /* Store buffer full stall */
|
||||
#define XTPERF_MASK_D_STALL_STORE_BUF_CONFLICT 0x0004 /* Store buffer conflict stall */
|
||||
#define XTPERF_MASK_D_STALL_CACHE_MISS 0x0008 /* DCache-miss stall */
|
||||
#define XTPERF_MASK_D_STALL_BUSY 0x0010 /* Data RAM/ROM/XLMI busy stall */
|
||||
#define XTPERF_MASK_D_STALL_IN_PIF 0x0020 /* Data inbound-PIF request stall (incl s32c1i) */
|
||||
#define XTPERF_MASK_D_STALL_MHT_LOOKUP 0x0040 /* MHT lookup stall */
|
||||
#define XTPERF_MASK_D_STALL_UNCACHED_LOAD 0x0080 /* Uncached load stall (included in MHT lookup stall) */
|
||||
#define XTPERF_MASK_D_STALL_BANK_CONFLICT 0x0100 /* Bank-conflict stall */
|
||||
|
||||
/*
|
||||
* XTPERF_CNT_I_STALL selector mask
|
||||
*/
|
||||
|
||||
#define XTPERF_MASK_I_STALL_ALL 0x01FF
|
||||
|
||||
#define XTPERF_MASK_I_STALL_CACHE_MISS 0x0001 /* ICache-miss stall */
|
||||
#define XTPERF_MASK_I_STALL_BUSY 0x0002 /* Instruction RAM/ROM busy stall */
|
||||
#define XTPERF_MASK_I_STALL_IN_PIF 0x0004 /* Instruction RAM inbound-PIF request stall */
|
||||
#define XTPERF_MASK_I_STALL_TIE_PORT 0x0008 /* TIE port stall */
|
||||
#define XTPERF_MASK_I_STALL_EXTERNAL_SIGNAL 0x0010 /* External RunStall signal status */
|
||||
#define XTPERF_MASK_I_STALL_UNCACHED_FETCH 0x0020 /* Uncached fetch stall */
|
||||
#define XTPERF_MASK_I_STALL_FAST_L32R 0x0040 /* FastL32R stall */
|
||||
#define XTPERF_MASK_I_STALL_ITERATIVE_MUL 0x0080 /* Iterative multiply stall */
|
||||
#define XTPERF_MASK_I_STALL_ITERATIVE_DIV 0x0100 /* Iterative divide stall */
|
||||
|
||||
/*
|
||||
* XTPERF_CNT_EXR selector mask
|
||||
*/
|
||||
|
||||
#define XTPERF_MASK_EXR_ALL 0x01FF
|
||||
|
||||
#define XTPERF_MASK_EXR_REPLAYS 0x0001 /* Other Pipeline Replay (i.e. excludes $ miss etc.) */
|
||||
#define XTPERF_MASK_EXR_LEVEL1_INT 0x0002 /* Level-1 interrupt */
|
||||
#define XTPERF_MASK_EXR_LEVELH_INT 0x0004 /* Greater-than-level-1 interrupt */
|
||||
#define XTPERF_MASK_EXR_DEBUG 0x0008 /* Debug exception */
|
||||
#define XTPERF_MASK_EXR_NMI 0x0010 /* NMI */
|
||||
#define XTPERF_MASK_EXR_WINDOW 0x0020 /* Window exception */
|
||||
#define XTPERF_MASK_EXR_ALLOCA 0x0040 /* Alloca exception */
|
||||
#define XTPERF_MASK_EXR_OTHER 0x0080 /* Other exceptions */
|
||||
#define XTPERF_MASK_EXR_MEM_ERR 0x0100 /* HW-corrected memory error */
|
||||
|
||||
/*
|
||||
* XTPERF_CNT_BUBBLES selector mask
|
||||
*/
|
||||
|
||||
#define XTPERF_MASK_BUBBLES_ALL 0x01FD
|
||||
|
||||
#define XTPERF_MASK_BUBBLES_PSO 0x0001 /* Processor domain PSO bubble */
|
||||
#define XTPERF_MASK_BUBBLES_R_HOLD_D_CACHE_MISS 0x0004 /* R hold caused by DCache miss */
|
||||
#define XTPERF_MASK_BUBBLES_R_HOLD_STORE_RELEASE 0x0008 /* R hold caused by Store release */
|
||||
#define XTPERF_MASK_BUBBLES_R_HOLD_REG_DEP 0x0010 /* R hold caused by register dependency */
|
||||
#define XTPERF_MASK_BUBBLES_R_HOLD_WAIT 0x0020 /* R hold caused by MEMW, EXTW or EXCW */
|
||||
#define XTPERF_MASK_BUBBLES_R_HOLD_HALT 0x0040 /* R hold caused by Halt instruction (TX only) */
|
||||
#define XTPERF_MASK_BUBBLES_CTI 0x0080 /* CTI bubble (e.g. branch delay slot) */
|
||||
#define XTPERF_MASK_BUBBLES_WAITI 0x0100 /* WAITI bubble */
|
||||
|
||||
/*
|
||||
* XTPERF_CNT_I_TLB selector mask
|
||||
*/
|
||||
|
||||
#define XTPERF_MASK_I_TLB_ALL 0x000F
|
||||
|
||||
#define XTPERF_MASK_I_TLB_HITS 0x0001 /* Hit */
|
||||
#define XTPERF_MASK_I_TLB_REPLAYS 0x0002 /* Replay of instruction due to ITLB miss */
|
||||
#define XTPERF_MASK_I_TLB_REFILLS 0x0004 /* HW-assisted TLB Refill completes */
|
||||
#define XTPERF_MASK_I_TLB_MISSES 0x0008 /* ITLB Miss Exception */
|
||||
|
||||
/*
|
||||
* XTPERF_CNT_I_MEM selector mask
|
||||
*/
|
||||
|
||||
#define XTPERF_MASK_I_MEM_ALL 0x000F
|
||||
|
||||
#define XTPERF_MASK_I_MEM_CACHE_HITS 0x0001 /* ICache Hit */
|
||||
#define XTPERF_MASK_I_MEM_CACHE_MISSES 0x0002 /* ICache Miss (includes uncached) */
|
||||
#define XTPERF_MASK_I_MEM_IRAM 0x0004 /* InstRAM or InstROM */
|
||||
#define XTPERF_MASK_I_MEM_BYPASS 0x0008 /* Bypass (i.e. uncached) fetch */
|
||||
|
||||
/*
|
||||
* XTPERF_CNT_D_TLB selector mask
|
||||
*/
|
||||
|
||||
#define XTPERF_MASK_D_TLB_ALL 0x000F
|
||||
|
||||
#define XTPERF_MASK_D_TLB_HITS 0x0001 /* Hit */
|
||||
#define XTPERF_MASK_D_TLB_REPLAYS 0x0002 /* Replay of instruction due to DTLB miss */
|
||||
#define XTPERF_MASK_D_TLB_REFILLS 0x0004 /* HW-assisted TLB Refill completes */
|
||||
#define XTPERF_MASK_D_TLB_MISSES 0x0008 /* DTLB Miss Exception */
|
||||
|
||||
/*
|
||||
* XTPERF_CNT_D_LOAD_U* selector mask
|
||||
*/
|
||||
|
||||
#define XTPERF_MASK_D_LOAD_ALL 0x000F
|
||||
|
||||
#define XTPERF_MASK_D_LOAD_CACHE_HITS 0x0001 /* Cache Hit */
|
||||
#define XTPERF_MASK_D_LOAD_CACHE_MISSES 0x0002 /* Cache Miss */
|
||||
#define XTPERF_MASK_D_LOAD_LOCAL_MEM 0x0004 /* Local memory hit */
|
||||
#define XTPERF_MASK_D_LOAD_BYPASS 0x0008 /* Bypass (i.e. uncached) load */
|
||||
|
||||
/*
|
||||
* XTPERF_CNT_D_STORE_U* selector mask
|
||||
*/
|
||||
|
||||
#define XTPERF_MASK_D_STORE_ALL 0x000F
|
||||
|
||||
#define XTPERF_MASK_D_STORE_CACHE_HITS 0x0001 /* DCache Hit */
|
||||
#define XTPERF_MASK_D_STORE_CACHE_MISSES 0x0002 /* DCache Miss */
|
||||
#define XTPERF_MASK_D_STORE_LOCAL_MEM 0x0004 /* Local memory hit */
|
||||
#define XTPERF_MASK_D_STORE_PIF 0x0008 /* PIF Store */
|
||||
|
||||
/*
|
||||
* XTPERF_CNT_D_ACCESS_U* selector mask
|
||||
*/
|
||||
|
||||
#define XTPERF_MASK_D_ACCESS_ALL 0x000F
|
||||
|
||||
#define XTPERF_MASK_D_ACCESS_CACHE_MISSES 0x0001 /* DCache Miss */
|
||||
#define XTPERF_MASK_D_ACCESS_HITS_SHARED 0x0002 /* Hit Shared */
|
||||
#define XTPERF_MASK_D_ACCESS_HITS_EXCLUSIVE 0x0004 /* Hit Exclusive */
|
||||
#define XTPERF_MASK_D_ACCESS_HITS_MODIFIED 0x0008 /* Hit Modified */
|
||||
|
||||
/*
|
||||
* XTPERF_CNT_MULTIPLE_LS selector mask
|
||||
*/
|
||||
|
||||
#define XTPERF_MASK_MULTIPLE_LS_ALL 0x003F
|
||||
|
||||
#define XTPERF_MASK_MULTIPLE_LS_0S_0L 0x0001 /* 0 stores and 0 loads */
|
||||
#define XTPERF_MASK_MULTIPLE_LS_0S_1L 0x0002 /* 0 stores and 1 loads */
|
||||
#define XTPERF_MASK_MULTIPLE_LS_1S_0L 0x0004 /* 1 stores and 0 loads */
|
||||
#define XTPERF_MASK_MULTIPLE_LS_1S_1L 0x0008 /* 1 stores and 1 loads */
|
||||
#define XTPERF_MASK_MULTIPLE_LS_0S_2L 0x0010 /* 0 stores and 2 loads */
|
||||
#define XTPERF_MASK_MULTIPLE_LS_2S_0L 0x0020 /* 2 stores and 0 loads */
|
||||
|
||||
/*
|
||||
* XTPERF_CNT_OUTBOUND_PIF selector mask
|
||||
*/
|
||||
|
||||
#define XTPERF_MASK_OUTBOUND_PIF_ALL 0x0003
|
||||
|
||||
#define XTPERF_MASK_OUTBOUND_PIF_CASTOUT 0x0001 /* Castout */
|
||||
#define XTPERF_MASK_OUTBOUND_PIF_PREFETCH 0x0002 /* Prefetch */
|
||||
|
||||
/*
|
||||
* XTPERF_CNT_INBOUND_PIF selector mask
|
||||
*/
|
||||
|
||||
#define XTPERF_MASK_INBOUND_PIF_ALL 0x0003
|
||||
|
||||
#define XTPERF_MASK_INBOUND_PIF_I_DMA 0x0001 /* Instruction DMA */
|
||||
#define XTPERF_MASK_INBOUND_PIF_D_DMA 0x0002 /* Data DMA */
|
||||
|
||||
/*
|
||||
* XTPERF_CNT_PREFETCH selector mask
|
||||
*/
|
||||
|
||||
#define XTPERF_MASK_PREFETCH_ALL 0x002F
|
||||
|
||||
#define XTPERF_MASK_PREFETCH_I_HIT 0x0001 /* I prefetch-buffer-lookup hit */
|
||||
#define XTPERF_MASK_PREFETCH_D_HIT 0x0002 /* D prefetch-buffer-lookup hit */
|
||||
#define XTPERF_MASK_PREFETCH_I_MISS 0x0004 /* I prefetch-buffer-lookup miss */
|
||||
#define XTPERF_MASK_PREFETCH_D_MISS 0x0008 /* D prefetch-buffer-lookup miss */
|
||||
#define XTPERF_MASK_PREFETCH_D_L1_FILL 0x0020 /* Fill directly to DCache L1 */
|
||||
|
||||
#endif /* __XT_PERF_CONSTS_H__ */
|
||||
Executable
+183
@@ -0,0 +1,183 @@
|
||||
/*
|
||||
* Customer ID=11656; Build=0x5f626; Copyright (c) 2012 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef __XT_PERFMON_H__
|
||||
#define __XT_PERFMON_H__
|
||||
|
||||
#include <xtensa/config/core.h>
|
||||
#include <xtensa/xt_perf_consts.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef int counter_id_t;
|
||||
|
||||
/* xt_perf_init
|
||||
|
||||
Initialize the performance monitor library. Ordinarily, this
|
||||
function is called automatically via the .init section. If your
|
||||
environment does not support the .init section, you will need to
|
||||
call this function from your code.
|
||||
*/
|
||||
|
||||
extern void xt_perf_init(void);
|
||||
|
||||
/* xt_perf_enable
|
||||
|
||||
Turn on the performance monitor. Ordinarily, counting is off by
|
||||
default. If you turn off performance monitor using xt_perf_disable or
|
||||
by call to a function that disables performance monitor, you can turn
|
||||
it on again via this function.
|
||||
*/
|
||||
|
||||
extern void xt_perf_enable(void);
|
||||
|
||||
/* xt_perf_disable
|
||||
|
||||
Turn off the performance monitor. If you want to suspend counting
|
||||
events for a portion of your code, use this function and then call
|
||||
xt_perf_enable when you want to start again.
|
||||
*/
|
||||
|
||||
extern void xt_perf_disable(void);
|
||||
|
||||
/* xt_perf_clear
|
||||
|
||||
Disable performance monitor and clear all initialized hardware counters.
|
||||
All counter ids are invalid after call to this function and all hardware
|
||||
counters available for initialization.
|
||||
*/
|
||||
|
||||
extern void xt_perf_clear (void);
|
||||
|
||||
/* xt_perf_counters_num
|
||||
|
||||
Returns number of free hardware performance counters. After call to xt_perf_clear
|
||||
all counters are free and available for initialization. With each successful
|
||||
xt_perf_init_counter/xt_perf_init_event call this number is decreasing until
|
||||
no free counters available.
|
||||
*/
|
||||
|
||||
extern int xt_perf_counters_num (void);
|
||||
|
||||
/* xt_perf_init_counter32
|
||||
|
||||
Setup 32 bit performance counter. This function disables performance monitor
|
||||
if it was enabled.
|
||||
|
||||
Returns zero based counter id on success or negative value if failed.
|
||||
This function may fail if there is insufficient number of free hardware
|
||||
counters or function arguments are invalid.
|
||||
|
||||
The counter id returned on success can be used with xt_perf_reset_counter
|
||||
and xt_perf_counter32 functions.
|
||||
|
||||
<selector> - events group, one of XTPERF_CNT constants defined in
|
||||
xt_perf_consts.h;
|
||||
<mask> - events mask for selected group. Mask bit fields for each
|
||||
selector defined with XTPERF_MASK prefix in xt_perf_consts.h;
|
||||
<trace_level> - specifies interrupt levels at which to count events;
|
||||
if trace_level is greater or equal to zero events are
|
||||
counted only at interrupt levels below or equal to
|
||||
trace_level; if trace_level is negative events are
|
||||
counted only at (-trace_level) interrupt level or higher.
|
||||
*/
|
||||
|
||||
|
||||
extern counter_id_t xt_perf_init_counter32 ( unsigned int selector,
|
||||
unsigned int mask,
|
||||
int trace_level);
|
||||
|
||||
/* xt_perf_init_counter64
|
||||
|
||||
Setup 64 bit performance counter. Library emulates 64 bit counters by handling
|
||||
profiling interrupt and recording overflows of 32 bit hardware counters.
|
||||
This function disables performance monitor if it was enabled.
|
||||
|
||||
Returns zero based counter id on success or negative value if failed.
|
||||
This function may fail if there is insufficient number of free hardware
|
||||
counters or function arguments are invalid.
|
||||
|
||||
The counter id returned on success can be used with xt_perf_reset_counter
|
||||
and xt_perf_counter64 functions.
|
||||
|
||||
<selector> - events group, one of XTPERF_CNT constants defined in
|
||||
xt_perf_consts.h;
|
||||
<mask> - events mask for selected group. Mask bit fields for each
|
||||
selector defined with XTPERF_MASK prefix in xt_perf_consts.h;
|
||||
<trace_level> - specifies interrupt levels at which to count events;
|
||||
if trace_level is greater or equal to zero events are
|
||||
counted only at interrupt levels below or equal to
|
||||
trace_level; if trace_level is negative events are
|
||||
counted only at (-trace_level) interrupt level or higher.
|
||||
*/
|
||||
|
||||
extern counter_id_t xt_perf_init_counter64 ( unsigned int selector,
|
||||
unsigned int mask,
|
||||
int trace_level);
|
||||
|
||||
/* xt_perf_reset_counter
|
||||
|
||||
Reset counter value to 0.
|
||||
Returns zero on success or non zero if failed.
|
||||
*/
|
||||
|
||||
extern int xt_perf_reset_counter (counter_id_t counter_id);
|
||||
|
||||
/* xt_perf_counter32
|
||||
|
||||
Read 32 bit counter value.
|
||||
|
||||
Returns zero if counter id is not valid.
|
||||
*/
|
||||
|
||||
extern unsigned int xt_perf_counter32 (counter_id_t counter_id);
|
||||
|
||||
/* xt_perf_counter64
|
||||
|
||||
Read 64 bit counter value.
|
||||
|
||||
Counter must be initialized using xt_perf_init_counter64 function.
|
||||
|
||||
Returns zero if counter id is not valid.
|
||||
*/
|
||||
|
||||
extern unsigned long long xt_perf_counter64 (counter_id_t counter_id);
|
||||
|
||||
/* xt_perf_overflow32
|
||||
|
||||
Read overflow flag of 32 bit counter. This flag is dropped when
|
||||
counter initialized or reset. Once counter overflows and wraps
|
||||
around the flag is set and stays set until counter reset.
|
||||
|
||||
Returns negative value if counter id is invalid, zero if counter
|
||||
not overflowed, positive if in overflowed state.
|
||||
*/
|
||||
|
||||
extern int xt_perf_overflow32 (counter_id_t counter_id);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __XT_PERFMON_H__ */
|
||||
+233
@@ -0,0 +1,233 @@
|
||||
/*
|
||||
* Customer ID=11656; Build=0x5f626; Copyright (c) 2005-2012 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
#ifndef __XT_PROFILER_H__
|
||||
#define __XT_PROFILER_H__
|
||||
|
||||
#include <xtensa/config/core.h>
|
||||
|
||||
#if XCHAL_NUM_PERF_COUNTERS
|
||||
/* Performance monitor counters constants */
|
||||
#include <xtensa/xt_perf_consts.h>
|
||||
|
||||
#endif /* XCHAL_NUM_PERF_COUNTERS */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* This file defines an interface that allows a program being profiled
|
||||
to control when and how it is profiled, whether it is running under
|
||||
the instruction set simulator or under the hardware profiler.
|
||||
|
||||
Both ISS and HWP implement this interface, although in different
|
||||
ways. Both also do the right thing if you don't call any of these
|
||||
functions.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
xt_profile_init
|
||||
|
||||
ISS: a no op.
|
||||
|
||||
HWP: Initialize the profiler. Ordinarily, this function is called
|
||||
automatically via the .init section. If your environment does not
|
||||
support the .init section, you will need to call this function
|
||||
by hand.
|
||||
*/
|
||||
extern void xt_profile_init(void);
|
||||
|
||||
/*
|
||||
xt_profile_add_memory
|
||||
|
||||
ISS: a no op.
|
||||
|
||||
HWP:
|
||||
Makes "buf_size" bytes at "buf" available to the hardware profiler.
|
||||
This buffer should be initialized to zeros prior to this call.
|
||||
|
||||
The hardware profiler has already estimated the amount of memory it needs,
|
||||
but under certain circumstances may still run out of memory. If so, you can
|
||||
provide more memory with this routine.
|
||||
|
||||
*/
|
||||
extern void xt_profile_add_memory(void * buf, unsigned int buf_size);
|
||||
|
||||
|
||||
/* xt_profile_enable
|
||||
|
||||
Turn on the profiler. Ordinarily, profiling is on by default.
|
||||
If you turn off profiling using xt_profile_disable, You can turn
|
||||
it on again via this function.
|
||||
*/
|
||||
extern void xt_profile_enable(void);
|
||||
|
||||
/* xt_profile_disable
|
||||
|
||||
Turn off the profiler. If you don't want to profile a portion of your code,
|
||||
use this function and then xt_profile_enable when you want to start again.
|
||||
*/
|
||||
extern void xt_profile_disable(void);
|
||||
|
||||
/* xt_profile_save_and_reset
|
||||
|
||||
Save and reset the profiler's data.
|
||||
If there were errors, either during profiling or while attempting to
|
||||
write the data, no data will be written and this function will
|
||||
return non-zero.
|
||||
|
||||
*/
|
||||
extern int xt_profile_save_and_reset(void);
|
||||
|
||||
/* xt_profile_get_frequency
|
||||
|
||||
ISS: always returns 1.
|
||||
|
||||
HWP:
|
||||
Returns the number of cycles between samples for timer based profiler.
|
||||
In performance counters based profiler always returns 1.
|
||||
*/
|
||||
extern unsigned int xt_profile_get_frequency(void);
|
||||
|
||||
/* xt_profile_set_frequency
|
||||
|
||||
ISS: a no op.
|
||||
|
||||
HWP:
|
||||
Set the number of cycles between samples for timer based profiler.
|
||||
Ignored in performance counters based profiler.
|
||||
|
||||
sample frequency is the number of cycles to wait between samples. It should
|
||||
be a multiple of 1024.
|
||||
|
||||
If you set the sample frequency to a different value than was passed in xt_profile_init,
|
||||
then the labels in the output will reflect the later frequency, even though some samples may
|
||||
have been taken at the earlier frequency. Typically this does not make a significant difference
|
||||
in the results if this function is called early enough.
|
||||
*/
|
||||
extern void xt_profile_set_frequency(unsigned int sample_frequency);
|
||||
|
||||
/* xt_profile_num_errors
|
||||
|
||||
ISS: always returns 0
|
||||
|
||||
HWP:
|
||||
Returns the number of errors that occured while taking samples. Typically these
|
||||
are out of memory errors and you need to pass a bigger buffer to
|
||||
xt_profile_add_memory
|
||||
*/
|
||||
extern int xt_profile_num_errors(void);
|
||||
|
||||
|
||||
#if XCHAL_NUM_PERF_COUNTERS
|
||||
|
||||
|
||||
/* xt_profile_randomize
|
||||
|
||||
ISS: not available
|
||||
|
||||
HWP: Available in performance monitor based profiler.
|
||||
|
||||
Turns on or off sampling period randomization mode. Period randomization
|
||||
helps to avoid aliasing problems when code being profiled is highly periodic.
|
||||
Profiler maintains same average sampling period but individual sampling
|
||||
steps may vary.
|
||||
Period randomization is turned off by default.
|
||||
|
||||
<value> - non zero turns randomization on,
|
||||
zero turns randomization off.
|
||||
*/
|
||||
|
||||
extern void xt_profile_randomization(int value);
|
||||
|
||||
/* xt_profile_config_clear
|
||||
|
||||
ISS: not available
|
||||
|
||||
HWP: Available in performance monitor based profiler.
|
||||
|
||||
Stops profiling if it was enabled and clears performance counters
|
||||
parameters. Accumulated profile data stays in memory and will be
|
||||
saved when xt_profile_save_and_reset is called or at program exit.
|
||||
Number of configured performance counters is zero after this
|
||||
function call.
|
||||
*/
|
||||
|
||||
extern void xt_profile_config_clear(void);
|
||||
|
||||
|
||||
/* xt_profile_config_num
|
||||
|
||||
ISS: not available
|
||||
|
||||
HWP: Available in performance monitor based profiler.
|
||||
|
||||
Returns number of free performance counters.
|
||||
*/
|
||||
|
||||
extern int xt_profile_config_num(void);
|
||||
|
||||
|
||||
/* xt_profile_config_counter error codes
|
||||
*/
|
||||
|
||||
#define XTPROF_ERR_OUT_OF_MEM -1
|
||||
#define XTPROF_ERR_INVALID_ARGS -2
|
||||
#define XTPROF_ERR_NOT_ENOUGH_COUNTERS -3
|
||||
#define XTPROF_ERR_DEFUNCT -4
|
||||
|
||||
/* xt_profile_config_counter
|
||||
|
||||
ISS: not available
|
||||
|
||||
HWP: Available in performance monitor based profiler.
|
||||
|
||||
Allocating and initializing one or more performance counter for sampling.
|
||||
Even though event may require multiple performance counters allocated the
|
||||
profile data for event is merged and dumped into single gmon file.
|
||||
This function disables profiling if it was enabled.
|
||||
|
||||
Returns 0 on success, non zero if failed:
|
||||
XTPROF_ERR_OUT_OF_MEM - memory allocation failed;
|
||||
XTPROF_ERR_INVALID_ARGS - invalid function parameters;
|
||||
XTPROF_ERR_NOT_ENOUGH_COUNTERS - not enough free performance counters available;
|
||||
XTPROF_ERR_DEFUNCT - profiling is disabled because of previous errors
|
||||
(xt_profile_num_errors() is non zero)
|
||||
|
||||
<selector> - events group, one of XTPERF_CNT constants defined in xt_perf_consts.h
|
||||
<mask> - events mask for selected group. Mask bit fields for each
|
||||
selector defined with XTPERF_MASK prefix in xt_perf_consts.h
|
||||
<trace_level> - specifies interrupt levels at which to take samples;
|
||||
if trace_level is greater or equal to zero samples are
|
||||
taken only at interrupt levels below or equal to
|
||||
trace_level; if trace_level is negative samples are taken
|
||||
only at (-trace_level) interrupt level or higher.
|
||||
<period> - sampling period; 1 - record every event, 2 - record every
|
||||
other event and so on;
|
||||
Please note - there is overhead associated with events recording,
|
||||
high frequency events may produce incorrect profile when period
|
||||
is too small.
|
||||
*/
|
||||
|
||||
extern int xt_profile_config_counter ( unsigned int selector,
|
||||
unsigned int mask,
|
||||
int trace_level,
|
||||
unsigned int period);
|
||||
|
||||
|
||||
|
||||
#endif /* XCHAL_NUM_PERF_COUNTERS */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __XT_PROFILER_H__ */
|
||||
Executable
+86
@@ -0,0 +1,86 @@
|
||||
/*
|
||||
* Customer ID=11656; Build=0x5f626; Copyright (c) 2009-2013 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of
|
||||
* Tensilica Inc. They may be adapted and modified by bona fide
|
||||
* purchasers for internal use, but neither the original nor any
|
||||
* adapted or modified version may be disclosed or distributed to
|
||||
* third parties in any manner, medium, or form, in whole or in part,
|
||||
* without the prior written consent of Tensilica Inc.
|
||||
*
|
||||
* This software and its derivatives are to be executed solely on
|
||||
* products incorporating a Tensilica processor.
|
||||
*/
|
||||
|
||||
// Utility routines for returning pass/fail status in HW simulations
|
||||
|
||||
#ifndef XT_REF_TESTBENCH_H
|
||||
#define XT_REF_TESTBENCH_H 1
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// Exit routines for HW simulation
|
||||
extern int diag_pass();
|
||||
extern int diag_fail();
|
||||
|
||||
// Set exit status for HW simulation
|
||||
int set_diag_status(int stat);
|
||||
|
||||
// Setup for user power toggling
|
||||
extern int setup_power_toggle();
|
||||
|
||||
// Return exit status location
|
||||
extern unsigned int* testbench_exit_location();
|
||||
// Return power toggle location
|
||||
extern unsigned int* testbench_power_toggle_location();
|
||||
|
||||
|
||||
// Change exit status location
|
||||
// You must also change the plusarg "+DVMagicExit" sent to the HW simulator
|
||||
// or change the argument "--exit_location" sent to the ISS
|
||||
extern unsigned int* set_testbench_exit_location(unsigned int*);
|
||||
// Change power toggle location
|
||||
// You must also change the plusarg "+DVPowerLoc" sent to the HW simulator
|
||||
extern unsigned int* set_testbench_power_toggle_location(unsigned int*);
|
||||
|
||||
// Exit routines with status message
|
||||
//
|
||||
static inline
|
||||
int pass(const char *msg)
|
||||
{
|
||||
return diag_pass();
|
||||
}
|
||||
|
||||
static inline
|
||||
int fail(const char *msg)
|
||||
{
|
||||
return diag_fail();
|
||||
}
|
||||
|
||||
#define POWER_TOGGLE_ON 1
|
||||
#define POWER_TOGGLE_OFF 0
|
||||
|
||||
// Routine to turn on and off power toggle
|
||||
// Does a magic write that Monitors.v intercepts and appropriately turns
|
||||
// SAIF dumping on and offf
|
||||
//
|
||||
extern volatile unsigned int *_reftb_power_toggle;
|
||||
|
||||
__attribute__ ((always_inline))
|
||||
static inline
|
||||
int set_power_toggle(int val)
|
||||
{
|
||||
#ifdef __XTENSA__
|
||||
*_reftb_power_toggle = val;
|
||||
#endif
|
||||
return val;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // XT_REF_TESTBENCH_H
|
||||
|
||||
Executable
+313
@@ -0,0 +1,313 @@
|
||||
/* Copyright (c) 2007-2013 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
/ These coded instructions, statements, and computer programs are the
|
||||
/ copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
/ They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
/ third parties in any manner, medium, or form, in whole or in part, without
|
||||
/ the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* xtav110.h - Xtensa Avnet LX110 (XT-AV110) board specific definitions */
|
||||
|
||||
#ifndef _INC_XTAV110_H_
|
||||
#define _INC_XTAV110_H_
|
||||
|
||||
#include <xtensa/config/core.h>
|
||||
#include <xtensa/config/system.h>
|
||||
|
||||
#define XTBOARD_NAME "XT-AV110"
|
||||
|
||||
|
||||
/*
|
||||
* Default assignment of XTAV110 devices to external interrupts.
|
||||
*/
|
||||
|
||||
/* Ethernet interrupt: */
|
||||
#ifdef XCHAL_EXTINT1_NUM
|
||||
#define ETHERNET_INTNUM XCHAL_EXTINT1_NUM
|
||||
#define ETHERNET_INTLEVEL XCHAL_EXTINT1_LEVEL
|
||||
#define ETHERNET_INTMASK XCHAL_EXTINT1_MASK
|
||||
#else
|
||||
#define ETHERNET_INTMASK 0
|
||||
#endif
|
||||
|
||||
/* UART interrupt: */
|
||||
#ifdef XCHAL_EXTINT0_NUM
|
||||
#define UART16550_INTNUM XCHAL_EXTINT0_NUM
|
||||
#define UART16550_INTLEVEL XCHAL_EXTINT0_LEVEL
|
||||
#define UART16550_INTMASK XCHAL_EXTINT0_MASK
|
||||
#else
|
||||
#define UART16550_INTMASK 0
|
||||
#endif
|
||||
|
||||
/* Audio output interrupt (I2S transmitter FIFO): */
|
||||
#ifdef XCHAL_EXTINT2_NUM
|
||||
#define AUDIO_I2S_OUT_INTNUM XCHAL_EXTINT2_NUM
|
||||
#define AUDIO_I2S_OUT_INTLEVEL XCHAL_EXTINT2_LEVEL
|
||||
#define AUDIO_I2S_OUT_INTMASK XCHAL_EXTINT2_MASK
|
||||
#else
|
||||
#define AUDIO_I2S_OUT_INTMASK 0
|
||||
#endif
|
||||
|
||||
/* Audio input interrupt (I2S receiver FIFO): */
|
||||
#ifdef XCHAL_EXTINT3_NUM
|
||||
#define AUDIO_I2S_IN_INTNUM XCHAL_EXTINT3_NUM
|
||||
#define AUDIO_I2S_IN_INTLEVEL XCHAL_EXTINT3_LEVEL
|
||||
#define AUDIO_I2S_IN_INTMASK XCHAL_EXTINT3_MASK
|
||||
#else
|
||||
#define AUDIO_I2S_IN_INTMASK 0
|
||||
#endif
|
||||
|
||||
/* I2C interrupt */
|
||||
#ifdef XCHAL_EXTINT4_NUM
|
||||
#define I2C_INTNUM XCHAL_EXTINT4_NUM
|
||||
#define I2C_INTLEVEL XCHAL_EXTINT4_LEVEL
|
||||
#define I2C_INTMASK XCHAL_EXTINT4_MASK
|
||||
#else
|
||||
#define I2C_INTMASK 0
|
||||
#endif
|
||||
|
||||
/* USB interrupt */
|
||||
#ifdef XCHAL_EXTINT5_NUM
|
||||
#define USB_INTNUM XCHAL_EXTINT5_NUM
|
||||
#define USB_INTLEVEL XCHAL_EXTINT5_LEVEL
|
||||
#define USB_INTMASK XCHAL_EXTINT5_MASK
|
||||
#else
|
||||
#define USB_INTMASK 0
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Device addresses.
|
||||
*
|
||||
* Note: for endianness-independence, use 32-bit loads and stores for all
|
||||
* register accesses to Ethernet, UART and LED devices. Undefined bits
|
||||
* may need to be masked out if needed when reading if the actual register
|
||||
* size is smaller than 32 bits.
|
||||
*
|
||||
* Note: XTAV110 bus byte lanes are defined in terms of msbyte and lsbyte
|
||||
* relative to the processor. So 32-bit registers are accessed consistently
|
||||
* from both big and little endian processors. However, this means byte
|
||||
* sequences are not consistent between big and little endian processors.
|
||||
* This is fine for RAM, and for ROM if ROM is created for a specific
|
||||
* processor (and thus has correct byte sequences). However this may be
|
||||
* unexpected for Flash, which might contain a file-system that one wants
|
||||
* to use for multiple processor configurations (eg. the Flash might contain
|
||||
* the Ethernet card's address, endianness-independent application data, etc).
|
||||
* That is, byte sequences written in Flash by a core of a given endianness
|
||||
* will be byte-swapped when seen by a core of the other endianness.
|
||||
* Someone implementing an endianness-independent Flash file system will
|
||||
* likely handle this byte-swapping issue in the Flash driver software.
|
||||
*/
|
||||
|
||||
#define XTBOARD_FLASH_MAXSIZE 0x1000000 /* 16 MB */
|
||||
|
||||
#ifdef XSHAL_IOBLOCK_BYPASS_PADDR
|
||||
|
||||
/* Flash Memory: */
|
||||
# define XTBOARD_FLASH_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x08000000)
|
||||
|
||||
/* FPGA registers: */
|
||||
# define XTBOARD_FPGAREGS_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D020000)
|
||||
|
||||
/* Ethernet controller/transceiver SONIC SN83934: */
|
||||
# define ETHERNET_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D030000)
|
||||
|
||||
|
||||
/* UART National-Semi PC16550D: */
|
||||
# define UART16550_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D050000)
|
||||
|
||||
/* I2S transmitter */
|
||||
# define AUDIO_I2S_OUT_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D080000)
|
||||
|
||||
/* I2S receiver */
|
||||
# define AUDIO_I2S_IN_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D088000)
|
||||
|
||||
/* I2C master */
|
||||
# define I2C_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D090000)
|
||||
|
||||
/* SPI controller */
|
||||
# define SPI_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D0A0000)
|
||||
|
||||
/* Display controller Sunplus SPLC780D, 4bit mode,
|
||||
* LCD Display MYTech MOC-16216B-B: */
|
||||
# define SPLC780D_4BIT_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D0C0000)
|
||||
|
||||
/* USB Controller */
|
||||
# define USB_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D0D0000)
|
||||
|
||||
/* Ethernet buffer: */
|
||||
# define ETHERNET_BUFFER_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D800000)
|
||||
|
||||
#endif /* XSHAL_IOBLOCK_BYPASS_PADDR */
|
||||
|
||||
/* These devices might be accessed cached: */
|
||||
#ifdef XSHAL_IOBLOCK_CACHED_PADDR
|
||||
# define XTBOARD_FLASH_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x08000000)
|
||||
# define ETHERNET_BUFFER_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0D800000)
|
||||
#endif /* XSHAL_IOBLOCK_CACHED_PADDR */
|
||||
|
||||
|
||||
/*** Same thing over again, this time with virtual addresses: ***/
|
||||
|
||||
#ifdef XSHAL_IOBLOCK_BYPASS_VADDR
|
||||
|
||||
/* Flash Memory: */
|
||||
# define XTBOARD_FLASH_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x08000000)
|
||||
|
||||
/* FPGA registers: */
|
||||
# define XTBOARD_FPGAREGS_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D020000)
|
||||
|
||||
/* Ethernet controller/transceiver SONIC SN83934: */
|
||||
# define ETHERNET_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D030000)
|
||||
|
||||
|
||||
/* UART National-Semi PC16550D: */
|
||||
# define UART16550_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D050000)
|
||||
|
||||
/* I2S transmitter */
|
||||
# define AUDIO_I2S_OUT_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D080000)
|
||||
|
||||
/* I2S receiver */
|
||||
# define AUDIO_I2S_IN_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D088000)
|
||||
|
||||
/* I2C master */
|
||||
# define I2C_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D090000)
|
||||
|
||||
/* SPI controller */
|
||||
# define SPI_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D0A0000)
|
||||
|
||||
/* Display controller Sunplus SPLC780D, 4bit mode,
|
||||
* LCD Display MYTech MOC-16216B-B: */
|
||||
# define SPLC780D_4BIT_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D0C0000)
|
||||
|
||||
/* USB Controller */
|
||||
# define USB_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D0D0000)
|
||||
|
||||
/* Ethernet buffer: */
|
||||
# define ETHERNET_BUFFER_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D800000)
|
||||
|
||||
#endif /* XSHAL_IOBLOCK_BYPASS_VADDR */
|
||||
|
||||
/* These devices might be accessed cached: */
|
||||
#ifdef XSHAL_IOBLOCK_CACHED_VADDR
|
||||
# define XTBOARD_FLASH_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x08000000)
|
||||
# define ETHERNET_BUFFER_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D800000)
|
||||
#endif /* XSHAL_IOBLOCK_CACHED_VADDR */
|
||||
|
||||
|
||||
/* System ROM: */
|
||||
#define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE
|
||||
#ifdef XSHAL_ROM_VADDR
|
||||
#define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR
|
||||
#endif
|
||||
#ifdef XSHAL_ROM_PADDR
|
||||
#define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR
|
||||
#endif
|
||||
|
||||
/* System RAM: */
|
||||
#define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE
|
||||
#ifdef XSHAL_RAM_VADDR
|
||||
#define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR
|
||||
#endif
|
||||
#ifdef XSHAL_RAM_PADDR
|
||||
#define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR
|
||||
#endif
|
||||
#define XTBOARD_RAM_BYPASS_VADDR XSHAL_RAM_BYPASS_VADDR
|
||||
#define XTBOARD_RAM_BYPASS_PADDR XSHAL_RAM_BYPASS_PADDR
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Things that depend on device addresses.
|
||||
*/
|
||||
|
||||
|
||||
#define XTBOARD_CACHEATTR_WRITEBACK XSHAL_XT2000_CACHEATTR_WRITEBACK
|
||||
#define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_XT2000_CACHEATTR_WRITEALLOC
|
||||
#define XTBOARD_CACHEATTR_WRITETHRU XSHAL_XT2000_CACHEATTR_WRITETHRU
|
||||
#define XTBOARD_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS
|
||||
#define XTBOARD_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT
|
||||
|
||||
#define XTBOARD_BUSINT_PIPE_REGIONS XSHAL_XT2000_PIPE_REGIONS
|
||||
#define XTBOARD_BUSINT_SDRAM_REGIONS XSHAL_XT2000_SDRAM_REGIONS
|
||||
|
||||
|
||||
/*
|
||||
* FPGA registers.
|
||||
* All these registers are normally accessed using 32-bit loads/stores.
|
||||
*/
|
||||
|
||||
/* Register offsets: */
|
||||
#define XTBOARD_DATECD_OFS 0x00 /* date code (read-only) */
|
||||
#define XTBOARD_CLKFRQ_OFS 0x04 /* clock frequency Hz (read-only) */
|
||||
#define XTBOARD_SYSLED_OFS 0x08 /* LEDs */
|
||||
#define XTBOARD_DIPSW_OFS 0x0C /* DIP switch bits (read-only) */
|
||||
#define XTBOARD_SWRST_OFS 0x10 /* software reset */
|
||||
|
||||
/* Physical register addresses: */
|
||||
#ifdef XTBOARD_FPGAREGS_PADDR
|
||||
#define XTBOARD_DATECD_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DATECD_OFS)
|
||||
#define XTBOARD_CLKFRQ_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_CLKFRQ_OFS)
|
||||
#define XTBOARD_SYSLED_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_SYSLED_OFS)
|
||||
#define XTBOARD_DIPSW_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DIPSW_OFS)
|
||||
#define XTBOARD_SWRST_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_SWRST_OFS)
|
||||
#endif
|
||||
|
||||
/* Virtual register addresses: */
|
||||
#ifdef XTBOARD_FPGAREGS_VADDR
|
||||
#define XTBOARD_DATECD_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DATECD_OFS)
|
||||
#define XTBOARD_CLKFRQ_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_CLKFRQ_OFS)
|
||||
#define XTBOARD_SYSLED_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_SYSLED_OFS)
|
||||
#define XTBOARD_DIPSW_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DIPSW_OFS)
|
||||
#define XTBOARD_SWRST_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_SWRST_OFS)
|
||||
/* Register access (for C code): */
|
||||
#define XTBOARD_DATECD_REG (*(volatile unsigned*) XTBOARD_DATECD_VADDR)
|
||||
#define XTBOARD_CLKFRQ_REG (*(volatile unsigned*) XTBOARD_CLKFRQ_VADDR)
|
||||
#define XTBOARD_SYSLED_REG (*(volatile unsigned*) XTBOARD_SYSLED_VADDR)
|
||||
#define XTBOARD_DIPSW_REG (*(volatile unsigned*) XTBOARD_DIPSW_VADDR)
|
||||
#define XTBOARD_SWRST_REG (*(volatile unsigned*) XTBOARD_SWRST_VADDR)
|
||||
#endif
|
||||
|
||||
/* DATECD (date code; when core was built) bit fields: */
|
||||
/* BCD-coded month (01..12): */
|
||||
#define XTBOARD_DATECD_MONTH_SHIFT 24
|
||||
#define XTBOARD_DATECD_MONTH_BITS 8
|
||||
#define XTBOARD_DATECD_MONTH_MASK 0xFF000000
|
||||
/* BCD-coded day (01..31): */
|
||||
#define XTBOARD_DATECD_DAY_SHIFT 16
|
||||
#define XTBOARD_DATECD_DAY_BITS 8
|
||||
#define XTBOARD_DATECD_DAY_MASK 0x00FF0000
|
||||
/* BCD-coded year (2001..9999): */
|
||||
#define XTBOARD_DATECD_YEAR_SHIFT 0
|
||||
#define XTBOARD_DATECD_YEAR_BITS 16
|
||||
#define XTBOARD_DATECD_YEAR_MASK 0x0000FFFF
|
||||
|
||||
/* SYSLED (system LED) bit fields: */
|
||||
|
||||
/* LED control bits (off=0, on=1): */
|
||||
#define XTBOARD_SYSLED_USER_SHIFT 0
|
||||
#define XTBOARD_SYSLED_USER_BITS 2
|
||||
#define XTBOARD_SYSLED_USER_MASK 0x00000003
|
||||
|
||||
/* DIP Switch SW5 (left=sw1=lsb=bit0, right=sw4=msb=bit3; off=0, on=1): */
|
||||
/* DIP switch bit fields (bit2/sw3 is reserved and presently unused): */
|
||||
#define XTBOARD_DIPSW_USER_SHIFT 0 /* labeled 1-2 (1=lsb) */
|
||||
#define XTBOARD_DIPSW_USER_BITS 2
|
||||
#define XTBOARD_DIPSW_USER_MASK 0x00000003
|
||||
#define XTBOARD_DIPSW_BOOT_SHIFT 3 /* labeled 8 (msb) */
|
||||
#define XTBOARD_DIPSW_BOOT_BITS 1
|
||||
#define XTBOARD_DIPSW_BOOT_MASK 0x00000008
|
||||
/* Boot settings: bit3/sw4, off=0, on=1 (this switch controls hardware): */
|
||||
#define XTBOARD_DIPSW_BOOT_RAM (0<<XTBOARD_DIPSW_BOOT_SHIFT) /* off */
|
||||
#define XTBOARD_DIPSW_BOOT_FLASH (1<<XTBOARD_DIPSW_BOOT_SHIFT) /* on */
|
||||
|
||||
/* SWRST (software reset; allows s/w to generate power-on equivalent reset): */
|
||||
/* Software reset bits: */
|
||||
#define XTBOARD_SWRST_SWR_SHIFT 0
|
||||
#define XTBOARD_SWRST_SWR_BITS 16
|
||||
#define XTBOARD_SWRST_SWR_MASK 0x0000FFFF
|
||||
/* Software reset value -- writing this value resets the board: */
|
||||
#define XTBOARD_SWRST_RESETVALUE 0x0000DEAD
|
||||
|
||||
|
||||
#endif /*_INC_XTAV110_H_*/
|
||||
|
||||
+13
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* board.h - Include board-specific definitions
|
||||
*
|
||||
* Copyright (c) 2010 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
#include <xtensa/xtav110.h>
|
||||
|
||||
Executable
+280
@@ -0,0 +1,280 @@
|
||||
/* Copyright (c) 2007-2013 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
/ These coded instructions, statements, and computer programs are the
|
||||
/ copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
/ They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
/ third parties in any manner, medium, or form, in whole or in part, without
|
||||
/ the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* xtav200.h - Xtensa Avnet LX200 (XT-AV200) board specific definitions */
|
||||
|
||||
#ifndef _INC_XTAV200_H_
|
||||
#define _INC_XTAV200_H_
|
||||
|
||||
#include <xtensa/config/core.h>
|
||||
#include <xtensa/config/system.h>
|
||||
|
||||
#define XTBOARD_NAME "XT-AV200"
|
||||
|
||||
|
||||
/*
|
||||
* Default assignment of XTAV200 devices to external interrupts.
|
||||
*/
|
||||
|
||||
/* Ethernet interrupt: */
|
||||
#ifdef XCHAL_EXTINT1_NUM
|
||||
#define ETHERNET_INTNUM XCHAL_EXTINT1_NUM
|
||||
#define ETHERNET_INTLEVEL XCHAL_EXTINT1_LEVEL
|
||||
#define ETHERNET_INTMASK XCHAL_EXTINT1_MASK
|
||||
#else
|
||||
#define ETHERNET_INTMASK 0
|
||||
#endif
|
||||
|
||||
/* UART interrupt: */
|
||||
#ifdef XCHAL_EXTINT0_NUM
|
||||
#define UART16550_INTNUM XCHAL_EXTINT0_NUM
|
||||
#define UART16550_INTLEVEL XCHAL_EXTINT0_LEVEL
|
||||
#define UART16550_INTMASK XCHAL_EXTINT0_MASK
|
||||
#else
|
||||
#define UART16550_INTMASK 0
|
||||
#endif
|
||||
|
||||
/* Audio output interrupt (I2S FIFO underrun): */
|
||||
#ifdef XCHAL_EXTINT2_NUM
|
||||
#define AUDIO_INTNUM XCHAL_EXTINT2_NUM
|
||||
#define AUDIO_INTLEVEL XCHAL_EXTINT2_LEVEL
|
||||
#define AUDIO_INTMASK XCHAL_EXTINT2_MASK
|
||||
#else
|
||||
#define AUDIO_INTMASK 0
|
||||
#endif
|
||||
|
||||
/* Audio output (I2S FIFO level) interrupt: */
|
||||
#ifdef XCHAL_EXTINT3_NUM
|
||||
#define AUDIO_I2SLVL_INTNUM XCHAL_EXTINT3_NUM
|
||||
#define AUDIO_I2SLVL_INTLEVEL XCHAL_EXTINT3_LEVEL
|
||||
#define AUDIO_I2SLVL_INTMASK XCHAL_EXTINT3_MASK
|
||||
#else
|
||||
#define AUDIO_I2SLVL_INTMASK 0
|
||||
#endif
|
||||
|
||||
/* Audio input (ADC FIFO level) interrupt: */
|
||||
#ifdef XCHAL_EXTINT4_NUM
|
||||
#define AUDIO_ADCLVL_INTNUM XCHAL_EXTINT4_NUM
|
||||
#define AUDIO_ADCLVL_INTLEVEL XCHAL_EXTINT4_LEVEL
|
||||
#define AUDIO_ADCLVL_INTMASK XCHAL_EXTINT4_MASK
|
||||
#else
|
||||
#define AUDIO_ADCLVL_INTMASK 0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Device addresses.
|
||||
*
|
||||
* Note: for endianness-independence, use 32-bit loads and stores for all
|
||||
* register accesses to Ethernet, UART and LED devices. Undefined bits
|
||||
* may need to be masked out if needed when reading if the actual register
|
||||
* size is smaller than 32 bits.
|
||||
*
|
||||
* Note: XTAV200 bus byte lanes are defined in terms of msbyte and lsbyte
|
||||
* relative to the processor. So 32-bit registers are accessed consistently
|
||||
* from both big and little endian processors. However, this means byte
|
||||
* sequences are not consistent between big and little endian processors.
|
||||
* This is fine for RAM, and for ROM if ROM is created for a specific
|
||||
* processor (and thus has correct byte sequences). However this may be
|
||||
* unexpected for Flash, which might contain a file-system that one wants
|
||||
* to use for multiple processor configurations (eg. the Flash might contain
|
||||
* the Ethernet card's address, endianness-independent application data, etc).
|
||||
* That is, byte sequences written in Flash by a core of a given endianness
|
||||
* will be byte-swapped when seen by a core of the other endianness.
|
||||
* Someone implementing an endianness-independent Flash file system will
|
||||
* likely handle this byte-swapping issue in the Flash driver software.
|
||||
*/
|
||||
|
||||
#define XTBOARD_FLASH_MAXSIZE 0x1000000 /* 16 MB */
|
||||
|
||||
#ifdef XSHAL_IOBLOCK_BYPASS_PADDR
|
||||
|
||||
/* Flash Memory: */
|
||||
# define XTBOARD_FLASH_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x08000000)
|
||||
|
||||
/* FPGA registers: */
|
||||
# define XTBOARD_FPGAREGS_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D020000)
|
||||
|
||||
/* Ethernet controller/transceiver SONIC SN83934: */
|
||||
# define ETHERNET_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D030000)
|
||||
|
||||
/* UART National-Semi PC16550D: */
|
||||
# define UART16550_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D050000)
|
||||
|
||||
/* TI 320AIC23/28-TSSOP Stereo Audio Codec: */
|
||||
# define AUDIO_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D070000)
|
||||
|
||||
/* Boot 128K Sram address: */
|
||||
# define BOOT_SRAM_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D400000)
|
||||
|
||||
/* Ethernet buffer: */
|
||||
# define ETHERNET_BUFFER_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D800000)
|
||||
|
||||
#endif /* XSHAL_IOBLOCK_BYPASS_PADDR */
|
||||
|
||||
/* These devices might be accessed cached: */
|
||||
#ifdef XSHAL_IOBLOCK_CACHED_PADDR
|
||||
# define XTBOARD_FLASH_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x08000000)
|
||||
# define ETHERNET_BUFFER_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0D800000)
|
||||
# define BOOT_SRAM_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0D400000)
|
||||
#endif /* XSHAL_IOBLOCK_CACHED_PADDR */
|
||||
|
||||
|
||||
/*** Same thing over again, this time with virtual addresses: ***/
|
||||
|
||||
#ifdef XSHAL_IOBLOCK_BYPASS_VADDR
|
||||
|
||||
/* Flash Memory: */
|
||||
# define XTBOARD_FLASH_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x08000000)
|
||||
|
||||
/* FPGA registers: */
|
||||
# define XTBOARD_FPGAREGS_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D020000)
|
||||
|
||||
/* Ethernet controller/transceiver SONIC SN83934: */
|
||||
# define ETHERNET_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D030000)
|
||||
|
||||
/* UART National-Semi PC16550D: */
|
||||
# define UART16550_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D050000)
|
||||
|
||||
/* TI 320AIC23/28-TSSOP Stereo Audio Codec: */
|
||||
# define AUDIO_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D070000)
|
||||
|
||||
/* 128K Sram address: */
|
||||
# define BOOT_SRAM_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D400000)
|
||||
|
||||
/* Ethernet buffer: */
|
||||
# define ETHERNET_BUFFER_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D800000)
|
||||
|
||||
#endif /* XSHAL_IOBLOCK_BYPASS_VADDR */
|
||||
|
||||
/* These devices might be accessed cached: */
|
||||
#ifdef XSHAL_IOBLOCK_CACHED_VADDR
|
||||
# define XTBOARD_FLASH_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x08000000)
|
||||
# define AUDIO_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D070000)
|
||||
# define ETHERNET_BUFFER_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D800000)
|
||||
# define BOOT_SRAM_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D400000)
|
||||
#endif /* XSHAL_IOBLOCK_CACHED_VADDR */
|
||||
|
||||
|
||||
/* System ROM: */
|
||||
#define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE
|
||||
#ifdef XSHAL_ROM_VADDR
|
||||
#define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR
|
||||
#endif
|
||||
#ifdef XSHAL_ROM_PADDR
|
||||
#define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR
|
||||
#endif
|
||||
|
||||
/* System RAM: */
|
||||
#define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE
|
||||
#ifdef XSHAL_RAM_VADDR
|
||||
#define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR
|
||||
#endif
|
||||
#ifdef XSHAL_RAM_PADDR
|
||||
#define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR
|
||||
#endif
|
||||
#define XTBOARD_RAM_BYPASS_VADDR XSHAL_RAM_BYPASS_VADDR
|
||||
#define XTBOARD_RAM_BYPASS_PADDR XSHAL_RAM_BYPASS_PADDR
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Things that depend on device addresses.
|
||||
*/
|
||||
|
||||
|
||||
#define XTBOARD_CACHEATTR_WRITEBACK XSHAL_XT2000_CACHEATTR_WRITEBACK
|
||||
#define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_XT2000_CACHEATTR_WRITEALLOC
|
||||
#define XTBOARD_CACHEATTR_WRITETHRU XSHAL_XT2000_CACHEATTR_WRITETHRU
|
||||
#define XTBOARD_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS
|
||||
#define XTBOARD_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT
|
||||
|
||||
#define XTBOARD_BUSINT_PIPE_REGIONS XSHAL_XT2000_PIPE_REGIONS
|
||||
#define XTBOARD_BUSINT_SDRAM_REGIONS XSHAL_XT2000_SDRAM_REGIONS
|
||||
|
||||
|
||||
/*
|
||||
* FPGA registers.
|
||||
* All these registers are normally accessed using 32-bit loads/stores.
|
||||
*/
|
||||
|
||||
/* Register offsets: */
|
||||
#define XTBOARD_DATECD_OFS 0x00 /* date code (read-only) */
|
||||
#define XTBOARD_CLKFRQ_OFS 0x04 /* clock frequency Hz (read-only) */
|
||||
#define XTBOARD_SYSLED_OFS 0x08 /* LEDs */
|
||||
#define XTBOARD_DIPSW_OFS 0x0C /* DIP switch bits (read-only) */
|
||||
#define XTBOARD_SWRST_OFS 0x10 /* software reset */
|
||||
|
||||
/* Physical register addresses: */
|
||||
#ifdef XTBOARD_FPGAREGS_PADDR
|
||||
#define XTBOARD_DATECD_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DATECD_OFS)
|
||||
#define XTBOARD_CLKFRQ_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_CLKFRQ_OFS)
|
||||
#define XTBOARD_SYSLED_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_SYSLED_OFS)
|
||||
#define XTBOARD_DIPSW_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DIPSW_OFS)
|
||||
#define XTBOARD_SWRST_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_SWRST_OFS)
|
||||
#endif
|
||||
|
||||
/* Virtual register addresses: */
|
||||
#ifdef XTBOARD_FPGAREGS_VADDR
|
||||
#define XTBOARD_DATECD_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DATECD_OFS)
|
||||
#define XTBOARD_CLKFRQ_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_CLKFRQ_OFS)
|
||||
#define XTBOARD_SYSLED_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_SYSLED_OFS)
|
||||
#define XTBOARD_DIPSW_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DIPSW_OFS)
|
||||
#define XTBOARD_SWRST_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_SWRST_OFS)
|
||||
/* Register access (for C code): */
|
||||
#define XTBOARD_DATECD_REG (*(volatile unsigned*) XTBOARD_DATECD_VADDR)
|
||||
#define XTBOARD_CLKFRQ_REG (*(volatile unsigned*) XTBOARD_CLKFRQ_VADDR)
|
||||
#define XTBOARD_SYSLED_REG (*(volatile unsigned*) XTBOARD_SYSLED_VADDR)
|
||||
#define XTBOARD_DIPSW_REG (*(volatile unsigned*) XTBOARD_DIPSW_VADDR)
|
||||
#define XTBOARD_SWRST_REG (*(volatile unsigned*) XTBOARD_SWRST_VADDR)
|
||||
#endif
|
||||
|
||||
/* DATECD (date code; when core was built) bit fields: */
|
||||
/* BCD-coded month (01..12): */
|
||||
#define XTBOARD_DATECD_MONTH_SHIFT 24
|
||||
#define XTBOARD_DATECD_MONTH_BITS 8
|
||||
#define XTBOARD_DATECD_MONTH_MASK 0xFF000000
|
||||
/* BCD-coded day (01..31): */
|
||||
#define XTBOARD_DATECD_DAY_SHIFT 16
|
||||
#define XTBOARD_DATECD_DAY_BITS 8
|
||||
#define XTBOARD_DATECD_DAY_MASK 0x00FF0000
|
||||
/* BCD-coded year (2001..9999): */
|
||||
#define XTBOARD_DATECD_YEAR_SHIFT 0
|
||||
#define XTBOARD_DATECD_YEAR_BITS 16
|
||||
#define XTBOARD_DATECD_YEAR_MASK 0x0000FFFF
|
||||
|
||||
/* SYSLED (system LED) bit fields: */
|
||||
|
||||
/* LED control bits (off=0, on=1): */
|
||||
#define XTBOARD_SYSLED_USER_SHIFT 0
|
||||
#define XTBOARD_SYSLED_USER_BITS 4
|
||||
#define XTBOARD_SYSLED_USER_MASK 0x0000000F
|
||||
|
||||
/* DIP Switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): */
|
||||
/* DIP switch bit fields (bit6/sw7 is reserved and presently unused): */
|
||||
#define XTBOARD_DIPSW_USER_SHIFT 0 /* labeled 1-6 (1=lsb) */
|
||||
#define XTBOARD_DIPSW_USER_BITS 6
|
||||
#define XTBOARD_DIPSW_USER_MASK 0x0000003F
|
||||
#define XTBOARD_DIPSW_BOOT_SHIFT 7 /* labeled 8 (msb) */
|
||||
#define XTBOARD_DIPSW_BOOT_BITS 1
|
||||
#define XTBOARD_DIPSW_BOOT_MASK 0x00000080
|
||||
/* Boot settings: bit7/sw8, off=0, on=1 (this switch controls hardware): */
|
||||
#define XTBOARD_DIPSW_BOOT_RAM (0<<XTBOARD_DIPSW_BOOT_SHIFT) /* off */
|
||||
#define XTBOARD_DIPSW_BOOT_FLASH (1<<XTBOARD_DIPSW_BOOT_SHIFT) /* on */
|
||||
|
||||
/* SWRST (software reset; allows s/w to generate power-on equivalent reset): */
|
||||
/* Software reset bits: */
|
||||
#define XTBOARD_SWRST_SWR_SHIFT 0
|
||||
#define XTBOARD_SWRST_SWR_BITS 16
|
||||
#define XTBOARD_SWRST_SWR_MASK 0x0000FFFF
|
||||
/* Software reset value -- writing this value resets the board: */
|
||||
#define XTBOARD_SWRST_RESETVALUE 0x0000DEAD
|
||||
|
||||
|
||||
#endif /*_INC_XTAV200_H_*/
|
||||
|
||||
+13
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* board.h - Include board-specific definitions
|
||||
*
|
||||
* Copyright (c) 2008 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
#include <xtensa/xtav200.h>
|
||||
|
||||
Executable
+241
@@ -0,0 +1,241 @@
|
||||
/* Copyright (c) 2002-2013 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
/ These coded instructions, statements, and computer programs are the
|
||||
/ copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
/ They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
/ third parties in any manner, medium, or form, in whole or in part, without
|
||||
/ the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* xtav60.h - Xtensa Avnet LX60 (XT-AV60) board specific definitions */
|
||||
|
||||
#ifndef _INC_XTAV60_H_
|
||||
#define _INC_XTAV60_H_
|
||||
|
||||
#include <xtensa/config/core.h>
|
||||
#include <xtensa/config/system.h>
|
||||
|
||||
#define XTBOARD_NAME "XT-AV60"
|
||||
|
||||
|
||||
/*
|
||||
* Default assignment of XTAV60 devices to external interrupts.
|
||||
*/
|
||||
|
||||
/* Ethernet interrupt: */
|
||||
#ifdef XCHAL_EXTINT1_NUM
|
||||
#define ETHERNET_INTNUM XCHAL_EXTINT1_NUM
|
||||
#define ETHERNET_INTLEVEL XCHAL_EXTINT1_LEVEL
|
||||
#define ETHERNET_INTMASK XCHAL_EXTINT1_MASK
|
||||
#else
|
||||
#define ETHERNET_INTMASK 0
|
||||
#endif
|
||||
|
||||
/* UART interrupt: */
|
||||
#ifdef XCHAL_EXTINT0_NUM
|
||||
#define UART16550_INTNUM XCHAL_EXTINT0_NUM
|
||||
#define UART16550_INTLEVEL XCHAL_EXTINT0_LEVEL
|
||||
#define UART16550_INTMASK XCHAL_EXTINT0_MASK
|
||||
#else
|
||||
#define UART16550_INTMASK 0
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Device addresses.
|
||||
*
|
||||
* Note: for endianness-independence, use 32-bit loads and stores for all
|
||||
* register accesses to Ethernet, UART and LED devices. Undefined bits
|
||||
* may need to be masked out if needed when reading if the actual register
|
||||
* size is smaller than 32 bits.
|
||||
*
|
||||
* Note: XTAV60 bus byte lanes are defined in terms of msbyte and lsbyte
|
||||
* relative to the processor. So 32-bit registers are accessed consistently
|
||||
* from both big and little endian processors. However, this means byte
|
||||
* sequences are not consistent between big and little endian processors.
|
||||
* This is fine for RAM, and for ROM if ROM is created for a specific
|
||||
* processor (and thus has correct byte sequences). However this may be
|
||||
* unexpected for Flash, which might contain a file-system that one wants
|
||||
* to use for multiple processor configurations (eg. the Flash might contain
|
||||
* the Ethernet card's address, endianness-independent application data, etc).
|
||||
* That is, byte sequences written in Flash by a core of a given endianness
|
||||
* will be byte-swapped when seen by a core of the other endianness.
|
||||
* Someone implementing an endianness-independent Flash file system will
|
||||
* likely handle this byte-swapping issue in the Flash driver software.
|
||||
*/
|
||||
|
||||
#define XTBOARD_FLASH_MAXSIZE 0x400000 /* 4 MB */
|
||||
|
||||
#ifdef XSHAL_IOBLOCK_BYPASS_PADDR
|
||||
|
||||
/* Flash Memory: */
|
||||
# define XTBOARD_FLASH_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x08000000)
|
||||
|
||||
/* FPGA registers: */
|
||||
# define XTBOARD_FPGAREGS_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D020000)
|
||||
|
||||
/* Ethernet controller/transceiver SONIC SN83934: */
|
||||
# define ETHERNET_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D030000)
|
||||
# define ETHERNET_CONTROLLER_PADDR ETHERNET_PADDR /* legacy macro */
|
||||
|
||||
/* Display controller Sunplus SPLC780D, LCD Display MYTech MOC-16216B-B: */
|
||||
# define SPLC780D_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D040000)
|
||||
|
||||
/* UART National-Semi PC16550D: */
|
||||
# define UART16550_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D050000)
|
||||
|
||||
/* Boot 128K Sram address: */
|
||||
# define BOOT_SRAM_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D400000)
|
||||
|
||||
/* Ethernet buffer: */
|
||||
# define ETHERNET_BUFFER_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D800000)
|
||||
|
||||
#endif /* XSHAL_IOBLOCK_BYPASS_PADDR */
|
||||
|
||||
/* These devices might be accessed cached: */
|
||||
#ifdef XSHAL_IOBLOCK_CACHED_PADDR
|
||||
# define XTBOARD_FLASH_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x08000000)
|
||||
# define ETHERNET_BUFFER_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0D800000)
|
||||
# define BOOT_SRAM_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0D400000)
|
||||
#endif /* XSHAL_IOBLOCK_CACHED_PADDR */
|
||||
|
||||
|
||||
/*** Same thing over again, this time with virtual addresses: ***/
|
||||
|
||||
#ifdef XSHAL_IOBLOCK_BYPASS_VADDR
|
||||
|
||||
/* Flash Memory: */
|
||||
# define XTBOARD_FLASH_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x08000000)
|
||||
|
||||
/* FPGA registers: */
|
||||
# define XTBOARD_FPGAREGS_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D020000)
|
||||
|
||||
/* Ethernet controller/transceiver SONIC SN83934: */
|
||||
# define ETHERNET_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D030000)
|
||||
|
||||
/* Display controller Sunplus SPLC780D, LCD Display MYTech MOC-16216B-B: */
|
||||
# define SPLC780D_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D040000)
|
||||
|
||||
/* UART National-Semi PC16550D: */
|
||||
# define UART16550_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D050000)
|
||||
|
||||
/* 128K Sram address: */
|
||||
# define BOOT_SRAM_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D400000)
|
||||
|
||||
/* Ethernet buffer: */
|
||||
# define ETHERNET_BUFFER_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D800000)
|
||||
|
||||
#endif /* XSHAL_IOBLOCK_BYPASS_VADDR */
|
||||
|
||||
/* These devices might be accessed cached: */
|
||||
#ifdef XSHAL_IOBLOCK_CACHED_VADDR
|
||||
# define XTBOARD_FLASH_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x08000000)
|
||||
# define ETHERNET_BUFFER_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D800000)
|
||||
# define BOOT_SRAM_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D400000)
|
||||
#endif /* XSHAL_IOBLOCK_CACHED_VADDR */
|
||||
|
||||
|
||||
/* System ROM: */
|
||||
#define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE
|
||||
#ifdef XSHAL_ROM_VADDR
|
||||
#define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR
|
||||
#endif
|
||||
#ifdef XSHAL_ROM_PADDR
|
||||
#define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR
|
||||
#endif
|
||||
|
||||
/* System RAM: */
|
||||
#define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE
|
||||
#ifdef XSHAL_RAM_VADDR
|
||||
#define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR
|
||||
#endif
|
||||
#ifdef XSHAL_RAM_PADDR
|
||||
#define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR
|
||||
#endif
|
||||
#define XTBOARD_RAM_BYPASS_VADDR XSHAL_RAM_BYPASS_VADDR
|
||||
#define XTBOARD_RAM_BYPASS_PADDR XSHAL_RAM_BYPASS_PADDR
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Things that depend on device addresses.
|
||||
*/
|
||||
|
||||
|
||||
#define XTBOARD_CACHEATTR_WRITEBACK XSHAL_XT2000_CACHEATTR_WRITEBACK
|
||||
#define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_XT2000_CACHEATTR_WRITEALLOC
|
||||
#define XTBOARD_CACHEATTR_WRITETHRU XSHAL_XT2000_CACHEATTR_WRITETHRU
|
||||
#define XTBOARD_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS
|
||||
#define XTBOARD_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT
|
||||
|
||||
#define XTBOARD_BUSINT_PIPE_REGIONS XSHAL_XT2000_PIPE_REGIONS
|
||||
#define XTBOARD_BUSINT_SDRAM_REGIONS XSHAL_XT2000_SDRAM_REGIONS
|
||||
|
||||
|
||||
/*
|
||||
* FPGA registers.
|
||||
* All these registers are normally accessed using 32-bit loads/stores.
|
||||
*/
|
||||
|
||||
/* Register offsets: */
|
||||
#define XTBOARD_DATECD_OFS 0x00 /* date code (read-only) */
|
||||
#define XTBOARD_CLKFRQ_OFS 0x04 /* clock frequency Hz (read-only) */
|
||||
#define XTBOARD_DIPSW_OFS 0x0C /* DIP switch bits (read-only) */
|
||||
#define XTBOARD_SWRST_OFS 0x10 /* software reset */
|
||||
|
||||
/* Physical register addresses: */
|
||||
#ifdef XTBOARD_FPGAREGS_PADDR
|
||||
#define XTBOARD_DATECD_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DATECD_OFS)
|
||||
#define XTBOARD_CLKFRQ_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_CLKFRQ_OFS)
|
||||
#define XTBOARD_DIPSW_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DIPSW_OFS)
|
||||
#define XTBOARD_SWRST_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_SWRST_OFS)
|
||||
#endif
|
||||
|
||||
/* Virtual register addresses: */
|
||||
#ifdef XTBOARD_FPGAREGS_VADDR
|
||||
#define XTBOARD_DATECD_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DATECD_OFS)
|
||||
#define XTBOARD_CLKFRQ_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_CLKFRQ_OFS)
|
||||
#define XTBOARD_DIPSW_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DIPSW_OFS)
|
||||
#define XTBOARD_SWRST_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_SWRST_OFS)
|
||||
/* Register access (for C code): */
|
||||
#define XTBOARD_DATECD_REG (*(volatile unsigned*) XTBOARD_DATECD_VADDR)
|
||||
#define XTBOARD_CLKFRQ_REG (*(volatile unsigned*) XTBOARD_CLKFRQ_VADDR)
|
||||
#define XTBOARD_DIPSW_REG (*(volatile unsigned*) XTBOARD_DIPSW_VADDR)
|
||||
#define XTBOARD_SWRST_REG (*(volatile unsigned*) XTBOARD_SWRST_VADDR)
|
||||
#endif
|
||||
|
||||
/* DATECD (date code; when core was built) bit fields: */
|
||||
/* BCD-coded month (01..12): */
|
||||
#define XTBOARD_DATECD_MONTH_SHIFT 24
|
||||
#define XTBOARD_DATECD_MONTH_BITS 8
|
||||
#define XTBOARD_DATECD_MONTH_MASK 0xFF000000
|
||||
/* BCD-coded day (01..31): */
|
||||
#define XTBOARD_DATECD_DAY_SHIFT 16
|
||||
#define XTBOARD_DATECD_DAY_BITS 8
|
||||
#define XTBOARD_DATECD_DAY_MASK 0x00FF0000
|
||||
/* BCD-coded year (2001..9999): */
|
||||
#define XTBOARD_DATECD_YEAR_SHIFT 0
|
||||
#define XTBOARD_DATECD_YEAR_BITS 16
|
||||
#define XTBOARD_DATECD_YEAR_MASK 0x0000FFFF
|
||||
|
||||
/* DIP Switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): */
|
||||
/* DIP switch bit fields (bit6/sw7 is reserved and presently unused): */
|
||||
#define XTBOARD_DIPSW_USER_SHIFT 0 /* labeled 1-6 (1=lsb) */
|
||||
#define XTBOARD_DIPSW_USER_BITS 6
|
||||
#define XTBOARD_DIPSW_USER_MASK 0x0000003F
|
||||
#define XTBOARD_DIPSW_BOOT_SHIFT 7 /* labeled 8 (msb) */
|
||||
#define XTBOARD_DIPSW_BOOT_BITS 1
|
||||
#define XTBOARD_DIPSW_BOOT_MASK 0x00000080
|
||||
/* Boot settings: bit7/sw8, off=0, on=1 (this switch controls hardware): */
|
||||
#define XTBOARD_DIPSW_BOOT_RAM (0<<XTBOARD_DIPSW_BOOT_SHIFT) /* off */
|
||||
#define XTBOARD_DIPSW_BOOT_FLASH (1<<XTBOARD_DIPSW_BOOT_SHIFT) /* on */
|
||||
|
||||
/* SWRST (software reset; allows s/w to generate power-on equivalent reset): */
|
||||
/* Software reset bits: */
|
||||
#define XTBOARD_SWRST_SWR_SHIFT 0
|
||||
#define XTBOARD_SWRST_SWR_BITS 16
|
||||
#define XTBOARD_SWRST_SWR_MASK 0x0000FFFF
|
||||
/* Software reset value -- writing this value resets the board: */
|
||||
#define XTBOARD_SWRST_RESETVALUE 0x0000DEAD
|
||||
|
||||
|
||||
#endif /*_INC_XTAV60_H_*/
|
||||
|
||||
+13
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* board.h - Include board-specific definitions
|
||||
*
|
||||
* Copyright (c) 2008 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
#include <xtensa/xtav60.h>
|
||||
|
||||
@@ -0,0 +1,60 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Copyright (c) 2006-2007 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
These coded instructions, statements, and computer programs are the
|
||||
copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
third parties in any manner, medium, or form, in whole or in part, without
|
||||
the prior written consent of Tensilica Inc.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
lcd-splc780d-board.h Board-specific LCD info on Avnet AV60 (XT-AV60) board.
|
||||
|
||||
Interface between board-independent driver and board-specific header.
|
||||
|
||||
This is used by a board-independent SPLC780D LCD controller driver to obtain
|
||||
board-specific information about LCD displays on the board, such as the
|
||||
controller register base address and spacing (a function of how the address
|
||||
lines are connected on the board) and length of the visible window of the
|
||||
display (a function of the LCD panel the controller drives). The driver does
|
||||
not refer directly to the board-specific header, which therefore is not
|
||||
constrained to use macro names consistent with other boards.
|
||||
|
||||
!! Must not contain any board-specific macro names (only controller specific) !!
|
||||
|
||||
Included at compile-time via an include path specific to the board.
|
||||
|
||||
The XT-AV60 board contains a single MYTech MOC-16216B-B display driven by
|
||||
a Sunplus SPLC870D controller.
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _LCD_SPLC780D_BOARD_H
|
||||
#define _LCD_SPLC780D_BOARD_H
|
||||
|
||||
#include <xtensa/xtav60.h> /* Board info */
|
||||
|
||||
|
||||
/* Base address of the controller's registers. */
|
||||
#ifdef SPLC780D_VADDR
|
||||
#define SPLC780D_REGBASE SPLC780D_VADDR
|
||||
#endif
|
||||
|
||||
/*
|
||||
The controller's registers are connected at word addresses on the XT-AV60.
|
||||
Each byte-wide register appears as the least-significant-byte (LSB) of the
|
||||
word regardless of the endianness of the processor (so if using word accesses
|
||||
then endianness doesn't matter).
|
||||
*/
|
||||
#define SPLC780D_REGSPACING 4
|
||||
typedef unsigned splc780d_reg_t;
|
||||
|
||||
/* Include generic information shared by all boards that use this device. */
|
||||
#include <xtensa/lcd-splc780d.h>
|
||||
|
||||
|
||||
/* Display limits of the LCD panel. */
|
||||
#define DISPLAY_VISIBLE_LEN 16 /* length (chars) of visible window */
|
||||
|
||||
#endif /* _LCD_SPLC780D_BOARD_H */
|
||||
|
||||
Executable
+269
@@ -0,0 +1,269 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Copyright (c) 2006-2009 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
xtbsp.h Xtensa Board Support Package API
|
||||
|
||||
This API defines a minimal set of board-support functions that every supported
|
||||
Xtensa board is expected to provide in the board-support-package (BSP) library
|
||||
associated with the board-specific LSP. Only basic board functions are provided
|
||||
in this board-independent API. API functions not applicable to a board must be
|
||||
stubbed in its BSP library. More complex operations must use a board-specific
|
||||
interface. Functions are grouped by type of peripheral device.
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _XTBSP_H_
|
||||
#define _XTBSP_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
BOARD INITIALIZATION.
|
||||
The board with all its devices is initialized by xtbsp_board_init().
|
||||
Individual devices represented by this API can be reinitialized at any
|
||||
time by calling their inidividual device init functions (grouped with
|
||||
other device functions). This might be useful to (say) change the baud
|
||||
rate of the UART.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
Initialize the board. Must call before any other API function.
|
||||
Iniitializes BSP, board in general, and all devices on the board.
|
||||
*/
|
||||
extern void xtbsp_board_init(void);
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
BOARD CHARACTERISTICS and CONVENIENCE FUNCTIONS.
|
||||
Board support functions not associated with a particular peripheral device.
|
||||
*/
|
||||
|
||||
/*
|
||||
Return a short string representing the type of board.
|
||||
If the board has a display, the string must fit on a single line.
|
||||
*/
|
||||
extern const char * xtbsp_board_name(void);
|
||||
|
||||
/*
|
||||
Hardware reset the entire board (if possible). Does not return if successful.
|
||||
If this function returns, it is stubbed out or not possible with this board.
|
||||
*/
|
||||
extern void xtbsp_board_reset(void);
|
||||
|
||||
/*
|
||||
Return the clock frequency in Hertz. May be constant or computed.
|
||||
*/
|
||||
extern unsigned xtbsp_clock_freq_hz(void);
|
||||
|
||||
/*
|
||||
Return the clock period in picoseconds. May be constant or computed.
|
||||
*/
|
||||
extern unsigned xtbsp_clock_period_ps(void);
|
||||
|
||||
/*
|
||||
Spin (at least) a number of cycles per the processor's CCOUNT register.
|
||||
Unlike a s/w delay loop, the duration is not affected by compiler
|
||||
optimization or interrupts completed within the delay period.
|
||||
If the processor doesn't have CCOUNT, a s/w delay loop is used to obtain
|
||||
a rough approximation of the cycle count.
|
||||
*/
|
||||
extern void xtbsp_delay_cycles(unsigned cycles);
|
||||
|
||||
/*
|
||||
Spin at least a number of nanoseconds (approximate and err in the high side).
|
||||
BSP implementation should do this efficiently, avoiding integer overflow or
|
||||
excessive loss of precision, run-time division or floating point.
|
||||
Function implementation (vs. macro) allows BSP to optimize for the clock
|
||||
frequency by pre-computing (or using constant) scale factors.
|
||||
*/
|
||||
extern void xtbsp_delay_ns(unsigned ns);
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
C LIBRARY SUPPORT.
|
||||
These functions are called by the C library libgloss interface.
|
||||
Their names are predetermined apart from this BSP API.
|
||||
*/
|
||||
|
||||
/*
|
||||
Initialize the board. Called by C library initialization code.
|
||||
Usually simply calls xtbsp_board_init().
|
||||
*/
|
||||
extern void board_init(void);
|
||||
|
||||
/*
|
||||
(Wait for and) Input a single byte from the default character I/O
|
||||
device. Return -1 if there is no input device.
|
||||
This device is usually a UART and this function calls xtbsp_uart_getchar().
|
||||
On some boards (eg.) it might be a directly connected keyboard.
|
||||
*/
|
||||
extern int inbyte(void);
|
||||
|
||||
/*
|
||||
Output a single char to the default character I/O device (and wait
|
||||
until it's been taken).
|
||||
This device is usually a UART and this function calls xtbsp_uart_putchar().
|
||||
On some boards (eg.) it might be a directly connected bit-mapped screen.
|
||||
*/
|
||||
extern void outbyte(int c);
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
UART (SERIAL I/O).
|
||||
Supports a single UART in a simple polling mode and provides control of
|
||||
receiver and transmitter data interrupts (client must provide handler).
|
||||
Provides a mapping to processor interrupt number which can be used with
|
||||
the HAL to control processor interrupt enable (INTENABLE) etc.
|
||||
*/
|
||||
|
||||
/* Bitmasks to identify UART interrupts. */
|
||||
typedef enum xtbsp_uart_int {
|
||||
xtbsp_uart_int_rx = 1<<0,
|
||||
xtbsp_uart_int_tx = 1<<1,
|
||||
/* mask of all valid interrupt bits */
|
||||
xtbsp_uart_int_all = (1<<2)-1
|
||||
} xtbsp_uart_int;
|
||||
|
||||
/*
|
||||
Return non-zero if the board has a UART.
|
||||
*/
|
||||
extern int xtbsp_uart_exists(void);
|
||||
|
||||
/*
|
||||
Initialize the UART:
|
||||
parity = 0 (none), 1 (odd), or 2 (even).
|
||||
nstop = 1 or 2 (stop bits).
|
||||
ndata = 7 or 8 (data bits).
|
||||
Disables all UART interrupts.
|
||||
Returns non-zero if failed (perhaps due to unsupported parameter values).
|
||||
Must call before any of the following functions.
|
||||
*/
|
||||
extern int xtbsp_uart_init(unsigned baud, unsigned ndata,
|
||||
unsigned parity, unsigned nstop);
|
||||
#define xtbsp_uart_init_default() xtbsp_uart_init(38400, 8, 0, 1)
|
||||
|
||||
/*
|
||||
(Wait for and) Input a single char from the UART.
|
||||
Any pending xtbsp_uart_int_rx interrupt is cleared.
|
||||
*/
|
||||
extern char xtbsp_uart_getchar(void);
|
||||
|
||||
/*
|
||||
(Wait for transmitter ready and) Output a single char to the UART.
|
||||
Any pending xtbsp_uart_int_tx interrupt is cleared.
|
||||
*/
|
||||
extern void xtbsp_uart_putchar(const char c);
|
||||
|
||||
/*
|
||||
Return true (non-zero) if a character has been received and is ready
|
||||
to be input by xtbsp_uart_getchar() without waiting, else return 0.
|
||||
*/
|
||||
extern int xtbsp_uart_get_isready(void);
|
||||
|
||||
/*
|
||||
Return non-zero if a character may be output by xtbsp_uart_putchar()
|
||||
without waiting, else return 0.
|
||||
Any pending xtbsp_uart_int_tx interrupt is cleared.
|
||||
*/
|
||||
extern int xtbsp_uart_put_isready(void);
|
||||
|
||||
/*
|
||||
Return the enable status of all UART interrupts represented by this API,
|
||||
that is those with bits defined in type xtbsp_uart_int (1 bit = enabled).
|
||||
This is the enable status at the device, not the processor's INTENABLE.
|
||||
*/
|
||||
extern xtbsp_uart_int xtbsp_uart_int_enable_status(void);
|
||||
|
||||
/*
|
||||
Enable selected UART interrupts at the device.
|
||||
*/
|
||||
extern void xtbsp_uart_int_enable(const xtbsp_uart_int mask);
|
||||
|
||||
/*
|
||||
Disable selected UART interrupts at the device.
|
||||
*/
|
||||
extern void xtbsp_uart_int_disable(const xtbsp_uart_int mask);
|
||||
|
||||
/*
|
||||
Return the interrupt number (0..31) to which the selected UART interrupt
|
||||
is connected. May be used with the link-time HAL to obtain more information,
|
||||
eg. Xthal_intlevel_mask[xtbsp_uart_int_number(xtbsp_uart_int_rx)]
|
||||
This information can be used to control the processor's INTENABLE, etc.
|
||||
Result is -1 if not connected, undefined if mask has more than 1 bit set.
|
||||
*/
|
||||
extern int xtbsp_uart_int_number(const xtbsp_uart_int mask);
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
DISPLAY.
|
||||
Supports a single display that can render a series of ASCII characters.
|
||||
Functions are provided to perform generic display tasks such as display
|
||||
a string, display character by character, or blank the display.
|
||||
Chars are 7-bit printable ASCII. Strings are C style NUL \0 terminated.
|
||||
These functions busy-wait for any required timing delays so the caller does
|
||||
not have to deal with timing. Some displays require long delays which in
|
||||
some client applications warrant a board and RTOS specific approach to
|
||||
driving the display, however that is beyond the scope of this API.
|
||||
*/
|
||||
|
||||
/*
|
||||
Return non-zero if board has a display.
|
||||
*/
|
||||
extern int xtbsp_display_exists(void);
|
||||
|
||||
/*
|
||||
Initialize the display. Must call before any of the following functions.
|
||||
*/
|
||||
extern void xtbsp_display_init(void);
|
||||
|
||||
/*
|
||||
Display a single char at position pos (0 is leftmost). Other positions are
|
||||
left untouched. Positions beyond the width of the display are ignored.
|
||||
*/
|
||||
extern void xtbsp_display_char(unsigned pos, const char c);
|
||||
|
||||
/*
|
||||
Display a string. Blank-pad to or truncate at the end of the display
|
||||
(overwrites any previous string so don't need to blank display first).
|
||||
*/
|
||||
extern void xtbsp_display_string(const char *s);
|
||||
|
||||
/*
|
||||
Blank (clear) the entire display.
|
||||
*/
|
||||
extern void xtbsp_display_blank(void);
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _XTBSP_H_ */
|
||||
+161
@@ -0,0 +1,161 @@
|
||||
/*
|
||||
* xtensa-libdb-macros.h
|
||||
*/
|
||||
|
||||
/* $Id: //depot/rel/Eaglenest/Xtensa/Software/libdb/xtensa-libdb-macros.h#1 $ */
|
||||
|
||||
/* Copyright (c) 2004-2008 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef __H_LIBDB_MACROS
|
||||
#define __H_LIBDB_MACROS
|
||||
|
||||
/*
|
||||
* This header file provides macros used to construct, identify and use
|
||||
* "target numbers" that are assigned to various types of Xtensa processor
|
||||
* registers and states. These target numbers are used by GDB in the remote
|
||||
* protocol, and are thus used by all GDB debugger agents (targets).
|
||||
* They are also used in ELF debugger information sections (stabs, dwarf, etc).
|
||||
*
|
||||
* These macros are separated from xtensa-libdb.h because they are needed
|
||||
* by certain debugger agents that do not use or have access to libdb,
|
||||
* e.g. the OCD daemon, RedBoot, XMON, etc.
|
||||
*
|
||||
* For the time being, for compatibility with certain 3rd party debugger
|
||||
* software vendors, target numbers are limited to 16 bits. It is
|
||||
* conceivable that this will be extended in the future to 32 bits.
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef uint32
|
||||
#define uint32 unsigned int
|
||||
#endif
|
||||
#ifndef int32
|
||||
#define int32 int
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Macros to form register "target numbers" for various standard registers/states:
|
||||
*/
|
||||
#define XTENSA_DBREGN_INVALID -1 /* not a valid target number */
|
||||
#define XTENSA_DBREGN_A(n) (0x0000+(n)) /* address registers a0..a15 */
|
||||
#define XTENSA_DBREGN_B(n) (0x0010+(n)) /* boolean bits b0..b15 */
|
||||
#define XTENSA_DBREGN_PC 0x0020 /* program counter */
|
||||
/* 0x0021 RESERVED for use by Tensilica */
|
||||
#define XTENSA_DBREGN_BO(n) (0x0022+(n)) /* boolean octuple-bits bo0..bo1 */
|
||||
#define XTENSA_DBREGN_BQ(n) (0x0024+(n)) /* boolean quadruple-bits bq0..bq3 */
|
||||
#define XTENSA_DBREGN_BD(n) (0x0028+(n)) /* boolean double-bits bd0..bd7 */
|
||||
#define XTENSA_DBREGN_F(n) (0x0030+(n)) /* floating point registers f0..f15 */
|
||||
#define XTENSA_DBREGN_VEC(n) (0x0040+(n)) /* Vectra vec regs v0..v15 */
|
||||
#define XTENSA_DBREGN_VSEL(n) (0x0050+(n)) /* Vectra sel s0..s3 (V1) ..s7 (V2) */
|
||||
#define XTENSA_DBREGN_VALIGN(n) (0x0058+(n)) /* Vectra valign regs u0..u3 */
|
||||
#define XTENSA_DBREGN_VCOEFF(n) (0x005C+(n)) /* Vectra I vcoeff regs c0..c1 */
|
||||
/* 0x005E..0x005F RESERVED for use by Tensilica */
|
||||
#define XTENSA_DBREGN_AEP(n) (0x0060+(n)) /* HiFi2 Audio Engine regs aep0..aep7 */
|
||||
#define XTENSA_DBREGN_AEQ(n) (0x0068+(n)) /* HiFi2 Audio Engine regs aeq0..aeq3 */
|
||||
/* 0x006C..0x00FF RESERVED for use by Tensilica */
|
||||
#define XTENSA_DBREGN_AR(n) (0x0100+(n)) /* physical address regs ar0..ar63
|
||||
(note: only with window option) */
|
||||
/* 0x0140..0x01FF RESERVED for use by Tensilica */
|
||||
#define XTENSA_DBREGN_SREG(n) (0x0200+(n)) /* special registers 0..255 (core) */
|
||||
#define XTENSA_DBREGN_BR XTENSA_DBREGN_SREG(0x04) /* all 16 boolean bits, BR */
|
||||
#define XTENSA_DBREGN_MR(n) XTENSA_DBREGN_SREG(0x20+(n)) /* MAC16 registers m0..m3 */
|
||||
#define XTENSA_DBREGN_UREG(n) (0x0300+(n)) /* user registers 0..255 (TIE) */
|
||||
/* 0x0400..0x0FFF RESERVED for use by Tensilica */
|
||||
/* 0x1000..0x1FFF user-defined regfiles */
|
||||
/* 0x2000..0xEFFF other states (and regfiles) */
|
||||
#define XTENSA_DBREGN_DBAGENT(n) (0xF000+(n)) /* non-processor "registers" 0..4095 for
|
||||
3rd-party debugger agent defined use */
|
||||
/* > 0xFFFF (32-bit) RESERVED for use by Tensilica */
|
||||
/*#define XTENSA_DBREGN_CONTEXT(n) (0x02000000+((n)<<20))*/ /* add this macro's value to a target
|
||||
number to identify a specific context 0..31
|
||||
for context-replicated registers */
|
||||
#define XTENSA_DBREGN_MASK 0xFFFF /* mask of valid target_number bits */
|
||||
#define XTENSA_DBREGN_WRITE_SIDE 0x04000000 /* flag to request write half of a register
|
||||
split into distinct read and write entries
|
||||
with the same target number (currently only
|
||||
valid in a couple of libdb API functions;
|
||||
see xtensa-libdb.h for details) */
|
||||
|
||||
/*
|
||||
* Macros to identify specific ranges of target numbers (formed above):
|
||||
* NOTE: any context number (or other upper 12 bits) are considered
|
||||
* modifiers and are thus stripped out for identification purposes.
|
||||
*/
|
||||
#define XTENSA_DBREGN_IS_VALID(tn) (((tn) & ~0xFFFF) == 0) /* just tests it's 16-bit unsigned */
|
||||
#define XTENSA_DBREGN_IS_A(tn) (((tn) & 0xFFF0)==0x0000) /* is a0..a15 */
|
||||
#define XTENSA_DBREGN_IS_B(tn) (((tn) & 0xFFF0)==0x0010) /* is b0..b15 */
|
||||
#define XTENSA_DBREGN_IS_PC(tn) (((tn) & 0xFFFF)==0x0020) /* is program counter */
|
||||
#define XTENSA_DBREGN_IS_BO(tn) (((tn) & 0xFFFE)==0x0022) /* is bo0..bo1 */
|
||||
#define XTENSA_DBREGN_IS_BQ(tn) (((tn) & 0xFFFC)==0x0024) /* is bq0..bq3 */
|
||||
#define XTENSA_DBREGN_IS_BD(tn) (((tn) & 0xFFF8)==0x0028) /* is bd0..bd7 */
|
||||
#define XTENSA_DBREGN_IS_F(tn) (((tn) & 0xFFF0)==0x0030) /* is f0..f15 */
|
||||
#define XTENSA_DBREGN_IS_VEC(tn) (((tn) & 0xFFF0)==0x0040) /* is v0..v15 */
|
||||
#define XTENSA_DBREGN_IS_VSEL(tn) (((tn) & 0xFFF8)==0x0050) /* is s0..s7 (s0..s3 in V1) */
|
||||
#define XTENSA_DBREGN_IS_VALIGN(tn) (((tn) & 0xFFFC)==0x0058) /* is u0..u3 */
|
||||
#define XTENSA_DBREGN_IS_VCOEFF(tn) (((tn) & 0xFFFE)==0x005C) /* is c0..c1 */
|
||||
#define XTENSA_DBREGN_IS_AEP(tn) (((tn) & 0xFFF8)==0x0060) /* is aep0..aep7 */
|
||||
#define XTENSA_DBREGN_IS_AEQ(tn) (((tn) & 0xFFFC)==0x0068) /* is aeq0..aeq3 */
|
||||
#define XTENSA_DBREGN_IS_AR(tn) (((tn) & 0xFFC0)==0x0100) /* is ar0..ar63 */
|
||||
#define XTENSA_DBREGN_IS_SREG(tn) (((tn) & 0xFF00)==0x0200) /* is special register */
|
||||
#define XTENSA_DBREGN_IS_BR(tn) (((tn) & 0xFFFF)==XTENSA_DBREGN_SREG(0x04)) /* is BR */
|
||||
#define XTENSA_DBREGN_IS_MR(tn) (((tn) & 0xFFFC)==XTENSA_DBREGN_SREG(0x20)) /* m0..m3 */
|
||||
#define XTENSA_DBREGN_IS_UREG(tn) (((tn) & 0xFF00)==0x0300) /* is user register */
|
||||
#define XTENSA_DBREGN_IS_DBAGENT(tn) (((tn) & 0xF000)==0xF000) /* is non-processor */
|
||||
/*#define XTENSA_DBREGN_IS_CONTEXT(tn) (((tn) & 0x02000000) != 0)*/ /* specifies context # */
|
||||
|
||||
/*
|
||||
* Macros to extract register index from a register "target number"
|
||||
* when a specific range has been identified using one of the _IS_ macros above.
|
||||
* These macros only return a useful value if the corresponding _IS_ macro returns true.
|
||||
*/
|
||||
#define XTENSA_DBREGN_A_INDEX(tn) ((tn) & 0x0F) /* 0..15 for a0..a15 */
|
||||
#define XTENSA_DBREGN_B_INDEX(tn) ((tn) & 0x0F) /* 0..15 for b0..b15 */
|
||||
#define XTENSA_DBREGN_BO_INDEX(tn) ((tn) & 0x01) /* 0..1 for bo0..bo1 */
|
||||
#define XTENSA_DBREGN_BQ_INDEX(tn) ((tn) & 0x03) /* 0..3 for bq0..bq3 */
|
||||
#define XTENSA_DBREGN_BD_INDEX(tn) ((tn) & 0x07) /* 0..7 for bd0..bd7 */
|
||||
#define XTENSA_DBREGN_F_INDEX(tn) ((tn) & 0x0F) /* 0..15 for f0..f15 */
|
||||
#define XTENSA_DBREGN_VEC_INDEX(tn) ((tn) & 0x0F) /* 0..15 for v0..v15 */
|
||||
#define XTENSA_DBREGN_VSEL_INDEX(tn) ((tn) & 0x07) /* 0..7 for s0..s7 */
|
||||
#define XTENSA_DBREGN_VALIGN_INDEX(tn) ((tn) & 0x03) /* 0..3 for u0..u3 */
|
||||
#define XTENSA_DBREGN_VCOEFF_INDEX(tn) ((tn) & 0x01) /* 0..1 for c0..c1 */
|
||||
#define XTENSA_DBREGN_AEP_INDEX(tn) ((tn) & 0x07) /* 0..7 for aep0..aep7 */
|
||||
#define XTENSA_DBREGN_AEQ_INDEX(tn) ((tn) & 0x03) /* 0..3 for aeq0..aeq3 */
|
||||
#define XTENSA_DBREGN_AR_INDEX(tn) ((tn) & 0x3F) /* 0..63 for ar0..ar63 */
|
||||
#define XTENSA_DBREGN_SREG_INDEX(tn) ((tn) & 0xFF) /* 0..255 for special registers */
|
||||
#define XTENSA_DBREGN_MR_INDEX(tn) ((tn) & 0x03) /* 0..3 for m0..m3 */
|
||||
#define XTENSA_DBREGN_UREG_INDEX(tn) ((tn) & 0xFF) /* 0..255 for user registers */
|
||||
#define XTENSA_DBREGN_DBAGENT_INDEX(tn) ((tn) & 0xFFF) /* 0..4095 for non-processor */
|
||||
/*#define XTENSA_DBREGN_CONTEXT_INDEX(tn) (((tn) >> 20) & 0x1F)*/ /* 0..31 context numbers */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __H_LIBDB_MACROS */
|
||||
|
||||
+347
@@ -0,0 +1,347 @@
|
||||
/*
|
||||
xtensa-versions.h -- definitions of Xtensa version and release numbers
|
||||
|
||||
This file defines most Xtensa-related product versions and releases
|
||||
that exist so far.
|
||||
It also provides a bit of information about which ones are current.
|
||||
This file changes every release, as versions/releases get added.
|
||||
|
||||
|
||||
$Id: //depot/rel/Eaglenest/Xtensa/Software/misc/xtensa-versions.h.tpp#2 $
|
||||
|
||||
Copyright (c) 2006-2010 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef XTENSA_VERSIONS_H
|
||||
#define XTENSA_VERSIONS_H
|
||||
|
||||
|
||||
/*
|
||||
* NOTE: A "release" is a collection of product versions
|
||||
* made available at once (together) to customers.
|
||||
* In the past, release and version names all matched in T####.# form,
|
||||
* making the distinction irrelevant.
|
||||
* Starting with the RA-2004.1 release, this is no longer the case.
|
||||
*/
|
||||
|
||||
|
||||
/* Hardware (Xtensa/Diamond processor) versions: */
|
||||
#define XTENSA_HWVERSION_T1020_0 102000 /* versions T1020.0 */
|
||||
#define XTENSA_HWCIDSCHEME_T1020_0 10
|
||||
#define XTENSA_HWCIDVERS_T1020_0 2
|
||||
#define XTENSA_HWVERSION_T1020_1 102001 /* versions T1020.1 */
|
||||
#define XTENSA_HWCIDSCHEME_T1020_1 10
|
||||
#define XTENSA_HWCIDVERS_T1020_1 3
|
||||
#define XTENSA_HWVERSION_T1020_2B 102002 /* versions T1020.2b */
|
||||
#define XTENSA_HWCIDSCHEME_T1020_2B 10
|
||||
#define XTENSA_HWCIDVERS_T1020_2B 5
|
||||
#define XTENSA_HWVERSION_T1020_2 102002 /* versions T1020.2 */
|
||||
#define XTENSA_HWCIDSCHEME_T1020_2 10
|
||||
#define XTENSA_HWCIDVERS_T1020_2 4
|
||||
#define XTENSA_HWVERSION_T1020_3 102003 /* versions T1020.3 */
|
||||
#define XTENSA_HWCIDSCHEME_T1020_3 10
|
||||
#define XTENSA_HWCIDVERS_T1020_3 6
|
||||
#define XTENSA_HWVERSION_T1020_4 102004 /* versions T1020.4 */
|
||||
#define XTENSA_HWCIDSCHEME_T1020_4 10
|
||||
#define XTENSA_HWCIDVERS_T1020_4 7
|
||||
#define XTENSA_HWVERSION_T1030_0 103000 /* versions T1030.0 */
|
||||
#define XTENSA_HWCIDSCHEME_T1030_0 10
|
||||
#define XTENSA_HWCIDVERS_T1030_0 9
|
||||
#define XTENSA_HWVERSION_T1030_1 103001 /* versions T1030.1 */
|
||||
#define XTENSA_HWCIDSCHEME_T1030_1 10
|
||||
#define XTENSA_HWCIDVERS_T1030_1 10
|
||||
#define XTENSA_HWVERSION_T1030_2 103002 /* versions T1030.2 */
|
||||
#define XTENSA_HWCIDSCHEME_T1030_2 10
|
||||
#define XTENSA_HWCIDVERS_T1030_2 11
|
||||
#define XTENSA_HWVERSION_T1030_3 103003 /* versions T1030.3 */
|
||||
#define XTENSA_HWCIDSCHEME_T1030_3 10
|
||||
#define XTENSA_HWCIDVERS_T1030_3 12
|
||||
#define XTENSA_HWVERSION_T1040_0 104000 /* versions T1040.0 */
|
||||
#define XTENSA_HWCIDSCHEME_T1040_0 10
|
||||
#define XTENSA_HWCIDVERS_T1040_0 15
|
||||
#define XTENSA_HWVERSION_T1040_1 104001 /* versions T1040.1 */
|
||||
#define XTENSA_HWCIDSCHEME_T1040_1 01
|
||||
#define XTENSA_HWCIDVERS_T1040_1 32
|
||||
#define XTENSA_HWVERSION_T1040_1P 104001 /* versions T1040.1-prehotfix */
|
||||
#define XTENSA_HWCIDSCHEME_T1040_1P 10
|
||||
#define XTENSA_HWCIDVERS_T1040_1P 16
|
||||
#define XTENSA_HWVERSION_T1040_2 104002 /* versions T1040.2 */
|
||||
#define XTENSA_HWCIDSCHEME_T1040_2 01
|
||||
#define XTENSA_HWCIDVERS_T1040_2 33
|
||||
#define XTENSA_HWVERSION_T1040_3 104003 /* versions T1040.3 */
|
||||
#define XTENSA_HWCIDSCHEME_T1040_3 01
|
||||
#define XTENSA_HWCIDVERS_T1040_3 34
|
||||
#define XTENSA_HWVERSION_T1050_0 105000 /* versions T1050.0 */
|
||||
#define XTENSA_HWCIDSCHEME_T1050_0 1100
|
||||
#define XTENSA_HWCIDVERS_T1050_0 1
|
||||
#define XTENSA_HWVERSION_T1050_1 105001 /* versions T1050.1 */
|
||||
#define XTENSA_HWCIDSCHEME_T1050_1 1100
|
||||
#define XTENSA_HWCIDVERS_T1050_1 2
|
||||
#define XTENSA_HWVERSION_T1050_2 105002 /* versions T1050.2 */
|
||||
#define XTENSA_HWCIDSCHEME_T1050_2 1100
|
||||
#define XTENSA_HWCIDVERS_T1050_2 4
|
||||
#define XTENSA_HWVERSION_T1050_3 105003 /* versions T1050.3 */
|
||||
#define XTENSA_HWCIDSCHEME_T1050_3 1100
|
||||
#define XTENSA_HWCIDVERS_T1050_3 6
|
||||
#define XTENSA_HWVERSION_T1050_4 105004 /* versions T1050.4 */
|
||||
#define XTENSA_HWCIDSCHEME_T1050_4 1100
|
||||
#define XTENSA_HWCIDVERS_T1050_4 7
|
||||
#define XTENSA_HWVERSION_T1050_5 105005 /* versions T1050.5 */
|
||||
#define XTENSA_HWCIDSCHEME_T1050_5 1100
|
||||
#define XTENSA_HWCIDVERS_T1050_5 8
|
||||
#define XTENSA_HWVERSION_RA_2004_1 210000 /* versions LX1.0.0 */
|
||||
#define XTENSA_HWCIDSCHEME_RA_2004_1 1100
|
||||
#define XTENSA_HWCIDVERS_RA_2004_1 3
|
||||
#define XTENSA_HWVERSION_RA_2005_1 210001 /* versions LX1.0.1 */
|
||||
#define XTENSA_HWCIDSCHEME_RA_2005_1 1100
|
||||
#define XTENSA_HWCIDVERS_RA_2005_1 20
|
||||
#define XTENSA_HWVERSION_RA_2005_2 210002 /* versions LX1.0.2 */
|
||||
#define XTENSA_HWCIDSCHEME_RA_2005_2 1100
|
||||
#define XTENSA_HWCIDVERS_RA_2005_2 21
|
||||
#define XTENSA_HWVERSION_RA_2005_3 210003 /* versions LX1.0.3, X6.0.3 */
|
||||
#define XTENSA_HWCIDSCHEME_RA_2005_3 1100
|
||||
#define XTENSA_HWCIDVERS_RA_2005_3 22
|
||||
#define XTENSA_HWVERSION_RA_2006_4 210004 /* versions LX1.0.4, X6.0.4 */
|
||||
#define XTENSA_HWCIDSCHEME_RA_2006_4 1100
|
||||
#define XTENSA_HWCIDVERS_RA_2006_4 23
|
||||
#define XTENSA_HWVERSION_RA_2006_5 210005 /* versions LX1.0.5, X6.0.5 */
|
||||
#define XTENSA_HWCIDSCHEME_RA_2006_5 1100
|
||||
#define XTENSA_HWCIDVERS_RA_2006_5 24
|
||||
#define XTENSA_HWVERSION_RA_2006_6 210006 /* versions LX1.0.6, X6.0.6 */
|
||||
#define XTENSA_HWCIDSCHEME_RA_2006_6 1100
|
||||
#define XTENSA_HWCIDVERS_RA_2006_6 25
|
||||
#define XTENSA_HWVERSION_RA_2007_7 210007 /* versions LX1.0.7, X6.0.7 */
|
||||
#define XTENSA_HWCIDSCHEME_RA_2007_7 1100
|
||||
#define XTENSA_HWCIDVERS_RA_2007_7 26
|
||||
#define XTENSA_HWVERSION_RA_2008_8 210008 /* versions LX1.0.8, X6.0.8 */
|
||||
#define XTENSA_HWCIDSCHEME_RA_2008_8 1100
|
||||
#define XTENSA_HWCIDVERS_RA_2008_8 27
|
||||
#define XTENSA_HWVERSION_RB_2006_0 220000 /* versions LX2.0.0, X7.0.0 */
|
||||
#define XTENSA_HWCIDSCHEME_RB_2006_0 1100
|
||||
#define XTENSA_HWCIDVERS_RB_2006_0 48
|
||||
#define XTENSA_HWVERSION_RB_2007_1 220001 /* versions LX2.0.1, X7.0.1 */
|
||||
#define XTENSA_HWCIDSCHEME_RB_2007_1 1100
|
||||
#define XTENSA_HWCIDVERS_RB_2007_1 49
|
||||
#define XTENSA_HWVERSION_RB_2007_2 221000 /* versions LX2.1.0, X7.1.0 */
|
||||
#define XTENSA_HWCIDSCHEME_RB_2007_2 1100
|
||||
#define XTENSA_HWCIDVERS_RB_2007_2 52
|
||||
#define XTENSA_HWVERSION_RB_2008_3 221001 /* versions LX2.1.1, X7.1.1 */
|
||||
#define XTENSA_HWCIDSCHEME_RB_2008_3 1100
|
||||
#define XTENSA_HWCIDVERS_RB_2008_3 53
|
||||
#define XTENSA_HWVERSION_RB_2008_4 221002 /* versions LX2.1.2, X7.1.2 */
|
||||
#define XTENSA_HWCIDSCHEME_RB_2008_4 1100
|
||||
#define XTENSA_HWCIDVERS_RB_2008_4 54
|
||||
#define XTENSA_HWVERSION_RB_2009_5 221003 /* versions LX2.1.3, X7.1.3 */
|
||||
#define XTENSA_HWCIDSCHEME_RB_2009_5 1100
|
||||
#define XTENSA_HWCIDVERS_RB_2009_5 55
|
||||
#define XTENSA_HWVERSION_RB_2007_2_MP 221100 /* versions LX2.1.8-MP, X7.1.8-MP */
|
||||
#define XTENSA_HWCIDSCHEME_RB_2007_2_MP 1100
|
||||
#define XTENSA_HWCIDVERS_RB_2007_2_MP 64
|
||||
#define XTENSA_HWVERSION_RC_2009_0 230000 /* versions LX3.0.0, X8.0.0, MX1.0.0 */
|
||||
#define XTENSA_HWCIDSCHEME_RC_2009_0 1100
|
||||
#define XTENSA_HWCIDVERS_RC_2009_0 65
|
||||
#define XTENSA_HWVERSION_RC_2010_1 230001 /* versions LX3.0.1, X8.0.1, MX1.0.1 */
|
||||
#define XTENSA_HWCIDSCHEME_RC_2010_1 1100
|
||||
#define XTENSA_HWCIDVERS_RC_2010_1 66
|
||||
#define XTENSA_HWVERSION_RC_2010_2 230002 /* versions LX3.0.2, X8.0.2, MX1.0.2 */
|
||||
#define XTENSA_HWCIDSCHEME_RC_2010_2 1100
|
||||
#define XTENSA_HWCIDVERS_RC_2010_2 67
|
||||
#define XTENSA_HWVERSION_RC_2011_3 230003 /* versions LX3.0.3, X8.0.3, MX1.0.3 */
|
||||
#define XTENSA_HWCIDSCHEME_RC_2011_3 1100
|
||||
#define XTENSA_HWCIDVERS_RC_2011_3 68
|
||||
#define XTENSA_HWVERSION_RD_2010_0 240000 /* versions LX4.0.0, X9.0.0, MX1.1.0, TX1.0.0 */
|
||||
#define XTENSA_HWCIDSCHEME_RD_2010_0 1100
|
||||
#define XTENSA_HWCIDVERS_RD_2010_0 80
|
||||
#define XTENSA_HWVERSION_RD_2011_1 240001 /* versions LX4.0.1, X9.0.1, MX1.1.1, TX1.0.1 */
|
||||
#define XTENSA_HWCIDSCHEME_RD_2011_1 1100
|
||||
#define XTENSA_HWCIDVERS_RD_2011_1 81
|
||||
#define XTENSA_HWVERSION_RD_2011_2 240002 /* versions LX4.0.2, X9.0.2, MX1.1.2, TX1.0.2 */
|
||||
#define XTENSA_HWCIDSCHEME_RD_2011_2 1100
|
||||
#define XTENSA_HWCIDVERS_RD_2011_2 82
|
||||
#define XTENSA_HWVERSION_RD_2011_3 240003 /* versions LX4.0.3, X9.0.3, MX1.1.3, TX1.0.3 */
|
||||
#define XTENSA_HWCIDSCHEME_RD_2011_3 1100
|
||||
#define XTENSA_HWCIDVERS_RD_2011_3 83
|
||||
#define XTENSA_HWVERSION_RD_2012_4 240004 /* versions LX4.0.4, X9.0.4, MX1.1.4, TX1.0.4 */
|
||||
#define XTENSA_HWCIDSCHEME_RD_2012_4 1100
|
||||
#define XTENSA_HWCIDVERS_RD_2012_4 84
|
||||
#define XTENSA_HWVERSION_RD_2012_5 240005 /* versions LX4.0.5, X9.0.5, MX1.1.5, TX1.0.5 */
|
||||
#define XTENSA_HWCIDSCHEME_RD_2012_5 1100
|
||||
#define XTENSA_HWCIDVERS_RD_2012_5 85
|
||||
#define XTENSA_HWVERSION_RE_2012_0 250000 /* versions LX5.0.0, X10.0.0, MX1.2.0, TX2.0.0 */
|
||||
#define XTENSA_HWCIDSCHEME_RE_2012_0 1100
|
||||
#define XTENSA_HWCIDVERS_RE_2012_0 96
|
||||
#define XTENSA_HWVERSION_RE_2012_1 250001 /* versions LX5.0.1, X10.0.1, MX1.2.1, TX2.0.1 */
|
||||
#define XTENSA_HWCIDSCHEME_RE_2012_1 1100
|
||||
#define XTENSA_HWCIDVERS_RE_2012_1 97
|
||||
#define XTENSA_HWVERSION_RE_2013_2 250002 /* versions LX5.0.2, X10.0.2, MX1.2.2, TX2.0.2 */
|
||||
#define XTENSA_HWCIDSCHEME_RE_2013_2 1100
|
||||
#define XTENSA_HWCIDVERS_RE_2013_2 98
|
||||
#define XTENSA_HWVERSION_RE_2013_3 250003 /* versions LX5.0.3, X10.0.3, MX1.2.3, TX2.0.3 */
|
||||
#define XTENSA_HWCIDSCHEME_RE_2013_3 1100
|
||||
#define XTENSA_HWCIDVERS_RE_2013_3 99
|
||||
#define XTENSA_HWVERSION_RE_2013_4 250004 /* versions LX5.0.4, X10.0.4, MX1.2.4, TX2.0.4 */
|
||||
#define XTENSA_HWCIDSCHEME_RE_2013_4 1100
|
||||
#define XTENSA_HWCIDVERS_RE_2013_4 100
|
||||
#define XTENSA_HWVERSION_RE_2014_5 250005 /* versions LX5.0.5, X10.0.5, MX1.2.5, TX2.0.5 */
|
||||
#define XTENSA_HWCIDSCHEME_RE_2014_5 1100
|
||||
#define XTENSA_HWCIDVERS_RE_2014_5 101
|
||||
#define XTENSA_HWVERSION_RE_2015_6 250006 /* versions LX5.0.6, X10.0.6, MX1.2.6, TX2.0.6 */
|
||||
#define XTENSA_HWCIDSCHEME_RE_2015_6 1100
|
||||
#define XTENSA_HWCIDVERS_RE_2015_6 102
|
||||
#define XTENSA_HWVERSION_RF_2014_0 260000 /* versions LX6.0.0, X11.0.0, MX1.3.0, TX3.0.0 */
|
||||
#define XTENSA_HWCIDSCHEME_RF_2014_0 1100
|
||||
#define XTENSA_HWCIDVERS_RF_2014_0 112
|
||||
#define XTENSA_HWVERSION_RF_2014_1 260001 /* versions LX6.0.1, X11.0.1 */
|
||||
#define XTENSA_HWCIDSCHEME_RF_2014_1 1100
|
||||
#define XTENSA_HWCIDVERS_RF_2014_1 113
|
||||
#define XTENSA_HWVERSION_RF_2015_2 260002 /* versions LX6.0.2, X11.0.2 */
|
||||
#define XTENSA_HWCIDSCHEME_RF_2015_2 1100
|
||||
#define XTENSA_HWCIDVERS_RF_2015_2 114
|
||||
#define XTENSA_HWVERSION_RF_2015_3 260003 /* versions LX6.0.3, X11.0.3 */
|
||||
#define XTENSA_HWCIDSCHEME_RF_2015_3 1100
|
||||
#define XTENSA_HWCIDVERS_RF_2015_3 115
|
||||
#define XTENSA_HWVERSION_RG_2015_0 270000 /* versions LX7.0.0, X12.0.0, NX1.0.0, SX1.0.0, MX1.4.0, TX4.0.0 */
|
||||
#define XTENSA_HWCIDSCHEME_RG_2015_0 1100
|
||||
#define XTENSA_HWCIDVERS_RG_2015_0 128
|
||||
|
||||
/* Software (Xtensa Tools) versions: */
|
||||
#define XTENSA_SWVERSION_T1020_0 102000 /* versions T1020.0 */
|
||||
#define XTENSA_SWVERSION_T1020_1 102001 /* versions T1020.1 */
|
||||
#define XTENSA_SWVERSION_T1020_2B 102002 /* versions T1020.2b */
|
||||
#define XTENSA_SWVERSION_T1020_2 102002 /* versions T1020.2 */
|
||||
#define XTENSA_SWVERSION_T1020_3 102003 /* versions T1020.3 */
|
||||
#define XTENSA_SWVERSION_T1020_4 102004 /* versions T1020.4 */
|
||||
#define XTENSA_SWVERSION_T1030_0 103000 /* versions T1030.0 */
|
||||
#define XTENSA_SWVERSION_T1030_1 103001 /* versions T1030.1 */
|
||||
#define XTENSA_SWVERSION_T1030_2 103002 /* versions T1030.2 */
|
||||
#define XTENSA_SWVERSION_T1030_3 103003 /* versions T1030.3 */
|
||||
#define XTENSA_SWVERSION_T1040_0 104000 /* versions T1040.0 */
|
||||
#define XTENSA_SWVERSION_T1040_1 104001 /* versions T1040.1 */
|
||||
#define XTENSA_SWVERSION_T1040_1P 104001 /* versions T1040.1-prehotfix */
|
||||
#define XTENSA_SWVERSION_T1040_2 104002 /* versions T1040.2 */
|
||||
#define XTENSA_SWVERSION_T1040_3 104003 /* versions T1040.3 */
|
||||
#define XTENSA_SWVERSION_T1050_0 105000 /* versions T1050.0 */
|
||||
#define XTENSA_SWVERSION_T1050_1 105001 /* versions T1050.1 */
|
||||
#define XTENSA_SWVERSION_T1050_2 105002 /* versions T1050.2 */
|
||||
#define XTENSA_SWVERSION_T1050_3 105003 /* versions T1050.3 */
|
||||
#define XTENSA_SWVERSION_T1050_4 105004 /* versions T1050.4 */
|
||||
#define XTENSA_SWVERSION_T1050_5 105005 /* versions T1050.5 */
|
||||
#define XTENSA_SWVERSION_RA_2004_1 600000 /* versions 6.0.0 */
|
||||
#define XTENSA_SWVERSION_RA_2005_1 600001 /* versions 6.0.1 */
|
||||
#define XTENSA_SWVERSION_RA_2005_2 600002 /* versions 6.0.2 */
|
||||
#define XTENSA_SWVERSION_RA_2005_3 600003 /* versions 6.0.3 */
|
||||
#define XTENSA_SWVERSION_RA_2006_4 600004 /* versions 6.0.4 */
|
||||
#define XTENSA_SWVERSION_RA_2006_5 600005 /* versions 6.0.5 */
|
||||
#define XTENSA_SWVERSION_RA_2006_6 600006 /* versions 6.0.6 */
|
||||
#define XTENSA_SWVERSION_RA_2007_7 600007 /* versions 6.0.7 */
|
||||
#define XTENSA_SWVERSION_RA_2008_8 600008 /* versions 6.0.8 */
|
||||
#define XTENSA_SWVERSION_RB_2006_0 700000 /* versions 7.0.0 */
|
||||
#define XTENSA_SWVERSION_RB_2007_1 700001 /* versions 7.0.1 */
|
||||
#define XTENSA_SWVERSION_RB_2007_2 701000 /* versions 7.1.0 */
|
||||
#define XTENSA_SWVERSION_RB_2008_3 701001 /* versions 7.1.1 */
|
||||
#define XTENSA_SWVERSION_RB_2008_4 701002 /* versions 7.1.2 */
|
||||
#define XTENSA_SWVERSION_RB_2009_5 701003 /* versions 7.1.3 */
|
||||
#define XTENSA_SWVERSION_RB_2007_2_MP 701100 /* versions 7.1.8-MP */
|
||||
#define XTENSA_SWVERSION_RC_2009_0 800000 /* versions 8.0.0 */
|
||||
#define XTENSA_SWVERSION_RC_2010_1 800001 /* versions 8.0.1 */
|
||||
#define XTENSA_SWVERSION_RC_2010_2 800002 /* versions 8.0.2 */
|
||||
#define XTENSA_SWVERSION_RC_2011_3 800003 /* versions 8.0.3 */
|
||||
#define XTENSA_SWVERSION_RD_2010_0 900000 /* versions 9.0.0 */
|
||||
#define XTENSA_SWVERSION_RD_2011_1 900001 /* versions 9.0.1 */
|
||||
#define XTENSA_SWVERSION_RD_2011_2 900002 /* versions 9.0.2 */
|
||||
#define XTENSA_SWVERSION_RD_2011_3 900003 /* versions 9.0.3 */
|
||||
#define XTENSA_SWVERSION_RD_2012_4 900004 /* versions 9.0.4 */
|
||||
#define XTENSA_SWVERSION_RD_2012_5 900005 /* versions 9.0.5 */
|
||||
#define XTENSA_SWVERSION_RE_2012_0 1000000 /* versions 10.0.0 */
|
||||
#define XTENSA_SWVERSION_RE_2012_1 1000001 /* versions 10.0.1 */
|
||||
#define XTENSA_SWVERSION_RE_2013_2 1000002 /* versions 10.0.2 */
|
||||
#define XTENSA_SWVERSION_RE_2013_3 1000003 /* versions 10.0.3 */
|
||||
#define XTENSA_SWVERSION_RE_2013_4 1000004 /* versions 10.0.4 */
|
||||
#define XTENSA_SWVERSION_RE_2014_5 1000005 /* versions 10.0.5 */
|
||||
#define XTENSA_SWVERSION_RE_2015_6 1000006 /* versions 10.0.6 */
|
||||
#define XTENSA_SWVERSION_RF_2014_0 1100000 /* versions 11.0.0 */
|
||||
#define XTENSA_SWVERSION_RF_2014_1 1100001 /* versions 11.0.1 */
|
||||
#define XTENSA_SWVERSION_RF_2015_2 1100002 /* versions 11.0.2 */
|
||||
#define XTENSA_SWVERSION_RF_2015_3 1100003 /* versions 11.0.3 */
|
||||
#define XTENSA_SWVERSION_RG_2015_0 1200000 /* versions 12.0.0 */
|
||||
#define XTENSA_SWVERSION_T1040_1_PREHOTFIX XTENSA_SWVERSION_T1040_1P /* T1040.1-prehotfix */
|
||||
#define XTENSA_SWVERSION_6_0_0 XTENSA_SWVERSION_RA_2004_1 /* 6.0.0 */
|
||||
#define XTENSA_SWVERSION_6_0_1 XTENSA_SWVERSION_RA_2005_1 /* 6.0.1 */
|
||||
#define XTENSA_SWVERSION_6_0_2 XTENSA_SWVERSION_RA_2005_2 /* 6.0.2 */
|
||||
#define XTENSA_SWVERSION_6_0_3 XTENSA_SWVERSION_RA_2005_3 /* 6.0.3 */
|
||||
#define XTENSA_SWVERSION_6_0_4 XTENSA_SWVERSION_RA_2006_4 /* 6.0.4 */
|
||||
#define XTENSA_SWVERSION_6_0_5 XTENSA_SWVERSION_RA_2006_5 /* 6.0.5 */
|
||||
#define XTENSA_SWVERSION_6_0_6 XTENSA_SWVERSION_RA_2006_6 /* 6.0.6 */
|
||||
#define XTENSA_SWVERSION_6_0_7 XTENSA_SWVERSION_RA_2007_7 /* 6.0.7 */
|
||||
#define XTENSA_SWVERSION_6_0_8 XTENSA_SWVERSION_RA_2008_8 /* 6.0.8 */
|
||||
#define XTENSA_SWVERSION_7_0_0 XTENSA_SWVERSION_RB_2006_0 /* 7.0.0 */
|
||||
#define XTENSA_SWVERSION_7_0_1 XTENSA_SWVERSION_RB_2007_1 /* 7.0.1 */
|
||||
#define XTENSA_SWVERSION_7_1_0 XTENSA_SWVERSION_RB_2007_2 /* 7.1.0 */
|
||||
#define XTENSA_SWVERSION_7_1_1 XTENSA_SWVERSION_RB_2008_3 /* 7.1.1 */
|
||||
#define XTENSA_SWVERSION_7_1_2 XTENSA_SWVERSION_RB_2008_4 /* 7.1.2 */
|
||||
#define XTENSA_SWVERSION_7_1_3 XTENSA_SWVERSION_RB_2009_5 /* 7.1.3 */
|
||||
#define XTENSA_SWVERSION_7_1_8_MP XTENSA_SWVERSION_RB_2007_2_MP /* 7.1.8-MP */
|
||||
#define XTENSA_SWVERSION_8_0_0 XTENSA_SWVERSION_RC_2009_0 /* 8.0.0 */
|
||||
#define XTENSA_SWVERSION_8_0_1 XTENSA_SWVERSION_RC_2010_1 /* 8.0.1 */
|
||||
#define XTENSA_SWVERSION_8_0_2 XTENSA_SWVERSION_RC_2010_2 /* 8.0.2 */
|
||||
#define XTENSA_SWVERSION_8_0_3 XTENSA_SWVERSION_RC_2011_3 /* 8.0.3 */
|
||||
#define XTENSA_SWVERSION_9_0_0 XTENSA_SWVERSION_RD_2010_0 /* 9.0.0 */
|
||||
#define XTENSA_SWVERSION_9_0_1 XTENSA_SWVERSION_RD_2011_1 /* 9.0.1 */
|
||||
#define XTENSA_SWVERSION_9_0_2 XTENSA_SWVERSION_RD_2011_2 /* 9.0.2 */
|
||||
#define XTENSA_SWVERSION_9_0_3 XTENSA_SWVERSION_RD_2011_3 /* 9.0.3 */
|
||||
#define XTENSA_SWVERSION_9_0_4 XTENSA_SWVERSION_RD_2012_4 /* 9.0.4 */
|
||||
#define XTENSA_SWVERSION_9_0_5 XTENSA_SWVERSION_RD_2012_5 /* 9.0.5 */
|
||||
#define XTENSA_SWVERSION_10_0_0 XTENSA_SWVERSION_RE_2012_0 /* 10.0.0 */
|
||||
#define XTENSA_SWVERSION_10_0_1 XTENSA_SWVERSION_RE_2012_1 /* 10.0.1 */
|
||||
#define XTENSA_SWVERSION_10_0_2 XTENSA_SWVERSION_RE_2013_2 /* 10.0.2 */
|
||||
#define XTENSA_SWVERSION_10_0_3 XTENSA_SWVERSION_RE_2013_3 /* 10.0.3 */
|
||||
#define XTENSA_SWVERSION_10_0_4 XTENSA_SWVERSION_RE_2013_4 /* 10.0.4 */
|
||||
#define XTENSA_SWVERSION_10_0_5 XTENSA_SWVERSION_RE_2014_5 /* 10.0.5 */
|
||||
#define XTENSA_SWVERSION_10_0_6 XTENSA_SWVERSION_RE_2015_6 /* 10.0.6 */
|
||||
#define XTENSA_SWVERSION_11_0_0 XTENSA_SWVERSION_RF_2014_0 /* 11.0.0 */
|
||||
#define XTENSA_SWVERSION_11_0_1 XTENSA_SWVERSION_RF_2014_1 /* 11.0.1 */
|
||||
#define XTENSA_SWVERSION_11_0_2 XTENSA_SWVERSION_RF_2015_2 /* 11.0.2 */
|
||||
#define XTENSA_SWVERSION_11_0_3 XTENSA_SWVERSION_RF_2015_3 /* 11.0.3 */
|
||||
#define XTENSA_SWVERSION_12_0_0 XTENSA_SWVERSION_RG_2015_0 /* 12.0.0 */
|
||||
|
||||
|
||||
/* The current release: */
|
||||
#define XTENSA_RELEASE_NAME "RF-2015.3"
|
||||
#define XTENSA_RELEASE_CANONICAL_NAME "RF-2015.3"
|
||||
|
||||
/* The product versions within the current release: */
|
||||
#define XTENSA_SWVERSION XTENSA_SWVERSION_RF_2015_3
|
||||
#define XTENSA_SWVERSION_NAME "11.0.3"
|
||||
#define XTENSA_SWVERSION_CANONICAL_NAME "11.0.3"
|
||||
#define XTENSA_SWVERSION_MAJORMID_NAME "11.0"
|
||||
#define XTENSA_SWVERSION_MAJOR_NAME "11"
|
||||
/* For product licensing (not necessarily same as *_MAJORMID_NAME): */
|
||||
#define XTENSA_SWVERSION_LICENSE_NAME "11.0"
|
||||
|
||||
/* Note: there may be multiple hardware products in one release,
|
||||
and software can target older hardware, so the notion of
|
||||
"current" hardware versions is partially configuration dependent.
|
||||
For now, "current" hardware product version info is left out
|
||||
to avoid confusion. */
|
||||
|
||||
#endif /*XTENSA_VERSIONS_H*/
|
||||
|
||||
Executable
+149
@@ -0,0 +1,149 @@
|
||||
/* xer-constants.h -- various constants describing external registers accessed
|
||||
via wer and rer.
|
||||
|
||||
TODO: find a better prefix. Also conditionalize certain constants based
|
||||
on number of cores and interrupts actually present.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 1999-2008 Tensilica Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <xtensa/config/core.h>
|
||||
|
||||
#define NUM_INTERRUPTS 27
|
||||
#define NUM_CORES 4
|
||||
|
||||
/* Routing of NMI (BInterrupt2) and interrupts 0..n-1 (BInterrupt3+)
|
||||
RER reads
|
||||
WER writes
|
||||
*/
|
||||
|
||||
#define XER_MIROUT 0x0000
|
||||
#define XER_MIROUT_LAST (XER_MIROUT + NUM_INTERRUPTS)
|
||||
|
||||
|
||||
/* IPI to core M (all 16 causes).
|
||||
|
||||
RER reads
|
||||
WER clears
|
||||
*/
|
||||
#define XER_MIPICAUSE 0x0100
|
||||
#define XER_MIPICAUSE_FIELD_A_FIRST 0x0
|
||||
#define XER_MIPICAUSE_FIELD_A_LAST 0x0
|
||||
#define XER_MIPICAUSE_FIELD_B_FIRST 0x1
|
||||
#define XER_MIPICAUSE_FIELD_B_LAST 0x3
|
||||
#define XER_MIPICAUSE_FIELD_C_FIRST 0x4
|
||||
#define XER_MIPICAUSE_FIELD_C_LAST 0x7
|
||||
#define XER_MIPICAUSE_FIELD_D_FIRST 0x8
|
||||
#define XER_MIPICAUSE_FIELD_D_LAST 0xF
|
||||
|
||||
|
||||
/* IPI from cause bit 0..15
|
||||
|
||||
RER invalid
|
||||
WER sets
|
||||
*/
|
||||
#define XER_MIPISET 0x0140
|
||||
#define XER_MIPISET_LAST 0x014F
|
||||
|
||||
|
||||
/* Global enable
|
||||
|
||||
RER read
|
||||
WER clear
|
||||
*/
|
||||
#define XER_MIENG 0x0180
|
||||
|
||||
|
||||
/* Global enable
|
||||
|
||||
RER invalid
|
||||
WER set
|
||||
*/
|
||||
#define XER_MIENG_SET 0x0184
|
||||
|
||||
/* Global assert
|
||||
|
||||
RER read
|
||||
WER clear
|
||||
*/
|
||||
#define XER_MIASG 0x0188
|
||||
|
||||
|
||||
/* Global enable
|
||||
|
||||
RER invalid
|
||||
WER set
|
||||
*/
|
||||
#define XER_MIASG_SET 0x018C
|
||||
|
||||
|
||||
/* IPI partition register
|
||||
|
||||
RER read
|
||||
WER write
|
||||
*/
|
||||
#define XER_PART 0x0190
|
||||
#define XER_IPI0 0x0
|
||||
#define XER_IPI1 0x1
|
||||
#define XER_IPI2 0x2
|
||||
#define XER_IPI3 0x3
|
||||
|
||||
#define XER_PART_ROUTE_IPI(NUM, FIELD) ((NUM) << ((FIELD) << 2))
|
||||
|
||||
#define XER_PART_ROUTE_IPI_CAUSE(TO_A, TO_B, TO_C, TO_D) \
|
||||
(XER_PART_ROUTE_IPI(TO_A, XER_IPI0) | \
|
||||
XER_PART_ROUTE_IPI(TO_B, XER_IPI1) | \
|
||||
XER_PART_ROUTE_IPI(TO_C, XER_IPI2) | \
|
||||
XER_PART_ROUTE_IPI(TO_D, XER_IPI3))
|
||||
|
||||
#define XER_IPI_WAKE_EXT_INTERRUPT XCHAL_EXTINT0_NUM
|
||||
#define XER_IPI_WAKE_CAUSE XER_MIPICAUSE_FIELD_C_FIRST
|
||||
#define XER_IPI_WAKE_ADDRESS (XER_MIPISET + XER_IPI_WAKE_CAUSE)
|
||||
#define XER_DEFAULT_IPI_ROUTING XER_PART_ROUTE_IPI_CAUSE(XER_IPI1, XER_IPI0, XER_IPI2, XER_IPI3)
|
||||
|
||||
|
||||
/* System configuration ID
|
||||
|
||||
RER read
|
||||
WER invalid
|
||||
*/
|
||||
#define XER_SYSCFGID 0x01A0
|
||||
|
||||
|
||||
/* RunStall to slave processors
|
||||
|
||||
RER read
|
||||
WER write
|
||||
*/
|
||||
#define XER_MPSCORE 0x0200
|
||||
|
||||
|
||||
/* Cache coherency ON
|
||||
|
||||
RER read
|
||||
WER write
|
||||
*/
|
||||
#define XER_CCON 0x0220
|
||||
|
||||
|
||||
Executable
+14
@@ -0,0 +1,14 @@
|
||||
/* Copyright (c) 2006-2013 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
/ These coded instructions, statements, and computer programs are the
|
||||
/ copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
/ They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
/ third parties in any manner, medium, or form, in whole or in part, without
|
||||
/ the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
/* xtkc705.h - Xtensa Xilinx KC705 (XT-KC705) board specific definitions */
|
||||
|
||||
/* 99.9% same as ML605, just indicate we're KC705 and include ML605 header: */
|
||||
#define XTBOARD_IS_KC705 1
|
||||
#include <xtensa/xtml605.h>
|
||||
|
||||
+13
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* board.h - Include board-specific definitions
|
||||
*
|
||||
* Copyright (c) 2013 by Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
* These coded instructions, statements, and computer programs are the
|
||||
* copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
* They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
* third parties in any manner, medium, or form, in whole or in part, without
|
||||
* the prior written consent of Tensilica Inc.
|
||||
*/
|
||||
|
||||
#include <xtensa/xtkc705.h>
|
||||
|
||||
Executable
+77
@@ -0,0 +1,77 @@
|
||||
/* Customer ID=11656; Build=0x5f626; Copyright (c) 2003-2012 Tensilica Inc. ALL RIGHTS RESERVED.
|
||||
These coded instructions, statements, and computer programs are the
|
||||
copyrighted works and confidential proprietary information of Tensilica Inc.
|
||||
They may not be modified, copied, reproduced, distributed, or disclosed to
|
||||
third parties in any manner, medium, or form, in whole or in part, without
|
||||
the prior written consent of Tensilica Inc. */
|
||||
|
||||
#ifndef _XTLOAD_API_H
|
||||
#define _XTLOAD_API_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define XTENSA_BYTES_PER_WORD 4
|
||||
#define XLOAD_ALL_CORES -1
|
||||
|
||||
typedef int core_number_t;
|
||||
typedef uint32_t xtload_address_t;
|
||||
typedef uint32_t xtload_word_count_t;
|
||||
typedef uint32_t * xtload_word_ptr_t;
|
||||
|
||||
/* These functions correspond one-to-one with xt-load script
|
||||
commands. See the documentation for xt-load for their usage.
|
||||
|
||||
There are however, several higher-level script commands--such as
|
||||
load-elf-file--which don't have direct analogues here. These
|
||||
"missing" commands are essentially just macros that result in
|
||||
several of these commands below. Note that you can execute several
|
||||
of these commands, then the results of a script, or vice-versa.
|
||||
*/
|
||||
|
||||
void xtload_bootloader_wake (void);
|
||||
void xtload_bootloader_sleep (void);
|
||||
void xtload_bootloader_done (void);
|
||||
void xtload_bootloader_not_done (void);
|
||||
void xtload_reset_and_cont (core_number_t core);
|
||||
void xtload_stall_and_reset (core_number_t core);
|
||||
#define xtload_reset_and_stall xtload_stall_and_reset
|
||||
void xtload_stall_and_target (core_number_t core);
|
||||
void xtload_ignore_and_stall (core_number_t core);
|
||||
void xtload_ignore_and_cont (core_number_t core);
|
||||
#define xtload_ignore_and_continue xtload_ignore_and_cont
|
||||
void xtload_read_words (xtload_address_t addr, xtload_word_count_t count);
|
||||
void xtload_zero_words (xtload_address_t addr, xtload_word_count_t count);
|
||||
void xtload_write_words (int swap, xtload_address_t addr,
|
||||
xtload_word_ptr_t ptr, xtload_word_count_t count);
|
||||
void xtload_setup_write_words (xtload_address_t addr, xtload_word_count_t count);
|
||||
void xtload_read_register (core_number_t core);
|
||||
|
||||
/* *I M P O R T A N T*
|
||||
|
||||
The bootloader API calls this function whenever it outputs a word
|
||||
to the bootloader hardware chain.
|
||||
|
||||
Because the API has no information about how the bootloader
|
||||
hardware is connected to the host hardware, the user must
|
||||
implement this function to write a word to the bootloader's register.
|
||||
|
||||
A user's implementation might write the bytes to an Xtensa queue or
|
||||
to a memory-mapped register.
|
||||
|
||||
For example, xt-load uses this API just like any other client. Its
|
||||
implementation of this function simply writes this word to an
|
||||
output file.
|
||||
*/
|
||||
|
||||
void xtload_user_output_word (uint32_t word);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _XTLOAD_API_H */
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user