feat(dsi): split the dphy config clock and pll reference clock
this is a breaking change in the esp32p4 ver3.0 silicon.
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@@ -143,15 +143,6 @@ void mipi_dsi_hal_host_gen_write_short_packet(mipi_dsi_hal_context_t *hal, uint8
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void mipi_dsi_hal_host_gen_read_short_packet(mipi_dsi_hal_context_t *hal, uint8_t vc,
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mipi_dsi_data_type_t dt, uint16_t header_data, void *ret_buffer, uint16_t buffer_size);
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/**
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* @brief Set DPI color coding
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*
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* @param hal Pointer to the HAL driver context
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* @param color_coding Color coding
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* @param sub_config Sub configuration
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*/
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void mipi_dsi_hal_host_dpi_set_color_coding(mipi_dsi_hal_context_t *hal, lcd_color_format_t color_coding, uint32_t sub_config);
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/**
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* @brief Set horizontal timing parameters for DPI
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*
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@@ -9,6 +9,7 @@
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#include <stdint.h>
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#include "soc/clk_tree_defs.h"
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#include "esp_assert.h"
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#include "soc/soc_caps.h"
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#ifdef __cplusplus
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extern "C" {
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@@ -58,17 +59,25 @@ typedef enum {
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} mipi_dsi_pattern_type_t;
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#if SOC_MIPI_DSI_SUPPORTED
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/**
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* @brief MIPI DSI PHY clock source
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* @brief MIPI DSI PHY PLL reference clock source
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*/
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typedef soc_periph_mipi_dsi_phy_clk_src_t mipi_dsi_phy_clock_source_t;
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typedef soc_periph_mipi_dsi_phy_pllref_clk_src_t mipi_dsi_phy_pllref_clock_source_t;
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/**
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* @brief MIPI DSI DPI clock source
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*/
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typedef soc_periph_mipi_dsi_dpi_clk_src_t mipi_dsi_dpi_clock_source_t;
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/**
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* @brief For backward compatibility
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*/
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typedef mipi_dsi_phy_pllref_clock_source_t mipi_dsi_phy_clock_source_t;
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#else
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typedef int mipi_dsi_phy_clock_source_t;
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typedef int mipi_dsi_phy_pllref_clock_source_t;
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typedef int mipi_dsi_dpi_clock_source_t;
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#endif // SOC_MIPI_DSI_SUPPORTED
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