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esp32h4: removed esp32h4 related codes

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This commit is contained in:
laokaiyao
2023-04-13 14:32:25 +08:00
committed by Kevin (Lao Kaiyao)
parent b16ed57b2e
commit bf2a7b2df6
110 changed files with 195 additions and 1997 deletions
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components/esp_system/Kconfig
+1 -2
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@@ -99,7 +99,6 @@ menu "ESP System Settings"
default y if IDF_TARGET_ESP32S2
default y if IDF_TARGET_ESP32C3
default y if IDF_TARGET_ESP32S3
default y if IDF_TARGET_ESP32H4
default y if IDF_TARGET_ESP32C6
default n if IDF_TARGET_ESP32H2 # IDF-5667
depends on SOC_RTC_FAST_MEM_SUPPORTED
@@ -280,7 +279,7 @@ menu "ESP System Settings"
config ESP_CONSOLE_MULTIPLE_UART
bool
default y if !IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32H4 && !IDF_TARGET_ESP32C2
default y if !IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32C2
choice ESP_CONSOLE_UART_NUM
prompt "UART peripheral to use for console output (0-1)"
components/esp_system/crosscore_int.c
+4 -4
View File
@@ -29,7 +29,7 @@
#define REASON_FREQ_SWITCH BIT(1)
#define REASON_GDB_CALL BIT(3)
#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H4 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C6
#if !CONFIG_IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C6
#define REASON_PRINT_BACKTRACE BIT(2)
#define REASON_TWDT_ABORT BIT(4)
#endif
@@ -66,7 +66,7 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) {
} else {
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, 0);
}
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
#elif CONFIG_IDF_TARGET_ESP32C3|| CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
#endif
@@ -147,7 +147,7 @@ static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask)
} else {
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, SYSTEM_CPU_INTR_FROM_CPU_1);
}
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
#endif
}
@@ -167,7 +167,7 @@ void IRAM_ATTR esp_crosscore_int_send_gdb_call(int core_id)
esp_crosscore_int_send(core_id, REASON_GDB_CALL);
}
#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H4 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2
#if !CONFIG_IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2
void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
{
esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE);
components/esp_system/fpga_overrides.c
-4
View File
@@ -17,8 +17,6 @@
#include "esp32s3/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32H4
#include "esp32h4/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C6
@@ -47,8 +45,6 @@ void bootloader_clock_configure(void)
uint32_t xtal_freq_mhz = 40;
#ifdef CONFIG_IDF_TARGET_ESP32S2
uint32_t apb_freq_hz = 20000000;
#elif CONFIG_IDF_TARGET_ESP32H4
uint32_t apb_freq_hz = 32000000;
#else
uint32_t apb_freq_hz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 1000000;
#endif // CONFIG_IDF_TARGET_ESP32S2
components/esp_system/include/esp_private/crosscore_int.h
+2 -2
View File
@@ -50,7 +50,7 @@ void esp_crosscore_int_send_freq_switch(int core_id);
void esp_crosscore_int_send_gdb_call(int core_id);
#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H4 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2
#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2
/**
* Send an interrupt to a CPU indicating it should print its current backtrace
*
@@ -75,7 +75,7 @@ void esp_crosscore_int_send_print_backtrace(int core_id);
void esp_crosscore_int_send_twdt_abort(int core_id);
#endif // CONFIG_ESP_TASK_WDT_EN
#endif // !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H4 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6
#endif // !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6
#ifdef __cplusplus
}
components/esp_system/port/cpu_start.c
-5
View File
@@ -56,11 +56,6 @@
#include "esp32h2/rtc.h"
#include "esp32h2/rom/cache.h"
#include "esp_memprot.h"
#elif CONFIG_IDF_TARGET_ESP32H4
#include "esp32h4/rtc.h"
#include "esp32h4/rom/cache.h"
#include "esp32h4/rom/secure_boot.h"
#include "esp_memprot.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rtc.h"
#include "esp32c2/rom/cache.h"
components/esp_system/system_time.c
-2
View File
@@ -21,8 +21,6 @@
#include "esp32s3/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32H4
#include "esp32h4/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C6
components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c
+1 -1
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@@ -43,7 +43,7 @@
#define BROWNOUT "BROWN_OUT_RST"
#define STORE_ERROR "StoreProhibited"
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2
#define DEEPSLEEP "DSLEEP"
#define LOAD_STORE_ERROR "Store access fault"
#define RESET "RTC_SW_CPU_RST"