sdm: support derive clock source from IO MUX

This commit is contained in:
morris
2022-12-13 14:39:38 +08:00
parent 672ac58ad5
commit cbe297e5a0
17 changed files with 76 additions and 10 deletions
+21
View File
@@ -26,6 +26,7 @@
#include "hal/sdm_ll.h"
#include "soc/sdm_periph.h"
#include "esp_private/esp_clk.h"
#include "esp_private/io_mux.h"
#if CONFIG_SDM_CTRL_FUNC_IN_IRAM
#define SDM_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
@@ -209,6 +210,7 @@ esp_err_t sdm_new_channel(const sdm_config_t *config, sdm_channel_handle_t *ret_
ESP_GOTO_ON_FALSE(group->clk_src == 0 || group->clk_src == config->clk_src, ESP_ERR_INVALID_ARG, err, TAG, "clock source conflict");
uint32_t src_clk_hz = 0;
switch (config->clk_src) {
#if SOC_SDM_CLK_SUPPORT_APB
case SDM_CLK_SRC_APB:
src_clk_hz = esp_clk_apb_freq();
#if CONFIG_PM_ENABLE
@@ -217,12 +219,31 @@ esp_err_t sdm_new_channel(const sdm_config_t *config, sdm_channel_handle_t *ret_
ESP_RETURN_ON_ERROR(ret, TAG, "create APB_FREQ_MAX lock failed");
#endif
break;
#endif // SOC_SDM_CLK_SUPPORT_APB
#if SOC_SDM_CLK_SUPPORT_XTAL
case SDM_CLK_SRC_XTAL:
src_clk_hz = esp_clk_xtal_freq();
break;
#endif // SOC_SDM_CLK_SUPPORT_XTAL
#if SOC_SDM_CLK_SUPPORT_PLL_F80M
case SDM_CLK_SRC_PLL_F80M:
src_clk_hz = 80 * 1000 * 1000;
#if CONFIG_PM_ENABLE
sprintf(chan->pm_lock_name, "sdm_%d_%d", group->group_id, chan_id); // e.g. sdm_0_0
ret = esp_pm_lock_create(ESP_PM_NO_LIGHT_SLEEP, 0, chan->pm_lock_name, &chan->pm_lock);
ESP_RETURN_ON_ERROR(ret, TAG, "create NO_LIGHT_SLEEP lock failed");
#endif
break;
#endif // SOC_SDM_CLK_SUPPORT_PLL_F80M
default:
ESP_GOTO_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, err, TAG, "clock source %d is not support", config->clk_src);
break;
}
group->clk_src = config->clk_src;
// SDM clock comes from IO MUX, but IO MUX clock might be shared with other submodules as well
ESP_GOTO_ON_ERROR(io_mux_set_clock_source((soc_module_clk_t)(group->clk_src)), err, TAG, "set IO MUX clock source failed");
// GPIO configuration
gpio_config_t gpio_conf = {
.intr_type = GPIO_INTR_DISABLE,