Merge branch 'feature/spi_dma_segmented_configure_transfer' into 'master'

feat(spi_master): new feature dma controlled segmented configure transfer(sct) mode (part_1)

Closes IDF-4998

See merge request espressif/esp-idf!22684

components/hal/include/hal/spi_hal.h

@@ -133,6 +133,33 @@ typedef struct {
     };//boolean configurations
 } spi_hal_dev_config_t;
 
+#if SOC_SPI_SCT_SUPPORTED
+/**
+ * SCT mode required configurations, per segment
+ */
+typedef struct {
+    /* CONF State */
+    bool seg_end;                       ///< True: this segment is the end; False: this segment isn't the end;
+    uint32_t seg_gap_len;               ///< spi clock length of CS inactive on config phase for sct
+    /* PREP State */
+    int cs_setup;                       ///< Setup time of CS active edge before the first SPI clock
+    /* CMD State */
+    uint16_t cmd;                       ///< Command value to be sent
+    int cmd_bits;                       ///< Length (in bits) of the command phase
+    /* ADDR State */
+    uint64_t addr;                      ///< Address value to be sent
+    int addr_bits;                      ///< Length (in bits) of the address phase
+    /* DUMMY State */
+    int dummy_bits;                     ///< Base length (in bits) of the dummy phase.
+    /* DOUT State */
+    int tx_bitlen;                      ///< TX length, in bits
+    /* DIN State */
+    int rx_bitlen;                      ///< RX length, in bits
+    /* DONE State */
+    int cs_hold;                        ///< Hold time of CS inactive edge after the last SPI clock
+} spi_hal_seg_config_t;
+#endif  //#if SOC_SPI_SCT_SUPPORTED
+
 /**
  * Init the peripheral and the context.
  *
@@ -266,6 +293,59 @@ void spi_hal_cal_timing(int source_freq_hz, int eff_clk, bool gpio_is_used, int
  */
 int spi_hal_get_freq_limit(bool gpio_is_used, int input_delay_ns);
 
+#if SOC_SPI_SCT_SUPPORTED
+/*----------------------------------------------------------
+ * Segmented-Configure-Transfer (SCT) Mode
+ * ---------------------------------------------------------*/
+/**
+ * Initialise SCT mode required registers and hal states
+ *
+ * @param hal            Context of the HAL layer.
+ */
+void spi_hal_sct_init(spi_hal_context_t *hal);
+
+/**
+ * Initialise conf buffer, give it an initial value
+ *
+ * @param hal            Context of the HAL layer.
+ */
+void spi_hal_sct_init_conf_buffer(spi_hal_context_t *hal, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]);
+
+/**
+ * Format the conf buffer
+ * According to the `spi_hal_seg_config_t`, update the conf buffer
+ *
+ * @param hal            Context of the HAL layer.
+ * @param config         Conf buffer configuration, per segment. See `spi_hal_seg_config_t` to know what can be configured
+ * @param conf_buffer    Conf buffer
+ */
+void spi_hal_sct_format_conf_buffer(spi_hal_context_t *hal, const spi_hal_seg_config_t *config, const spi_hal_dev_config_t *dev, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]);
+
+/**
+ * Deinit SCT mode related registers and hal states
+ */
+void spi_hal_sct_deinit(spi_hal_context_t *hal);
+
+/**
+ * Set conf_bitslen to HW for sct.
+ */
+void spi_hal_sct_set_conf_bits_len(spi_hal_context_t *hal, uint32_t conf_len);
+
+/**
+ * Clear SPI interrupt bits by mask
+ */
+void spi_hal_clear_intr_mask(spi_hal_context_t *hal, uint32_t mask);
+
+/**
+ * Get SPI interrupt bits status by mask
+ */
+bool spi_hal_get_intr_mask(spi_hal_context_t *hal, uint32_t mask);
+
+/**
+ * Set conf_bitslen base to HW for sct, only supported on s2.
+ */
+#define spi_hal_sct_setup_conf_base(hal, conf_base)     spi_ll_set_conf_base_bitslen((hal)->hw, conf_base)
+#endif  //#if SOC_SPI_SCT_SUPPORTED
 #endif  //#if SOC_GPSPI_SUPPORTED
 
 #ifdef __cplusplus