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feat(esp_eth): a new folder structure of the driver and other improvements

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Fixed memory leak in emac_esp_new_dma function.

Polished ESP EMAC cache management.

Added emac_periph definitions based on SoC features and improved(generalized) ESP EMAC GPIO
initialization.

Added ESP EMAC GPIO reservation.

Added check for frame error condition indicated by EMAC DMA and created a target test.
This commit is contained in:
Ondrej Kosta
2024-04-26 12:27:54 +02:00
parent ee8a9e8410
commit d15a9c2c48
63 changed files with 2068 additions and 1442 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_eth/src/phy/esp_eth_phy_802_3.c
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/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <stdlib.h>
#include <sys/cdefs.h>
#include "esp_log.h"
#include "esp_check.h"
#include "esp_eth.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "driver/gpio.h"
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"
#include "esp_eth_phy_802_3.h"
// Default reset assertion time is selected to be 100us as it is most commonly used value among PHY chips.
#define PHY_RESET_ASSERTION_TIME_US 100
static const char *TAG = "eth_phy_802_3";
static esp_err_t set_mediator(esp_eth_phy_t *phy, esp_eth_mediator_t *eth)
{
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
return esp_eth_phy_802_3_set_mediator(phy_802_3, eth);
}
static esp_err_t reset(esp_eth_phy_t *phy)
{
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
return esp_eth_phy_802_3_reset(phy_802_3);
}
static esp_err_t reset_hw_default(esp_eth_phy_t *phy)
{
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
return esp_eth_phy_802_3_reset_hw(phy_802_3, PHY_RESET_ASSERTION_TIME_US);
}
static esp_err_t autonego_ctrl(esp_eth_phy_t *phy, eth_phy_autoneg_cmd_t cmd, bool *autonego_en_stat)
{
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
return esp_eth_phy_802_3_autonego_ctrl(phy_802_3, cmd, autonego_en_stat);
}
static esp_err_t pwrctl(esp_eth_phy_t *phy, bool enable)
{
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
return esp_eth_phy_802_3_pwrctl(phy_802_3, enable);
}
static esp_err_t set_addr(esp_eth_phy_t *phy, uint32_t addr)
{
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
return esp_eth_phy_802_3_set_addr(phy_802_3, addr);
}
static esp_err_t get_addr(esp_eth_phy_t *phy, uint32_t *addr)
{
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
return esp_eth_phy_802_3_get_addr(phy_802_3, addr);
}
static esp_err_t advertise_pause_ability(esp_eth_phy_t *phy, uint32_t ability)
{
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
return esp_eth_phy_802_3_advertise_pause_ability(phy_802_3, ability);
}
static esp_err_t loopback(esp_eth_phy_t *phy, bool enable)
{
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
return esp_eth_phy_802_3_loopback(phy_802_3, enable);
}
static esp_err_t set_speed(esp_eth_phy_t *phy, eth_speed_t speed)
{
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
return esp_eth_phy_802_3_set_speed(phy_802_3, speed);
}
static esp_err_t set_duplex(esp_eth_phy_t *phy, eth_duplex_t duplex)
{
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
return esp_eth_phy_802_3_set_duplex(phy_802_3, duplex);
}
static esp_err_t set_link(esp_eth_phy_t *phy, eth_link_t link)
{
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
return esp_eth_phy_802_3_set_link(phy_802_3, link);
}
static esp_err_t init(esp_eth_phy_t *phy)
{
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
return esp_eth_phy_802_3_init(phy_802_3);
}
static esp_err_t deinit(esp_eth_phy_t *phy)
{
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
return esp_eth_phy_802_3_deinit(phy_802_3);
}
static esp_err_t del(esp_eth_phy_t *phy)
{
free(phy);
return ESP_OK;
}
esp_err_t esp_eth_phy_802_3_set_mediator(phy_802_3_t *phy_802_3, esp_eth_mediator_t *eth)
{
esp_err_t ret = ESP_OK;
ESP_GOTO_ON_FALSE(eth, ESP_ERR_INVALID_ARG, err, TAG, "mediator can't be null");
phy_802_3->eth = eth;
return ESP_OK;
err:
return ret;
}
esp_err_t esp_eth_phy_802_3_reset(phy_802_3_t *phy_802_3)
{
esp_err_t ret = ESP_OK;
phy_802_3->link_status = ETH_LINK_DOWN;
esp_eth_mediator_t *eth = phy_802_3->eth;
bmcr_reg_t bmcr = {.reset = 1};
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
/* wait for reset complete */
uint32_t to = 0;
for (to = 0; to < phy_802_3->reset_timeout_ms / 10; to++) {
vTaskDelay(pdMS_TO_TICKS(10));
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
if (!bmcr.reset) {
break;
}
}
ESP_GOTO_ON_FALSE(to < phy_802_3->reset_timeout_ms / 10, ESP_FAIL, err, TAG, "reset timeout");
return ESP_OK;
err:
return ret;
}
/**
* @brief PHY hardware reset with default assert time
*
* @note Default reset assertion time is selected to be 100us as it is most commonly used value among PHY chips.
* If your PHY chip requires different value, redefine the `reset_hw` function in derived PHY specific driver structure.
*
* @param phy Ethernet PHY instance
* @return
* - ESP_OK on success
*/
esp_err_t esp_eth_phy_802_3_reset_hw_default(phy_802_3_t *phy_802_3)
{
return esp_eth_phy_802_3_reset_hw(phy_802_3, PHY_RESET_ASSERTION_TIME_US);
}
esp_err_t esp_eth_phy_802_3_autonego_ctrl(phy_802_3_t *phy_802_3, eth_phy_autoneg_cmd_t cmd, bool *autonego_en_stat)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = phy_802_3->eth;
bmcr_reg_t bmcr;
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
switch (cmd) {
case ESP_ETH_PHY_AUTONEGO_RESTART:
ESP_GOTO_ON_FALSE(bmcr.en_auto_nego, ESP_ERR_INVALID_STATE, err, TAG, "auto negotiation is disabled");
/* in case any link status has changed, let's assume we're in link down status */
phy_802_3->link_status = ETH_LINK_DOWN;
bmcr.restart_auto_nego = 1; /* Restart Auto Negotiation */
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
/* Wait for auto negotiation complete */
bmsr_reg_t bmsr;
uint32_t to = 0;
for (to = 0; to < phy_802_3->autonego_timeout_ms / 100; to++) {
vTaskDelay(pdMS_TO_TICKS(100));
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
if (bmsr.auto_nego_complete) {
break;
}
}
if ((to >= phy_802_3->autonego_timeout_ms / 100) && (phy_802_3->link_status == ETH_LINK_UP)) {
ESP_LOGW(TAG, "auto negotiation timeout");
}
break;
case ESP_ETH_PHY_AUTONEGO_DIS:
if (bmcr.en_auto_nego == 1) {
bmcr.en_auto_nego = 0; /* Disable Auto Negotiation */
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
/* read configuration back */
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
ESP_GOTO_ON_FALSE(bmcr.en_auto_nego == 0, ESP_FAIL, err, TAG, "disable auto-negotiation failed");
}
break;
case ESP_ETH_PHY_AUTONEGO_EN:
if (bmcr.en_auto_nego == 0) {
bmcr.en_auto_nego = 1; /* Enable Auto Negotiation */
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
/* read configuration back */
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
ESP_GOTO_ON_FALSE(bmcr.en_auto_nego == 1, ESP_FAIL, err, TAG, "enable auto-negotiation failed");
}
break;
case ESP_ETH_PHY_AUTONEGO_G_STAT:
/* do nothing autonego_en_stat is set at the function end */
break;
default:
return ESP_ERR_INVALID_ARG;
}
*autonego_en_stat = bmcr.en_auto_nego;
return ESP_OK;
err:
return ret;
}
esp_err_t esp_eth_phy_802_3_pwrctl(phy_802_3_t *phy_802_3, bool enable)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = phy_802_3->eth;
bmcr_reg_t bmcr;
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
if (!enable) {
/* Enable IEEE Power Down Mode */
bmcr.power_down = 1;
} else {
/* Disable IEEE Power Down Mode */
bmcr.power_down = 0;
}
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
if (!enable) {
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
ESP_GOTO_ON_FALSE(bmcr.power_down == 1, ESP_FAIL, err, TAG, "power down failed");
} else {
/* wait for power up complete */
uint32_t to = 0;
for (to = 0; to < phy_802_3->reset_timeout_ms / 10; to++) {
vTaskDelay(pdMS_TO_TICKS(10));
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
if (bmcr.power_down == 0) {
break;
}
}
ESP_GOTO_ON_FALSE(to < phy_802_3->reset_timeout_ms / 10, ESP_FAIL, err, TAG, "power up timeout");
}
return ESP_OK;
err:
return ret;
}
esp_err_t esp_eth_phy_802_3_set_addr(phy_802_3_t *phy_802_3, uint32_t addr)
{
phy_802_3->addr = addr;
return ESP_OK;
}
esp_err_t esp_eth_phy_802_3_get_addr(phy_802_3_t *phy_802_3, uint32_t *addr)
{
esp_err_t ret = ESP_OK;
ESP_GOTO_ON_FALSE(addr, ESP_ERR_INVALID_ARG, err, TAG, "addr can't be null");
*addr = phy_802_3->addr;
return ESP_OK;
err:
return ret;
}
esp_err_t esp_eth_phy_802_3_advertise_pause_ability(phy_802_3_t *phy_802_3, uint32_t ability)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = phy_802_3->eth;
/* Set PAUSE function ability */
anar_reg_t anar;
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_ANAR_REG_ADDR, &(anar.val)), err, TAG, "read ANAR failed");
if (ability) {
anar.asymmetric_pause = 1;
anar.symmetric_pause = 1;
} else {
anar.asymmetric_pause = 0;
anar.symmetric_pause = 0;
}
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, phy_802_3->addr, ETH_PHY_ANAR_REG_ADDR, anar.val), err, TAG, "write ANAR failed");
return ESP_OK;
err:
return ret;
}
esp_err_t esp_eth_phy_802_3_loopback(phy_802_3_t *phy_802_3, bool enable)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = phy_802_3->eth;
/* Set Loopback function */
bmcr_reg_t bmcr;
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
if (enable) {
bmcr.en_loopback = 1;
} else {
bmcr.en_loopback = 0;
}
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
return ESP_OK;
err:
return ret;
}
esp_err_t esp_eth_phy_802_3_set_speed(phy_802_3_t *phy_802_3, eth_speed_t speed)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = phy_802_3->eth;
/* Since the link is going to be reconfigured, consider it down to be status updated once the driver re-started */
phy_802_3->link_status = ETH_LINK_DOWN;
/* Set speed */
bmcr_reg_t bmcr;
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
bmcr.speed_select = speed == ETH_SPEED_100M ? 1 : 0;
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
return ESP_OK;
err:
return ret;
}
esp_err_t esp_eth_phy_802_3_set_duplex(phy_802_3_t *phy_802_3, eth_duplex_t duplex)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = phy_802_3->eth;
/* Since the link is going to be reconfigured, consider it down to be status updated once the driver re-started */
phy_802_3->link_status = ETH_LINK_DOWN;
/* Set duplex mode */
bmcr_reg_t bmcr;
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
if (bmcr.en_loopback) {
ESP_GOTO_ON_FALSE(duplex == ETH_DUPLEX_FULL, ESP_ERR_INVALID_STATE, err, TAG, "Duplex mode must be FULL for loopback operation");
}
bmcr.duplex_mode = duplex;
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
return ESP_OK;
err:
return ret;
}
esp_err_t esp_eth_phy_802_3_set_link(phy_802_3_t *phy_802_3, eth_link_t link)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = phy_802_3->eth;
if (phy_802_3->link_status != link) {
phy_802_3->link_status = link;
// link status changed, inmiedately report to upper layers
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)phy_802_3->link_status), err, TAG, "change link failed");
}
err:
return ret;
}
esp_err_t esp_eth_phy_802_3_init(phy_802_3_t *phy_802_3)
{
return esp_eth_phy_802_3_basic_phy_init(phy_802_3);
}
esp_err_t esp_eth_phy_802_3_deinit(phy_802_3_t *phy_802_3)
{
return esp_eth_phy_802_3_basic_phy_deinit(phy_802_3);
}
esp_err_t esp_eth_phy_802_3_del(phy_802_3_t *phy_802_3)
{
free(phy_802_3);
return ESP_OK;
}
esp_err_t esp_eth_phy_802_3_reset_hw(phy_802_3_t *phy_802_3, uint32_t reset_assert_us)
{
if (phy_802_3->reset_gpio_num >= 0) {
esp_rom_gpio_pad_select_gpio(phy_802_3->reset_gpio_num);
gpio_set_direction(phy_802_3->reset_gpio_num, GPIO_MODE_OUTPUT);
gpio_set_level(phy_802_3->reset_gpio_num, 0);
if (reset_assert_us < 10000) {
esp_rom_delay_us(reset_assert_us);
} else {
vTaskDelay(pdMS_TO_TICKS(reset_assert_us/1000));
}
gpio_set_level(phy_802_3->reset_gpio_num, 1);
}
return ESP_OK;
}
esp_err_t esp_eth_phy_802_3_detect_phy_addr(esp_eth_mediator_t *eth, int *detected_addr)
{
if (!eth || !detected_addr) {
ESP_LOGE(TAG, "eth and detected_addr can't be null");
return ESP_ERR_INVALID_ARG;
}
int addr_try = 0;
uint32_t reg_value = 0;
for (int i = 0; i < 3; i++){
for (addr_try = 0; addr_try < 32; addr_try++) {
eth->phy_reg_read(eth, addr_try, ETH_PHY_IDR1_REG_ADDR, &reg_value);
if (reg_value != 0xFFFF && reg_value != 0x00) {
*detected_addr = addr_try;
break;
}
}
if (addr_try < 32) {
ESP_LOGD(TAG, "Found PHY address: %d", addr_try);
return ESP_OK;
}
}
ESP_LOGE(TAG, "No PHY device detected");
return ESP_ERR_NOT_FOUND;
}
esp_err_t esp_eth_phy_802_3_basic_phy_init(phy_802_3_t *phy_802_3)
{
esp_err_t ret = ESP_OK;
// Detect PHY address
if (phy_802_3->addr == ESP_ETH_PHY_ADDR_AUTO) {
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_detect_phy_addr(phy_802_3->eth, &phy_802_3->addr), err, TAG, "Detect PHY address failed");
}
/* Power on Ethernet PHY */
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_pwrctl(phy_802_3, true), err, TAG, "power control failed");
/* Reset Ethernet PHY */
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_reset(phy_802_3), err, TAG, "reset failed");
return ESP_OK;
err:
return ret;
}
esp_err_t esp_eth_phy_802_3_basic_phy_deinit(phy_802_3_t *phy_802_3)
{
esp_err_t ret = ESP_OK;
/* Power off Ethernet PHY */
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_pwrctl(phy_802_3, false), err, TAG, "power control failed");
return ESP_OK;
err:
return ret;
}
esp_err_t esp_eth_phy_802_3_read_oui(phy_802_3_t *phy_802_3, uint32_t *oui)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = phy_802_3->eth;
phyidr1_reg_t id1;
phyidr2_reg_t id2;
ESP_GOTO_ON_FALSE(oui != NULL, ESP_ERR_INVALID_ARG, err, TAG, "oui can't be null");
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_IDR1_REG_ADDR, &(id1.val)), err, TAG, "read ID1 failed");
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_IDR2_REG_ADDR, &(id2.val)), err, TAG, "read ID2 failed");
*oui = (id1.oui_msb << 6) | id2.oui_lsb;
return ESP_OK;
err:
return ret;
}
esp_err_t esp_eth_phy_802_3_read_manufac_info(phy_802_3_t *phy_802_3, uint8_t *model, uint8_t *rev)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = phy_802_3->eth;
phyidr2_reg_t id2;
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_IDR2_REG_ADDR, &(id2.val)), err, TAG, "read ID2 failed");
if (model != NULL) {
*model = id2.vendor_model;
}
if (rev != NULL) {
*rev = id2.model_revision;
}
return ESP_OK;
err:
return ret;
}
esp_err_t esp_eth_phy_802_3_get_mmd_addr(phy_802_3_t *phy_802_3, uint8_t devaddr, uint16_t *mmd_addr)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = phy_802_3->eth;
ESP_GOTO_ON_FALSE(devaddr <= 31, ESP_ERR_INVALID_ARG, err, TAG, "MMD device address can not be greater then 31 (0x1F)");
mmdctrl_reg_t mmdctrl;
mmdad_reg_t mmdad;
mmdctrl.function = MMD_FUNC_ADDRESS;
mmdctrl.devaddr = devaddr;
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, phy_802_3->addr, ETH_PHY_MMDCTRL_REG_ADDR, mmdctrl.val), err, TAG, "write MMDCTRL failed");
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_MMDAD_REG_ADDR, &mmdad.val), err, TAG, "read MMDAD failed");
*mmd_addr = mmdad.adrdata;
return ESP_OK;
err:
return ret;
}
esp_err_t esp_eth_phy_802_3_set_mmd_addr(phy_802_3_t *phy_802_3, uint8_t devaddr, uint16_t mmd_addr)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = phy_802_3->eth;
ESP_GOTO_ON_FALSE(devaddr <= 31, ESP_ERR_INVALID_ARG, err, TAG, "MMD device address can not be greater then 31 (0x1F)");
mmdctrl_reg_t mmdctrl;
mmdad_reg_t mmdad;
mmdctrl.function = MMD_FUNC_ADDRESS;
mmdctrl.devaddr = devaddr;
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, phy_802_3->addr, ETH_PHY_MMDCTRL_REG_ADDR, mmdctrl.val), err, TAG, "write MMDCTRL failed");
mmdad.adrdata = mmd_addr;
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, phy_802_3->addr, ETH_PHY_MMDAD_REG_ADDR, mmdad.val), err, TAG, "write MMDAD failed");
return ESP_OK;
err:
return ret;
}
esp_err_t esp_eth_phy_802_3_read_mmd_data(phy_802_3_t *phy_802_3, uint8_t devaddr, esp_eth_phy_802_3_mmd_func_t function, uint32_t *data)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = phy_802_3->eth;
ESP_GOTO_ON_FALSE(devaddr <= 31, ESP_ERR_INVALID_ARG, err, TAG, "MMD device address can not be greater then 31 (0x1F)");
ESP_GOTO_ON_FALSE(function != MMD_FUNC_ADDRESS, ESP_ERR_INVALID_ARG, err, TAG, "Invalid MMD mode for accessing data");
mmdctrl_reg_t mmdctrl;
mmdad_reg_t mmdad;
mmdctrl.devaddr = devaddr;
mmdctrl.function = function;
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, phy_802_3->addr, ETH_PHY_MMDCTRL_REG_ADDR, mmdctrl.val), err, TAG, "write MMDCTRL failed");
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_MMDAD_REG_ADDR, &mmdad.val), err, TAG, "read MMDAD failed");
*data = mmdad.adrdata;
return ESP_OK;
err:
return ret;
}
esp_err_t esp_eth_phy_802_3_write_mmd_data(phy_802_3_t *phy_802_3, uint8_t devaddr, esp_eth_phy_802_3_mmd_func_t function, uint32_t data)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = phy_802_3->eth;
ESP_GOTO_ON_FALSE(devaddr <= 31, ESP_ERR_INVALID_ARG, err, TAG, "MMD device address can not be greater then 31 (0x1F)");
ESP_GOTO_ON_FALSE(function != MMD_FUNC_ADDRESS, ESP_ERR_INVALID_ARG, err, TAG, "Invalid MMD function for accessing data");
mmdctrl_reg_t mmdctrl;
mmdad_reg_t mmdad;
mmdctrl.devaddr = devaddr;
mmdctrl.function = function;
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, phy_802_3->addr, ETH_PHY_MMDCTRL_REG_ADDR, mmdctrl.val), err, TAG, "write MMDCTRL failed");
mmdad.adrdata = data;
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, phy_802_3->addr, ETH_PHY_MMDAD_REG_ADDR, mmdad.val), err, TAG, "read MMDAD failed");
return ESP_OK;
err:
return ret;
}
esp_err_t esp_eth_phy_802_3_read_mmd_register(phy_802_3_t *phy_802_3, uint8_t devaddr, uint16_t mmd_addr, uint32_t *data){
esp_err_t ret = ESP_OK;
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_set_mmd_addr(phy_802_3, devaddr, mmd_addr), err, TAG, "Set MMD address failed");
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_mmd_data(phy_802_3, devaddr, MMD_FUNC_DATA_NOINCR, data), err, TAG, "Read MMD data failed");
return ESP_OK;
err:
return ret;
}
esp_err_t esp_eth_phy_802_3_write_mmd_register(phy_802_3_t *phy_802_3, uint8_t devaddr, uint16_t mmd_addr, uint32_t data){
esp_err_t ret = ESP_OK;
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_set_mmd_addr(phy_802_3, devaddr, mmd_addr), err, TAG, "Set MMD address failed");
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_write_mmd_data(phy_802_3, devaddr, MMD_FUNC_DATA_NOINCR, data), err, TAG, "Write MMD data failed");
return ESP_OK;
err:
return ret;
}
esp_err_t esp_eth_phy_802_3_obj_config_init(phy_802_3_t *phy_802_3, const eth_phy_config_t *config)
{
esp_err_t ret = ESP_OK;
ESP_GOTO_ON_FALSE(config, ESP_ERR_INVALID_ARG, err, TAG, "can't set phy config to null");
phy_802_3->link_status = ETH_LINK_DOWN;
phy_802_3->addr = config->phy_addr;
phy_802_3->reset_timeout_ms = config->reset_timeout_ms;
phy_802_3->reset_gpio_num = config->reset_gpio_num;
phy_802_3->autonego_timeout_ms = config->autonego_timeout_ms;
phy_802_3->parent.reset = reset;
phy_802_3->parent.reset_hw = reset_hw_default;
phy_802_3->parent.init = init;
phy_802_3->parent.deinit = deinit;
phy_802_3->parent.set_mediator = set_mediator;
phy_802_3->parent.autonego_ctrl = autonego_ctrl;
phy_802_3->parent.pwrctl = pwrctl;
phy_802_3->parent.get_addr = get_addr;
phy_802_3->parent.set_addr = set_addr;
phy_802_3->parent.advertise_pause_ability = advertise_pause_ability;
phy_802_3->parent.loopback = loopback;
phy_802_3->parent.set_speed = set_speed;
phy_802_3->parent.set_duplex = set_duplex;
phy_802_3->parent.del = del;
phy_802_3->parent.set_link = set_link;
phy_802_3->parent.get_link = NULL;
phy_802_3->parent.custom_ioctl = NULL;
err:
return ret;
}
components/esp_eth/src/phy/esp_eth_phy_dp83848.c
+195
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@@ -0,0 +1,195 @@
/*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <stdlib.h>
#include <sys/cdefs.h>
#include "esp_log.h"
#include "esp_check.h"
#include "esp_eth_phy_802_3.h"
static const char *TAG = "dp83848";
/***************Vendor Specific Register***************/
/**
* @brief PHYSTS(PHY Status Register)
*
*/
typedef union {
struct {
uint32_t link_status : 1; /* Link Status */
uint32_t speed_status : 1; /* Speed Status */
uint32_t duplex_status : 1; /* Duplex Status */
uint32_t loopback_status : 1; /* MII Loopback */
uint32_t auto_nego_complete : 1; /* Auto-Negotiation Complete */
uint32_t jabber_detect : 1; /* Jabber Detect */
uint32_t remote_fault : 1; /* Remote Fault */
uint32_t mii_interrupt : 1; /* MII Interrupt Pending */
uint32_t page_received : 1; /* Link Code Word Page Received */
uint32_t descrambler_lock : 1; /* Descrambler Lock */
uint32_t signal_detect : 1; /* Signal Detect */
uint32_t false_carrier_sense_latch : 1; /* False Carrier Sense Latch */
uint32_t polarity_status : 1; /* Polarity Status */
uint32_t receive_error_latch : 1; /* Receive Error Latch */
uint32_t mdix_mode : 1; /* MDI-X mode reported by auto-negotiation */
uint32_t reserved : 1; /* Reserved */
};
uint32_t val;
} physts_reg_t;
#define ETH_PHY_STS_REG_ADDR (0x10)
/**
* @brief PHYCR(PHY Control Register)
*
*/
typedef union {
struct {
uint32_t phy_addr : 5; /* PHY Address */
uint32_t led_cfg : 2; /* LED Configuration Modes */
uint32_t bypass_led_stretching : 1; /* Bypass LED Stretching */
uint32_t bist_start : 1; /* BIST Start */
uint32_t bist_status : 1; /* BIST Test Status */
uint32_t psr_15 : 1; /* BIST Sequence select */
uint32_t bist_force_error : 1; /* BIST Force Error */
uint32_t pause_trans_negotiate : 1; /* Pause Transmit Negotiated Status */
uint32_t pause_receive_negotiat : 1; /* Pause Receive Negotiated Status */
uint32_t force_mdix : 1; /* Force MDIX */
uint32_t en_auto_mdix : 1; /* Auto-MDIX Enable */
};
uint32_t val;
} phycr_reg_t;
#define ETH_PHY_CR_REG_ADDR (0x19)
typedef struct {
phy_802_3_t phy_802_3;
} phy_dp83848_t;
static esp_err_t dp83848_update_link_duplex_speed(phy_dp83848_t *dp83848)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = dp83848->phy_802_3.eth;
uint32_t addr = dp83848->phy_802_3.addr;
eth_speed_t speed = ETH_SPEED_10M;
eth_duplex_t duplex = ETH_DUPLEX_HALF;
uint32_t peer_pause_ability = false;
anlpar_reg_t anlpar;
physts_reg_t physts;
bmsr_reg_t bmsr;
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
eth_link_t link = bmsr.link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
/* check if link status changed */
if (dp83848->phy_802_3.link_status != link) {
/* when link up, read negotiation result */
if (link == ETH_LINK_UP) {
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_ANLPAR_REG_ADDR, &(anlpar.val)), err, TAG, "read ANLPAR failed");
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_STS_REG_ADDR, &(physts.val)), err, TAG, "read PHYSTS failed");
if (physts.speed_status) {
speed = ETH_SPEED_10M;
} else {
speed = ETH_SPEED_100M;
}
if (physts.duplex_status) {
duplex = ETH_DUPLEX_FULL;
} else {
duplex = ETH_DUPLEX_HALF;
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed), err, TAG, "change speed failed");
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex), err, TAG, "change duplex failed");
/* if we're in duplex mode, and peer has the flow control ability */
if (duplex == ETH_DUPLEX_FULL && anlpar.symmetric_pause) {
peer_pause_ability = 1;
} else {
peer_pause_ability = 0;
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_PAUSE, (void *)peer_pause_ability), err, TAG, "change pause ability failed");
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link), err, TAG, "change link failed");
dp83848->phy_802_3.link_status = link;
}
return ESP_OK;
err:
return ret;
}
static esp_err_t dp83848_get_link(esp_eth_phy_t *phy)
{
esp_err_t ret = ESP_OK;
phy_dp83848_t *dp83848 = __containerof(esp_eth_phy_into_phy_802_3(phy), phy_dp83848_t, phy_802_3);
/* Update information about link, speed, duplex */
ESP_GOTO_ON_ERROR(dp83848_update_link_duplex_speed(dp83848), err, TAG, "update link duplex speed failed");
return ESP_OK;
err:
return ret;
}
static esp_err_t dp83848_autonego_ctrl(esp_eth_phy_t *phy, eth_phy_autoneg_cmd_t cmd, bool *autonego_en_stat)
{
esp_err_t ret = ESP_OK;
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
esp_eth_mediator_t *eth = phy_802_3->eth;
if (cmd == ESP_ETH_PHY_AUTONEGO_EN) {
bmcr_reg_t bmcr;
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
ESP_GOTO_ON_FALSE(bmcr.en_loopback == 0, ESP_ERR_INVALID_STATE, err, TAG, "Autonegotiation can't be enabled while in loopback operation");
}
return esp_eth_phy_802_3_autonego_ctrl(phy_802_3, cmd, autonego_en_stat);
err:
return ret;
}
static esp_err_t dp83848_loopback(esp_eth_phy_t *phy, bool enable)
{
esp_err_t ret = ESP_OK;
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
bool auto_nego_en = true;
ESP_GOTO_ON_ERROR(dp83848_autonego_ctrl(phy, ESP_ETH_PHY_AUTONEGO_G_STAT, &auto_nego_en), err, TAG, "get status of autonegotiation failed");
ESP_GOTO_ON_FALSE(!(auto_nego_en && enable), ESP_ERR_INVALID_STATE, err, TAG, "Unable to set loopback while autonegotiation is enabled. Disable it to use loopback");
return esp_eth_phy_802_3_loopback(phy_802_3, enable);
err:
return ret;
}
static esp_err_t dp83848_init(esp_eth_phy_t *phy)
{
esp_err_t ret = ESP_OK;
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
/* Basic PHY init */
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_basic_phy_init(phy_802_3), err, TAG, "failed to init PHY");
/* Check PHY ID */
uint32_t oui;
uint8_t model;
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_oui(phy_802_3, &oui), err, TAG, "read OUI failed");
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_manufac_info(phy_802_3, &model, NULL), err, TAG, "read manufacturer's info failed");
ESP_GOTO_ON_FALSE(oui == 0x80017 && model == 0x09, ESP_FAIL, err, TAG, "wrong chip ID");
return ESP_OK;
err:
return ret;
}
esp_eth_phy_t *esp_eth_phy_new_dp83848(const eth_phy_config_t *config)
{
esp_eth_phy_t *ret = NULL;
phy_dp83848_t *dp83848 = calloc(1, sizeof(phy_dp83848_t));
ESP_GOTO_ON_FALSE(dp83848, NULL, err, TAG, "calloc dp83848 failed");
ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&dp83848->phy_802_3, config) == ESP_OK,
NULL, err, TAG, "configuration initialization of PHY 802.3 failed");
// redefine functions which need to be customized for sake of dp83848
dp83848->phy_802_3.parent.init = dp83848_init;
dp83848->phy_802_3.parent.get_link = dp83848_get_link;
dp83848->phy_802_3.parent.autonego_ctrl = dp83848_autonego_ctrl;
dp83848->phy_802_3.parent.loopback = dp83848_loopback;
return &dp83848->phy_802_3.parent;
err:
if (dp83848 != NULL) {
free(dp83848);
}
return ret;
}
components/esp_eth/src/phy/esp_eth_phy_ip101.c
+223
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/*
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <stdlib.h>
#include <sys/cdefs.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_log.h"
#include "esp_check.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_eth_phy_802_3.h"
static const char *TAG = "ip101";
#define IP101_PHY_RESET_ASSERTION_TIME_US 10000
#define IP101_PHY_POST_RESET_INIT_TIME_MS 10
/***************Vendor Specific Register***************/
/**
* @brief PCR(Page Control Register)
*
*/
typedef union {
struct {
uint32_t register_page_select : 5; /* Select register page, default is 16 */
uint32_t reserved : 11; /* Reserved */
};
uint32_t val;
} pcr_reg_t;
#define ETH_PHY_PCR_REG_ADDR (0x14)
/**
* @brief ISR(Interrupt Status Register), Page 16
*
*/
typedef union {
struct {
uint32_t link_changed : 1; /* Flag to indicate link status change interrupt */
uint32_t duplex_changed : 1; /* Flag to indicate duplex change interrupt */
uint32_t speed_changed : 1; /* Flag to indicate speed change interrupt */
uint32_t intr_status : 1; /* Flag to indicate interrupt status */
uint32_t reserved1 : 4; /* Reserved */
uint32_t link_mask : 1; /* Mask link change interrupt */
uint32_t duplex_mask : 1; /* Mask duplex change interrupt */
uint32_t speed_mask : 1; /* Mask speed change interrupt */
uint32_t all_mask : 1; /* Mask all interrupt */
uint32_t reserved2 : 3; /* Reserved */
uint32_t use_intr_pin : 1; /* Set high to use INTR and INTR_32 as an interrupt pin */
};
uint32_t val;
} isr_reg_t;
#define ETH_PHY_ISR_REG_ADDR (0x11)
/**
* @brief PHY MDI/MDIX Control and Specific Status Register, Page 16
*
*/
typedef union {
struct {
uint32_t op_mode : 3; /* Operation Mode Indicator */
uint32_t force_mdix : 1; /* Force the MDIX channel to be selected */
uint32_t reserved1 : 4; /* Reserved */
uint32_t link_up : 1; /* Indicate the link status is OK or FAIL */
uint32_t reserved2 : 7; /* Reserved */
};
uint32_t val;
} cssr_reg_t;
#define ETH_PHY_CSSR_REG_ADDR (0x1E)
/**
* @brief PSCR(PHY Specific Control Register), Page 1
*
*/
typedef union {
struct {
uint32_t reserved1 : 7; /* Reserved */
uint32_t force_link_100 : 1; /* Force Link 100 */
uint32_t force_link_10 : 1; /* Force Link 10 */
uint32_t reserved2 : 7; /* Reserved */
};
uint32_t val;
} pscr_reg_t;
#define ETH_PHY_PSCR_REG_ADDR (0x11)
typedef struct {
phy_802_3_t phy_802_3;
} phy_ip101_t;
static esp_err_t ip101_page_select(phy_ip101_t *ip101, uint32_t page)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = ip101->phy_802_3.eth;
pcr_reg_t pcr = {
.register_page_select = page
};
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, ip101->phy_802_3.addr, ETH_PHY_PCR_REG_ADDR, pcr.val), err, TAG, "write PCR failed");
return ESP_OK;
err:
return ret;
}
static esp_err_t ip101_update_link_duplex_speed(phy_ip101_t *ip101)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = ip101->phy_802_3.eth;
uint32_t addr = ip101->phy_802_3.addr;
eth_speed_t speed = ETH_SPEED_10M;
eth_duplex_t duplex = ETH_DUPLEX_HALF;
uint32_t peer_pause_ability = false;
cssr_reg_t cssr;
anlpar_reg_t anlpar;
ESP_GOTO_ON_ERROR(ip101_page_select(ip101, 16), err, TAG, "select page 16 failed");
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_CSSR_REG_ADDR, &(cssr.val)), err, TAG, "read CSSR failed");
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_ANLPAR_REG_ADDR, &(anlpar.val)), err, TAG, "read ANLPAR failed");
eth_link_t link = cssr.link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
/* check if link status changed */
if (ip101->phy_802_3.link_status != link) {
/* when link up, read negotiation result */
if (link == ETH_LINK_UP) {
switch (cssr.op_mode) {
case 1: //10M Half
speed = ETH_SPEED_10M;
duplex = ETH_DUPLEX_HALF;
break;
case 2: //100M Half
speed = ETH_SPEED_100M;
duplex = ETH_DUPLEX_HALF;
break;
case 5: //10M Full
speed = ETH_SPEED_10M;
duplex = ETH_DUPLEX_FULL;
break;
case 6: //100M Full
speed = ETH_SPEED_100M;
duplex = ETH_DUPLEX_FULL;
break;
default:
break;
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed), err, TAG, "change speed failed");
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex), err, TAG, "change duplex failed");
/* if we're in duplex mode, and peer has the flow control ability */
if (duplex == ETH_DUPLEX_FULL && anlpar.symmetric_pause) {
peer_pause_ability = 1;
} else {
peer_pause_ability = 0;
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_PAUSE, (void *)peer_pause_ability), err, TAG, "change pause ability failed");
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link), err, TAG, "change link failed");
ip101->phy_802_3.link_status = link;
}
return ESP_OK;
err:
return ret;
}
static esp_err_t ip101_get_link(esp_eth_phy_t *phy)
{
esp_err_t ret = ESP_OK;
phy_ip101_t *ip101 = __containerof(esp_eth_phy_into_phy_802_3(phy), phy_ip101_t, phy_802_3);
/* Update information about link, speed, duplex */
ESP_GOTO_ON_ERROR(ip101_update_link_duplex_speed(ip101), err, TAG, "update link duplex speed failed");
return ESP_OK;
err:
return ret;
}
static esp_err_t ip101_reset_hw(esp_eth_phy_t *phy)
{
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
esp_err_t ret = esp_eth_phy_802_3_reset_hw(phy_802_3, IP101_PHY_RESET_ASSERTION_TIME_US);
vTaskDelay(pdMS_TO_TICKS(IP101_PHY_POST_RESET_INIT_TIME_MS));
return ret;
}
static esp_err_t ip101_init(esp_eth_phy_t *phy)
{
esp_err_t ret = ESP_OK;
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
/* Basic PHY init */
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_basic_phy_init(phy_802_3), err, TAG, "failed to init PHY");
/* Check PHY ID */
uint32_t oui;
uint8_t model;
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_oui(phy_802_3, &oui), err, TAG, "read OUI failed");
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_manufac_info(phy_802_3, &model, NULL), err, TAG, "read manufacturer's info failed");
ESP_GOTO_ON_FALSE(oui == 0x90C3 && model == 0x5, ESP_FAIL, err, TAG, "wrong chip ID");
return ESP_OK;
err:
return ret;
}
esp_eth_phy_t *esp_eth_phy_new_ip101(const eth_phy_config_t *config)
{
esp_eth_phy_t *ret = NULL;
phy_ip101_t *ip101 = calloc(1, sizeof(phy_ip101_t));
ESP_GOTO_ON_FALSE(ip101, NULL, err, TAG, "calloc ip101 failed");
ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&ip101->phy_802_3, config) == ESP_OK,
NULL, err, TAG, "configuration initialization of PHY 802.3 failed");
// redefine functions which need to be customized for sake of IP101
ip101->phy_802_3.parent.init = ip101_init;
ip101->phy_802_3.parent.get_link = ip101_get_link;
ip101->phy_802_3.parent.reset_hw = ip101_reset_hw;
return &ip101->phy_802_3.parent;
err:
if (ip101 != NULL) {
free(ip101);
}
return ret;
}
components/esp_eth/src/phy/esp_eth_phy_ksz80xx.c
+219
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@@ -0,0 +1,219 @@
/*
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <stdlib.h>
#include <sys/cdefs.h>
#include <inttypes.h>
#include "esp_log.h"
#include "esp_check.h"
#include "esp_eth_phy_802_3.h"
#define KSZ80XX_PHY_ID_MSB (0x22)
#define KSZ80XX_PHY_ID_LSB (0x05)
#define KSZ80XX_PHY_OUI (KSZ80XX_PHY_ID_MSB << 6 | KSZ80XX_PHY_ID_LSB)
#define KSZ80XX_PC1R_REG_ADDR (0x1E)
#define KSZ80XX_PC2R_REG_ADDR (0x1F)
typedef enum
{
KSZ80XX_MODEL_NUMBER_11 = 0x11, // KSZ8041
KSZ80XX_MODEL_NUMBER_13 = 0x13, // KSZ8041RLNI
KSZ80XX_MODEL_NUMBER_15 = 0x15, // KSZ8021/31
KSZ80XX_MODEL_NUMBER_16 = 0x16, // KSZ8051/81/91
KSZ80XX_MODEL_NUMBER_17 = 0x17, // KSZ8061
KSZ80XX_MODEL_NUMBER_21 = 0x21, // KSZ8001
} ksz80xx_model_number_t;
typedef struct
{
phy_802_3_t phy_802_3;
uint8_t model_number;
uint32_t op_mode_reg;
uint32_t op_mode_offset;
} phy_ksz80xx_t;
static const uint8_t supported_model_numbers[] =
{
KSZ80XX_MODEL_NUMBER_11,
KSZ80XX_MODEL_NUMBER_13,
KSZ80XX_MODEL_NUMBER_15,
KSZ80XX_MODEL_NUMBER_16,
KSZ80XX_MODEL_NUMBER_17,
KSZ80XX_MODEL_NUMBER_21,
};
static const char *model_names[] = {
"41", // models with model number 0x11
"41RLNI", // models with model number 0x13
"21/31", // models with model number 0x15
"51/81/91", // models with model number 0x16
"61", // models with model number 0x17
"01", // models with model number 0x21
};
static const char *TAG = "ksz80xx";
static esp_err_t ksz80xx_update_link_duplex_speed(phy_ksz80xx_t * ksz80xx)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = ksz80xx->phy_802_3.eth;
uint32_t addr = ksz80xx->phy_802_3.addr;
eth_speed_t speed = ETH_SPEED_10M;
eth_duplex_t duplex = ETH_DUPLEX_HALF;
uint32_t peer_pause_ability = false;
anlpar_reg_t anlpar;
bmsr_reg_t bmsr;
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_ANLPAR_REG_ADDR, &(anlpar.val)), err, TAG, "read ANLPAR failed");
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
eth_link_t link = bmsr.link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
/* check if link status changed */
if (ksz80xx->phy_802_3.link_status != link) {
/* when link up, read negotiation result */
if (link == ETH_LINK_UP) {
uint32_t reg_value = 0;
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ksz80xx->op_mode_reg, &reg_value), err, TAG, "read %#04" PRIx32 " failed", ksz80xx->op_mode_reg);
uint8_t op_mode = (reg_value >> ksz80xx->op_mode_offset) & 0x07;
switch (op_mode) {
case 1: //10Base-T half-duplex
speed = ETH_SPEED_10M;
duplex = ETH_DUPLEX_HALF;
break;
case 2: //100Base-TX half-duplex
speed = ETH_SPEED_100M;
duplex = ETH_DUPLEX_HALF;
break;
case 5: //10Base-T full-duplex
speed = ETH_SPEED_10M;
duplex = ETH_DUPLEX_FULL;
break;
case 6: //100Base-TX full-duplex
speed = ETH_SPEED_100M;
duplex = ETH_DUPLEX_FULL;
break;
default:
break;
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed), err, TAG, "change speed failed");
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex), err, TAG, "change duplex failed");
/* if we're in duplex mode, and peer has the flow control ability */
if (duplex == ETH_DUPLEX_FULL && anlpar.symmetric_pause) {
peer_pause_ability = 1;
} else {
peer_pause_ability = 0;
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_PAUSE, (void *)peer_pause_ability), err, TAG, "change pause ability failed");
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link), err, TAG, "change link failed");
ksz80xx->phy_802_3.link_status = link;
}
return ESP_OK;
err:
return ret;
}
static esp_err_t ksz80xx_get_link(esp_eth_phy_t *phy)
{
esp_err_t ret = ESP_OK;
phy_ksz80xx_t *ksz80xx = __containerof(esp_eth_phy_into_phy_802_3(phy), phy_ksz80xx_t, phy_802_3);
/* Update information about link, speed, duplex */
ESP_GOTO_ON_ERROR(ksz80xx_update_link_duplex_speed(ksz80xx), err, TAG, "update link duplex speed failed");
return ESP_OK;
err:
return ret;
}
static bool ksz80xx_init_model(phy_ksz80xx_t *ksz80xx)
{
// set variables for op_mode access
switch (ksz80xx->model_number) {
case KSZ80XX_MODEL_NUMBER_21: // models KSZ8001
case KSZ80XX_MODEL_NUMBER_11: // models KSZ8041
case KSZ80XX_MODEL_NUMBER_13: // models KSZ8041RLNI
ksz80xx->op_mode_reg = KSZ80XX_PC2R_REG_ADDR;
ksz80xx->op_mode_offset = 2; // bits 4:2
break;
case KSZ80XX_MODEL_NUMBER_15: // models KSZ8021/31
case KSZ80XX_MODEL_NUMBER_16: // models KSZ8051/81/91
case KSZ80XX_MODEL_NUMBER_17: // models KSZ8061
ksz80xx->op_mode_reg = KSZ80XX_PC1R_REG_ADDR;
ksz80xx->op_mode_offset = 0; // bits 2:0
break;
default:
return false;
}
return true;
}
static esp_err_t ksz80xx_init(esp_eth_phy_t *phy)
{
esp_err_t ret = ESP_OK;
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
phy_ksz80xx_t *ksz80xx = __containerof(phy_802_3, phy_ksz80xx_t, phy_802_3);
/* Basic PHY init */
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_basic_phy_init(phy_802_3), err, TAG, "failed to init PHY");
/* Check PHY ID */
uint32_t oui;
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_oui(phy_802_3, &oui), err, TAG, "read OUI failed");
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_manufac_info(phy_802_3, &ksz80xx->model_number, NULL), err, TAG, "read manufacturer's info failed");
ESP_GOTO_ON_FALSE(oui == KSZ80XX_PHY_OUI, ESP_FAIL, err, TAG, "wrong chip ID");
const char* supported_model_name = NULL;
for (size_t i = 0; i < sizeof(supported_model_numbers); i++) {
if (ksz80xx->model_number == supported_model_numbers[i]) {
supported_model_name = model_names[i];
break;
}
}
ESP_GOTO_ON_FALSE(supported_model_name != NULL && ksz80xx_init_model(ksz80xx), ESP_FAIL, err, TAG, "unsupported model number: %#04" PRIx8, ksz80xx->model_number);
ESP_LOGI(TAG, "auto detected phy KSZ80%s", supported_model_name);
return ESP_OK;
err:
return ret;
}
static esp_err_t ksz80xx_set_speed(esp_eth_phy_t *phy, eth_speed_t speed)
{
esp_err_t ret = ESP_OK;
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
esp_eth_mediator_t *eth = phy_802_3->eth;
/* Check if loopback is enabled, and if so, can it work with proposed speed or not */
bmcr_reg_t bmcr;
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
if (bmcr.en_loopback) {
ESP_GOTO_ON_FALSE(speed == ETH_SPEED_100M, ESP_ERR_INVALID_STATE, err, TAG, "Speed must be 100M for loopback operation");
}
return esp_eth_phy_802_3_set_speed(phy_802_3, speed);
err:
return ret;
}
esp_eth_phy_t *esp_eth_phy_new_ksz80xx(const eth_phy_config_t *config)
{
esp_eth_phy_t *ret = NULL;
phy_ksz80xx_t *ksz80xx = calloc(1, sizeof(phy_ksz80xx_t));
ESP_GOTO_ON_FALSE(ksz80xx, NULL, err, TAG, "calloc ksz80xx failed");
ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&ksz80xx->phy_802_3, config) == ESP_OK,
NULL, err, TAG, "configuration initialization of PHY 802.3 failed");
// redefine functions which need to be customized for sake of ksz80xx
ksz80xx->phy_802_3.parent.init = ksz80xx_init;
ksz80xx->phy_802_3.parent.get_link = ksz80xx_get_link;
ksz80xx->phy_802_3.parent.set_speed = ksz80xx_set_speed;
return &ksz80xx->phy_802_3.parent;
err:
if (ksz80xx != NULL) {
free(ksz80xx);
}
return ret;
}
components/esp_eth/src/phy/esp_eth_phy_lan87xx.c
+386
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@@ -0,0 +1,386 @@
/*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <stdlib.h>
#include <sys/cdefs.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_log.h"
#include "esp_check.h"
#include "esp_eth_phy_802_3.h"
static const char *TAG = "lan87xx";
/***************List of Supported Models***************/
// See Microchip's Application Note AN25.3 summarizing differences among below models
#define LAN8710A_MODEL_NUM 0x0F
#define LAN8720A_MODEL_NUM 0x0F
#define LAN8740A_MODEL_NUM 0x11
#define LAN8741A_MODEL_NUM 0x12
#define LAN8742A_MODEL_NUM 0x13
static const uint8_t supported_models[] = {
LAN8710A_MODEL_NUM,
#if (LAN8710A_MODEL_NUM != LAN8720A_MODEL_NUM)
LAN8720A_MODEL_NUM,
#endif
LAN8740A_MODEL_NUM,
LAN8741A_MODEL_NUM,
LAN8742A_MODEL_NUM
};
/***************Vendor Specific Register***************/
/**
* @brief MCSR(Mode Control Status Register)
*
*/
typedef union {
struct {
uint32_t reserved1 : 1; /* Reserved */
uint32_t energy_is_on : 1; /* Energy is On */
uint32_t reserved2 : 4; /* Reserved */
uint32_t en_alternate_interrupt : 1; /* Enable Alternate Interrupt Mode */
uint32_t reserved3 : 2; /* Reserved */
uint32_t en_far_loopback : 1; /* Enable Far Loopback Mode */
uint32_t reserved4 : 3; /* Reserved */
uint32_t en_energy_detect_powerdown : 1; /* Enable Energy Detect Power Down */
uint32_t reserved5 : 2; /* Reserved */
};
uint32_t val;
} mcsr_reg_t;
#define ETH_PHY_MCSR_REG_ADDR (0x11)
/**
* @brief SMR(Special Modes Register)
*
*/
typedef union {
struct {
uint32_t phy_addr : 5; /* PHY Address */
uint32_t mode : 3; /* Transceiver Mode of Operation */
uint32_t reserved_1 : 6; /* Reserved */
uint32_t mii_mode : 1; /* Mode of the digital interface (only LAN8710A/LAN8740A/LAN8741A) */
uint32_t reserved_2 : 1; /* Reserved */
};
uint32_t val;
} smr_reg_t;
#define ETH_PHY_SMR_REG_ADDR (0x12)
/**
* @brief Time Domain Reflectometry Patterns/Delay Control Register
* Only available in LAN8740A/LAN8742A
*/
typedef union {
struct {
uint32_t tdr_pattern_low : 6; /* Data pattern sent in TDR mode for the low cycle */
uint32_t tdr_pattern_high : 6; /* Data pattern sent in TDR mode for the high cycle */
uint32_t tdr_line_break_counter : 3; /* Increments of 256ms of break time */
uint32_t tdr_delay_in : 1; /* Line break counter used */
};
uint32_t val;
} tdr_pattern_reg_t;
#define EHT_PHY_TDRPD_REG_ADDR (0x18)
/**
* @brief Time Domain Reflectometry Control/Status Register)
* Only available in LAN8740A/LAN8742A
*/
typedef union {
struct {
uint32_t tdr_channel_length : 8; /* TDR channel length */
uint32_t tdr_channel_status : 1; /* TDR channel status */
uint32_t tdr_channel_cable_type : 2; /* TDR channel cable type */
uint32_t reserved : 3; /* Reserved */
uint32_t tdr_a2d_filter_enable: 1; /* Analog to Digital Filter Enabled */
uint32_t tdr_enable : 1; /* Enable TDR */
};
uint32_t val;
} tdr_control_reg_t;
#define EHT_PHY_TDRC_REG_ADDR (0x19)
/**
* @brief SECR(Symbol Error Counter Register)
*
*/
typedef union {
struct {
uint32_t symbol_err_count : 16; /* Symbol Error Counter */
};
uint32_t val;
} secr_reg_t;
#define EHT_PHY_SECR_REG_ADDR (0x1A)
/**
* @brief CSIR(Control Status Indications Register)
*
*/
typedef union {
struct {
uint32_t reserved1 : 4; /* Reserved */
uint32_t base10_t_polarity : 1; /* Polarity State of 10Base-T */
uint32_t reserved2 : 6; /* Reserved */
uint32_t dis_sqe : 1; /* Disable SQE test(Heartbeat) */
uint32_t reserved3 : 1; /* Reserved */
uint32_t select_channel : 1; /* Manual channel select:MDI(0) or MDIX(1) */
uint32_t reserved4 : 1; /* Reserved */
uint32_t auto_mdix_ctrl : 1; /* Auto-MDIX Control: EN(0) or DE(1) */
};
uint32_t val;
} scsir_reg_t;
#define ETH_PHY_CSIR_REG_ADDR (0x1B)
/**
* @brief Cable Length Register
* Only available in LAN8740A/LAN8742A
*/
typedef union {
struct {
uint32_t reserved : 12; /* Reserved */
uint32_t cable_length : 4; /* Cable length */
};
uint32_t val;
} cbln_reg_t;
#define EHT_PHY_CBLN_REG_ADDR (0x1C)
/**
* @brief ISR(Interrupt Source Register)
*
*/
typedef union {
struct {
uint32_t reserved1 : 1; /* Reserved */
uint32_t auto_nego_page_received : 1; /* Auto-Negotiation Page Received */
uint32_t parallel_detect_fault : 1; /* Parallel Detection Fault */
uint32_t auto_nego_lp_acknowledge : 1; /* Auto-Negotiation LP Acknowledge */
uint32_t link_down : 1; /* Link Down */
uint32_t remote_fault_detect : 1; /* Remote Fault Detect */
uint32_t auto_nego_complete : 1; /* Auto-Negotiation Complete */
uint32_t energy_on_generate : 1; /* ENERGY ON generated */
uint32_t wake_on_lan : 1; /* Wake on Lan (WOL) event detected (only LAN8740A/LAN8742A) */
uint32_t reserved2 : 7; /* Reserved */
};
uint32_t val;
} isfr_reg_t;
#define ETH_PHY_ISR_REG_ADDR (0x1D)
/**
* @brief IMR(Interrupt Mask Register)
*
*/
typedef union {
struct {
uint32_t reserved1 : 1; /* Reserved */
uint32_t auto_nego_page_received : 1; /* Auto-Negotiation Page Received */
uint32_t parallel_detect_fault : 1; /* Parallel Detection Fault */
uint32_t auto_nego_lp_acknowledge : 1; /* Auto-Negotiation LP Acknowledge */
uint32_t link_down : 1; /* Link Down */
uint32_t remote_fault_detect : 1; /* Remote Fault Detect */
uint32_t auto_nego_complete : 1; /* Auto-Negotiation Complete */
uint32_t energy_on_generate : 1; /* ENERGY ON generated */
uint32_t wake_on_lan : 1; /* Wake on Lan (WOL) event detected (only LAN8740A/LAN8742A) */
uint32_t reserved2 : 7; /* Reserved */
};
uint32_t val;
} imr_reg_t;
#define ETH_PHY_IMR_REG_ADDR (0x1E)
/**
* @brief PSCSR(PHY Special Control Status Register)
*
*/
typedef union {
struct {
uint32_t reserved1 : 2; /* Reserved */
uint32_t speed_indication : 3; /* Speed Indication */
uint32_t reserved2 : 1; /* Reserved */
uint32_t enable_4b5b : 1; /* Enable 4B5B encoder (only LAN8740A/LAN8741A) */
uint32_t reserved3 : 5; /* Reserved */
uint32_t auto_nego_done : 1; /* Auto Negotiation Done */
uint32_t reserved4 : 3; /* Reserved */
};
uint32_t val;
} pscsr_reg_t;
#define ETH_PHY_PSCSR_REG_ADDR (0x1F)
typedef struct {
phy_802_3_t phy_802_3;
} phy_lan87xx_t;
static esp_err_t lan87xx_update_link_duplex_speed(phy_lan87xx_t *lan87xx)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = lan87xx->phy_802_3.eth;
uint32_t addr = lan87xx->phy_802_3.addr;
eth_speed_t speed = ETH_SPEED_10M;
eth_duplex_t duplex = ETH_DUPLEX_HALF;
bmsr_reg_t bmsr;
bmcr_reg_t bmcr;
pscsr_reg_t pscsr;
uint32_t peer_pause_ability = false;
anlpar_reg_t anlpar;
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_ANLPAR_REG_ADDR, &(anlpar.val)), err, TAG, "read ANLPAR failed");
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
/* link status is forced up because LAN87xx reports link down when loopback is enabled and cable is unplugged */
eth_link_t link;
if(bmcr.en_loopback) {
link = ETH_LINK_UP;
} else {
link = bmsr.link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
}
/* check if link status changed */
if (lan87xx->phy_802_3.link_status != link) {
/* when link up, read negotiation result */
if (link == ETH_LINK_UP) {
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_PSCSR_REG_ADDR, &(pscsr.val)), err, TAG, "read PSCSR failed");
switch (pscsr.speed_indication) {
case 1: //10Base-T half-duplex
speed = ETH_SPEED_10M;
duplex = ETH_DUPLEX_HALF;
break;
case 2: //100Base-TX half-duplex
speed = ETH_SPEED_100M;
duplex = ETH_DUPLEX_HALF;
break;
case 5: //10Base-T full-duplex
speed = ETH_SPEED_10M;
duplex = ETH_DUPLEX_FULL;
break;
case 6: //100Base-TX full-duplex
speed = ETH_SPEED_100M;
duplex = ETH_DUPLEX_FULL;
break;
default:
break;
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed), err, TAG, "change speed failed");
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex), err, TAG, "change duplex failed");
/* if we're in duplex mode, and peer has the flow control ability */
if (duplex == ETH_DUPLEX_FULL && anlpar.symmetric_pause) {
peer_pause_ability = 1;
} else {
peer_pause_ability = 0;
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_PAUSE, (void *)peer_pause_ability), err, TAG, "change pause ability failed");
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link), err, TAG, "change link failed");
lan87xx->phy_802_3.link_status = link;
}
return ESP_OK;
err:
return ret;
}
static esp_err_t lan87xx_get_link(esp_eth_phy_t *phy)
{
esp_err_t ret = ESP_OK;
phy_lan87xx_t *lan87xx = __containerof(esp_eth_phy_into_phy_802_3(phy), phy_lan87xx_t, phy_802_3);
/* Updata information about link, speed, duplex */
ESP_GOTO_ON_ERROR(lan87xx_update_link_duplex_speed(lan87xx), err, TAG, "update link duplex speed failed");
return ESP_OK;
err:
return ret;
}
static esp_err_t lan87xx_reset_hw(esp_eth_phy_t *phy)
{
/* It was observed that assert nRST signal on LAN87xx needs to be a little longer than the minimum specified in datasheet */
return esp_eth_phy_802_3_reset_hw(esp_eth_phy_into_phy_802_3(phy), 150);
}
static esp_err_t lan87xx_autonego_ctrl(esp_eth_phy_t *phy, eth_phy_autoneg_cmd_t cmd, bool *autonego_en_stat)
{
esp_err_t ret = ESP_OK;
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
esp_eth_mediator_t *eth = phy_802_3->eth;
if (cmd == ESP_ETH_PHY_AUTONEGO_EN) {
bmcr_reg_t bmcr;
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
ESP_GOTO_ON_FALSE(bmcr.en_loopback == 0, ESP_ERR_INVALID_STATE, err, TAG, "Autonegotiation can't be enabled while in loopback operation");
}
return esp_eth_phy_802_3_autonego_ctrl(phy_802_3, cmd, autonego_en_stat);
err:
return ret;
}
static esp_err_t lan87xx_loopback(esp_eth_phy_t *phy, bool enable)
{
esp_err_t ret = ESP_OK;
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
bool auto_nego_en;
ESP_GOTO_ON_ERROR(lan87xx_autonego_ctrl(phy, ESP_ETH_PHY_AUTONEGO_G_STAT, &auto_nego_en), err, TAG, "get status of autonegotiation failed");
ESP_GOTO_ON_FALSE(!(auto_nego_en && enable), ESP_ERR_INVALID_STATE, err, TAG, "Unable to set loopback while autonegotiation is enabled. Disable it to use loopback");
return esp_eth_phy_802_3_loopback(phy_802_3, enable);
err:
return ret;
}
static esp_err_t lan87xx_set_speed(esp_eth_phy_t *phy, eth_speed_t speed)
{
esp_err_t ret = ESP_OK;
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
/* It was observed that a delay needs to be introduced after setting speed and prior driver's start.
Otherwise, the very first read of PHY registers is not valid data (0xFFFF's). */
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_set_speed(phy_802_3, speed), err, TAG, "set speed failed");
vTaskDelay(pdMS_TO_TICKS(10));
err:
return ret;
}
static esp_err_t lan87xx_init(esp_eth_phy_t *phy)
{
esp_err_t ret = ESP_OK;
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
/* Basic PHY init */
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_basic_phy_init(phy_802_3), err, TAG, "failed to init PHY");
/* Check PHY ID */
uint32_t oui;
uint8_t model;
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_oui(phy_802_3, &oui), err, TAG, "read OUI failed");
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_manufac_info(phy_802_3, &model, NULL), err, TAG, "read manufacturer's info failed");
ESP_GOTO_ON_FALSE(oui == 0x1F0, ESP_FAIL, err, TAG, "wrong chip OUI");
bool supported_model = false;
for (unsigned int i = 0; i < sizeof(supported_models); i++) {
if (model == supported_models[i]) {
supported_model = true;
break;
}
}
ESP_GOTO_ON_FALSE(supported_model, ESP_FAIL, err, TAG, "unsupported chip model");
return ESP_OK;
err:
return ret;
}
esp_eth_phy_t *esp_eth_phy_new_lan87xx(const eth_phy_config_t *config)
{
esp_eth_phy_t *ret = NULL;
phy_lan87xx_t *lan87xx = calloc(1, sizeof(phy_lan87xx_t));
ESP_GOTO_ON_FALSE(lan87xx, NULL, err, TAG, "calloc lan87xx failed");
ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&lan87xx->phy_802_3, config) == ESP_OK,
NULL, err, TAG, "configuration initialization of PHY 802.3 failed");
// redefine functions which need to be customized for sake of LAN87xx
lan87xx->phy_802_3.parent.reset_hw = lan87xx_reset_hw;
lan87xx->phy_802_3.parent.init = lan87xx_init;
lan87xx->phy_802_3.parent.get_link = lan87xx_get_link;
lan87xx->phy_802_3.parent.autonego_ctrl = lan87xx_autonego_ctrl;
lan87xx->phy_802_3.parent.loopback = lan87xx_loopback;
lan87xx->phy_802_3.parent.set_speed = lan87xx_set_speed;
return &lan87xx->phy_802_3.parent;
err:
if (lan87xx != NULL) {
free(lan87xx);
}
return ret;
}
components/esp_eth/src/phy/esp_eth_phy_rtl8201.c
+202
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@@ -0,0 +1,202 @@
/*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <stdlib.h>
#include <sys/cdefs.h>
#include "esp_log.h"
#include "esp_check.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_eth_phy_802_3.h"
#define RTL8201_PHY_RESET_ASSERTION_TIME_US 10000
#define RTL8201_PHY_POST_RESET_INIT_TIME_MS 150
static const char *TAG = "rtl8201";
/***************Vendor Specific Register***************/
/**
* @brief PSMR(Power Saving Mode Register)
*
*/
typedef union {
struct {
uint16_t reserved : 15; /* Reserved */
uint16_t en_pwr_save : 1; /* Enable power saving mode */
};
uint16_t val;
} psmr_reg_t;
#define ETH_PHY_PSMR_REG_ADDR (0x18)
/**
* @brief PSR(Page Select Register)
*
*/
typedef union {
struct {
uint16_t page_select : 8; /* Select register page, default is 0 */
uint16_t reserved : 8; /* Reserved */
};
uint16_t val;
} psr_reg_t;
#define ETH_PHY_PSR_REG_ADDR (0x1F)
typedef struct {
phy_802_3_t phy_802_3;
} phy_rtl8201_t;
static esp_err_t rtl8201_page_select(phy_rtl8201_t *rtl8201, uint32_t page)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = rtl8201->phy_802_3.eth;
psr_reg_t psr = {
.page_select = page
};
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, rtl8201->phy_802_3.addr, ETH_PHY_PSR_REG_ADDR, psr.val), err, TAG, "write PSR failed");
return ESP_OK;
err:
return ret;
}
static esp_err_t rtl8201_update_link_duplex_speed(phy_rtl8201_t *rtl8201)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = rtl8201->phy_802_3.eth;
uint32_t addr = rtl8201->phy_802_3.addr;
eth_speed_t speed = ETH_SPEED_10M;
eth_duplex_t duplex = ETH_DUPLEX_HALF;
bmcr_reg_t bmcr;
bmsr_reg_t bmsr;
uint32_t peer_pause_ability = false;
anlpar_reg_t anlpar;
ESP_GOTO_ON_ERROR(rtl8201_page_select(rtl8201, 0), err, TAG, "select page 0 failed");
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_ANLPAR_REG_ADDR, &(anlpar.val)), err, TAG, "read ANLPAR failed");
eth_link_t link = bmsr.link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
/* check if link status changed */
if (rtl8201->phy_802_3.link_status != link) {
/* when link up, read negotiation result */
if (link == ETH_LINK_UP) {
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
if (bmcr.speed_select) {
speed = ETH_SPEED_100M;
} else {
speed = ETH_SPEED_10M;
}
if (bmcr.duplex_mode) {
duplex = ETH_DUPLEX_FULL;
} else {
duplex = ETH_DUPLEX_HALF;
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed), err, TAG, "change speed failed");
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex), err, TAG, "change duplex failed");
/* if we're in duplex mode, and peer has the flow control ability */
if (duplex == ETH_DUPLEX_FULL && anlpar.symmetric_pause) {
peer_pause_ability = 1;
} else {
peer_pause_ability = 0;
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_PAUSE, (void *)peer_pause_ability), err, TAG, "change pause ability failed");
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link), err, TAG, "change link failed");
rtl8201->phy_802_3.link_status = link;
}
return ESP_OK;
err:
return ret;
}
static esp_err_t rtl8201_get_link(esp_eth_phy_t *phy)
{
esp_err_t ret = ESP_OK;
phy_rtl8201_t *rtl8201 = __containerof(esp_eth_phy_into_phy_802_3(phy), phy_rtl8201_t, phy_802_3);
/* Updata information about link, speed, duplex */
ESP_GOTO_ON_ERROR(rtl8201_update_link_duplex_speed(rtl8201), err, TAG, "update link duplex speed failed");
return ESP_OK;
err:
return ret;
}
static esp_err_t rtl8201_autonego_ctrl(esp_eth_phy_t *phy, eth_phy_autoneg_cmd_t cmd, bool *autonego_en_stat)
{
esp_err_t ret = ESP_OK;
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
esp_eth_mediator_t *eth = phy_802_3->eth;
if (cmd == ESP_ETH_PHY_AUTONEGO_EN) {
bmcr_reg_t bmcr;
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
ESP_GOTO_ON_FALSE(bmcr.en_loopback == 0, ESP_ERR_INVALID_STATE, err, TAG, "Autonegotiation can't be enabled while in loopback operation");
}
return esp_eth_phy_802_3_autonego_ctrl(phy_802_3, cmd, autonego_en_stat);
err:
return ret;
}
static esp_err_t rtl8201_loopback(esp_eth_phy_t *phy, bool enable)
{
esp_err_t ret = ESP_OK;
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
bool auto_nego_en;
ESP_GOTO_ON_ERROR(rtl8201_autonego_ctrl(phy, ESP_ETH_PHY_AUTONEGO_G_STAT, &auto_nego_en), err, TAG, "get status of autonegotiation failed");
ESP_GOTO_ON_FALSE(!(auto_nego_en && enable), ESP_ERR_INVALID_STATE, err, TAG, "Unable to set loopback while autonegotiation is enabled. Disable it to use loopback");
return esp_eth_phy_802_3_loopback(phy_802_3, enable);
err:
return ret;
}
static esp_err_t rtl8201_reset_hw(esp_eth_phy_t *phy)
{
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
esp_err_t ret = esp_eth_phy_802_3_reset_hw(phy_802_3, RTL8201_PHY_RESET_ASSERTION_TIME_US);
vTaskDelay(pdMS_TO_TICKS(RTL8201_PHY_POST_RESET_INIT_TIME_MS));
return ret;
}
static esp_err_t rtl8201_init(esp_eth_phy_t *phy)
{
esp_err_t ret = ESP_OK;
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
/* Basic PHY init */
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_basic_phy_init(phy_802_3), err, TAG, "failed to init PHY");
/* Check PHY ID */
uint32_t oui;
uint8_t model;
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_oui(phy_802_3, &oui), err, TAG, "read OUI failed");
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_manufac_info(phy_802_3, &model, NULL), err, TAG, "read manufacturer's info failed");
ESP_GOTO_ON_FALSE(oui == 0x732 && model == 0x1, ESP_FAIL, err, TAG, "wrong chip ID");
return ESP_OK;
err:
return ret;
}
esp_eth_phy_t *esp_eth_phy_new_rtl8201(const eth_phy_config_t *config)
{
esp_eth_phy_t *ret = NULL;
phy_rtl8201_t *rtl8201 = calloc(1, sizeof(phy_rtl8201_t));
ESP_GOTO_ON_FALSE(rtl8201, NULL, err, TAG, "calloc rtl8201 failed");
ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&rtl8201->phy_802_3, config) == ESP_OK,
NULL, err, TAG, "configuration initialization of PHY 802.3 failed");
// redefine functions which need to be customized for sake of RTL8201
rtl8201->phy_802_3.parent.init = rtl8201_init;
rtl8201->phy_802_3.parent.get_link = rtl8201_get_link;
rtl8201->phy_802_3.parent.autonego_ctrl = rtl8201_autonego_ctrl;
rtl8201->phy_802_3.parent.loopback = rtl8201_loopback;
rtl8201->phy_802_3.parent.reset_hw = rtl8201_reset_hw;
return &rtl8201->phy_802_3.parent;
err:
if (rtl8201 != NULL) {
free(rtl8201);
}
return ret;
}