fix(bootloader_support): Reorder write protection bits of some shared security efuses
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@@ -44,7 +44,7 @@ esp_err_t esp_flash_encryption_enable_secure_features(void)
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esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
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#if defined(CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE) && defined(SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND)
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#if defined(CONFIG_SECURE_FLASH_PSEUDO_ROUND_FUNC)
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ESP_LOGI(TAG, "Enable XTS-AES pseudo rounds function...");
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uint8_t xts_pseudo_level = CONFIG_SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH;
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esp_efuse_write_field_blob(ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL, &xts_pseudo_level, ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[0]->bit_count);
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@@ -53,8 +53,6 @@ esp_err_t esp_secure_boot_enable_secure_features(void)
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esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_SHA384_EN);
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#endif
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esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_SECURE_BOOT_SHA384_EN);
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esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_EN);
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#ifndef CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS
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@@ -40,7 +40,7 @@ esp_err_t esp_flash_encryption_enable_secure_features(void)
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esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
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#if defined(CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE) && defined(SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND)
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#if defined(CONFIG_SECURE_FLASH_PSEUDO_ROUND_FUNC)
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ESP_LOGI(TAG, "Enable XTS-AES pseudo rounds function...");
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uint8_t xts_pseudo_level = CONFIG_SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH;
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esp_efuse_write_field_blob(ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL, &xts_pseudo_level, ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[0]->bit_count);
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@@ -36,7 +36,7 @@ esp_err_t esp_flash_encryption_enable_secure_features(void)
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esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
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#if defined(CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE) && defined(SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND)
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#if defined(CONFIG_SECURE_FLASH_PSEUDO_ROUND_FUNC)
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if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) {
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ESP_LOGI(TAG, "Enable XTS-AES pseudo rounds function...");
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uint8_t xts_pseudo_level = CONFIG_SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH;
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@@ -210,13 +210,6 @@ void esp_flash_encryption_set_release_mode(void)
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#endif // CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED
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#endif // !CONFIG_IDF_TARGET_ESP32
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#ifdef SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND
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if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) {
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uint8_t xts_pseudo_level = ESP_XTS_AES_PSEUDO_ROUNDS_LOW;
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esp_efuse_write_field_blob(ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL, &xts_pseudo_level, ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[0]->bit_count);
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}
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#endif
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#ifdef CONFIG_IDF_TARGET_ESP32
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esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_DIS_CACHE);
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#else
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@@ -429,6 +429,13 @@ bool esp_secure_boot_cfg_verify_release_mode(void)
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}
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#if SOC_ECDSA_SUPPORT_CURVE_P384
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#if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS
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secure = esp_efuse_read_field_bit(ESP_EFUSE_SECURE_BOOT_SHA384_EN);
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result &= secure;
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if (!secure) {
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ESP_LOGW(TAG, "Not enabled Secure Boot using SHA-384 mode (set SECURE_BOOT_SHA384_EN->1)");
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}
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#else
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/* When using Secure Boot with SHA-384, the efuse bit representing Secure Boot with SHA-384 would already be programmed.
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* But in the case of the existing Secure Boot V2 schemes using SHA-256, the efuse bit representing
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* Secure Boot with SHA-384 needs to be write-protected, so that an attacker cannot perform a denial-of-service
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@@ -439,6 +446,7 @@ bool esp_secure_boot_cfg_verify_release_mode(void)
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if (!secure) {
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ESP_LOGW(TAG, "Not write-protected secure boot using SHA-384 mode (set WR_DIS_SECURE_BOOT_SHA384_EN->1)");
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}
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#endif
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#endif
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secure = (num_keys != 0);
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