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feat(2ddma): ESP32P4 ECO5 2DDMA related updates

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Added one more pair of 2DDMA channels
Priority bit width increased corespondingly
Added three new CSC modes for RX channel 0
This commit is contained in:
Song Ruo Jing
2025-09-12 16:45:58 +08:00
parent a9b2bd1b72
commit e69eeb7355
14 changed files with 2227 additions and 10000 deletions
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components/esp_hw_support/test_apps/dma2d/main/test_dma2d.c
+1 -1
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@@ -22,7 +22,7 @@
// This tests the hardware capability of multiple 2D-DMA transactions running together, and the driver capbility of
// transactions being send to a queue, and waiting for free channels becoming available, and being picked to start the
// real hardware operation.
#define M2M_TRANS_TIMES (8)
#define M2M_TRANS_TIMES (12)
// Descriptor and buffer address and size should aligned to 64 bytes (the cacheline size alignment restriction) to be used by CPU