From e6accf792c1ab6b5a52ce65be9686313e7106f82 Mon Sep 17 00:00:00 2001 From: Jason2866 <24528715+Jason2866@users.noreply.github.com> Date: Wed, 12 Nov 2025 15:25:02 +0100 Subject: [PATCH] pioarduino changes --- .github/workflows/dangerjs.yml | 27 --- .github/workflows/release_zips.yml | 17 +- components/esp_eth/CMakeLists.txt | 3 +- components/esp_eth/include/esp_eth_phy.h | 11 ++ .../esp_eth/src/phy/esp_eth_phy_jl1101.c | 186 ++++++++++++++++++ components/esp_hw_support/mac_addr.c | 2 + .../esp_psram/esp32/esp_psram_impl_quad.c | 2 +- components/soc/esp32c2/include/soc/soc.h | 2 +- components/soc/esp32c3/include/soc/soc.h | 2 +- components/soc/esp32c6/include/soc/soc.h | 2 +- components/soc/esp32h2/include/soc/soc.h | 2 +- components/soc/esp32s2/include/soc/soc.h | 2 +- components/soc/esp32s3/include/soc/soc.h | 2 +- package.json | 27 +++ tools/cmake/build.cmake | 6 +- version.txt | 1 + 16 files changed, 247 insertions(+), 47 deletions(-) delete mode 100644 .github/workflows/dangerjs.yml create mode 100644 components/esp_eth/src/phy/esp_eth_phy_jl1101.c create mode 100644 package.json create mode 100644 version.txt diff --git a/.github/workflows/dangerjs.yml b/.github/workflows/dangerjs.yml deleted file mode 100644 index 07871a79a9..0000000000 --- a/.github/workflows/dangerjs.yml +++ /dev/null @@ -1,27 +0,0 @@ -name: DangerJS Pull Request review - -on: - pull_request_target: - types: [opened, edited, reopened, synchronize] - -permissions: - pull-requests: write - contents: write - -jobs: - pull-request-style-linter: - runs-on: ubuntu-latest - steps: - - name: Check out PR head - uses: actions/checkout@v4 - with: - ref: ${{ github.event.pull_request.head.sha }} - - - name: DangerJS pull request linter - uses: espressif/shared-github-dangerjs@v1 - env: - GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} - with: - instructions-gitlab-mirror: 'true' - instructions-contributions-file: 'CONTRIBUTING.md' - instructions-cla-link: 'https://cla-assistant.io/espressif/esp-idf' diff --git a/.github/workflows/release_zips.yml b/.github/workflows/release_zips.yml index bc2bf7b5c0..9d4be8aca6 100644 --- a/.github/workflows/release_zips.yml +++ b/.github/workflows/release_zips.yml @@ -1,4 +1,4 @@ -name: Create zip file with recursive source clone for release +name: Create tar.xz archive with recursive source clone for release on: push: @@ -7,12 +7,11 @@ on: jobs: release_zips: - name: Create release zip file - runs-on: ubuntu-24.04 + name: Create release tar.xz archive + runs-on: ubuntu-latest steps: - - name: Create a recursive clone source zip - uses: espressif/release-zips-action@v1 - with: - github_token: ${{ secrets.GITHUB_TOKEN }} - release_project_name: ESP-IDF - git_extra_args: --shallow-since="1 year ago" + - name: Create a recursive clone source and stripped archive + uses: Jason2866/github-actions/release_zips@tar_xz + env: + RELEASE_PROJECT_NAME: ESP-IDF + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} diff --git a/components/esp_eth/CMakeLists.txt b/components/esp_eth/CMakeLists.txt index 6a6941397d..696ed43242 100644 --- a/components/esp_eth/CMakeLists.txt +++ b/components/esp_eth/CMakeLists.txt @@ -35,7 +35,8 @@ if(CONFIG_ETH_ENABLED) "src/phy/esp_eth_phy_ip101.c" "src/phy/esp_eth_phy_ksz80xx.c" "src/phy/esp_eth_phy_lan87xx.c" - "src/phy/esp_eth_phy_rtl8201.c") + "src/phy/esp_eth_phy_rtl8201.c" + "src/phy/esp_eth_phy_jl1101.c") endif() if(CONFIG_ETH_SPI_ETHERNET_DM9051) diff --git a/components/esp_eth/include/esp_eth_phy.h b/components/esp_eth/include/esp_eth_phy.h index 109a8014dc..d551c6270a 100644 --- a/components/esp_eth/include/esp_eth_phy.h +++ b/components/esp_eth/include/esp_eth_phy.h @@ -374,6 +374,17 @@ esp_eth_phy_t *esp_eth_phy_new_dp83848(const eth_phy_config_t *config); */ esp_eth_phy_t *esp_eth_phy_new_ksz80xx(const eth_phy_config_t *config); +/** +* @brief Create a PHY instance of JL1101 +* +* @param[in] config: configuration of PHY +* +* @return +* - instance: create PHY instance successfully +* - NULL: create PHY instance failed because some error occurred +*/ +esp_eth_phy_t *esp_eth_phy_new_jl1101(const eth_phy_config_t *config); + #if CONFIG_ETH_SPI_ETHERNET_DM9051 /** * @brief Create a PHY instance of DM9051 diff --git a/components/esp_eth/src/phy/esp_eth_phy_jl1101.c b/components/esp_eth/src/phy/esp_eth_phy_jl1101.c new file mode 100644 index 0000000000..512e5fe024 --- /dev/null +++ b/components/esp_eth/src/phy/esp_eth_phy_jl1101.c @@ -0,0 +1,186 @@ +/* + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include "esp_log.h" +#include "esp_check.h" +#include "esp_eth_phy_802_3.h" + +static const char *TAG = "jl1101"; + +/***************Vendor Specific Register***************/ + +/** + * @brief PSMR(Power Saving Mode Register) + * + */ +typedef union { + struct { + uint16_t reserved : 15; /* Reserved */ + uint16_t en_pwr_save : 1; /* Enable power saving mode */ + }; + uint16_t val; +} psmr_reg_t; + +/** + * @brief PSR(Page Select Register) + * + */ +typedef union { + struct { + uint16_t page_select : 8; /* Select register page, default is 0 */ + uint16_t reserved : 8; /* Reserved */ + }; + uint16_t val; +} psr_reg_t; +#define ETH_PHY_PSR_REG_ADDR (0x1F) + +typedef struct { + phy_802_3_t phy_802_3; +} phy_jl1101_t; + +static esp_err_t jl1101_page_select(phy_jl1101_t *jl1101, uint32_t page) +{ + esp_err_t ret = ESP_OK; + esp_eth_mediator_t *eth = jl1101->phy_802_3.eth; + psr_reg_t psr = { + .page_select = page + }; + ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, jl1101->phy_802_3.addr, ETH_PHY_PSR_REG_ADDR, psr.val), err, TAG, "write PSR failed"); + return ESP_OK; +err: + return ret; +} + +static esp_err_t jl1101_update_link_duplex_speed(phy_jl1101_t *jl1101) +{ + esp_err_t ret = ESP_OK; + esp_eth_mediator_t *eth = jl1101->phy_802_3.eth; + uint32_t addr = jl1101->phy_802_3.addr; + eth_speed_t speed = ETH_SPEED_10M; + eth_duplex_t duplex = ETH_DUPLEX_HALF; + bmcr_reg_t bmcr; + bmsr_reg_t bmsr; + uint32_t peer_pause_ability = false; + anlpar_reg_t anlpar; + ESP_GOTO_ON_ERROR(jl1101_page_select(jl1101, 0), err, TAG, "select page 0 failed"); + ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed"); + ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_ANLPAR_REG_ADDR, &(anlpar.val)), err, TAG, "read ANLPAR failed"); + eth_link_t link = bmsr.link_status ? ETH_LINK_UP : ETH_LINK_DOWN; + /* check if link status changed */ + if (jl1101->phy_802_3.link_status != link) { + /* when link up, read negotiation result */ + if (link == ETH_LINK_UP) { + ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed"); + if (bmcr.speed_select) { + speed = ETH_SPEED_100M; + } else { + speed = ETH_SPEED_10M; + } + if (bmcr.duplex_mode) { + duplex = ETH_DUPLEX_FULL; + } else { + duplex = ETH_DUPLEX_HALF; + } + ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed), err, TAG, "change speed failed"); + ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex), err, TAG, "change duplex failed"); + /* if we're in duplex mode, and peer has the flow control ability */ + if (duplex == ETH_DUPLEX_FULL && anlpar.symmetric_pause) { + peer_pause_ability = 1; + } else { + peer_pause_ability = 0; + } + ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_PAUSE, (void *)peer_pause_ability), err, TAG, "change pause ability failed"); + } + ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link), err, TAG, "change link failed"); + jl1101->phy_802_3.link_status = link; + } + return ESP_OK; +err: + return ret; +} + +static esp_err_t jl1101_get_link(esp_eth_phy_t *phy) +{ + esp_err_t ret = ESP_OK; + phy_jl1101_t *jl1101 = __containerof(esp_eth_phy_into_phy_802_3(phy), phy_jl1101_t, phy_802_3); + /* Updata information about link, speed, duplex */ + ESP_GOTO_ON_ERROR(jl1101_update_link_duplex_speed(jl1101), err, TAG, "update link duplex speed failed"); + return ESP_OK; +err: + return ret; +} + +static esp_err_t jl1101_autonego_ctrl(esp_eth_phy_t *phy, eth_phy_autoneg_cmd_t cmd, bool *autonego_en_stat) +{ + esp_err_t ret = ESP_OK; + phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy); + esp_eth_mediator_t *eth = phy_802_3->eth; + if (cmd == ESP_ETH_PHY_AUTONEGO_EN) { + bmcr_reg_t bmcr; + ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed"); + ESP_GOTO_ON_FALSE(bmcr.en_loopback == 0, ESP_ERR_INVALID_STATE, err, TAG, "Autonegotiation can't be enabled while in loopback operation"); + } + return esp_eth_phy_802_3_autonego_ctrl(phy_802_3, cmd, autonego_en_stat); +err: + return ret; +} + +static esp_err_t jl1101_loopback(esp_eth_phy_t *phy, bool enable) +{ + esp_err_t ret = ESP_OK; + phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy); + bool auto_nego_en; + ESP_GOTO_ON_ERROR(jl1101_autonego_ctrl(phy, ESP_ETH_PHY_AUTONEGO_G_STAT, &auto_nego_en), err, TAG, "get status of autonegotiation failed"); + ESP_GOTO_ON_FALSE(!(auto_nego_en && enable), ESP_ERR_INVALID_STATE, err, TAG, "Unable to set loopback while autonegotiation is enabled. Disable it to use loopback"); + return esp_eth_phy_802_3_loopback(phy_802_3, enable); +err: + return ret; +} + +static esp_err_t jl1101_init(esp_eth_phy_t *phy) +{ + esp_err_t ret = ESP_OK; + phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy); + + /* Basic PHY init */ + ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_basic_phy_init(phy_802_3), err, TAG, "failed to init PHY"); + + /* Check PHY ID */ + uint32_t oui; + uint8_t model; + ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_oui(phy_802_3, &oui), err, TAG, "read OUI failed"); + ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_manufac_info(phy_802_3, &model, NULL), err, TAG, "read manufacturer's info failed"); + ESP_GOTO_ON_FALSE(oui == 0x24DF10 && model == 0x2, ESP_FAIL, err, TAG, "wrong chip ID"); + + return ESP_OK; +err: + return ret; +} + +esp_eth_phy_t *esp_eth_phy_new_jl1101(const eth_phy_config_t *config) +{ + esp_eth_phy_t *ret = NULL; + phy_jl1101_t *jl1101 = calloc(1, sizeof(phy_jl1101_t)); + ESP_GOTO_ON_FALSE(jl1101, NULL, err, TAG, "calloc jl1101 failed"); + ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&jl1101->phy_802_3, config) == ESP_OK, + NULL, err, TAG, "configuration initialization of PHY 802.3 failed"); + + // redefine functions which need to be customized for sake of jl1101 + jl1101->phy_802_3.parent.init = jl1101_init; + jl1101->phy_802_3.parent.get_link = jl1101_get_link; + jl1101->phy_802_3.parent.autonego_ctrl = jl1101_autonego_ctrl; + jl1101->phy_802_3.parent.loopback = jl1101_loopback; + + return &jl1101->phy_802_3.parent; +err: + if (jl1101 != NULL) { + free(jl1101); + } + return ret; +} diff --git a/components/esp_hw_support/mac_addr.c b/components/esp_hw_support/mac_addr.c index 6059a92aaf..ac72aea9df 100644 --- a/components/esp_hw_support/mac_addr.c +++ b/components/esp_hw_support/mac_addr.c @@ -287,6 +287,8 @@ static esp_err_t get_efuse_factory_mac(uint8_t *mac) uint32_t mac_low = ((uint32_t)mac[2] << 24) | ((uint32_t)mac[3] << 16) | ((uint32_t)mac[4] << 8) | mac[5]; if (((mac_high & 0xFFFF) == 0x18fe) && (mac_low >= 0x346a85c7) && (mac_low <= 0x346a85f8)) { return ESP_OK; + } else if (esp_efuse_get_pkg_ver() == 3) { + return ESP_OK; // override for Xiaomi SOC's and maybe others too } else { ESP_LOGE(TAG, "Base MAC address from BLK0 of EFUSE CRC error, efuse_crc = 0x%02x; calc_crc = 0x%02x", efuse_crc, calc_crc); #ifdef CONFIG_ESP_MAC_IGNORE_MAC_CRC_ERROR diff --git a/components/esp_psram/esp32/esp_psram_impl_quad.c b/components/esp_psram/esp32/esp_psram_impl_quad.c index 6a4f643c17..d2a8ec5674 100644 --- a/components/esp_psram/esp32/esp_psram_impl_quad.c +++ b/components/esp_psram/esp32/esp_psram_impl_quad.c @@ -905,7 +905,7 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(void) //psram init psram_io.psram_cs_io = D0WDR2_V3_PSRAM_CS_IO; } else { ESP_EARLY_LOGE(TAG, "Not a valid or known package id: %" PRIu32, pkg_ver); - abort(); + return ESP_FAIL; } s_psram_cs_io = psram_io.psram_cs_io; diff --git a/components/soc/esp32c2/include/soc/soc.h b/components/soc/esp32c2/include/soc/soc.h index a1d7b8fa47..1140edb80c 100644 --- a/components/soc/esp32c2/include/soc/soc.h +++ b/components/soc/esp32c2/include/soc/soc.h @@ -29,7 +29,7 @@ #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) -#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI +#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (DR_REG_SPI0_BASE - ((i) * 0x1000))) // only one GPSPI #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) //Registers Operation {{ diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index 1b47dd70fb..4a288847cc 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -23,7 +23,7 @@ #define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C3 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) -#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI +#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (DR_REG_SPI0_BASE - ((i) * 0x1000))) // only one GPSPI #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) //Registers Operation {{ diff --git a/components/soc/esp32c6/include/soc/soc.h b/components/soc/esp32c6/include/soc/soc.h index afd44da86c..77e2273fa5 100644 --- a/components/soc/esp32c6/include/soc/soc.h +++ b/components/soc/esp32c6/include/soc/soc.h @@ -23,7 +23,7 @@ #define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C6 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 -#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C6 +#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (DR_REG_SPI0_BASE - ((i) * 0x1000))) // only one GPSPI on C6 #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C6 #define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C6 #define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1 diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index b35b9cc15f..36d5f9a06e 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -23,7 +23,7 @@ #define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on H2 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) -#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI +#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (i - 2) * 0x1000) // only one GPSPI #define REG_I2C_BASE(i) (DR_REG_I2C_EXT0_BASE + (i) * 0x1000) //Registers Operation {{ diff --git a/components/soc/esp32s2/include/soc/soc.h b/components/soc/esp32s2/include/soc/soc.h index 1c2a5becaf..2103310c87 100644 --- a/components/soc/esp32s2/include/soc/soc.h +++ b/components/soc/esp32s2/include/soc/soc.h @@ -25,7 +25,7 @@ #define REG_I2S_BASE( i ) (DR_REG_I2S_BASE) #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) -#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3 +#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (((i)>3) ? (((i-2)* 0x1000) + 0x10000) : ((i - 2)* 0x1000 ))) // GPSPI2 and GPSPI3 #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) //Convenient way to replace the register ops when ulp riscv projects diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index 1955df7db0..519a1f1804 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -33,7 +33,7 @@ #define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000) #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) -#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3 +#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (DR_REG_SPI0_BASE - ((i) * 0x1000))) // GPSPI2 and GPSPI3 #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) //Convenient way to replace the register ops when ulp riscv projects diff --git a/package.json b/package.json new file mode 100644 index 0000000000..42a461a597 --- /dev/null +++ b/package.json @@ -0,0 +1,27 @@ +{ + "name": "framework-espidf", + "version": "3.50501", + "description": "Espressif IoT Development Framework", + "keywords": [ + "framework", + "esp32", + "esp32s2", + "esp32s3", + "esp32c2", + "esp32c3", + "esp32c5", + "esp32c6", + "esp32c61", + "esp32h2", + "esp32h21", + "esp32h4", + "esp32p4", + "espressif" + ], + "homepage": "https://docs.espressif.com/projects/esp-idf/en/latest/esp32/", + "license": "Apache-2.0", + "repository": { + "type": "git", + "url": "https://github.com/espressif/esp-idf" + } +} diff --git a/tools/cmake/build.cmake b/tools/cmake/build.cmake index 6f77a72278..5e5328c02c 100644 --- a/tools/cmake/build.cmake +++ b/tools/cmake/build.cmake @@ -129,13 +129,13 @@ function(__build_set_default_build_specifications) list(APPEND compile_options "-ffunction-sections" "-fdata-sections" # warning-related flags - "-Wall" - "-Werror" + # "-Wall" + # "-Werror" "-Wno-error=unused-function" "-Wno-error=unused-variable" "-Wno-error=unused-but-set-variable" "-Wno-error=deprecated-declarations" - "-Wextra" + # "-Wextra" "-Wno-error=extra" "-Wno-unused-parameter" "-Wno-sign-compare" diff --git a/version.txt b/version.txt new file mode 100644 index 0000000000..062be9b7f8 --- /dev/null +++ b/version.txt @@ -0,0 +1 @@ +5.5.1.251106