diff --git a/components/hal/esp32p4/include/hal/psram_ctrlr_ll.h b/components/hal/esp32p4/include/hal/psram_ctrlr_ll.h
index 7579bd674e..5858406bfb 100644
--- a/components/hal/esp32p4/include/hal/psram_ctrlr_ll.h
+++ b/components/hal/esp32p4/include/hal/psram_ctrlr_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,6 +17,7 @@
 #include <sys/param.h>
 #include "hal/assert.h"
 #include "hal/misc.h"
+#include "hal/config.h"
 #include "soc/spi_mem_s_struct.h"
 #include "soc/spi_mem_s_reg.h"
 #include "soc/spi1_mem_s_reg.h"
@@ -256,6 +257,52 @@ static inline void psram_ctrlr_ll_enable_axi_access(uint32_t mspi_id, bool en)
     SPIMEM2.mem_cache_fctrl.close_axi_inf_en = !en;
 }
 
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+/**
+ * @brief Enable PSRAM AXI weight arbiter for TX / RX AXI requests
+ *
+ * @param mspi_id      mspi_id
+ * @param en           enable / disable
+ */
+__attribute__((always_inline))
+static inline void psram_ctrlr_ll_enable_axi_req_weight_arbiter(uint32_t mspi_id, bool en)
+{
+    (void)mspi_id;
+    SPIMEM2.mem_cache_fctrl.mem_arb_wei_en = en;
+}
+
+/**
+ * @brief Set PSRAM AXI request weight
+ *
+ * @param mspi_id      mspi_id
+ * @param rd_weight    read weight
+ * @param wr_weight    write weight
+ */
+__attribute__((always_inline))
+static inline void psram_ctrlr_ll_set_axi_req_weight(uint32_t mspi_id, uint32_t rd_weight, uint32_t wr_weight)
+{
+    //1~15
+    HAL_ASSERT(rd_weight && rd_weight < 16);
+    HAL_ASSERT(wr_weight && wr_weight < 16);
+
+    SPIMEM2.mem_cache_fctrl.mem_arb_req0_wei = rd_weight;
+    SPIMEM2.mem_cache_fctrl.mem_arb_req1_wei = wr_weight;
+}
+
+/**
+ * @brief Set PSRAM AXI request priority
+ *
+ * @param mspi_id      mspi_id
+ * @param rd_prio      read priority
+ * @param wr_prio      write priority
+ */
+static inline void psram_ctrlr_ll_set_axi_req_priority(uint32_t mspi_id, uint32_t rd_prio, uint32_t wr_prio)
+{
+    SPIMEM2.mem_cache_fctrl.mem_arb_req0_pri = rd_prio;
+    SPIMEM2.mem_cache_fctrl.mem_arb_req1_pri = wr_prio;
+}
+#endif
+
 /**
  * @brief Enable PSRAM write splice transfer
  *