feature(spi_flash): Promote the c61 mspi clock frequency from 40 to 80M

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c

@@ -24,6 +24,7 @@
 #include "hal/mmu_ll.h"
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
+#include "hal/mspi_timing_tuning_ll.h"
 
 static const char *TAG __attribute__((unused))  = "boot.esp32c61";
 
@@ -197,6 +198,13 @@ static void bootloader_spi_flash_resume(void)
 
 esp_err_t bootloader_init_spi_flash(void)
 {
+
+    // Set source mspi pll clock as 80M in bootloader stage.
+    // SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz
+    // in this stage, set divider as 6
+    mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
+    mspi_ll_fast_set_hs_divider(6);
+
     bootloader_init_flash_configure();
     bootloader_spi_flash_resume();
     bootloader_flash_unlock();