feat(spi_flash): implement dynamic CPU frequency switching workaround for encrypted writes

This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency
normally, while automatically reducing CPU frequency during encrypted flash writes to
ensure correct operation. The frequency limit is chip revision dependent:
- v1.2 and above: limited to 160MHz during encrypted writes
- v1.0 and below: limited to 80MHz during encrypted writes

Key implementation details:
- Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called
- Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer
- Works with both PM enabled and disabled configurations
- Frequency is automatically restored after encrypted write completes
- For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when
  CPU frequency is reduced to 80MHz
- SPI1 timing registers are configured during frequency switching since encrypted writes
  use SPI1 and must work correctly at reduced CPU frequencies

Code improvements:
- Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks
- Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of
  hardcoded macros
- Add comprehensive test cases covering various PM configurations and edge cases

This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance
while maintaining reliable encrypted flash write functionality.

components/spi_flash/include/esp_private/spi_flash_freq_limit_cbs.h

@@ -0,0 +1,49 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "sdkconfig.h"
+#include "esp_flash.h"
+#include "esp_attr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if CONFIG_SPI_FLASH_FREQ_LIMIT_C5_240MHZ
+/**
+ * @brief Callback to limit CPU frequency for flash encryption writes (ESP32-C5 only, 240MHz)
+ *
+ * This function limits CPU frequency to <= 160MHz during encrypted flash writes.
+ * It should be called before starting an encrypted flash write operation.
+ *
+ * @note This is an internal function, not exposed to users.
+ * @note This function is placed in IRAM (implementation uses IRAM_ATTR).
+ * @note This function is called from spi_flash_os_func_app.c::spi1_start() after cache
+ *       and scheduler locks are acquired. As a result, there is no concurrency concern
+ *       and no need for internal locking or reference counting.
+ */
+void esp_flash_freq_limit_cb(void);
+
+/**
+ * @brief Callback to unlimit CPU frequency after flash encryption writes (ESP32-C5 only, 240MHz)
+ *
+ * This function restores the CPU frequency after an encrypted flash write operation.
+ * It should be called after completing an encrypted flash write operation.
+ *
+ * @note This is an internal function, not exposed to users.
+ * @note This function is placed in IRAM (implementation uses IRAM_ATTR).
+ * @note This function is called from spi_flash_os_func_app.c::spi1_end() before cache
+ *       and scheduler locks are released. As a result, there is no concurrency concern
+ *       and no need for internal locking or reference counting.
+ */
+void esp_flash_freq_unlimit_cb(void);
+#endif // CONFIG_SPI_FLASH_FREQ_LIMIT_C5_240MHZ
+
+#ifdef __cplusplus
+}
+#endif