980e8289a1
refactor(tests): add missing sdkconfig files in the driver test
2026-01-07 10:18:58 +08:00
46ae86b4cf
fix(cache): fixed cache sync ops concurrent call issue
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Closes https://github.com/espressif/esp-idf/issues/18023
2025-12-25 09:57:57 +08:00
27f1484774
test(esp_flash): fixed test config that c5 not support 120MHz
2025-12-17 12:16:55 +08:00
faf6cc4f84
feat(spi_flash): implement dynamic CPU frequency switching workaround for encrypted writes
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This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency
normally, while automatically reducing CPU frequency during encrypted flash writes to
ensure correct operation. The frequency limit is chip revision dependent:
- v1.2 and above: limited to 160MHz during encrypted writes
- v1.0 and below: limited to 80MHz during encrypted writes
Key implementation details:
- Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called
- Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer
- Works with both PM enabled and disabled configurations
- Frequency is automatically restored after encrypted write completes
- For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when
CPU frequency is reduced to 80MHz
- SPI1 timing registers are configured during frequency switching since encrypted writes
use SPI1 and must work correctly at reduced CPU frequencies
Code improvements:
- Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks
- Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of
hardcoded macros
- Add comprehensive test cases covering various PM configurations and edge cases
This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance
while maintaining reliable encrypted flash write functionality.
2025-12-17 03:33:29 +08:00
9ab736cbd1
fix(spi_flash): limit CPU clock to 160MHz for encrypted flash writes
2025-12-17 03:33:29 +08:00
8d5ae41df3
feat(spi_flash): Support flash suspend on esp32p4 resivion 3
2025-10-22 19:31:16 +08:00
695f8e46d6
Merge branch 'fix/make_bootloader_flash_size_correct_v5.5' into 'release/v5.5'
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fix(bootloader_flash): Make bootloader flash size accurate , etc. (backport v5.5)
See merge request espressif/esp-idf!41706
2025-10-20 14:21:40 +08:00
1bbffc5998
fix(spi_flash): Fix spi flash qio/dio read failed on gpspi flash
2025-10-14 17:45:29 +08:00
4016917f28
fix(spi_flash): Fix spi_flash clock for gpspi on esp32c5/p4
2025-10-14 17:45:29 +08:00
ff1c10e385
refactor(spi_flash): Refactor gpspi flash for making it's clock accurate
2025-10-14 17:45:29 +08:00
e6d4eec507
feat(p4): p4 rev3 real chip support
2025-10-13 15:25:23 +08:00
cfe8d1fb66
feat(spi_flash): Add support for gd55f flash chip
2025-07-30 17:31:16 +08:00
536a807665
Merge branch 'bugfix/esp_flash_escape_checking_v5.5' into 'release/v5.5'
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fix(esp_flash): fixed issue of escaping boundary check (v5.5)
See merge request espressif/esp-idf!40117
2025-07-22 17:16:49 +08:00
3c39b32195
Chip/support esp32c61 v5.5
2025-07-22 12:21:36 +08:00
da939fa729
fix(esp_flash): fixed issue of escaping boundary check
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Also patched corresponding ROM functions
2025-06-25 01:35:21 +08:00
62d4115e08
docs: Fix some typos
2025-04-30 18:35:39 +08:00
e65efb9156
Merge branch 'test/enable_xip_mmap_cases' into 'master'
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fix(mmap): fixed cache2phys and phy2cache not patched when XIP on PSRAM
Closes IDF-10983
See merge request espressif/esp-idf!33629
2025-04-16 15:30:23 +08:00
e97b1a8b51
fix(mmap): fixed cache2phys and phy2cache not patched when XIP on PSRAM
2025-04-11 11:02:11 +08:00
477af3b4a8
ci(mmap): enable mmap and XIP related cases for c5
2025-04-11 11:02:11 +08:00
15fa7843ae
refactor(spi_flash): Add spi_flash driver list linked check
2025-04-10 15:36:11 +08:00
da316111c9
Merge branch 'fix/fix_l2_cache_miss_issue' into 'master'
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cache: fixed l2 cache suspended/frozen but l1cache triggers l2 writeback issue
Closes IDF-12717
See merge request espressif/esp-idf!37967
2025-04-03 19:50:26 +08:00
8994f8fe70
feat(spi_flash): add support gpspi ext_flash
2025-04-03 11:27:13 +08:00
46be72437b
fix(cache): fixed l2 cache suspended/frozen but l1cache triggers l2 writeback issue
2025-04-02 18:03:43 +08:00
c3a3cc8657
Merge branch 'feat/h4_enable_ci_build' into 'master'
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feat(esp32h4): enable ESP32H4 ci build
Closes IDF-12332
See merge request espressif/esp-idf!37921
2025-03-31 23:49:48 +08:00
1785e1d329
refactor(flash): spilt flash cap in esp_rom
2025-03-28 15:04:25 +08:00
b38ac5ad82
feat(uart): add uart_detect_bitrate_bps API for data line bitrate measurement
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Closes https://github.com/espressif/esp-idf/issues/14721
2025-03-28 15:03:19 +08:00
6c4271d4bb
feat(esp32h4): disable unsupported build
2025-03-28 14:41:29 +08:00
c34b4eb882
feat(esp32h4): enable ESP32H4 ci build
2025-03-28 14:41:28 +08:00
64ff6ec274
Merge branch 'fix/mutex_between_oct_flash_and_flash_rom_impl' into 'master'
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flash: mutex between oct flash and flash rom impl
See merge request espressif/esp-idf!37760
2025-03-21 14:51:08 +08:00
ee5042095b
Merge branch 'refactor/psram_structure_refactor' into 'master'
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refactor(psram): cleanup psram component code structure
See merge request espressif/esp-idf!37870
2025-03-21 00:52:03 +08:00
9b845f9f8b
fix(flash): mutex between flash rom impl and flash opi
2025-03-20 15:32:21 +08:00
ac8cfadab0
refactor(psram): cleanup psram component code structure
2025-03-20 15:17:01 +08:00
45ba78940f
feat(esp32h4): finnal introduce hello world
2025-03-19 18:48:41 +08:00
cbcee1625f
refactor(flash): rename SOC_SPI_MEM_SUPPORT_OPI_MODE to SOC_SPI_MEM_SUPPORT_FLASH_OPI_MOD
2025-03-19 14:01:22 +08:00
9aba44a2d9
test(spi_flash): Flash suspend test evolution
2025-03-11 16:21:07 +08:00
6c3d67b234
fix(spi_flash): Add suspend check on esp32c6 and esp32h2 for some reason
2025-03-11 11:11:39 +08:00
ae50c71222
fix(spi_flash): Return false directly in suspend caps check
2025-03-11 11:11:39 +08:00
d64ca3a5d1
fix(mspi): fixed cpu and mspi freq mismatch issue when in dfs/sleep on p4
2025-03-07 12:27:16 +08:00
daf2d31008
test: format all test scripts
2025-03-05 12:08:48 +08:00
add27dfbd3
fix(spi_flash): Fix flash encryption write verify,
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Closes https://github.com/espressif/esp-idf/issues/15380
2025-02-28 15:57:24 +08:00
b66e140fbc
refactor(spi_flash): optimize flash functions to save iram memory
2025-02-26 18:28:49 +08:00
53d8b70e8b
fix(gpio): fix IO output enable control
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oen_sel and oen_inv_sel fields from func_out_sel_cfg register
2025-02-20 19:49:28 +08:00
e111d92af6
refactor(spi_flash): remove redundent flash suspend check
2025-02-19 11:35:09 +08:00
43121c0d47
test(flash_mmap): added psram enabled test for esp32p4 as mmu is per target
2025-02-17 16:15:09 +08:00
870a1846b1
Merge branch 'feature/esp_tee_flash_prot_spi1' into 'master'
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feat(esp_tee): Add support for flash memory isolation and protection (SPI1)
Closes IDF-10481, IDF-10083, and IDF-8915
See merge request espressif/esp-idf!36454
2025-02-12 18:35:49 +08:00
d59f732718
Merge branch 'refactor/gpio_apis_modification' into 'master'
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refactor(gpio): refactor some GPIO APIs
See merge request espressif/esp-idf!36384
2025-02-12 11:33:37 +08:00
c23714f775
feat(esp_tee): Add support for flash memory isolation and protection (SPI1)
2025-02-11 12:30:05 +05:30
3a8d065908
refactor(gpio): improve gpio_iomux_in/out API
2025-02-10 21:44:07 +08:00
3e79641afa
test(spi_flash): Add framework to test driver can work under flash auto-suspend
2025-02-10 13:51:11 +08:00
1e8a48db74
Merge branch 'feat/h21_enable_ci_build_test' into 'master'
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feat(esp32h21): enable ESP32H21 ci build
Closes IDF-11561
See merge request espressif/esp-idf!36197
2025-02-07 14:10:54 +08:00
morris