ea36c4f609
Merge branch 'feature/esp_tee_c5_v5.5' into 'release/v5.5'
...
feat(esp_tee): Initial support for ESP32-C5 and related changes (v5.5)
See merge request espressif/esp-idf!42357
2025-10-16 09:39:23 +05:30
508a659001
feat(esp_tee): Support for ESP32-C5 - the rest of the components
2025-10-14 10:12:11 +05:30
e6d4eec507
feat(p4): p4 rev3 real chip support
2025-10-13 15:25:23 +08:00
30f2578e75
fix(esp32h4): fix g0 component build
2025-03-04 16:17:18 +08:00
121f56ef6d
change(esp_hw_support): disable CPU wait-for-event mode on cpu start
2025-01-14 21:34:44 +08:00
e51d2c1da3
feat(esp_tee): Support for ESP-TEE - riscv component
2024-12-02 12:20:04 +05:30
8a608da2b0
refactor(intr): add plic and intc interrupt rv util apis
...
refactor(intr): remove the extra instructions in plic and intc
2024-09-11 18:26:07 +08:00
6e51c0525d
fix(wdt): changed register dump on non panic task WDT to be more descriptive
...
Closes https://github.com/espressif/esp-idf/issues/14400
2024-08-22 10:48:26 +08:00
f06b235709
fix(riscv): fix a that affected mintstatus CSR value in the CLIC
2024-07-26 13:56:40 +08:00
c880f697da
feat(panic): supported more cache error cactch
2024-07-11 15:26:13 +08:00
21f870ecd5
remove(c5beta3): remove c5 beta3 system files
2024-06-17 12:02:15 +08:00
4b4f4c200a
fix(interrupt): fixed interrupt thresholds not working on C5
2024-05-14 10:56:22 +08:00
f6e935e013
fix(esp32c5): add CLIC interrupt controller support for the ESP32-C5
2024-04-16 10:38:14 +08:00
102d5bbf72
refactor(riscv): added a new API for the interrupts
2024-01-18 16:36:53 +08:00
9a6de4cb3e
fix(panic): fixed cache error being reported as illegal instruction
...
On riscv chips accessing cache mapped memory regions over the ibus would
result in an illegal instructions exception triggering faster than the cache
error interrupt/exception.
Added a cache error check in the panic handler, if any cache errors are active
the panic handler will now report a cache error, even if the trigger exception
was a illegal instructions.
2023-12-04 10:49:00 +08:00
22091c8744
feat(wdt): add multicore support for WDTs on RISCV
2023-10-23 18:26:08 +08:00
8ca191e4c1
fix(esp32p4): Fixed interrupt handling to use the CLIC controller
2023-08-31 12:16:08 +08:00
ecf1461f1c
feat(panic): base support on p4
2023-07-25 05:59:10 +00:00
4df3ff619e
feat(esp_system): implement hw stack guard for riscv chips
...
- add hardware stack guard based on assist-debug module
- enable hardware stack guard by default
- disable hardware stack guard for freertos ci.release test
- refactor rtos_int_enter/rtos_int_exit to change SP register inside them
- fix panic_reason.h header for RISC-V
- update docs to include information about the new feature
2023-07-01 16:27:40 +00:00
336d0b64de
riscv: fix panic_reasons being an instance of enum, not type name
2022-01-27 11:00:09 +07:00
69096ddce5
Security: ESP32C3 memory protection feature (IRAM0/DRAM0)
...
Software support for PMS module.
Allows controlled memory access to IRAM (R/W/X) and DRAM0 (R/W)
On/locked by default, configurable in Kconfig (esp_system)
Closes https://jira.espressif.com:8443/browse/IDF-2092
2021-01-27 08:44:03 +01:00
c218f669ba
panic on RISC-V: Take into account Merge Request comments
2020-12-31 15:46:17 +08:00
4cc6b5571b
esp_system: support riscv panic
2020-11-13 07:49:11 +11:00
Mahavir Jain