08f5f0d66b
fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption
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This reverts commit 7145fc9558752a6532072bb272e94389807eda51.
2025-12-24 02:31:57 +08:00
187f43a3bb
Revert "fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption"
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This reverts commit 3c5d2e6b5843da853fb81067eb2bd287f7fbd735.
2025-12-17 03:33:30 +08:00
376f396e20
Merge branch 'bugfix/esp32c5_encrypted_flash_write_v5.5' into 'release/v5.5'
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fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption (v5.5)
See merge request espressif/esp-idf!43326
2025-11-17 15:02:40 +08:00
3fd00b4d80
fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption
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Encrypted flash write operation sometimes result in random corruption in
certain bytes. Root cause points to sudden current surge due to involvement of
encryption block overwhelming LDO supply. More details will be provided
in the ESP32-C5 SoC Errata document.
This fix limits the CPU clock to 160MHz for flash encryption enabled
case. Failing encrypted flash write tests could successfully pass in
this configuration. Going ahead, a dynamic clock adjustment in flash
driver will be considered to mitigate this issue.
2025-11-13 13:26:06 +05:30
6ea63548d4
fix(esp_security): Set WR_DIS_SECURE_BOOT_SHA384_EN by default when
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Flash Encryption Release mode is enabled and Secure Boot P384 scheme not is enabled.
2025-11-11 17:53:04 +05:30
7b57a1cd16
fix(esp_security): Fix undefined efuse build failure in case of ESP32-P4
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- The `wr_dis` efuse bit corresponding to `SECURE_BOOT_SHA384_EN` is absent in P4
2025-11-11 17:53:04 +05:30
042f29dd66
Merge branch 'fix/change_write_protection_bit_of_shared_security_efuses_v5.5' into 'release/v5.5'
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Reorder write protection bits of some shared security efuses (v5.5)
See merge request espressif/esp-idf!42033
2025-10-15 09:38:59 +05:30
6ab5a2f883
fix(esp_security): Configure the Key Manager to use XTS-AES efuse key by-default
2025-10-13 10:40:50 +05:30
70a8b4d842
fix(bootloader_support): Reorder write disabling ECDSA_CURVE_MODE
2025-10-13 10:40:16 +05:30
d902072d80
fix(bootloader_support): Reorder write protection bits of some shared security efuses
2025-10-13 10:40:16 +05:30
3c39b32195
Chip/support esp32c61 v5.5
2025-07-22 12:21:36 +08:00
c65858287a
feat: enabled secure boot support esp32h21
2025-04-25 17:48:25 +05:30
aae4bfb6f3
feat: enable ecdsa support for esp32h21
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This commit enabled suppot for ECDSA peripheral in ESP32H21.
2025-04-14 10:26:46 +05:30
9269b785f8
refactor(ecdsa): rely on efuse to get chip revision
2025-01-24 11:50:17 +08:00
d8d9ba3dc2
fix(soc): Fixed ECDSA register compatibility
2025-01-24 11:50:17 +08:00
bef2a72ecb
fix(hal): Make the ECDSA countermeasure dynamically applicable
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This commit makes the ECDSA countermeasure dynamically applicable
across different revisions of the ESP32H2 SoC.
2025-01-24 11:50:17 +08:00
6875cbf022
feat(ecc): enable ECC constant time mode for ESP32-H2 ECO5
2025-01-24 11:50:17 +08:00
82db0feab2
fix(security): Update key manager specific initializations for esp32c5
2024-10-28 11:13:43 +08:00
e52e2d282a
refactor(startup): move key manager specific code to esp_security component
2024-09-25 14:21:19 +05:30
39872a5575
feat(esp_security): Config to forcefully enable ECC constant-time operations during bootup
2024-09-20 18:46:55 +05:30
79f9c7d157
feat(esp_security): Move DS, HMAC, DPA and crypto lock implementation
2024-08-20 12:35:22 +08:00
Xiao Xufeng