Xiao Xufeng
faf6cc4f84
This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency normally, while automatically reducing CPU frequency during encrypted flash writes to ensure correct operation. The frequency limit is chip revision dependent: - v1.2 and above: limited to 160MHz during encrypted writes - v1.0 and below: limited to 80MHz during encrypted writes Key implementation details: - Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called - Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer - Works with both PM enabled and disabled configurations - Frequency is automatically restored after encrypted write completes - For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when CPU frequency is reduced to 80MHz - SPI1 timing registers are configured during frequency switching since encrypted writes use SPI1 and must work correctly at reduced CPU frequencies Code improvements: - Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks - Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of hardcoded macros - Add comprehensive test cases covering various PM configurations and edge cases This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance while maintaining reliable encrypted flash write functionality.
90 lines
2.8 KiB
YAML
90 lines
2.8 KiB
YAML
# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
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components/spi_flash/test_apps/esp_flash:
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disable:
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- if: IDF_TARGET in ["esp32h21", "esp32h4"]
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temporary: true
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reason: not support yet # TODO: [esp32h21] IDF-11609 [ESP32H4] IDF-12388
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depends_filepatterns:
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- components/bootloader_support/bootloader_flash/**/*
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depends_components:
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- esp_mm
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- esp_psram
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- spi_flash
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- esp_driver_gpio
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- esp_driver_spi
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- esptool_py # Some flash related kconfigs are listed here.
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components/spi_flash/test_apps/esp_flash_freq_limit:
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enable:
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- if: IDF_TARGET == "esp32c5"
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depends_components:
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- spi_flash
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- esp_pm
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- esp_driver_gptimer
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- esp_hw_support
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components/spi_flash/test_apps/esp_flash_stress:
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disable:
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- if: IDF_TARGET == "esp32h4"
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temporary: true
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reason: not support yet # TODO: [ESP32H4] IDF-12388
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depends_components:
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- esp_mm
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- spi_flash
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components/spi_flash/test_apps/flash_encryption:
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disable:
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- if: IDF_TARGET == "esp32h4"
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temporary: true
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reason: not support yet # TODO: [ESP32H4] IDF-12388
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disable_test:
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- if: IDF_TARGET in ["esp32c2", "esp32s2", "esp32c6", "esp32h2", "esp32p4", "esp32c5", "esp32c61", "esp32h21", "esp32h4"]
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temporary: true
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reason: No runners # IDF-5634
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depends_components:
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- esp_mm
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- spi_flash
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components/spi_flash/test_apps/flash_mmap:
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depends_components:
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- esp_mm
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- spi_flash
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enable:
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- if: CONFIG_NAME == "release" and IDF_TARGET != "linux"
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- if: CONFIG_NAME == "rom_impl" and ESP_ROM_HAS_SPI_FLASH == 1
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- if: CONFIG_NAME == "psram" and SOC_MMU_PER_EXT_MEM_TARGET == 1 # MMU per target needs test. On unified MMU chips, the entry ID is unique
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- if: CONFIG_NAME == "xip_psram" and SOC_SPIRAM_XIP_SUPPORTED == 1
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# S2 doesn't have ROM for flash
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- if: CONFIG_NAME == "xip_psram_with_rom_impl" and SOC_SPIRAM_XIP_SUPPORTED == 1 and IDF_TARGET != "esp32s2"
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disable:
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- if: IDF_TARGET == "esp32c61" and CONFIG_NAME == "xip_psram_with_rom_impl"
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temporary: true
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reason: not supported yet # TODO: [ESP32C61] IDF-12784
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components/spi_flash/test_apps/flash_suspend:
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disable:
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- if: SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND != 1
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disable_test:
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- if: IDF_TARGET != "esp32c3"
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temporary: true
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reason: lack of runners
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depends_components:
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- spi_flash
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- esp_driver_gptimer
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components/spi_flash/test_apps/mspi_test:
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disable:
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- if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1
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- if: CONFIG_NAME == "xip_psram" and SOC_SPIRAM_SUPPORTED != 1
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depends_filepatterns:
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- components/bootloader_support/bootloader_flash/**/*
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depends_components:
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- esp_mm
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- esp_psram
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- spi_flash
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- esp_driver_gpio
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- esp_driver_spi
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- esptool_py # Some flash related kconfigs are listed here.
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