Laukik Hase
06ba6bb4b4
Currently, REE SPI flash HAL operations are routed as service calls to TEE, but the TEE implementation incorrectly uses ROM APIs instead of HAL APIs. This leads to issues and is not the recommended approach.
235 lines
8.4 KiB
C++
235 lines
8.4 KiB
C++
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <string.h>
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#include <stdlib.h>
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#include "hal/spi_flash_hal.h"
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#include "hal/assert.h"
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#include "soc/soc_caps.h"
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#include "soc/chip_revision.h"
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#include "hal/efuse_hal.h"
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#include "sdkconfig.h"
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#define ADDRESS_MASK_24BIT 0xFFFFFF
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#define COMPUTE_DUMMY_CYCLELEN(host, base) ((base) + ((spi_flash_hal_context_t*)host)->extra_dummy)
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static inline spi_dev_t *get_spi_dev(spi_flash_host_inst_t *host)
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{
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return ((spi_flash_hal_context_t*)host)->spi;
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}
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static inline int get_host_id(spi_flash_host_inst_t* host)
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{
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spi_dev_t *dev = get_spi_dev(host);
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return spi_flash_ll_hw_get_id(dev);
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}
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void spi_flash_hal_poll_cmd_done(spi_flash_host_inst_t *host)
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{
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while (!spi_flash_ll_cmd_is_done(get_spi_dev(host))) {
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//nop
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}
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}
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esp_err_t spi_flash_hal_device_config(spi_flash_host_inst_t *host)
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{
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spi_flash_hal_context_t* ctx = (spi_flash_hal_context_t*)host;
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spi_dev_t *dev = get_spi_dev(host);
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spi_flash_ll_reset(dev);
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spi_flash_ll_set_cs_pin(dev, ctx->cs_num);
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spi_flash_ll_set_clock(dev, &ctx->clock_conf);
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int cs_hold = ctx->cs_hold;
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spi_flash_ll_set_hold(dev, cs_hold);
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spi_flash_ll_set_cs_setup(dev, ctx->cs_setup);
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#ifndef GPSPI_BUILD
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#if SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
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if ((ctx->flags & SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_SUSPEND) != 0) {
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spi_flash_hal_setup_auto_suspend_mode(host);
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} else {
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spi_flash_hal_disable_auto_suspend_mode(host);
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}
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if ((ctx->flags & SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_RESUME) != 0) {
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spi_flash_hal_setup_auto_resume_mode(host);
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} else {
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spi_flash_hal_disable_auto_resume_mode(host);
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}
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#endif //SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
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#if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
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// Always keep the extra dummy on SPI1 is 0, add extra dummy to user dummy
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spimem_flash_ll_set_extra_dummy((spi_mem_dev_t*)dev, 0);
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#endif
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#else
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gpspi_flash_ll_set_hold_pol(dev, 1);
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#endif //GPSPI_BUILD
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return ESP_OK;
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}
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esp_err_t spi_flash_hal_configure_host_io_mode(
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spi_flash_host_inst_t *host,
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uint32_t command,
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uint32_t addr_bitlen,
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int dummy_cyclelen_base,
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esp_flash_io_mode_t io_mode)
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{
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spi_dev_t *dev = get_spi_dev(host);
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int host_id = spi_flash_ll_hw_get_id(dev);
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uint32_t extra_bits = io_mode & 0xFFFF0000;
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io_mode = io_mode & 0xFFFF;
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/*
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* Some flash chips, when working under some IO modes (DIO, QIO and OIO in the future), treat
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* the first 8 bits of the dummy bits as the bits. When the bits meet some pattern, the chip
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* will go into a "continuous (XIP)" mode, where the command field will be skipped in the next
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* transaction. We have to output all ones in these cycles because we don't need this feature.
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*/
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bool conf_required = ((extra_bits & SPI_FLASH_CONFIG_CONF_BITS) != 0);
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if (!SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) && io_mode > SPI_FLASH_FASTRD) {
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return ESP_ERR_NOT_SUPPORTED;
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}
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#ifndef GPSPI_BUILD
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#if SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT
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// The CONTROL_DUMMY_OUTPUT feature is used to control M7-M0 bits.
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spi_flash_ll_set_dummy_out(dev, (conf_required? 1: 0), 1);
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#else
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/**
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* - On current chips, addr phase can support 32 bits at most.
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* - Flash chip requires continuous mode bits
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*
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* We send continuous mode bits via the dummy output feature, so as to support
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* 32-bit address.
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*
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* On chips without dummy output feature (ESP32, ESP32C6), we fallback to use
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* addr phase to send the continuous mode bits:
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* - On ESP32 (QIO), qio_dummy: 6 - 4 / 4 = 5, addr_bitlen: 24 + 4 = 28. (This
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* setting exists for long time, we keep this on ESP32)
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* - On ESP32C6 (QIO), qio_dummy: 6 - 8 / 4 = 4, addr_bitlen: 24 + 8 = 32
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* - On future chips without dummy output feature, we follow the ESP32C6 (QIO)
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* way.
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* - Above two ways, the timings are same.
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* - DIO is similar.
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*/
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if (conf_required) {
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int line_width = (io_mode == SPI_FLASH_DIO? 2: 4);
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dummy_cyclelen_base -= SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS / line_width;
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#if !SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
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addr_bitlen += SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS;
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#endif
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spi_flash_ll_set_extra_address(dev, 0);
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#if SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
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spi_flash_ll_wb_mode_enable(dev, true);
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#endif
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}
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#endif
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#else
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if (conf_required) {
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gpspi_flash_ll_set_dummy_out(dev, (conf_required? 1: 0), 1);
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}
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#endif
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#if CONFIG_IDF_TARGET_ESP32P4
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// TODO: This is temporarily for ESP32P4-ECO0, please remove it when eco0 is not widly used. IDF-10019
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unsigned chip_version = efuse_hal_chip_revision();
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if (unlikely(!ESP_CHIP_REV_ABOVE(chip_version, 1))) {
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if (conf_required) {
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int line_width = (io_mode == SPI_FLASH_DIO? 2: 4);
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dummy_cyclelen_base -= SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS / line_width;
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addr_bitlen += SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS;
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spi_flash_ll_set_extra_address(dev, 0);
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}
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}
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#endif
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if (command >= 0x100) {
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spi_flash_ll_set_command(dev, command, 16);
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} else {
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spi_flash_ll_set_command(dev, command, 8);
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}
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spi_flash_ll_set_addr_bitlen(dev, addr_bitlen);
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// Add dummy cycles to compensate for latency of GPIO matrix and external delay, if necessary...
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spi_flash_ll_set_dummy(dev, COMPUTE_DUMMY_CYCLELEN(host, dummy_cyclelen_base));
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//disable all data phases, enable them later if needed
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spi_flash_ll_set_miso_bitlen(dev, 0);
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spi_flash_ll_set_mosi_bitlen(dev, 0);
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spi_flash_ll_set_read_mode(dev, io_mode);
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#if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
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spi_flash_hal_context_t* ctx = (spi_flash_hal_context_t*)host;
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if (ctx->fdummy_rin) {
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spimem_flash_ll_set_fdummy_rin((spi_mem_dev_t*)dev, ctx->fdummy_rin);
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}
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#endif
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return ESP_OK;
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}
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esp_err_t spi_flash_hal_common_command(spi_flash_host_inst_t *host, spi_flash_trans_t *trans)
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{
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spi_dev_t *dev = get_spi_dev(host);
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esp_flash_io_mode_t io_mode = ((spi_flash_hal_context_t*)host)->base_io_mode;
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uint16_t command;
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uint8_t dummy_bitlen;
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bool pe_ops = false;
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command = trans->command;
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dummy_bitlen = trans->dummy_bitlen;
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if ((trans->flags & SPI_FLASH_TRANS_FLAG_IGNORE_BASEIO) != 0) {
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io_mode = trans->io_mode;
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}
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host->driver->configure_host_io_mode(host, command, trans->address_bitlen, dummy_bitlen, io_mode);
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spi_flash_ll_set_usr_address(dev, trans->address, trans->address_bitlen);
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//No extra dummy cycles for compensation if no input data
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if (trans->miso_len == 0) {
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spi_flash_ll_set_dummy(dev, dummy_bitlen);
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}
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spi_flash_ll_set_mosi_bitlen(dev, trans->mosi_len * 8);
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spi_flash_ll_set_buffer_data(dev, trans->mosi_data, trans->mosi_len);
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spi_flash_ll_set_miso_bitlen(dev, trans->miso_len * 8);
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if ((trans->flags & SPI_FLASH_TRANS_FLAG_PE_CMD) != 0) {
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pe_ops = true;
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}
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spi_flash_ll_user_start(dev, pe_ops);
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host->driver->poll_cmd_done(host);
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if (trans->miso_len > 0) {
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spi_flash_ll_get_buffer_data(dev, trans->miso_data, trans->miso_len);
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}
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#if SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
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spi_flash_ll_wb_mode_enable(dev, false);
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#endif
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return ESP_OK;
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}
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esp_err_t spi_flash_hal_read(spi_flash_host_inst_t *host, void *buffer, uint32_t address, uint32_t read_len)
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{
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spi_dev_t *dev = get_spi_dev(host);
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int bitlen = spi_flash_ll_get_addr_bitlen(dev);
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//Only 24-bit and 32-bit address are supported. The extra length are for M7-M0, which should be
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//filled with ones by the function below
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spi_flash_ll_set_usr_address(dev, address, bitlen & (~7));
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spi_flash_ll_set_miso_bitlen(dev, read_len * 8);
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spi_flash_ll_user_start(dev, false);
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host->driver->poll_cmd_done(host);
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if (read_len > 0) {
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spi_flash_ll_get_buffer_data(dev, buffer, read_len);
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}
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return ESP_OK;
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}
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