Xiao Xufeng
faf6cc4f84
This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency normally, while automatically reducing CPU frequency during encrypted flash writes to ensure correct operation. The frequency limit is chip revision dependent: - v1.2 and above: limited to 160MHz during encrypted writes - v1.0 and below: limited to 80MHz during encrypted writes Key implementation details: - Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called - Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer - Works with both PM enabled and disabled configurations - Frequency is automatically restored after encrypted write completes - For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when CPU frequency is reduced to 80MHz - SPI1 timing registers are configured during frequency switching since encrypted writes use SPI1 and must work correctly at reduced CPU frequencies Code improvements: - Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks - Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of hardcoded macros - Add comprehensive test cases covering various PM configurations and edge cases This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance while maintaining reliable encrypted flash write functionality.
81 lines
1.8 KiB
C
81 lines
1.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdarg.h>
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#include "sdkconfig.h"
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#include "esp_flash.h"
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#include "esp_attr.h"
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#include "esp_rom_sys.h"
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#include "esp_cpu.h"
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#include "rom/cache.h"
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#include "hal/cache_hal.h"
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#include "hal/cache_ll.h"
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#include "soc/soc_caps.h"
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static IRAM_ATTR esp_err_t start(void *arg, uint32_t flags)
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{
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#if SOC_BRANCH_PREDICTOR_SUPPORTED
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//branch predictor will start cache request as well
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esp_cpu_branch_prediction_disable();
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Read_Disable(0);
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Cache_Read_Disable(1);
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#else
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cache_hal_suspend(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
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#endif
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return ESP_OK;
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}
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static IRAM_ATTR esp_err_t end(void *arg)
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{
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Read_Enable(0);
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Cache_Read_Enable(1);
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#else
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cache_hal_resume(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
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#endif
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#if SOC_BRANCH_PREDICTOR_SUPPORTED
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esp_cpu_branch_prediction_enable();
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#endif
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return ESP_OK;
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}
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static esp_err_t delay_us(void *arg, uint32_t us)
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{
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esp_rom_delay_us(us);
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return ESP_OK;
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}
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// Currently when the os is not up yet, the caller is supposed to call esp_flash APIs with proper
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// buffers.
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void* get_temp_buffer_not_supported(void* arg, size_t reqest_size, size_t* out_size)
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{
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return NULL;
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}
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const DRAM_ATTR esp_flash_os_functions_t esp_flash_noos_functions = {
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.start = start,
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.end = end,
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.delay_us = delay_us,
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.region_protected = NULL,
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/* the caller is supposed to call esp_flash_read/esp_flash_write APIs with buffers in DRAM */
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.get_temp_buffer = NULL,
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.release_temp_buffer = NULL,
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.yield = NULL,
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};
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esp_err_t esp_flash_app_disable_os_functions(esp_flash_t* chip)
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{
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chip->os_func = &esp_flash_noos_functions;
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return ESP_OK;
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}
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