Tomas Rezucha
230 lines
6.6 KiB
C
230 lines
6.6 KiB
C
/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Following register description is taken from
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* U2OPHYT40LL USB 2.0 OTG PHY specification v2.0
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*/
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typedef union {
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struct {
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/** clk_gate_rx : R/W; bitpos: [0]; default 2'b0;
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* Clock Gating Control Signal for Rx.
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* 2'b0 Lower power consumption
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* 2'b1 Lowest power consumption mode
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* 2'b2 Normal power consumption mode
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*/
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uint32_t clk_gate_rx:2;
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/** clk_gate_tx : R/W; bitpos: [2]; default: 1'b0;
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* Clock Gating Control Signal for Rx.
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* 1'b0 Low power consumption mode
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* 1'b1 Normal power consumption mode
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*/
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uint32_t clk_gate_tx:1;
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/** adj_res_fs : Reserved; bitpos: [3]; default: 0;
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* Fine tune the 45ohm termination resistor (FS)
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* Reserved
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*/
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uint32_t adj_res_fs:2;
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/** adj_res_hs : R/W; bitpos: [5]; default: 3'b100;
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* Fine tune the 45ohm termination resistor (HS)
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* 3'b000 40 Ohm
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* 3'b100 45 Ohm
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* 3'b110 50 Ohm
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*/
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uint32_t adj_res_hs:3;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} usb_utmi_fc_00_reg_t;
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typedef union {
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struct {
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/** adj_vref_sq : R/W; bitpos: [0]; default: 4'b0010;
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* Squelch detection threshold voltage control bits
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* 4'b0000 92 mV
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* 4'b0010 124 mV
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* 4'b0011 152 mV
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*/
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uint32_t adj_vref_sq:4;
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/** adj_pw_hs : R/W; bitpos: [4]; default: 4'b1111;
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* Super power saving with reduced output swing mode control bits (for HS mode only)
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* 4'b0001 100 mV output swing
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* 4'b0011 200 mV output swing
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* 4'b0111 300 mV output swing
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* 4'b1111 400 mV output swing
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*/
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uint32_t adj_pw_hs:4;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} usb_utmi_fc_01_reg_t;
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typedef union {
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struct {
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/** adj_iref_res : R/W; bitpos: [0]; default: 4'b0111
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* Internal bias current adjustment control bits
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* 4'b0000 125 uA
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* 4'b0111 100 uA
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* 4'b1111 78 uA
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*/
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uint32_t adj_iref_res:4;
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/** adj_vsw_hs : R/W; bitpos: [4]; default: 3'b100
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* Output eye shape adjustment control bits
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* 3'b000 320 mV
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* 3'b100 400 mV
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* 3'b111 460 mV
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*/
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uint32_t adj_vsw_hs:3;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} usb_utmi_fc_02_reg_t;
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typedef union {
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struct {
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/** adj_pll : R/W; bitpos: [0]; default: 4'b0101
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* PLL adjustment signal
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*/
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uint32_t adj_pll:4;
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/** adj_osc : R/W; bitpos: [4]; default: 3'b000
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* TX Clock phase adjust signal
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*/
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uint32_t adj_txclk_phase:3;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} usb_utmi_fc_03_reg_t;
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typedef union {
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struct {
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/** test_sel : R/W; bitpos: [0]; default: 8'b0
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* The PHY has test_sel register here, which normally drives DTO (Digital Test Output) signal.
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* In our implementation output of this register is left floating and DTO is driven from Probe module.
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* Thus writing to this register has no effect and is renamed to 'reserved'
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*/
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uint32_t reserved:8;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} usb_utmi_fc_04_reg_t;
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typedef union {
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struct {
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/** rxgap_fix_en : R/W; bitpos: [0]; default: 1'b1
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* RXGAP fix enable
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*/
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uint32_t rxgap_fix_en:1;
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/** counter_sel : R/W; bitpos: [1]; default: 1'b0
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* SIE_input sample enable
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*/
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uint32_t counter_sel:1;
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/** clk_sel : R/W; bitpos: [2]; default: 1'b0
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* CLK60_30 source select
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*/
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uint32_t clk_sel:1;
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/** phy_mode_sel : R/W; bitpos: [3]; default: 1'b0
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* PHY MODE select
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*/
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uint32_t phy_mode_sel:1;
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/** uni_bidi_i : R/W; bitpos: [4]; default: 1'b0
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* UNI_BIDI signal
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*/
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uint32_t uni_bidi_i:1;
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/** short_5v : R/W; bitpos: [5]; default: 1'b0
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* SHORT_5V signal
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*/
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uint32_t short_5v:1;
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/** short_5v_enable : R/W; bitpos: [6]; default: 1'b1
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* SHORT_5V_ENABLE signal
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*/
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uint32_t short_5v_enable:1;
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/** usable_en : R/W; bitpos: [7]; default: 1'b1
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* compare_begin delay time select
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*/
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uint32_t usable_en:1;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} usb_utmi_fc_05_reg_t;
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typedef union {
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struct {
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/** ls_par_en : R/W; bitpos: [0]; default: 1'b0
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* LS mode with parallel enable
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*/
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uint32_t ls_par_en:1;
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/** det_fseop_en : R/W; bitpos: [1]; default: 1'b0
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* FS EOP detect enable
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*/
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uint32_t det_fseop_en:1;
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/** pre_hphy_lsie : R/W; bitpos: [2]; default: 1'b0
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* Dis_preamble enable
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*/
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uint32_t pre_hphy_lsie:1;
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/** ls_kpalv_en : R/W; bitpos: [3]; default: 1'b0
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* LS mode keep alive enable
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*/
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uint32_t ls_kpalv_en:1;
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/** hs_tx2rx_dly_cnt_sel : R/W; bitpos: [4]; default: 3'b100
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* PHY High-SPeed bus turn-around time select
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*/
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uint32_t hs_tx2rx_dly_cnt_sel:3;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} usb_utmi_fc_06_reg_t;
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typedef union {
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struct {
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/** cnt_num : R/W; bitpos: [1:0]; default: 2'b00
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* 3 ms counter select
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* 00: 392us (Default)
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* 01: 682us
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* 10: 1.36ms
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* 11: 2.72ms
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*/
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uint32_t cnt_num:2;
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/** clk480_sel : R/W; bitpos: [2]; default: 1'b0
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* CLK_480 output time select
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* 0: CLK_480 is valid after a delay time when PLL is locked
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* 1: CLK_480 is valid immediately after PLL is locked
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*/
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uint32_t clk480_sel:1;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} usb_utmi_fc_07_reg_t;
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typedef struct usb_utmi_dev_t {
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volatile usb_utmi_fc_00_reg_t fc_00;
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volatile usb_utmi_fc_01_reg_t fc_01;
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volatile usb_utmi_fc_02_reg_t fc_02;
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volatile usb_utmi_fc_03_reg_t fc_03;
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volatile usb_utmi_fc_04_reg_t fc_04;
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volatile usb_utmi_fc_05_reg_t fc_05;
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volatile usb_utmi_fc_06_reg_t fc_06;
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volatile usb_utmi_fc_07_reg_t fc_07;
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} usb_utmi_dev_t;
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extern usb_utmi_dev_t USB_UTMI;
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#ifndef __cplusplus
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_Static_assert(sizeof(usb_utmi_dev_t) == 0x20, "Invalid size of usb_utmi_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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