Chen Jichang 62700fa36f feat(esp32h4): add soc register header files (stage2_3) ...

add soc headers made by hand

2025-02-24 12:20:27 +08:00

..

csr_hwlp.h

fix(riscv): make HWLP feature use direct saving of lazy saving

2024-05-21 17:27:46 +08:00

csr_pie.h

feat(riscv): add support for PIE coprocessor and HWLP feature

2024-05-20 10:47:58 +08:00

csr.h

feat(esp_tee): Support for ESP-TEE - riscv component

2024-12-02 12:20:04 +05:30

encoding.h

change(esp_hw_support): disable CPU wait-for-event mode on cpu start

2025-01-14 21:34:44 +08:00

instruction_decode.h

refactor(tools): Tidy up core component files copyright ignore

2024-01-22 18:07:35 +08:00

interrupt.h

feat(esp_tee): Support for ESP-TEE - riscv component

2024-12-02 12:20:04 +05:30

rv_utils.h

feat(esp32h4): add soc register header files (stage2_3)

2025-02-24 12:20:27 +08:00

rvruntime-frames.h

feat(riscv): add support for PIE coprocessor and HWLP feature

2024-05-20 10:47:58 +08:00

semihosting.h

semihosting: version 2

2022-05-05 09:12:42 +00:00