Ivan Grokhotkov f355ecac40 ci(sdspi): re-enable probe/rw tests for slot 1 ...

These tests were disabled since SDMMC_FREQ_HIGHSPEED with sdspi didn't
work on ESP32 and ESP32-S3. However we don't have other tests for
slot 1, meaning that we weren't running probe and perf tests at all.

This commit re-enables the tests, keeping them with SDMMC_FREQ_DEFAULT

2024-05-02 16:44:16 +02:00

..

sdspi

ci(sdspi): re-enable probe/rw tests for slot 1

2024-05-02 16:44:16 +02:00

.build-test-rules.yml

refactor(sdspi): added component pytest cases and enabled them on CI

2023-11-29 12:13:03 +08:00