120 lines
3.6 KiB
C
120 lines
3.6 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _ESP32_HAL_CPU_H_
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#define _ESP32_HAL_CPU_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdlib.h>
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#include "sdkconfig.h"
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#include "soc/soc_caps.h"
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// When adding a new target, update the appropriate group(s) below
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// Targets that support XTAL frequency queries via rtc_clk_xtal_freq_get()
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#if (!defined(CONFIG_IDF_TARGET_ESP32C5) && !defined(CONFIG_IDF_TARGET_ESP32P4))
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#define TARGET_HAS_XTAL_FREQ 1
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#else
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#define TARGET_HAS_XTAL_FREQ 0
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#endif
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// Targets that need dynamic APB frequency updates via rtc_clk_apb_freq_update()
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#if (defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32C3))
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#define TARGET_HAS_DYNAMIC_APB 1
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#else
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#define TARGET_HAS_DYNAMIC_APB 0
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#endif
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// Xtensa architecture targets that need FreeRTOS tick divisor updates
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#if (defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32S2))
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#define TARGET_HAS_XTENSA_TICK 1
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#else
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#define TARGET_HAS_XTENSA_TICK 0
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#endif
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// Targets with APLL support (uses IDF SOC capability macro)
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// Note: ESP32-P4 APLL support is not yet fully implemented in IDF
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#if (defined(SOC_CLK_APLL_SUPPORTED) && !defined(CONFIG_IDF_TARGET_ESP32P4))
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#define TARGET_HAS_APLL 1
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#else
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#define TARGET_HAS_APLL 0
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#endif
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// Targets grouped by maximum CPU frequency support
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#if (defined(CONFIG_IDF_TARGET_ESP32P4))
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#define TARGET_CPU_FREQ_MAX_400 1
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#else
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#define TARGET_CPU_FREQ_MAX_400 0
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#endif
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#if (defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32C5) || defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3))
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#define TARGET_CPU_FREQ_MAX_240 1
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#else
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#define TARGET_CPU_FREQ_MAX_240 0
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#endif
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#if (defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32C6) || defined(CONFIG_IDF_TARGET_ESP32C61))
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#define TARGET_CPU_FREQ_MAX_160 1
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#else
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#define TARGET_CPU_FREQ_MAX_160 0
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#endif
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#if (defined(CONFIG_IDF_TARGET_ESP32C2))
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#define TARGET_CPU_FREQ_MAX_120 1
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#else
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#define TARGET_CPU_FREQ_MAX_120 0
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#endif
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#if (defined(CONFIG_IDF_TARGET_ESP32H2))
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#define TARGET_CPU_FREQ_MAX_96 1
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#else
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#define TARGET_CPU_FREQ_MAX_96 0
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#endif
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typedef enum {
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APB_BEFORE_CHANGE,
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APB_AFTER_CHANGE
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} apb_change_ev_t;
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typedef void (*apb_change_cb_t)(void *arg, apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb);
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bool addApbChangeCallback(void *arg, apb_change_cb_t cb);
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bool removeApbChangeCallback(void *arg, apb_change_cb_t cb);
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//function takes the following frequencies as valid values:
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// 240, 160, 80 <<< For all XTAL types
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// 40, 20, 10 <<< For 40MHz XTAL
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// 26, 13 <<< For 26MHz XTAL
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// 24, 12 <<< For 24MHz XTAL
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bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz);
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const char *getSupportedCpuFrequencyMhz(uint8_t xtal);
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const char *getClockSourceName(uint8_t source);
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uint32_t getCpuFrequencyMhz(); // In MHz
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uint32_t getXtalFrequencyMhz(); // In MHz
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uint32_t getApbFrequency(); // In Hz
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ESP32_HAL_CPU_H_ */
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