Update build script for ESP-IDF v3.0
This commit is contained in:
Valerii Koval
@@ -1,4 +1,4 @@
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/* Uart Example
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/* UART Echo Example
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This example code is in the Public Domain (or CC0 licensed, at your option.)
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@@ -7,177 +7,56 @@
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CONDITIONS OF ANY KIND, either express or implied.
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*/
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "esp_system.h"
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#include "nvs_flash.h"
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#include "driver/uart.h"
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#include "freertos/queue.h"
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#include "esp_log.h"
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#include "soc/uart_struct.h"
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static const char *TAG = "uart_example";
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/**
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* Test code brief
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* This example shows how to configure uart settings and install uart driver.
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* This is an example which echos any data it receives on UART1 back to the sender,
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* with hardware flow control turned off. It does not use UART driver event queue.
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*
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* uart_evt_test() is an example that read and write data on UART0, and handler some of the special events.
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* - port: UART0
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* - rx buffer: on
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* - tx buffer: on
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* - flow control: off
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* - event queue: on
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* - pin assignment: txd(default), rxd(default)
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*
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* uart_echo_test() is an example that read and write data on UART1, with hardware flow control turning on.
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* - port: UART1
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* - rx buffer: on
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* - tx buffer: off
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* - flow control: on
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* - event queue: off
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* - pin assignment: txd(io4), rxd(io5), rts(18), cts(19)
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* - Port: UART1
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* - Receive (Rx) buffer: on
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* - Transmit (Tx) buffer: off
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* - Flow control: off
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* - Event queue: off
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* - Pin assignment: see defines below
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*/
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#define ECHO_TEST_TXD (GPIO_NUM_4)
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#define ECHO_TEST_RXD (GPIO_NUM_5)
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#define ECHO_TEST_RTS (UART_PIN_NO_CHANGE)
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#define ECHO_TEST_CTS (UART_PIN_NO_CHANGE)
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#define BUF_SIZE (1024)
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#define ECHO_TEST_TXD (4)
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#define ECHO_TEST_RXD (5)
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#define ECHO_TEST_RTS (18)
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#define ECHO_TEST_CTS (19)
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QueueHandle_t uart0_queue;
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void uart_task(void *pvParameters)
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static void echo_task()
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{
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int uart_num = (int) pvParameters;
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uart_event_t event;
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size_t buffered_size;
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uint8_t* dtmp = (uint8_t*) malloc(BUF_SIZE);
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for(;;) {
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//Waiting for UART event.
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if(xQueueReceive(uart0_queue, (void * )&event, (portTickType)portMAX_DELAY)) {
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ESP_LOGI(TAG, "uart[%d] event:", uart_num);
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switch(event.type) {
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//Event of UART receving data
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/*We'd better handler data event fast, there would be much more data events than
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other types of events. If we take too much time on data event, the queue might
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be full.
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in this example, we don't process data in event, but read data outside.*/
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case UART_DATA:
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uart_get_buffered_data_len(uart_num, &buffered_size);
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ESP_LOGI(TAG, "data, len: %d; buffered len: %d", event.size, buffered_size);
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break;
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//Event of HW FIFO overflow detected
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case UART_FIFO_OVF:
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ESP_LOGI(TAG, "hw fifo overflow\n");
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//If fifo overflow happened, you should consider adding flow control for your application.
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//We can read data out out the buffer, or directly flush the rx buffer.
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uart_flush(uart_num);
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break;
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//Event of UART ring buffer full
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case UART_BUFFER_FULL:
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ESP_LOGI(TAG, "ring buffer full\n");
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//If buffer full happened, you should consider encreasing your buffer size
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//We can read data out out the buffer, or directly flush the rx buffer.
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uart_flush(uart_num);
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break;
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//Event of UART RX break detected
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case UART_BREAK:
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ESP_LOGI(TAG, "uart rx break\n");
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break;
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//Event of UART parity check error
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case UART_PARITY_ERR:
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ESP_LOGI(TAG, "uart parity error\n");
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break;
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//Event of UART frame error
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case UART_FRAME_ERR:
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ESP_LOGI(TAG, "uart frame error\n");
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break;
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//UART_PATTERN_DET
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case UART_PATTERN_DET:
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ESP_LOGI(TAG, "uart pattern detected\n");
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break;
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//Others
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default:
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ESP_LOGI(TAG, "uart event type: %d\n", event.type);
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break;
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}
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}
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}
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free(dtmp);
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dtmp = NULL;
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vTaskDelete(NULL);
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}
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void uart_evt_test()
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{
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int uart_num = UART_NUM_0;
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uart_config_t uart_config = {
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.baud_rate = 115200,
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.data_bits = UART_DATA_8_BITS,
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.parity = UART_PARITY_DISABLE,
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.stop_bits = UART_STOP_BITS_1,
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.flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
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.rx_flow_ctrl_thresh = 122,
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};
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//Set UART parameters
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uart_param_config(uart_num, &uart_config);
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//Set UART log level
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esp_log_level_set(TAG, ESP_LOG_INFO);
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//Install UART driver, and get the queue.
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uart_driver_install(uart_num, BUF_SIZE * 2, BUF_SIZE * 2, 10, &uart0_queue, 0);
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//Set UART pins,(-1: default pin, no change.)
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//For UART0, we can just use the default pins.
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//uart_set_pin(uart_num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
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//Set uart pattern detect function.
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uart_enable_pattern_det_intr(uart_num, '+', 3, 10000, 10, 10);
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//Create a task to handler UART event from ISR
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xTaskCreate(uart_task, "uart_task", 2048, (void*)uart_num, 12, NULL);
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//process data
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uint8_t* data = (uint8_t*) malloc(BUF_SIZE);
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do {
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int len = uart_read_bytes(uart_num, data, BUF_SIZE, 100 / portTICK_RATE_MS);
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if(len > 0) {
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ESP_LOGI(TAG, "uart read : %d", len);
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uart_write_bytes(uart_num, (const char*)data, len);
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}
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} while(1);
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}
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//an example of echo test with hardware flow control on UART1
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void uart_echo_test()
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{
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int uart_num = UART_NUM_1;
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/* Configure parameters of an UART driver,
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* communication pins and install the driver */
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uart_config_t uart_config = {
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.baud_rate = 115200,
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.data_bits = UART_DATA_8_BITS,
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.parity = UART_PARITY_DISABLE,
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.parity = UART_PARITY_DISABLE,
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.stop_bits = UART_STOP_BITS_1,
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.flow_ctrl = UART_HW_FLOWCTRL_CTS_RTS,
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.rx_flow_ctrl_thresh = 122,
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.flow_ctrl = UART_HW_FLOWCTRL_DISABLE
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};
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//Configure UART1 parameters
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uart_param_config(uart_num, &uart_config);
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//Set UART1 pins(TX: IO4, RX: I05, RTS: IO18, CTS: IO19)
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uart_set_pin(uart_num, ECHO_TEST_TXD, ECHO_TEST_RXD, ECHO_TEST_RTS, ECHO_TEST_CTS);
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//Install UART driver( We don't need an event queue here)
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//In this example we don't even use a buffer for sending data.
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uart_driver_install(uart_num, BUF_SIZE * 2, 0, 0, NULL, 0);
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uart_param_config(UART_NUM_1, &uart_config);
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uart_set_pin(UART_NUM_1, ECHO_TEST_TXD, ECHO_TEST_RXD, ECHO_TEST_RTS, ECHO_TEST_CTS);
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uart_driver_install(UART_NUM_1, BUF_SIZE * 2, 0, 0, NULL, 0);
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uint8_t* data = (uint8_t*) malloc(BUF_SIZE);
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while(1) {
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//Read data from UART
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int len = uart_read_bytes(uart_num, data, BUF_SIZE, 20 / portTICK_RATE_MS);
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//Write data back to UART
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uart_write_bytes(uart_num, (const char*) data, len);
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// Configure a temporary buffer for the incoming data
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uint8_t *data = (uint8_t *) malloc(BUF_SIZE);
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while (1) {
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// Read data from the UART
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int len = uart_read_bytes(UART_NUM_1, data, BUF_SIZE, 20 / portTICK_RATE_MS);
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// Write data back to the UART
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uart_write_bytes(UART_NUM_1, (const char *) data, len);
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}
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}
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void app_main()
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{
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//A uart read/write example without event queue;
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xTaskCreate(uart_echo_test, "uart_echo_test", 1024, NULL, 10, NULL);
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//A uart example with event queue.
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uart_evt_test();
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}
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xTaskCreate(echo_task, "uart_echo_task", 1024, NULL, 10, NULL);
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}
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@@ -6,120 +6,218 @@
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*/
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#define CONFIG_GATTC_ENABLE 1
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#define CONFIG_ESP32_PHY_MAX_TX_POWER 20
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#define CONFIG_PHY_ENABLED 1
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#define CONFIG_TRACEMEM_RESERVE_DRAM 0x0
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#define CONFIG_FREERTOS_MAX_TASK_NAME_LEN 16
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#define CONFIG_BLE_SMP_ENABLE 1
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#define CONFIG_FATFS_LFN_NONE 1
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#define CONFIG_TCP_RECVMBOX_SIZE 6
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#define CONFIG_FATFS_CODEPAGE_437 1
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#define CONFIG_LWIP_ETHARP_TRUST_IP_MAC 1
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#define CONFIG_TCP_WND_DEFAULT 5744
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#define CONFIG_SPIFFS_USE_MAGIC_LENGTH 1
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#define CONFIG_IPC_TASK_STACK_SIZE 1024
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#define CONFIG_FATFS_PER_FILE_CACHE 1
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#define CONFIG_ESPTOOLPY_FLASHFREQ "40m"
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#define CONFIG_NEWLIB_STDOUT_ADDCR 1
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#define CONFIG_TASK_WDT_CHECK_IDLE_TASK 1
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#define CONFIG_MBEDTLS_KEY_EXCHANGE_RSA 1
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#define CONFIG_UDP_RECVMBOX_SIZE 6
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#define CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE 0
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#define CONFIG_MBEDTLS_AES_C 1
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#define CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED 1
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#define CONFIG_MBEDTLS_GCM_C 1
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#define CONFIG_ESPTOOLPY_FLASHSIZE "2MB"
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#define CONFIG_HEAP_POISONING_DISABLED 1
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#define CONFIG_SPIFFS_CACHE_WR 1
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#define CONFIG_BROWNOUT_DET_LVL_SEL_0 1
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#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER 1
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#define CONFIG_ETHERNET 1
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#define CONFIG_SPIFFS_CACHE 1
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#define CONFIG_INT_WDT 1
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#define CONFIG_MBEDTLS_SSL_PROTO_TLS1 1
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#define CONFIG_MBEDTLS_ECDSA_C 1
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#define CONFIG_ESPTOOLPY_FLASHFREQ_40M 1
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#define CONFIG_LOG_BOOTLOADER_LEVEL_INFO 1
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#define CONFIG_ESPTOOLPY_FLASHSIZE_2MB 1
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#define CONFIG_AWS_IOT_MQTT_PORT 8883
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#define CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE 0
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#define CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS 1
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#define CONFIG_MBEDTLS_ECDH_C 1
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#define CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE 1
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#define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM 10
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#define CONFIG_MBEDTLS_SSL_ALPN 1
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#define CONFIG_MBEDTLS_PEM_WRITE_C 1
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#define CONFIG_LOG_DEFAULT_LEVEL_INFO 1
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#define CONFIG_BT_RESERVE_DRAM 0x10000
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#define CONFIG_FATFS_FS_LOCK 0
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#define CONFIG_IP_LOST_TIMER_INTERVAL 120
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#define CONFIG_SPIFFS_META_LENGTH 4
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#define CONFIG_ESP32_PANIC_PRINT_REBOOT 1
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#define CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED 1
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#define CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED 1
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#define CONFIG_CONSOLE_UART_BAUDRATE 115200
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#define CONFIG_LWIP_MAX_SOCKETS 10
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#define CONFIG_LWIP_NETIF_LOOPBACK 1
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#define CONFIG_EMAC_TASK_PRIORITY 20
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#define CONFIG_TIMER_TASK_STACK_DEPTH 2048
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#define CONFIG_FATFS_CODEPAGE 1
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#define CONFIG_TCP_MSS 1436
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#define CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED 1
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#define CONFIG_FATFS_CODEPAGE 437
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#define CONFIG_ESP32_DEFAULT_CPU_FREQ_160 1
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#define CONFIG_ULP_COPROC_RESERVE_MEM 0
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#define CONFIG_LWIP_MAX_UDP_PCBS 16
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#define CONFIG_ESPTOOLPY_BAUD 115200
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#define CONFIG_INT_WDT_CHECK_CPU1 1
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#define CONFIG_ADC_CAL_LUT_ENABLE 1
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#define CONFIG_FLASHMODE_DIO 1
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#define CONFIG_ESPTOOLPY_AFTER_RESET 1
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#define CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED 1
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#define CONFIG_LWIP_DHCPS_MAX_STATION_NUM 8
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#define CONFIG_TOOLPREFIX "xtensa-esp32-elf-"
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#define CONFIG_MBEDTLS_ECP_C 1
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#define CONFIG_FREERTOS_IDLE_TASK_STACKSIZE 1024
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#define CONFIG_ESP32_WIFI_AMPDU_ENABLED 1
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#define CONFIG_MBEDTLS_RC4_DISABLED 1
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#define CONFIG_CONSOLE_UART_NUM 0
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#define CONFIG_ESP32_APPTRACE_LOCK_ENABLE 1
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#define CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC 1
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#define CONFIG_ESPTOOLPY_BAUD_115200B 1
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#define CONFIG_LWIP_THREAD_LOCAL_STORAGE_INDEX 0
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#define CONFIG_TCP_OVERSIZE_MSS 1
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#define CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS 1
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#define CONFIG_CONSOLE_UART_DEFAULT 1
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#define CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN 16384
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#define CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS 4
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#define CONFIG_ESPTOOLPY_FLASHSIZE_DETECT 1
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#define CONFIG_TIMER_TASK_STACK_SIZE 3584
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#define CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE 1
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#define CONFIG_BTDM_CONTROLLER_RUN_CPU 0
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#define CONFIG_TCPIP_TASK_STACK_SIZE 2560
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#define CONFIG_MBEDTLS_X509_CRL_PARSE_C 1
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#define CONFIG_LWIP_DHCPS_LEASE_UNIT 60
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#define CONFIG_SPIFFS_USE_MAGIC 1
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#define CONFIG_TCPIP_TASK_STACK_SIZE 2048
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#define CONFIG_BLUEDROID_PINNED_TO_CORE_0 1
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#define CONFIG_TASK_WDT 1
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#define CONFIG_MAIN_TASK_STACK_SIZE 4096
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#define CONFIG_MAIN_TASK_STACK_SIZE 3584
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#define CONFIG_SPIFFS_PAGE_CHECK 1
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#define CONFIG_LWIP_MAX_ACTIVE_TCP 16
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#define CONFIG_TASK_WDT_TIMEOUT_S 5
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#define CONFIG_INT_WDT_TIMEOUT_MS 300
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#define CONFIG_ESPTOOLPY_FLASHMODE "dio"
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#define CONFIG_BTC_TASK_STACK_SIZE 3072
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#define CONFIG_BLUEDROID_ENABLED 1
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#define CONFIG_NEWLIB_STDIN_LINE_ENDING_CR 1
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#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA 1
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#define CONFIG_ESPTOOLPY_BEFORE "default_reset"
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#define CONFIG_LOG_DEFAULT_LEVEL 3
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#define CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION 1
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#define CONFIG_TIMER_QUEUE_LENGTH 10
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#define CONFIG_MAKE_WARN_UNDEFINED_VARIABLES 1
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#define CONFIG_FATFS_TIMEOUT_MS 10000
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#define CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM 32
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#define CONFIG_MBEDTLS_CCM_C 1
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#define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER 20
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#define CONFIG_ESP32_RTC_CLK_CAL_CYCLES 1024
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#define CONFIG_ESP32_WIFI_TX_BA_WIN 6
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#define CONFIG_ESP32_WIFI_NVS_ENABLED 1
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#define CONFIG_AWS_IOT_SDK 1
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#define CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED 1
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#define CONFIG_LIBSODIUM_USE_MBEDTLS_SHA 1
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#define CONFIG_DMA_RX_BUF_NUM 10
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#define CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED 1
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#define CONFIG_TCP_SYNMAXRTX 6
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#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA 1
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#define CONFIG_PYTHON "python"
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#define CONFIG_MBEDTLS_ECP_NIST_OPTIM 1
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#define CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1 1
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#define CONFIG_ESPTOOLPY_COMPRESSED 1
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#define CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp.csv"
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#define CONFIG_TCP_SND_BUF_DEFAULT 5744
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#define CONFIG_LWIP_DHCP_MAX_NTP_SERVERS 1
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#define CONFIG_TCP_MSL 60000
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#define CONFIG_MBEDTLS_SSL_PROTO_TLS1_1 1
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#define CONFIG_LWIP_SO_REUSE_RXTOALL 1
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#define CONFIG_PARTITION_TABLE_SINGLE_APP 1
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#define CONFIG_WIFI_ENABLED 1
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#define CONFIG_ESP32_WIFI_RX_BA_WIN 6
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#define CONFIG_MBEDTLS_X509_CSR_PARSE_C 1
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#define CONFIG_SPIFFS_USE_MTIME 1
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#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA 1
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#define CONFIG_LWIP_DHCP_DOES_ARP_CHECK 1
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#define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE 4096
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#define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE 2048
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#define CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V 1
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#define CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY 2000
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#define CONFIG_BROWNOUT_DET_LVL 0
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#define CONFIG_MBEDTLS_PEM_PARSE_C 1
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#define CONFIG_SPIFFS_GC_MAX_RUNS 10
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#define CONFIG_ESP32_APPTRACE_DEST_NONE 1
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#define CONFIG_PARTITION_TABLE_CUSTOM_APP_BIN_OFFSET 0x10000
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#define CONFIG_MBEDTLS_SSL_PROTO_TLS1_2 1
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#define CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA 1
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#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM 32
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#define CONFIG_FATFS_CODEPAGE_ASCII 1
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#define CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED 1
|
||||
#define CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED 1
|
||||
#define CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1 1
|
||||
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 160
|
||||
#define CONFIG_MBEDTLS_HARDWARE_AES 1
|
||||
#define CONFIG_FREERTOS_HZ 100
|
||||
#define CONFIG_LOG_COLORS 1
|
||||
#define CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE 1
|
||||
#define CONFIG_STACK_CHECK_NONE 1
|
||||
#define CONFIG_ADC_CAL_EFUSE_TP_ENABLE 1
|
||||
#define CONFIG_FREERTOS_ASSERT_FAIL_ABORT 1
|
||||
#define CONFIG_ESP32_XTAL_FREQ 0
|
||||
#define CONFIG_BROWNOUT_DET 1
|
||||
#define CONFIG_ESP32_XTAL_FREQ 40
|
||||
#define CONFIG_MONITOR_BAUD_115200B 1
|
||||
#define CONFIG_LOG_BOOTLOADER_LEVEL 3
|
||||
#define CONFIG_MBEDTLS_TLS_ENABLED 1
|
||||
#define CONFIG_LWIP_MAX_RAW_PCBS 16
|
||||
#define CONFIG_SMP_ENABLE 1
|
||||
#define CONFIG_MBEDTLS_SSL_SESSION_TICKETS 1
|
||||
#define CONFIG_SPIFFS_MAX_PARTITIONS 3
|
||||
#define CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE_0 1
|
||||
#define CONFIG_MBEDTLS_SSL_RENEGOTIATION 1
|
||||
#define CONFIG_ESPTOOLPY_BEFORE_RESET 1
|
||||
#define CONFIG_ESPTOOLPY_BAUD_OTHER_VAL 115200
|
||||
#define CONFIG_ESP32_XTAL_FREQ_AUTO 1
|
||||
#define CONFIG_SPIFFS_OBJ_NAME_LEN 32
|
||||
#define CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT 5
|
||||
#define CONFIG_TCPIP_RECVMBOX_SIZE 32
|
||||
#define CONFIG_TCP_MAXRTX 12
|
||||
#define CONFIG_ESPTOOLPY_AFTER "hard_reset"
|
||||
#define CONFIG_LWIP_SO_REUSE 1
|
||||
#define CONFIG_ESP32_XTAL_FREQ_40 1
|
||||
#define CONFIG_DMA_TX_BUF_NUM 10
|
||||
#define CONFIG_LWIP_MAX_LISTENING_TCP 16
|
||||
#define CONFIG_FREERTOS_INTERRUPT_BACKTRACE 1
|
||||
#define CONFIG_WL_SECTOR_SIZE 4096
|
||||
#define CONFIG_ESP32_DEBUG_OCDAWARE 1
|
||||
#define CONFIG_TIMER_TASK_PRIORITY 1
|
||||
#define CONFIG_MBEDTLS_TLS_CLIENT 1
|
||||
#define CONFIG_BTDM_CONTROLLER_HCI_MODE_VHCI 1
|
||||
#define CONFIG_BT_ENABLED 1
|
||||
#define CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED 1
|
||||
#define CONFIG_MONITOR_BAUD 115200
|
||||
#define CONFIG_FREERTOS_CORETIMER_0 1
|
||||
#define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv"
|
||||
#define CONFIG_MBEDTLS_HAVE_TIME 1
|
||||
#define CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY 1
|
||||
#define CONFIG_TCP_QUEUE_OOSEQ 1
|
||||
#define CONFIG_GATTS_ENABLE 1
|
||||
#define CONFIG_ADC_CAL_EFUSE_VREF_ENABLE 1
|
||||
#define CONFIG_MBEDTLS_TLS_SERVER 1
|
||||
#define CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT 1
|
||||
#define CONFIG_FREERTOS_ISR_STACKSIZE 1536
|
||||
#define CONFIG_OPENSSL_ASSERT_DO_NOTHING 1
|
||||
#define CONFIG_AWS_IOT_MQTT_HOST ""
|
||||
#define CONFIG_WL_SECTOR_SIZE_4096 1
|
||||
#define CONFIG_OPTIMIZATION_LEVEL_DEBUG 1
|
||||
#define CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED 1
|
||||
#define CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED 1
|
||||
#define CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED 1
|
||||
#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA 1
|
||||
#define CONFIG_SYSTEM_EVENT_QUEUE_SIZE 32
|
||||
#define CONFIG_BT_ACL_CONNECTIONS 4
|
||||
#define CONFIG_FATFS_MAX_LFN 255
|
||||
#define CONFIG_ESP32_WIFI_TX_BUFFER_TYPE 1
|
||||
#define CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED 1
|
||||
#define CONFIG_LWIP_LOOPBACK_MAX_PBUFS 8
|
||||
#define CONFIG_APP_OFFSET 0x10000
|
||||
#define CONFIG_MEMMAP_SMP 1
|
||||
#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
|
||||
#define CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED 1
|
||||
#define CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0 1
|
||||
#define CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT 3072
|
||||
#define CONFIG_MONITOR_BAUD_OTHER_VAL 115200
|
||||
#define CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF 1
|
||||
#define CONFIG_ESPTOOLPY_PORT "/dev/ttyUSB0"
|
||||
#define CONFIG_OPTIMIZATION_LEVEL_RELEASE 1
|
||||
#define CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS 1
|
||||
#define CONFIG_BLUEDROID_PINNED_TO_CORE 0
|
||||
|
||||
Reference in New Issue
Block a user