Merge branch 'espressif:release/v5.5' into release/v5.5
This commit is contained in:
Jason2866
@@ -967,7 +967,7 @@ menu "Security features"
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config SECURE_BOOT_SKIP_WRITE_PROTECTION_SCA
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bool "Skip write-protection of SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH"
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default y if SECURE_FLASH_PSEUDO_ROUND_FUNC
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default y if SECURE_FLASH_PSEUDO_ROUND_FUNC && !SECURE_FLASH_ENCRYPTION_MODE_RELEASE
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default n
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depends on SOC_ECDSA_SUPPORT_CURVE_P384 && SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND
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help
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@@ -5,6 +5,14 @@ config BLE_LOG_ENABLED
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Enable BLE Log Module
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if BLE_LOG_ENABLED
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config BLE_LOG_TASK_STACK_SIZE
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int "Stack size for BLE Log Task"
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default 1024 if IDF_TARGET_ARCH_RISCV
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default 2048 if IDF_TARGET_ARCH_XTENSA
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default 1024
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help
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Stack size for BLE Log Task
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config BLE_LOG_LBM_TRANS_SIZE
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int "Buffer size for each peripheral transport"
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default 512
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@@ -41,7 +41,14 @@
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#define SPI_OUT_LOG_STR_BUF_SIZE (100)
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#define SPI_OUT_MALLOC(size) heap_caps_malloc(size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
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#define SPI_OUT_TASK_PRIORITY (ESP_TASK_PRIO_MAX - 1)
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#if CONFIG_IDF_TARGET_ARCH_RISCV
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#define SPI_OUT_TASK_STACK_SIZE (1024)
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#elif CONFIG_IDF_TARGET_ARCH_XTENSA
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#define SPI_OUT_TASK_STACK_SIZE (2048)
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#else
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static_assert(false, "BLE Log SPI Out: Unsupported target architecture");
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#endif /* CONFIG_IDF_TARGET_ARCH_RISCV */
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#if SPI_OUT_TS_SYNC_ENABLED
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#define SPI_OUT_TS_SYNC_TIMEOUT_MS (1000)
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@@ -247,9 +254,9 @@ extern uint32_t r_ble_lll_timer_current_tick_get(void);
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#elif defined(CONFIG_IDF_TARGET_ESP32C2)
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extern uint32_t r_os_cputime_get32(void);
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#define SPI_OUT_GET_LC_TIME r_os_cputime_get32()
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// #elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3)
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// extern uint32_t lld_read_clock_us(void);
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// #define SPI_OUT_GET_LC_TIME lld_read_clock_us()
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#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3)
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extern uint32_t lld_read_clock_us(void);
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#define SPI_OUT_GET_LC_TIME lld_read_clock_us()
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#else
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#define SPI_OUT_GET_LC_TIME esp_timer_get_time()
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#endif
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@@ -1365,12 +1372,13 @@ int ble_log_spi_out_hci_write(uint8_t source, const uint8_t *addr, uint16_t len)
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return -1;
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}
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if (source == BLE_LOG_SPI_OUT_SOURCE_HCI_UPSTREAM) {
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#if SPI_OUT_LL_ENABLED
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if (source == BLE_LOG_SPI_OUT_SOURCE_HCI_UPSTREAM) {
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ble_log_spi_out_ll_write(len, addr, 0, NULL, BIT(LL_LOG_FLAG_HCI_UPSTREAM));
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#endif // SPI_OUT_LL_ENABLED
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}
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if (source == BLE_LOG_SPI_OUT_SOURCE_HCI_DOWNSTREAM) {
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if (source == BLE_LOG_SPI_OUT_SOURCE_HCI_DOWNSTREAM)
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#endif /* SPI_OUT_LL_ENABLED */
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{
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spi_out_log_cb_t *log_cb;
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bool fallback = false;
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if (!spi_out_get_task_mapping(LOG_MODULE_TASK_MAP(hci),
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@@ -21,7 +21,7 @@
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/* MACRO */
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#define BLE_LOG_TASK_PRIO (ESP_TASK_PRIO_MAX - 1)
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#define BLE_LOG_TASK_STACK_SIZE (1024)
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#define BLE_LOG_TASK_STACK_SIZE CONFIG_BLE_LOG_TASK_STACK_SIZE
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#define BLE_LOG_TASK_HOOK_TIMEOUT_MS (1000)
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/* INTERFACE */
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@@ -241,8 +241,5 @@ void *osi_calloc_func(size_t size)
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void osi_free_func(void *ptr)
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{
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#if HEAP_MEMORY_DEBUG
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osi_mem_dbg_clean(ptr, __func__, __LINE__);
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#endif
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free(ptr);
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osi_free(ptr);
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}
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@@ -616,15 +616,15 @@ menu "Controller debug log Options (Experimental)"
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config BT_CTRL_LE_LOG_MODE_EN
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depends on BT_CTRL_LE_LOG_EN
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int "Enable log for specified BLE mode"
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range 0 4095
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default 4093
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hex "Enable log for specified BLE mode"
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range 0 0xFFFF
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default 0xDB7F
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config BT_CTRL_LE_LOG_LEVEL
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depends on BT_CTRL_LE_LOG_EN
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int "The level of BLE log"
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range 0 5
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default 2
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default 1
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config BT_CTRL_LE_LOG_BUF1_SIZE
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depends on BT_CTRL_LE_LOG_EN
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@@ -241,7 +241,12 @@ struct osi_funcs_t {
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};
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#if CONFIG_BT_CTRL_LE_LOG_EN
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typedef void (*interface_func_t) (uint32_t len, const uint8_t*addr, bool end);
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typedef void (*interface_func_t) (uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag);
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enum {
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BLE_LOG_INTERFACE_FLAG_CONTINUE = 0,
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BLE_LOG_INTERFACE_FLAG_END,
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};
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#endif // CONFIG_BT_CTRL_LE_LOG_EN
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/* External functions or values
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@@ -304,11 +309,14 @@ extern void btdm_aa_check_enhance_enable(void);
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/* BLE Log module */
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#if CONFIG_BT_CTRL_LE_LOG_EN
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extern int r_ble_log_init_simple(interface_func_t interface, void *handler);
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extern void r_ble_log_deinit_simple(void);
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extern int r_ble_log_init_async(interface_func_t bt_controller_log_interface, bool task_create, uint8_t buffers, uint32_t *bufs_size);
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extern int r_ble_log_deinit_async(void);
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extern void r_ble_log_async_select_dump_buffers(uint8_t buffers);
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extern void r_ble_log_async_output_dump_all(bool output);
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extern void esp_panic_handler_feed_wdts(void);
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extern int r_ble_log_ctrl_level_and_mod(uint8_t level, uint32_t mod_en);
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#endif // CONFIG_BT_CTRL_LE_LOG_EN
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#if (CONFIG_BT_BLUEDROID_ENABLED || CONFIG_BT_NIMBLE_ENABLED)
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extern void scan_stack_enableAdvFlowCtrlVsCmd(bool en);
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@@ -399,12 +407,13 @@ static esp_err_t try_heap_caps_add_region(intptr_t start, intptr_t end);
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static void bt_controller_deinit_internal(void);
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#if CONFIG_BT_CTRL_LE_LOG_EN
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static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end);
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#if !CONFIG_BT_CTRL_LE_LOG_MODE_BLE_LOG_V2
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#if CONFIG_BT_CTRL_LE_LOG_STORAGE_EN
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void esp_bt_read_ctrl_log_from_flash(bool output);
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static int esp_bt_controller_log_storage(uint32_t len, const uint8_t *addr, bool end);
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static void esp_bt_ctrl_log_partition_get_and_erase_first_block(void);
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#endif // #if CONFIG_BT_CTRL_LE_LOG_STORAGE_EN
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#endif // CONFIG_BT_CTRL_LE_LOG_STORAGE_EN
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#endif // !CONFIG_BT_CTRL_LE_LOG_MODE_BLE_LOG_V2
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#endif // CONFIG_BT_CTRL_LE_LOG_EN
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/* Local variable definition
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@@ -538,18 +547,14 @@ static bool is_filled = false;
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#endif // CONFIG_BT_CTRL_LE_LOG_STORAGE_EN
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#if CONFIG_BT_CTRL_LE_LOG_MODE_BLE_LOG_V2
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static IRAM_ATTR void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end)
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{
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ble_log_write_hex_ll(len, addr, 0, NULL, 0);
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}
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void esp_ble_controller_log_dump_all(bool output)
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{
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ble_log_dump_to_console();
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}
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#else /* !CONFIG_BT_CTRL_LE_LOG_MODE_BLE_LOG_V2 */
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static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end)
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static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag)
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{
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bool end = (flag & BIT(BLE_LOG_INTERFACE_FLAG_END));
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if (log_output_mode == LOG_STORAGE_TO_FLASH) {
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#if CONFIG_BT_CTRL_LE_LOG_STORAGE_EN
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esp_bt_controller_log_storage(len, addr, end);
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@@ -558,24 +563,19 @@ static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, b
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portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
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portENTER_CRITICAL_SAFE(&spinlock);
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esp_panic_handler_feed_wdts();
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for (int i = 0; i < len; i++) {
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esp_rom_printf("%02x ", addr[i]);
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}
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if (end) {
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esp_rom_printf("\n");
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if (len && addr) {
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for (int i = 0; i < len; i++) { esp_rom_printf("%02x ", addr[i]); }
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}
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if (len_append && addr_append) {
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for (int i = 0; i < len_append; i++) { esp_rom_printf("%02x ", addr_append[i]); }
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}
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if (end) { esp_rom_printf("\n"); }
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portEXIT_CRITICAL_SAFE(&spinlock);
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}
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}
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#if CONFIG_BT_CTRL_LE_LOG_SPI_OUT_EN
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static IRAM_ATTR void esp_bt_controller_spi_log_interface(uint32_t len, const uint8_t *addr, bool end)
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{
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ble_log_spi_out_ll_write(len, addr, 0, NULL, 0);
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}
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#endif // CONFIG_BT_CTRL_LE_LOG_SPI_OUT_EN
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void esp_ble_controller_log_dump_all(bool output)
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{
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if (log_output_mode == LOG_STORAGE_TO_FLASH) {
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@@ -612,16 +612,13 @@ esp_err_t esp_bt_controller_log_init(uint8_t log_output_mode)
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}
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esp_err_t ret = ESP_OK;
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uint8_t buffers = 0;
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#if CONFIG_BT_CTRL_LE_LOG_EN
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buffers |= ESP_BLE_LOG_BUF_CONTROLLER;
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#endif // CONFIG_BT_CTRL_LE_LOG_EN
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#if CONFIG_BT_CTRL_LE_HCI_LOG_EN
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buffers |= ESP_BLE_LOG_BUF_HCI;
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#endif // CONFIG_BT_CTRL_LE_HCI_LOG_EN
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ret = r_ble_log_init_simple(ble_log_write_hex_ll, NULL);
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if (ret != ESP_OK) {
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return ret;
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}
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ret = r_ble_log_init_async(esp_bt_controller_log_interface, true, buffers, (uint32_t *)log_bufs_size);
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ret = r_ble_log_ctrl_level_and_mod(BLE_LOG_LEVEL, BLE_LOG_MODE_EN);
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if (ret == ESP_OK) {
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log_is_inited = true;
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}
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@@ -664,7 +661,7 @@ esp_err_t esp_bt_controller_log_init(uint8_t log_output_mode)
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case LOG_SPI_OUT:
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task_create = true;
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#if CONFIG_BT_CTRL_LE_LOG_SPI_OUT_EN
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bt_controller_log_interface = esp_bt_controller_spi_log_interface;
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bt_controller_log_interface = ble_log_spi_out_ll_write;
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#endif // CONFIG_BT_CTRL_LE_LOG_SPI_OUT_EN
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break;
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default:
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@@ -672,6 +669,11 @@ esp_err_t esp_bt_controller_log_init(uint8_t log_output_mode)
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}
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ret = r_ble_log_init_async(bt_controller_log_interface, task_create, buffers, (uint32_t *)log_bufs_size);
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if (ret != ESP_OK) {
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return ret;
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}
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ret = r_ble_log_ctrl_level_and_mod(BLE_LOG_LEVEL, BLE_LOG_MODE_EN);
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if (ret == ESP_OK) {
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log_is_inited = true;
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}
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Submodule components/bt/controller/lib_esp32c3_family updated: 42c965137e...099a7e1ab8
@@ -223,7 +223,7 @@ void bt_mesh_ble_ext_adv_report(tBTM_BLE_EXT_ADV_REPORT *ext_adv_report)
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memcpy(adv_rpt.dir_addr, ext_adv_report->dir_addr, BLE_MESH_ADDR_LEN);
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adv_rpt.addr_type = ext_adv_report->addr_type;
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adv_rpt.data = ext_adv_report->adv_data;
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adv_rpt.data = ext_adv_report->adv_data_len ? ext_adv_report->adv_data : NULL;
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adv_rpt.length = ext_adv_report->adv_data_len;
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adv_rpt.rssi = ext_adv_report->rssi;
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adv_rpt.event_type = ext_adv_report->event_type;
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@@ -474,7 +474,7 @@ void bt_mesh_ble_ext_adv_report(struct ble_gap_ext_disc_desc *desc)
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/* Here, only a shallow copy needs to be implemented;
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* deep copying behavior occurs in btc_ble_mesh_ble_copy_req_data. */
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adv_rpt.data = desc->data;
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adv_rpt.data = desc->length_data ? desc->data : NULL;
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adv_rpt.event_type = desc->props;
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adv_rpt.addr_type = desc->addr.type;
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@@ -380,7 +380,7 @@ static void inline callback_ble_adv_pkt(const bt_mesh_addr_t *addr,
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adv_rpt.addr_type = addr->type;
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adv_rpt.adv_type = adv_type;
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adv_rpt.length = length;
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adv_rpt.data = data;
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adv_rpt.data = length ? data : NULL;
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adv_rpt.rssi = rssi;
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bt_mesh_ble_scan_cb_evt_to_btc(&adv_rpt);
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}
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@@ -133,7 +133,7 @@ esp_err_t esp_bt_hid_device_send_report(esp_hidd_report_type_t type, uint8_t id,
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args.send_report.data = data;
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bt_status_t stat = btc_transfer_context(&msg, &args, sizeof(btc_hidd_args_t),
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btc_hd_arg_deep_copy, btc_hd_cb_arg_deep_free);
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btc_hd_arg_deep_copy, btc_hd_call_arg_deep_free);
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return (stat == BT_STATUS_SUCCESS) ? ESP_OK : ESP_FAIL;
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}
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@@ -117,7 +117,7 @@ esp_err_t esp_bt_hid_host_set_info(esp_bd_addr_t bd_addr, esp_hidh_hid_info_t *h
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arg.set_info.hid_info = hid_info;
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bt_status_t stat = btc_transfer_context(&msg, &arg, sizeof(btc_hidh_args_t),
|
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btc_hh_arg_deep_copy, btc_hh_cb_arg_deep_free);
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btc_hh_arg_deep_copy, btc_hh_call_arg_deep_free);
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return (stat == BT_STATUS_SUCCESS) ? ESP_OK : ESP_FAIL;
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}
|
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|
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@@ -224,7 +224,7 @@ esp_err_t esp_bt_hid_host_set_report(esp_bd_addr_t bd_addr, esp_hidh_report_type
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arg.set_report.report = report;
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|
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bt_status_t stat = btc_transfer_context(&msg, &arg, sizeof(btc_hidh_args_t),
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btc_hh_arg_deep_copy, btc_hh_cb_arg_deep_free);
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btc_hh_arg_deep_copy, btc_hh_call_arg_deep_free);
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||||
return (stat == BT_STATUS_SUCCESS) ? ESP_OK : ESP_FAIL;
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||||
}
|
||||
|
||||
@@ -243,7 +243,7 @@ esp_err_t esp_bt_hid_host_send_data(esp_bd_addr_t bd_addr, uint8_t *data, size_t
|
||||
arg.send_data.data = data;
|
||||
|
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bt_status_t stat = btc_transfer_context(&msg, &arg, sizeof(btc_hidh_args_t),
|
||||
btc_hh_arg_deep_copy, btc_hh_cb_arg_deep_free);
|
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btc_hh_arg_deep_copy, btc_hh_call_arg_deep_free);
|
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return (stat == BT_STATUS_SUCCESS) ? ESP_OK : ESP_FAIL;
|
||||
}
|
||||
|
||||
|
||||
@@ -75,6 +75,8 @@ btc_hd_cb_t btc_hd_cb = {0};
|
||||
|
||||
typedef void (bt_hid_copy_cb_t)(btc_msg_t *msg, void *p_dest, void *p_src);
|
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|
||||
static void btc_hd_cb_arg_deep_free(btc_msg_t *msg);
|
||||
|
||||
static inline void btc_hd_cb_to_app(esp_hidd_cb_event_t event, esp_hidd_cb_param_t *param)
|
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{
|
||||
esp_hd_cb_t btc_hd_cb = (esp_hd_cb_t)btc_profile_cb_get(BTC_PID_HD);
|
||||
@@ -705,7 +707,7 @@ static void btc_hd_virtual_cable_unplug(void)
|
||||
}
|
||||
}
|
||||
|
||||
static void btc_hd_call_arg_deep_free(btc_msg_t *msg)
|
||||
void btc_hd_call_arg_deep_free(btc_msg_t *msg)
|
||||
{
|
||||
btc_hidd_args_t *arg = (btc_hidd_args_t *)msg->arg;
|
||||
|
||||
@@ -756,7 +758,7 @@ void btc_hd_call_handler(btc_msg_t *msg)
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btc_hd_call_arg_deep_free(msg);
|
||||
}
|
||||
|
||||
void btc_hd_cb_arg_deep_free(btc_msg_t *msg)
|
||||
static void btc_hd_cb_arg_deep_free(btc_msg_t *msg)
|
||||
{
|
||||
tBTA_HD *arg = (tBTA_HD *)msg->arg;
|
||||
|
||||
|
||||
@@ -64,6 +64,8 @@ static bdstr_t bdstr;
|
||||
#define is_hidh_init() (btc_hh_cb.status > BTC_HH_DISABLED)
|
||||
#define BTC_TIMEOUT_VUP_MS (3 * 1000)
|
||||
|
||||
static void btc_hh_cb_arg_deep_free(btc_msg_t *msg);
|
||||
|
||||
static inline void btc_hh_cb_to_app(esp_hidh_cb_event_t event, esp_hidh_cb_param_t *param)
|
||||
{
|
||||
esp_hh_cb_t btc_hh_cb = (esp_hh_cb_t)btc_profile_cb_get(BTC_PID_HH);
|
||||
@@ -1097,7 +1099,7 @@ static void btc_hh_set_idle_time(btc_hidh_args_t *arg)
|
||||
}
|
||||
}
|
||||
|
||||
static void btc_hh_call_arg_deep_free(btc_msg_t *msg)
|
||||
void btc_hh_call_arg_deep_free(btc_msg_t *msg)
|
||||
{
|
||||
btc_hidh_args_t *arg = (btc_hidh_args_t *)msg->arg;
|
||||
|
||||
@@ -1166,7 +1168,7 @@ void btc_hh_call_handler(btc_msg_t *msg)
|
||||
btc_hh_call_arg_deep_free(msg);
|
||||
}
|
||||
|
||||
void btc_hh_cb_arg_deep_free(btc_msg_t *msg)
|
||||
static void btc_hh_cb_arg_deep_free(btc_msg_t *msg)
|
||||
{
|
||||
tBTA_HH *arg = (tBTA_HH *)msg->arg;
|
||||
|
||||
|
||||
@@ -99,7 +99,7 @@ void btc_hd_call_handler(btc_msg_t *msg);
|
||||
void btc_hd_cb_handler(btc_msg_t *msg);
|
||||
|
||||
void btc_hd_arg_deep_copy(btc_msg_t *msg, void *p_dest, void *p_src);
|
||||
void btc_hd_cb_arg_deep_free(btc_msg_t *msg);
|
||||
void btc_hd_call_arg_deep_free(btc_msg_t *msg);
|
||||
|
||||
void btc_hd_get_profile_status(esp_hidd_profile_status_t *param);
|
||||
|
||||
|
||||
@@ -181,8 +181,7 @@ void btc_hh_call_handler(btc_msg_t *msg);
|
||||
void btc_hh_cb_handler(btc_msg_t *msg);
|
||||
|
||||
void btc_hh_arg_deep_copy(btc_msg_t *msg, void *p_dest, void *p_src);
|
||||
|
||||
void btc_hh_cb_arg_deep_free(btc_msg_t *msg);
|
||||
void btc_hh_call_arg_deep_free(btc_msg_t *msg);
|
||||
|
||||
bool btc_hh_add_added_dev(BD_ADDR bd_addr, uint16_t attr_mask);
|
||||
|
||||
|
||||
@@ -240,13 +240,6 @@ tBTM_STATUS BTM_SetDiscoverability (UINT16 inq_mode, UINT16 window, UINT16 inter
|
||||
scan_mode |= HCI_PAGE_SCAN_ENABLED;
|
||||
}
|
||||
|
||||
if (btsnd_hcic_write_scan_enable (scan_mode)) {
|
||||
btm_cb.btm_inq_vars.discoverable_mode &= (~BTM_DISCOVERABLE_MASK);
|
||||
btm_cb.btm_inq_vars.discoverable_mode |= inq_mode;
|
||||
} else {
|
||||
return (BTM_NO_RESOURCES);
|
||||
}
|
||||
|
||||
/* Change the service class bit if mode has changed */
|
||||
p_cod = BTM_ReadDeviceClass();
|
||||
BTM_COD_SERVICE_CLASS(service_class, p_cod);
|
||||
@@ -266,6 +259,13 @@ tBTM_STATUS BTM_SetDiscoverability (UINT16 inq_mode, UINT16 window, UINT16 inter
|
||||
(void) BTM_SetDeviceClass (cod);
|
||||
}
|
||||
|
||||
if (btsnd_hcic_write_scan_enable (scan_mode)) {
|
||||
btm_cb.btm_inq_vars.discoverable_mode &= (~BTM_DISCOVERABLE_MASK);
|
||||
btm_cb.btm_inq_vars.discoverable_mode |= inq_mode;
|
||||
} else {
|
||||
return (BTM_NO_RESOURCES);
|
||||
}
|
||||
|
||||
return (BTM_SUCCESS);
|
||||
}
|
||||
|
||||
|
||||
@@ -775,6 +775,7 @@ tHID_STATUS hidd_conn_send_data(uint8_t channel, uint8_t msg_type, uint8_t param
|
||||
}
|
||||
return HID_SUCCESS;
|
||||
}
|
||||
osi_free(p_buf);
|
||||
return HID_ERR_NO_CONNECTION;
|
||||
}
|
||||
#ifdef REPORT_TRANSFER_TIMESTAMP
|
||||
|
||||
@@ -25,7 +25,6 @@
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "osi/allocator.h"
|
||||
#include "device/controller.h"
|
||||
#include "stack/bt_types.h"
|
||||
#include "stack/hcimsgs.h"
|
||||
@@ -36,6 +35,7 @@
|
||||
#include "stack/btm_api.h"
|
||||
#include "btm_int.h"
|
||||
#include "stack/hcidefs.h"
|
||||
#include "bt_common.h"
|
||||
#include "osi/allocator.h"
|
||||
#include "osi/list.h"
|
||||
|
||||
|
||||
@@ -30,7 +30,7 @@ extern "C" {
|
||||
*
|
||||
* @note Please do not modify this value
|
||||
*/
|
||||
#define ESP_BT_CTRL_CONFIG_VERSION 0x02505080
|
||||
#define ESP_BT_CTRL_CONFIG_VERSION 0x02509280
|
||||
|
||||
/**
|
||||
* @brief Internal use only
|
||||
@@ -376,8 +376,6 @@ typedef void (* esp_bt_hci_tl_callback_t) (void *arg, uint8_t status);
|
||||
.connect_en = BT_CTRL_BLE_MASTER, \
|
||||
.scan_en = BT_CTRL_BLE_SCAN, \
|
||||
.ble_aa_check = BLE_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS_ENABLED, \
|
||||
.ble_log_mode_en = BLE_LOG_MODE_EN, \
|
||||
.ble_log_level = BLE_LOG_LEVEL, \
|
||||
.adv_en = BT_CTRL_BLE_ADV, \
|
||||
}
|
||||
|
||||
@@ -504,8 +502,6 @@ typedef struct {
|
||||
bool connect_en; /*!< True if the connection feature is enabled (default); false otherwise. Configurable in menuconfig.*/
|
||||
bool scan_en; /*!< True if the scan feature is enabled (default); false otherwise. Configurable in menuconfig.*/
|
||||
bool ble_aa_check; /*!< True if adds a verification step for the Access Address within the CONNECT_IND PDU; false otherwise. Configurable in menuconfig */
|
||||
uint32_t ble_log_mode_en; /*!< BLE log mode enable */
|
||||
uint8_t ble_log_level; /*!< BLE log level */
|
||||
bool adv_en; /*!< True if the ADV feature is enabled (default); false otherwise. Configurable in menuconfig.*/
|
||||
} esp_bt_controller_config_t;
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,326 @@
|
||||
|
||||
# field_name, | efuse_block, | bit_start, | bit_count, |comment #
|
||||
# | (EFUSE_BLK0 | (0..255) | (1-256) | #
|
||||
# | EFUSE_BLK1 | | | #
|
||||
# | ...) | | | #
|
||||
##########################################################################
|
||||
# !!!!!!!!!!! #
|
||||
# After editing this file, run the command manually "idf.py efuse-common-table"
|
||||
# this will generate new source files, next rebuild all the sources.
|
||||
# !!!!!!!!!!! #
|
||||
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: 0b11fcae5408d9e48251cefb10178c11
|
||||
|
||||
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
|
||||
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
|
||||
WR_DIS.KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_RND_SWITCH_CYCLE
|
||||
WR_DIS.KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DEPLOY_ONLY_ONCE
|
||||
WR_DIS.FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of FORCE_USE_KEY_MANAGER_KEY
|
||||
WR_DIS.FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of FORCE_DISABLE_SW_INIT_KEY
|
||||
WR_DIS.KM_XTS_KEY_LENGTH_256, EFUSE_BLK0, 1, 1, [] wr_dis of KM_XTS_KEY_LENGTH_256
|
||||
WR_DIS.KM_DEPLOY_ONLY_ONCE_H, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DEPLOY_ONLY_ONCE_H
|
||||
WR_DIS.FORCE_USE_KEY_MANAGER_KEY_H, EFUSE_BLK0, 1, 1, [] wr_dis of FORCE_USE_KEY_MANAGER_KEY_H
|
||||
WR_DIS.LOCK_KM_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of LOCK_KM_KEY
|
||||
WR_DIS.KM_DISABLE_DEPLOY_MODE_H, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DISABLE_DEPLOY_MODE_H
|
||||
WR_DIS.KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DISABLE_DEPLOY_MODE
|
||||
WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG
|
||||
WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD
|
||||
WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 2, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
|
||||
WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_TWAI
|
||||
WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE
|
||||
WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG
|
||||
WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
|
||||
WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 2, 1, [] wr_dis of WDT_DELAY_SEL
|
||||
WR_DIS.HYS_EN_PAD, EFUSE_BLK0, 2, 1, [] wr_dis of HYS_EN_PAD
|
||||
WR_DIS.PXA0_TIEH_SEL_0, EFUSE_BLK0, 2, 1, [] wr_dis of PXA0_TIEH_SEL_0
|
||||
WR_DIS.DIS_WDT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_WDT
|
||||
WR_DIS.DIS_SWD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_SWD
|
||||
WR_DIS.PVT_GLITCH_EN, EFUSE_BLK0, 3, 1, [] wr_dis of PVT_GLITCH_EN
|
||||
WR_DIS.PVT_GLITCH_MODE, EFUSE_BLK0, 3, 1, [] wr_dis of PVT_GLITCH_MODE
|
||||
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
|
||||
WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
|
||||
WR_DIS.KEY_PURPOSE_0_H, EFUSE_BLK0, 8, 1, [] wr_dis of KEY_PURPOSE_0_H
|
||||
WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
|
||||
WR_DIS.KEY_PURPOSE_1_H, EFUSE_BLK0, 9, 1, [] wr_dis of KEY_PURPOSE_1_H
|
||||
WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
|
||||
WR_DIS.KEY_PURPOSE_2_H, EFUSE_BLK0, 10, 1, [] wr_dis of KEY_PURPOSE_2_H
|
||||
WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
|
||||
WR_DIS.KEY_PURPOSE_3_H, EFUSE_BLK0, 11, 1, [] wr_dis of KEY_PURPOSE_3_H
|
||||
WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
|
||||
WR_DIS.KEY_PURPOSE_4_H, EFUSE_BLK0, 12, 1, [] wr_dis of KEY_PURPOSE_4_H
|
||||
WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
|
||||
WR_DIS.KEY_PURPOSE_5_H, EFUSE_BLK0, 13, 1, [] wr_dis of KEY_PURPOSE_5_H
|
||||
WR_DIS.ECC_FORCE_CONST_TIME, EFUSE_BLK0, 14, 1, [] wr_dis of ECC_FORCE_CONST_TIME
|
||||
WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of SEC_DPA_LEVEL
|
||||
WR_DIS.XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_CLK_ENABLE
|
||||
WR_DIS.XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_PSEUDO_LEVEL
|
||||
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN
|
||||
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
|
||||
WR_DIS.HP_PWR_SRC_SEL, EFUSE_BLK0, 17, 1, [] wr_dis of HP_PWR_SRC_SEL
|
||||
WR_DIS.FLASH_ECC_EN, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_ECC_EN
|
||||
WR_DIS.DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE
|
||||
WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW
|
||||
WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE
|
||||
WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DIRECT_BOOT
|
||||
WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
|
||||
WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
|
||||
WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
|
||||
WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL
|
||||
WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME
|
||||
WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION
|
||||
WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE
|
||||
WR_DIS.HUK_GEN_STATE, EFUSE_BLK0, 19, 1, [] wr_dis of HUK_GEN_STATE
|
||||
WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1
|
||||
WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
|
||||
WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR
|
||||
WR_DIS.WAFER_VERSION_MAJOR_LO, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR_LO
|
||||
WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
|
||||
WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
|
||||
WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR
|
||||
WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR
|
||||
WR_DIS.PSRAM_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_CAP
|
||||
WR_DIS.TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of TEMP
|
||||
WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR
|
||||
WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
|
||||
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
|
||||
WR_DIS.WAFER_VERSION_MAJOR_HI, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR_HI
|
||||
WR_DIS.LDO_VO1_DREF, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO1_DREF
|
||||
WR_DIS.LDO_VO2_DREF, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO2_DREF
|
||||
WR_DIS.LDO_VO1_MUL, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO1_MUL
|
||||
WR_DIS.LDO_VO2_MUL, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO2_MUL
|
||||
WR_DIS.LDO_VO3_K, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO3_K
|
||||
WR_DIS.LDO_VO3_VOS, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO3_VOS
|
||||
WR_DIS.LDO_VO3_C, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO3_C
|
||||
WR_DIS.LDO_VO4_K, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO4_K
|
||||
WR_DIS.LDO_VO4_VOS, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO4_VOS
|
||||
WR_DIS.LDO_VO4_C, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO4_C
|
||||
WR_DIS.ACTIVE_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_HP_DBIAS
|
||||
WR_DIS.ACTIVE_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_LP_DBIAS
|
||||
WR_DIS.DSLP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_DBG
|
||||
WR_DIS.DSLP_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBIAS
|
||||
WR_DIS.LP_DCDC_DBIAS_VOL_GAP, EFUSE_BLK0, 20, 1, [] wr_dis of LP_DCDC_DBIAS_VOL_GAP
|
||||
WR_DIS.PVT_400M_BIAS, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_400M_BIAS
|
||||
WR_DIS.PVT_40M_BIAS, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_40M_BIAS
|
||||
WR_DIS.PVT_100M_BIAS, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_100M_BIAS
|
||||
WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
|
||||
WR_DIS.ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
|
||||
WR_DIS.ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
|
||||
WR_DIS.ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
|
||||
WR_DIS.ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
|
||||
WR_DIS.ADC2_AVE_INITCODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN0
|
||||
WR_DIS.ADC2_AVE_INITCODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN1
|
||||
WR_DIS.ADC2_AVE_INITCODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN2
|
||||
WR_DIS.ADC2_AVE_INITCODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN3
|
||||
WR_DIS.ADC1_HI_DOUT_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN0
|
||||
WR_DIS.ADC1_HI_DOUT_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN1
|
||||
WR_DIS.ADC1_HI_DOUT_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN2
|
||||
WR_DIS.ADC1_HI_DOUT_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN3
|
||||
WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
|
||||
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
|
||||
WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
|
||||
WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
|
||||
WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
|
||||
WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
|
||||
WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
|
||||
WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
|
||||
WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
|
||||
WR_DIS.ADC2_HI_DOUT_ATTEN0, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_HI_DOUT_ATTEN0
|
||||
WR_DIS.ADC2_HI_DOUT_ATTEN1, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_HI_DOUT_ATTEN1
|
||||
WR_DIS.ADC2_HI_DOUT_ATTEN2, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_HI_DOUT_ATTEN2
|
||||
WR_DIS.ADC2_HI_DOUT_ATTEN3, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_HI_DOUT_ATTEN3
|
||||
WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH6_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH7_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC2_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC2_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC2_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC2_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC2_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC2_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.TEMPERATURE_SENSOR, EFUSE_BLK0, 29, 1, [] wr_dis of TEMPERATURE_SENSOR
|
||||
WR_DIS.USB_DEVICE_EXCHG_PINS, EFUSE_BLK0, 29, 1, [] wr_dis of USB_DEVICE_EXCHG_PINS
|
||||
WR_DIS.USB_OTG11_EXCHG_PINS, EFUSE_BLK0, 29, 1, [] wr_dis of USB_OTG11_EXCHG_PINS
|
||||
WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG
|
||||
RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10
|
||||
RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
|
||||
RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
|
||||
RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
|
||||
RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
|
||||
RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
|
||||
RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
|
||||
RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
|
||||
RD_DIS.ADC2_HI_DOUT_ATTEN0, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_HI_DOUT_ATTEN0
|
||||
RD_DIS.ADC2_HI_DOUT_ATTEN1, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_HI_DOUT_ATTEN1
|
||||
RD_DIS.ADC2_HI_DOUT_ATTEN2, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_HI_DOUT_ATTEN2
|
||||
RD_DIS.ADC2_HI_DOUT_ATTEN3, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_HI_DOUT_ATTEN3
|
||||
RD_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC1_CH6_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC1_CH7_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC2_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC2_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC2_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC2_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC2_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC2_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.TEMPERATURE_SENSOR, EFUSE_BLK0, 38, 1, [] rd_dis of TEMPERATURE_SENSOR
|
||||
RD_DIS.USB_DEVICE_EXCHG_PINS, EFUSE_BLK0, 38, 1, [] rd_dis of USB_DEVICE_EXCHG_PINS
|
||||
RD_DIS.USB_OTG11_EXCHG_PINS, EFUSE_BLK0, 38, 1, [] rd_dis of USB_OTG11_EXCHG_PINS
|
||||
RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1, EFUSE_BLK0, 39, 2, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
|
||||
DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Set this bit to disable function of usb switch to jtag in module of usb device
|
||||
RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2, EFUSE_BLK0, 42, 1, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
|
||||
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Set this bit to disable the function that forces chip into download mode
|
||||
SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 45, 1, [] Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download
|
||||
DIS_TWAI, EFUSE_BLK0, 46, 1, [] Set this bit to disable TWAI function
|
||||
JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
|
||||
SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Set odd bits to disable JTAG in the soft way. JTAG can be enabled in HMAC module
|
||||
DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Set this bit to disable flash manual encrypt function (except in SPI boot mode)
|
||||
RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6, EFUSE_BLK0, 53, 4, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
|
||||
USB_PHY_SEL, EFUSE_BLK0, 57, 1, [] 0: intphy(gpio24/25) <---> usb_device 1: intphy(26/27) <---> usb_otg11.1: intphy(gpio26/27) <---> usb_device 1: intphy(24/25) <---> usb_otg11
|
||||
HUK_GEN_STATE, EFUSE_BLK0, 58, 5, [] Set the bits to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid
|
||||
RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7, EFUSE_BLK0, 63, 1, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
|
||||
RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10, EFUSE_BLK0, 64, 3, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
|
||||
RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11, EFUSE_BLK0, 67, 1, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
|
||||
KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 68, 1, [] Set the bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
|
||||
KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 69, 4, [] EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field: {EFUSE_KM_DEPLOY_ONLY_ONCE_H; EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram
|
||||
, EFUSE_BLK0, 118, 1, [] EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field: {EFUSE_KM_DEPLOY_ONLY_ONCE_H; EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram
|
||||
FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 73, 4, [] EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H; EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram
|
||||
, EFUSE_BLK0, 119, 1, [] EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H; EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram
|
||||
FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 77, 1, [] Set this bit to disable software written init key; and force use efuse_init_key
|
||||
KM_XTS_KEY_LENGTH_256, EFUSE_BLK0, 78, 1, [] Set this bit to config flash encryption xts-512 key; else use xts-256 key when using the key manager
|
||||
ECC_FORCE_CONST_TIME, EFUSE_BLK0, 79, 1, [] Set this bit to permanently turn on ECC const-time mode
|
||||
WDT_DELAY_SEL, EFUSE_BLK0, 81, 1, [] Select lp wdt timeout threshold at startup = initial timeout value * (2 ^ (EFUSE_WDT_DELAY_SEL + 1))
|
||||
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
|
||||
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key
|
||||
KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Purpose of Key0
|
||||
, EFUSE_BLK0, 155, 1, [] Purpose of Key0. The 5-th bit
|
||||
KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Purpose of Key1
|
||||
, EFUSE_BLK0, 156, 1, [] Purpose of Key1. The 5-th bit
|
||||
KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Purpose of Key2
|
||||
, EFUSE_BLK0, 157, 1, [] Purpose of Key2. The 5-th bit
|
||||
KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Purpose of Key3
|
||||
, EFUSE_BLK0, 158, 1, [] Purpose of Key3. The 5-th bit
|
||||
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Purpose of Key4
|
||||
, EFUSE_BLK0, 159, 1, [] Purpose of Key4. The 5-th bit
|
||||
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Purpose of Key5
|
||||
, EFUSE_BLK0, 164, 1, [] Purpose of Key5. The 5-th bit
|
||||
SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, [] Configures the clock random divide mode to determine the dpa secure level
|
||||
XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 115, 1, [] Sets this bit to enable xts clock anti-dpa attack function
|
||||
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Set this bit to enable secure boot
|
||||
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Set this bit to enable revoking aggressive secure boot
|
||||
FLASH_ECC_EN, EFUSE_BLK0, 122, 1, [] Set this bit to enable ECC for flash boot
|
||||
DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 123, 1, [] Set this bit to disable download via USB-OTG
|
||||
FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Configures flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the configurable value. Otherwise; the waiting time is 30
|
||||
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 4; 5; 6; 7)
|
||||
DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [] Set this bit to disable direct boot mode
|
||||
DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [] Set this bit to disable USB-Serial-JTAG print during rom boot
|
||||
LOCK_KM_KEY, EFUSE_BLK0, 131, 1, [] set this bit to lock the key manager key after deploy
|
||||
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [] Set this bit to disable the USB-Serial-JTAG download function
|
||||
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Set this bit to enable security download mode
|
||||
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the type of UART printing; 00: force enable printing; 01: enable printing when GPIO8 is reset at low level; 10: enable printing when GPIO8 is reset at high level; 11: force disable printing
|
||||
FORCE_SEND_RESUME, EFUSE_BLK0, 136, 1, [] Set this bit to force ROM code to send a resume command during SPI boot
|
||||
SECURE_VERSION, EFUSE_BLK0, 137, 16, [] Secure version used by ESP-IDF anti-rollback feature
|
||||
SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 153, 1, [] Represents whether secure boot do fast verification on wake is disabled. 0: enabled 1: disabled
|
||||
HYS_EN_PAD, EFUSE_BLK0, 154, 1, [] Set bits to enable hysteresis function of PAD0~27
|
||||
PXA0_TIEH_SEL_0, EFUSE_BLK0, 160, 2, [] Output LDO VO0 tieh source select. 0: 1'b1 1: sdmmc1 2: reg 3:sdmmc0
|
||||
PVT_GLITCH_EN, EFUSE_BLK0, 162, 1, [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable
|
||||
KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 168, 4, [] EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H; EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set each bit to control whether corresponding key's deploy mode of new value deployment is disabled. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram
|
||||
, EFUSE_BLK0, 167, 1, [] EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H; EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set each bit to control whether corresponding key's deploy mode of new value deployment is disabled. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram
|
||||
XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 176, 2, [] Sets this bit to control the xts pseudo-round anti-dpa attack function. 0: controlled by register. 1-3: the higher the value is; the more pseudo-rounds are inserted to the xts-aes calculation
|
||||
HP_PWR_SRC_SEL, EFUSE_BLK0, 178, 1, [] HP system power source select. 0:LDO 1: DCDC
|
||||
SECURE_BOOT_SHA384_EN, EFUSE_BLK0, 179, 1, [] Represents whether secure boot using SHA-384 is enabled. 0: disable 1: enable
|
||||
DIS_WDT, EFUSE_BLK0, 180, 1, [] Set this bit to disable watch dog
|
||||
DIS_SWD, EFUSE_BLK0, 181, 1, [] Set bit to disable super-watchdog
|
||||
PVT_GLITCH_MODE, EFUSE_BLK0, 182, 2, [] Use to configure glitch mode
|
||||
MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address
|
||||
WAFER_VERSION_MINOR, EFUSE_BLK1, 64, 4, [] Minor chip version
|
||||
WAFER_VERSION_MAJOR, EFUSE_BLK1, 68, 2, [] Major chip version (lower 2 bits)
|
||||
, EFUSE_BLK1, 87, 1, [] Major chip version (MSB)
|
||||
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 70, 1, [] Disables check of wafer version major
|
||||
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK1, 71, 1, [] Disables check of blk version major
|
||||
BLK_VERSION_MINOR, EFUSE_BLK1, 72, 3, [] BLK_VERSION_MINOR of BLOCK2
|
||||
BLK_VERSION_MAJOR, EFUSE_BLK1, 75, 2, [] BLK_VERSION_MAJOR of BLOCK2
|
||||
PSRAM_CAP, EFUSE_BLK1, 77, 3, [] PSRAM capacity
|
||||
TEMP, EFUSE_BLK1, 80, 2, [] Operating temperature of the ESP chip
|
||||
PSRAM_VENDOR, EFUSE_BLK1, 82, 2, [] PSRAM vendor
|
||||
PKG_VERSION, EFUSE_BLK1, 84, 3, [] Package version
|
||||
LDO_VO1_DREF, EFUSE_BLK1, 88, 4, [] Output VO1 parameter
|
||||
LDO_VO2_DREF, EFUSE_BLK1, 92, 4, [] Output VO2 parameter
|
||||
LDO_VO1_MUL, EFUSE_BLK1, 96, 3, [] Output VO1 parameter
|
||||
LDO_VO2_MUL, EFUSE_BLK1, 99, 3, [] Output VO2 parameter
|
||||
LDO_VO3_K, EFUSE_BLK1, 102, 8, [] Output VO3 calibration parameter
|
||||
LDO_VO3_VOS, EFUSE_BLK1, 110, 6, [] Output VO3 calibration parameter
|
||||
LDO_VO3_C, EFUSE_BLK1, 116, 6, [] Output VO3 calibration parameter
|
||||
LDO_VO4_K, EFUSE_BLK1, 122, 8, [] Output VO4 calibration parameter
|
||||
LDO_VO4_VOS, EFUSE_BLK1, 130, 6, [] Output VO4 calibration parameter
|
||||
LDO_VO4_C, EFUSE_BLK1, 136, 6, [] Output VO4 calibration parameter
|
||||
ACTIVE_HP_DBIAS, EFUSE_BLK1, 144, 4, [] Active HP DBIAS of fixed voltage
|
||||
ACTIVE_LP_DBIAS, EFUSE_BLK1, 148, 4, [] Active LP DBIAS of fixed voltage
|
||||
DSLP_DBG, EFUSE_BLK1, 156, 4, [] DSLP BDG of fixed voltage
|
||||
DSLP_LP_DBIAS, EFUSE_BLK1, 160, 5, [] DSLP LP DBIAS of fixed voltage
|
||||
LP_DCDC_DBIAS_VOL_GAP, EFUSE_BLK1, 165, 5, [] DBIAS gap between LP and DCDC
|
||||
PVT_400M_BIAS, EFUSE_BLK1, 171, 5, [] PVT_DCM_VSET when the CPU is at 400M
|
||||
PVT_40M_BIAS, EFUSE_BLK1, 176, 5, [] PVT_DCM_VSET corresponding to about 0.9V fixed voltage when the CPU is at 40M
|
||||
PVT_100M_BIAS, EFUSE_BLK1, 181, 5, [] PVT_DCM_VSET corresponding to about 1.0V fixed voltage when the CPU is at 100M
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
|
||||
ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK2, 128, 10, [] Average initcode of ADC1 atten0
|
||||
ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK2, 138, 10, [] Average initcode of ADC1 atten1
|
||||
ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK2, 148, 10, [] Average initcode of ADC1 atten2
|
||||
ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK2, 158, 10, [] Average initcode of ADC1 atten3
|
||||
ADC2_AVE_INITCODE_ATTEN0, EFUSE_BLK2, 168, 10, [] Average initcode of ADC2 atten0
|
||||
ADC2_AVE_INITCODE_ATTEN1, EFUSE_BLK2, 178, 10, [] Average initcode of ADC2 atten1
|
||||
ADC2_AVE_INITCODE_ATTEN2, EFUSE_BLK2, 188, 10, [] Average initcode of ADC2 atten2
|
||||
ADC2_AVE_INITCODE_ATTEN3, EFUSE_BLK2, 198, 10, [] Average initcode of ADC2 atten3
|
||||
ADC1_HI_DOUT_ATTEN0, EFUSE_BLK2, 208, 10, [] HI_DOUT of ADC1 atten0
|
||||
ADC1_HI_DOUT_ATTEN1, EFUSE_BLK2, 218, 10, [] HI_DOUT of ADC1 atten1
|
||||
ADC1_HI_DOUT_ATTEN2, EFUSE_BLK2, 228, 10, [] HI_DOUT of ADC1 atten2
|
||||
ADC1_HI_DOUT_ATTEN3, EFUSE_BLK2, 238, 10, [] HI_DOUT of ADC1 atten3
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
|
||||
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
|
||||
KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data
|
||||
KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data
|
||||
KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data
|
||||
KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data
|
||||
KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data
|
||||
ADC2_HI_DOUT_ATTEN0, EFUSE_BLK10, 0, 10, [] HI_DOUT of ADC2 atten0
|
||||
ADC2_HI_DOUT_ATTEN1, EFUSE_BLK10, 10, 10, [] HI_DOUT of ADC2 atten1
|
||||
ADC2_HI_DOUT_ATTEN2, EFUSE_BLK10, 20, 10, [] HI_DOUT of ADC2 atten2
|
||||
ADC2_HI_DOUT_ATTEN3, EFUSE_BLK10, 30, 10, [] HI_DOUT of ADC2 atten3
|
||||
ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 40, 4, [] Gap between ADC1_ch0 and average initcode
|
||||
ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 44, 4, [] Gap between ADC1_ch1 and average initcode
|
||||
ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 48, 4, [] Gap between ADC1_ch2 and average initcode
|
||||
ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 52, 4, [] Gap between ADC1_ch3 and average initcode
|
||||
ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 56, 4, [] Gap between ADC1_ch4 and average initcode
|
||||
ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 60, 4, [] Gap between ADC1_ch5 and average initcode
|
||||
ADC1_CH6_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 64, 4, [] Gap between ADC1_ch6 and average initcode
|
||||
ADC1_CH7_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 68, 4, [] Gap between ADC1_ch7 and average initcode
|
||||
ADC2_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 72, 4, [] Gap between ADC2_ch0 and average initcode
|
||||
ADC2_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 76, 4, [] Gap between ADC2_ch1 and average initcode
|
||||
ADC2_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 80, 4, [] Gap between ADC2_ch2 and average initcode
|
||||
ADC2_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 84, 4, [] Gap between ADC2_ch3 and average initcode
|
||||
ADC2_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 88, 4, [] Gap between ADC2_ch4 and average initcode
|
||||
ADC2_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 92, 4, [] Gap between ADC2_ch5 and average initcode
|
||||
TEMPERATURE_SENSOR, EFUSE_BLK10, 96, 10, [] Temperature calibration data
|
||||
USB_DEVICE_EXCHG_PINS, EFUSE_BLK10, 228, 1, [] Enable usb device exchange pins of D+ and D-
|
||||
USB_OTG11_EXCHG_PINS, EFUSE_BLK10, 229, 1, [] Enable usb otg11 exchange pins of D+ and D-
|
||||
|
Can't render this file because it contains an unexpected character in line 8 and column 53.
|
@@ -1,11 +1,13 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "sdkconfig.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
@@ -63,6 +65,11 @@ typedef enum {
|
||||
typedef enum {
|
||||
ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */
|
||||
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, /**< ECDSA private key (Expected in little endian order)*/
|
||||
|
||||
#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
|
||||
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P256 = ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY, /**< ECDSA private key (P256) (Expected in little endian order)*/
|
||||
#endif
|
||||
|
||||
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 = 2, /**< XTS_AES_256_KEY_1 (flash/PSRAM encryption) */
|
||||
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 = 3, /**< XTS_AES_256_KEY_2 (flash/PSRAM encryption) */
|
||||
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */
|
||||
@@ -74,7 +81,18 @@ typedef enum {
|
||||
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */
|
||||
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */
|
||||
ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY = 12, /**< KM_INIT_KEY */
|
||||
|
||||
#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
|
||||
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 = 13, /**< PSRAM encryption key (XTS_AES_256_KEY_1) */
|
||||
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 = 14, /**< PSRAM encryption key (XTS_AES_256_KEY_2) */
|
||||
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY = 15, /**< PSRAM encryption key (XTS_AES_128_KEY) */
|
||||
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 = 16, /**< ECDSA private key (P192) */
|
||||
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L = 17, /**< ECDSA private key (P384_L) */
|
||||
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H = 18, /**< ECDSA private key (P384_H) */
|
||||
ESP_EFUSE_KEY_PURPOSE_MAX = 32, /**< MAX PURPOSE */
|
||||
#else
|
||||
ESP_EFUSE_KEY_PURPOSE_MAX = 16, /**< MAX PURPOSE */
|
||||
#endif
|
||||
} esp_efuse_purpose_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -8,340 +8,13 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "esp_efuse.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
// md5_digest_table 665d4d3a1354653f8e46869d49df1a2f
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
// To show efuse_table run the command 'show_efuse_table'.
|
||||
|
||||
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_KEY_LENGTH_256[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_WDT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_SWD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_ENABLE_SOFT_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_HUK_GEN_STATE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_LO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_HI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_DREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_DREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_MUL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_MUL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_VOS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_C[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_VOS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_C[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_DCDC_DBIAS_VOL_GAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_TEMPERATURE_SENSOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_XTS_KEY_LENGTH_256[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
|
||||
#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
|
||||
#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
|
||||
#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
|
||||
#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
|
||||
#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
|
||||
#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_ENABLE_SOFT_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_HP_PWR_SRC_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_WDT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_SWD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
|
||||
#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR_LO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR_HI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_DREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_DREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_MUL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_MUL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_VOS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_C[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_VOS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_C[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LP_DCDC_DBIAS_VOL_GAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
||||
#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM
|
||||
#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
|
||||
#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
|
||||
#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
|
||||
#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
|
||||
#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
|
||||
#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
|
||||
#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[];
|
||||
#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
|
||||
#include "esp_efuse_table_v3.0.h"
|
||||
#else
|
||||
#include "esp_efuse_table_v0.0_v2.0.h"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -0,0 +1,348 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "esp_efuse.h"
|
||||
|
||||
// md5_digest_table 665d4d3a1354653f8e46869d49df1a2f
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
// To show efuse_table run the command 'show_efuse_table'.
|
||||
|
||||
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_KEY_LENGTH_256[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_WDT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_SWD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_ENABLE_SOFT_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_HUK_GEN_STATE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_LO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_HI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_DREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_DREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_MUL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_MUL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_VOS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_C[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_VOS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_C[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_DCDC_DBIAS_VOL_GAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_TEMPERATURE_SENSOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_XTS_KEY_LENGTH_256[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
|
||||
#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
|
||||
#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
|
||||
#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
|
||||
#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
|
||||
#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
|
||||
#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_ENABLE_SOFT_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_HP_PWR_SRC_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_WDT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_SWD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
|
||||
#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR_LO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR_HI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_DREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_DREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_MUL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_MUL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_VOS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_C[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_VOS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_C[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LP_DCDC_DBIAS_VOL_GAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
||||
#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM
|
||||
#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
|
||||
#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
|
||||
#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
|
||||
#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
|
||||
#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
|
||||
#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
|
||||
#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,361 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "esp_efuse.h"
|
||||
|
||||
// md5_digest_table d471a4221faaafb88f091d4549ecac55
|
||||
// This file was generated from the file esp_efuse_table_v3.0.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table_v3.0.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
// To show efuse_table run the command 'show_efuse_table'.
|
||||
|
||||
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_XTS_KEY_LENGTH_256[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE_H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY_H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE_H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_WDT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_SWD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0_H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1_H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2_H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3_H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4_H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5_H[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HUK_GEN_STATE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_LO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_HI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_DREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_DREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_MUL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_MUL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_VOS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_C[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_VOS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_C[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_DCDC_DBIAS_VOL_GAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_400M_BIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_40M_BIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_100M_BIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_TEMPERATURE_SENSOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_USB_DEVICE_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_USB_OTG11_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_HUK_GEN_STATE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KM_XTS_KEY_LENGTH_256[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
|
||||
#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
|
||||
#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
|
||||
#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
|
||||
#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
|
||||
#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
|
||||
#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_HP_PWR_SRC_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_SHA384_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_WDT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_SWD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
|
||||
#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_DREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_DREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_MUL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_MUL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_VOS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_C[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_VOS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_C[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LP_DCDC_DBIAS_VOL_GAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PVT_400M_BIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PVT_40M_BIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PVT_100M_BIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
||||
#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM
|
||||
#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
|
||||
#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
|
||||
#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
|
||||
#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
|
||||
#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
|
||||
#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
|
||||
#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_EXCHG_PINS[];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,4 +1,15 @@
|
||||
set(EFUSE_SOC_SRCS "esp_efuse_table.c"
|
||||
"esp_efuse_fields.c"
|
||||
"esp_efuse_rtc_calib.c"
|
||||
"esp_efuse_utility.c")
|
||||
set(EFUSE_SOC_SRCS
|
||||
"esp_efuse_utility.c"
|
||||
"esp_efuse_fields.c"
|
||||
)
|
||||
|
||||
if(CONFIG_ESP32P4_REV_MIN_FULL GREATER_EQUAL 300)
|
||||
list(APPEND EFUSE_SOC_SRCS
|
||||
"esp_efuse_table_v3.0.c"
|
||||
)
|
||||
else()
|
||||
list(APPEND EFUSE_SOC_SRCS
|
||||
"esp_efuse_table.c"
|
||||
"esp_efuse_rtc_calib.c"
|
||||
)
|
||||
endif()
|
||||
|
||||
@@ -177,7 +177,7 @@ esp_efuse_purpose_t esp_efuse_get_key_purpose(esp_efuse_block_t block)
|
||||
}
|
||||
unsigned idx = block - EFUSE_BLK_KEY0;
|
||||
uint8_t value = 0;
|
||||
esp_err_t err = esp_efuse_read_field_blob(s_table[idx].keypurpose, &value, s_table[idx].keypurpose[0]->bit_count);
|
||||
esp_err_t err = esp_efuse_read_field_blob(s_table[idx].keypurpose, &value, esp_efuse_get_field_size(s_table[idx].keypurpose));
|
||||
if (err != ESP_OK) {
|
||||
return ESP_EFUSE_KEY_PURPOSE_MAX;
|
||||
}
|
||||
@@ -190,7 +190,7 @@ esp_err_t esp_efuse_set_key_purpose(esp_efuse_block_t block, esp_efuse_purpose_t
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
unsigned idx = block - EFUSE_BLK_KEY0;
|
||||
return esp_efuse_write_field_blob(s_table[idx].keypurpose, &purpose, s_table[idx].keypurpose[0]->bit_count);
|
||||
return esp_efuse_write_field_blob(s_table[idx].keypurpose, &purpose, esp_efuse_get_field_size(s_table[idx].keypurpose));
|
||||
}
|
||||
|
||||
bool esp_efuse_get_keypurpose_dis_write(esp_efuse_block_t block)
|
||||
|
||||
@@ -25,7 +25,7 @@ menu "ESP-TLS"
|
||||
|
||||
config ESP_TLS_USE_DS_PERIPHERAL
|
||||
bool "Use Digital Signature (DS) Peripheral with ESP-TLS"
|
||||
depends on ESP_TLS_USING_MBEDTLS && SOC_DIG_SIGN_SUPPORTED
|
||||
depends on ESP_TLS_USING_MBEDTLS && SOC_DIG_SIGN_SUPPORTED && MBEDTLS_PK_RSA_ALT_SUPPORT
|
||||
default y
|
||||
help
|
||||
Enable use of the Digital Signature Peripheral for ESP-TLS.The DS peripheral
|
||||
|
||||
@@ -475,17 +475,16 @@ esp_err_t adc_continuous_config(adc_continuous_handle_t handle, const adc_contin
|
||||
}
|
||||
|
||||
ESP_RETURN_ON_FALSE(config->sample_freq_hz <= SOC_ADC_SAMPLE_FREQ_THRES_HIGH && config->sample_freq_hz >= SOC_ADC_SAMPLE_FREQ_THRES_LOW, ESP_ERR_INVALID_ARG, ADC_TAG, "ADC sampling frequency out of range");
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
ESP_RETURN_ON_FALSE(config->format == ADC_DIGI_OUTPUT_FORMAT_TYPE1, ESP_ERR_INVALID_ARG, ADC_TAG, "Please use type1");
|
||||
handle->format = ADC_DIGI_OUTPUT_FORMAT_TYPE1;
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
if (config->conv_mode == ADC_CONV_BOTH_UNIT || config->conv_mode == ADC_CONV_ALTER_UNIT) {
|
||||
ESP_RETURN_ON_FALSE(config->format == ADC_DIGI_OUTPUT_FORMAT_TYPE2, ESP_ERR_INVALID_ARG, ADC_TAG, "Please use type2");
|
||||
handle->format = ADC_DIGI_OUTPUT_FORMAT_TYPE2;
|
||||
} else if (config->conv_mode == ADC_CONV_SINGLE_UNIT_1 || config->conv_mode == ADC_CONV_SINGLE_UNIT_2) {
|
||||
ESP_RETURN_ON_FALSE(config->format == ADC_DIGI_OUTPUT_FORMAT_TYPE1, ESP_ERR_INVALID_ARG, ADC_TAG, "Please use type1");
|
||||
handle->format = ADC_DIGI_OUTPUT_FORMAT_TYPE1;
|
||||
}
|
||||
#else
|
||||
ESP_RETURN_ON_FALSE(config->format == ADC_DIGI_OUTPUT_FORMAT_TYPE2, ESP_ERR_INVALID_ARG, ADC_TAG, "Please use type2");
|
||||
handle->format = ADC_DIGI_OUTPUT_FORMAT_TYPE2;
|
||||
#endif
|
||||
|
||||
uint32_t clk_src_freq_hz = 0;
|
||||
@@ -583,3 +582,88 @@ esp_err_t adc_continuous_channel_to_io(adc_unit_t unit_id, adc_channel_t channel
|
||||
{
|
||||
return adc_channel_to_io(unit_id, channel, io_num);
|
||||
}
|
||||
|
||||
esp_err_t adc_continuous_parse_data(adc_continuous_handle_t handle,
|
||||
const uint8_t *raw_data,
|
||||
uint32_t raw_data_size,
|
||||
adc_continuous_data_t *parsed_data,
|
||||
uint32_t *num_parsed_samples)
|
||||
{
|
||||
// Parameter validation
|
||||
ESP_RETURN_ON_FALSE(handle && raw_data && parsed_data && num_parsed_samples, ESP_ERR_INVALID_ARG, ADC_TAG, "invalid argument");
|
||||
|
||||
// Buffer size validation
|
||||
if (raw_data_size == 0 || raw_data_size % SOC_ADC_DIGI_RESULT_BYTES != 0) {
|
||||
*num_parsed_samples = 0;
|
||||
return ESP_ERR_INVALID_SIZE;
|
||||
}
|
||||
|
||||
// Calculate number of samples
|
||||
uint32_t samples_to_parse = raw_data_size / SOC_ADC_DIGI_RESULT_BYTES;
|
||||
|
||||
for (uint32_t i = 0; i < samples_to_parse; i++) {
|
||||
adc_digi_output_data_t *p = (adc_digi_output_data_t*)&raw_data[i * SOC_ADC_DIGI_RESULT_BYTES];
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
parsed_data[i].unit = ADC_UNIT_1;
|
||||
parsed_data[i].channel = p->type1.channel;
|
||||
parsed_data[i].raw_data = p->type1.data;
|
||||
parsed_data[i].valid = (parsed_data[i].channel < SOC_ADC_CHANNEL_NUM(parsed_data[i].unit));
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
if (handle->format == ADC_DIGI_OUTPUT_FORMAT_TYPE2) {
|
||||
parsed_data[i].unit = p->type2.unit ? ADC_UNIT_2 : ADC_UNIT_1;
|
||||
parsed_data[i].channel = p->type2.channel;
|
||||
parsed_data[i].raw_data = p->type2.data;
|
||||
parsed_data[i].valid = (parsed_data[i].channel < SOC_ADC_CHANNEL_NUM(parsed_data[i].unit));
|
||||
} else if (handle->format == ADC_DIGI_OUTPUT_FORMAT_TYPE1) {
|
||||
parsed_data[i].unit = handle->use_adc1 ? ADC_UNIT_1 : ADC_UNIT_2;
|
||||
parsed_data[i].channel = p->type1.channel;
|
||||
parsed_data[i].raw_data = p->type1.data;
|
||||
parsed_data[i].valid = (parsed_data[i].channel < SOC_ADC_CHANNEL_NUM(parsed_data[i].unit));
|
||||
}
|
||||
#else
|
||||
#if CONFIG_SOC_ADC_PERIPH_NUM == 1
|
||||
parsed_data[i].unit = ADC_UNIT_1;
|
||||
#else
|
||||
parsed_data[i].unit = p->type2.unit ? ADC_UNIT_2 : ADC_UNIT_1;
|
||||
#endif
|
||||
parsed_data[i].channel = (parsed_data[i].unit == ADC_UNIT_2) ? p->type2.channel - ADC_LL_UNIT2_CHANNEL_SUBSTRATION : p->type2.channel;
|
||||
parsed_data[i].raw_data = p->type2.data;
|
||||
parsed_data[i].valid = (parsed_data[i].channel < SOC_ADC_CHANNEL_NUM(parsed_data[i].unit));
|
||||
#endif
|
||||
}
|
||||
|
||||
*num_parsed_samples = samples_to_parse;
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t adc_continuous_read_parse(adc_continuous_handle_t handle,
|
||||
adc_continuous_data_t *parsed_data,
|
||||
uint32_t max_samples,
|
||||
uint32_t *num_samples,
|
||||
uint32_t timeout_ms)
|
||||
{
|
||||
// Parameter validation
|
||||
ESP_RETURN_ON_FALSE(handle && parsed_data && num_samples, ESP_ERR_INVALID_ARG, ADC_TAG, "invalid argument");
|
||||
|
||||
// Allocate raw data buffer based on max_samples
|
||||
uint32_t raw_buffer_size = max_samples * SOC_ADC_DIGI_RESULT_BYTES;
|
||||
uint8_t *raw_data = malloc(raw_buffer_size);
|
||||
if (raw_data == NULL) {
|
||||
*num_samples = 0;
|
||||
return ESP_ERR_NO_MEM;
|
||||
}
|
||||
|
||||
uint32_t out_length = 0;
|
||||
esp_err_t read_ret = adc_continuous_read(handle, raw_data, raw_buffer_size, &out_length, timeout_ms);
|
||||
if (read_ret != ESP_OK) {
|
||||
free(raw_data);
|
||||
*num_samples = 0;
|
||||
return read_ret;
|
||||
}
|
||||
|
||||
esp_err_t parse_ret = adc_continuous_parse_data(handle, raw_data, out_length, parsed_data, num_samples);
|
||||
|
||||
free(raw_data);
|
||||
|
||||
return parse_ret;
|
||||
}
|
||||
|
||||
@@ -87,6 +87,7 @@ struct adc_continuous_ctx_t {
|
||||
adc_atten_t adc1_atten; //Attenuation for ADC1. On this chip each ADC can only support one attenuation.
|
||||
adc_atten_t adc2_atten; //Attenuation for ADC2. On this chip each ADC can only support one attenuation.
|
||||
adc_hal_digi_ctrlr_cfg_t hal_digi_ctrlr_cfg; //Hal digital controller configuration
|
||||
adc_digi_output_format_t format; //ADC DMA conversion output format
|
||||
adc_continuous_evt_cbs_t cbs; //Callbacks
|
||||
void *user_data; //User context
|
||||
esp_pm_lock_handle_t pm_lock; //For power management
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -238,6 +238,66 @@ esp_err_t adc_continuous_io_to_channel(int io_num, adc_unit_t * const unit_id, a
|
||||
*/
|
||||
esp_err_t adc_continuous_channel_to_io(adc_unit_t unit_id, adc_channel_t channel, int * const io_num);
|
||||
|
||||
/**
|
||||
* @brief Parsed ADC continuous mode data structure
|
||||
*/
|
||||
typedef struct {
|
||||
adc_unit_t unit; ///< ADC unit (ADC_UNIT_1 or ADC_UNIT_2)
|
||||
adc_channel_t channel; ///< ADC channel number (0-9)
|
||||
uint32_t raw_data; ///< ADC raw data value (0-4095, 12-bit resolution)
|
||||
bool valid; ///< Whether the data is valid
|
||||
} adc_continuous_data_t;
|
||||
|
||||
/**
|
||||
* @brief Parse ADC continuous mode raw data
|
||||
*
|
||||
* @param[in] handle ADC continuous mode driver handle
|
||||
* @param[in] raw_data Raw data buffer obtained from adc_continuous_read()
|
||||
* @param[in] raw_data_size Size of raw data buffer in bytes
|
||||
* @param[out] parsed_data Parsed data array
|
||||
* @param[out] num_parsed_samples Number of samples actually parsed and stored in parsed_data
|
||||
*
|
||||
* @note The function will parse all available samples from raw_data. User should ensure
|
||||
* parsed_data array is large enough to hold raw_data_size/SOC_ADC_DIGI_RESULT_BYTES samples.
|
||||
* The function includes comprehensive bounds checking to prevent buffer overflow and integer overflow.
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: Success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid arguments
|
||||
* - ESP_ERR_INVALID_SIZE: raw_data_size is not aligned to SOC_ADC_DIGI_RESULT_BYTES,
|
||||
* integer overflow detected, or buffer overflow detected
|
||||
*/
|
||||
esp_err_t adc_continuous_parse_data(adc_continuous_handle_t handle,
|
||||
const uint8_t *raw_data,
|
||||
uint32_t raw_data_size,
|
||||
adc_continuous_data_t *parsed_data,
|
||||
uint32_t *num_parsed_samples);
|
||||
|
||||
/**
|
||||
* @brief Read and parse ADC continuous mode data in one call
|
||||
*
|
||||
* @param[in] handle ADC continuous mode driver handle
|
||||
* @param[out] parsed_data Parsed data array
|
||||
* @param[in] max_samples Maximum number of samples that can be stored in parsed_data array
|
||||
* @param[out] num_samples Number of samples actually parsed and stored in parsed_data
|
||||
* @param[in] timeout_ms Timeout in milliseconds
|
||||
*
|
||||
* @note This function automatically handles raw data buffer allocation and cleanup.
|
||||
* User only needs to provide parsed_data array and specify max_samples.
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: Success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid arguments
|
||||
* - ESP_ERR_INVALID_SIZE: Buffer size issues or overflow detected
|
||||
* - ESP_ERR_TIMEOUT: Operation timed out
|
||||
* - ESP_ERR_NO_MEM: Memory allocation failed
|
||||
*/
|
||||
esp_err_t adc_continuous_read_parse(adc_continuous_handle_t handle,
|
||||
adc_continuous_data_t *parsed_data,
|
||||
uint32_t max_samples,
|
||||
uint32_t *num_samples,
|
||||
uint32_t timeout_ms);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -189,6 +189,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
|
||||
{
|
||||
gpio_func_sel(gpio_pin.priority, PIN_FUNC_GPIO);
|
||||
gpio_set_direction(gpio_pin.priority, GPIO_MODE_INPUT);
|
||||
gpio_set_pull_mode(gpio_pin.priority, GPIO_PULLDOWN_ONLY);
|
||||
esp_rom_gpio_connect_in_signal(gpio_pin.priority, EXTERNAL_COEX_SIGNAL_I1_IDX, false);
|
||||
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.priority), GPIO_PIN1_SYNC1_BYPASS, 2);
|
||||
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.priority), GPIO_PIN1_SYNC2_BYPASS, 2);
|
||||
@@ -206,6 +207,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
|
||||
{
|
||||
gpio_func_sel(gpio_pin.request, PIN_FUNC_GPIO);
|
||||
gpio_set_direction(gpio_pin.request, GPIO_MODE_INPUT);
|
||||
gpio_set_pull_mode(gpio_pin.request, GPIO_PULLDOWN_ONLY);
|
||||
esp_rom_gpio_connect_in_signal(gpio_pin.request, EXTERNAL_COEX_SIGNAL_I0_IDX, false);
|
||||
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.request), GPIO_PIN1_SYNC1_BYPASS, 2);
|
||||
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.request), GPIO_PIN1_SYNC2_BYPASS, 2);
|
||||
@@ -224,6 +226,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
|
||||
{
|
||||
gpio_func_sel(gpio_pin.tx_line, PIN_FUNC_GPIO);
|
||||
gpio_set_direction(gpio_pin.tx_line, GPIO_MODE_INPUT);
|
||||
gpio_set_pull_mode(gpio_pin.tx_line, GPIO_PULLDOWN_ONLY);
|
||||
esp_rom_gpio_connect_in_signal(gpio_pin.tx_line, EXTERNAL_COEX_SIGNAL_I1_IDX, false);
|
||||
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.tx_line), GPIO_PIN1_SYNC1_BYPASS, 2);
|
||||
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.tx_line), GPIO_PIN1_SYNC2_BYPASS, 2);
|
||||
@@ -241,6 +244,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
|
||||
{
|
||||
gpio_func_sel(gpio_pin.grant, PIN_FUNC_GPIO);
|
||||
gpio_set_direction(gpio_pin.grant, GPIO_MODE_INPUT);
|
||||
gpio_set_pull_mode(gpio_pin.grant, GPIO_PULLUP_ONLY);
|
||||
esp_rom_gpio_connect_in_signal(gpio_pin.grant, EXTERNAL_COEX_SIGNAL_I0_IDX, false);
|
||||
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.grant), GPIO_PIN1_SYNC1_BYPASS, 2);
|
||||
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.grant), GPIO_PIN1_SYNC2_BYPASS, 2);
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -38,8 +38,33 @@ typedef struct esp_cam_ctlr_dvp_config {
|
||||
uint32_t h_res; /*!< Input horizontal resolution, i.e. the number of pixels in a line */
|
||||
uint32_t v_res; /*!< Input vertical resolution, i.e. the number of lines in a frame */
|
||||
cam_ctlr_color_t input_data_color_type; /*!< Input pixel format */
|
||||
uint32_t cam_data_width; /*!< Byte width, 8, 16 or 24 bit, default to 8 */
|
||||
struct {
|
||||
uint32_t byte_swap_en : 1; /*!< Enable byte swap */
|
||||
uint32_t bit_swap_en : 1; /*!< Enable bit swap */
|
||||
uint32_t byte_swap_en : 1; /*!< Enable byte swap
|
||||
*
|
||||
* GDMA Data Byte Order Table (input: B0,B1,B2,B3,B4,B5, addresses from low to high)
|
||||
*
|
||||
* | cam_data_width | bit_swap_en | byte_swap_en | Stage 1 Output Data Sequence |
|
||||
* |----------------|-------------|--------------|------------------------------ |
|
||||
* | 8-bit | 0 | 0 | {B0}{B1}{B2}{B3}{B4}{B5} |
|
||||
* | 8-bit | 0 | 1 | {B1,B0}{B3,B2}{B5,B4} |
|
||||
* | 8-bit | 1 | 0 | {B0'}{B1'}{B2'}{B3'}{B4'}{B5'} |
|
||||
* | 8-bit | 1 | 1 | {B1',B0'}{B3',B2'}{B5',B4'} |
|
||||
*
|
||||
* | 16-bit | 0 | 0 | {B1,B0}{B3,B2}{B5,B4} |
|
||||
* | 16-bit | 0 | 1 | {B0,B1}{B2,B3}{B4,B5} |
|
||||
* | 16-bit | 1 | 0 | {B1',B0'}{B3',B2'}{B5',B4'} |
|
||||
* | 16-bit | 1 | 1 | {B0',B1'}{B2',B3'}{B4',B5'} |
|
||||
*
|
||||
* | 24-bit | 0 | 0 | {B2,B1,B0}{B5,B4,B3} |
|
||||
* | 24-bit | 0 | 1 | {B0,B1,B2}{B3,B4,B5} |
|
||||
* | 24-bit | 1 | 0 | {B2',B1',B0'}{B5',B4',B3'} |
|
||||
* | 24-bit | 1 | 1 | {B0',B1',B2'}{B3',B4',B5'} |
|
||||
*
|
||||
* Where B0' = bit-reversed B0，Bn'[7:0] = Bn[0:7]
|
||||
* Each {} contains big-endian parallel data, {} are in serial relationship, output order is left to right
|
||||
*/
|
||||
uint32_t bk_buffer_dis : 1; /*!< Disable backup buffer */
|
||||
uint32_t pin_dont_init : 1; /*!< Don't initialize DVP pins if users have called "esp_cam_ctlr_dvp_init" before */
|
||||
uint32_t pic_format_jpeg : 1; /*!< Input picture format is JPEG, if set this flag and "input_data_color_type" will be ignored */
|
||||
|
||||
@@ -771,7 +771,9 @@ static void *esp_cam_ctlr_dvp_cam_alloc_buffer(esp_cam_ctlr_t *handle, size_t si
|
||||
* @param cam_handle Camera controller handle
|
||||
* @param src_format Source format
|
||||
* @param dst_format Destination format
|
||||
* @return ESP_OK on success, ESP_FAIL on failure
|
||||
* @return
|
||||
* - ESP_OK on success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid argument
|
||||
*/
|
||||
esp_err_t esp_cam_ctlr_dvp_format_conversion(esp_cam_ctlr_handle_t cam_handle,
|
||||
const cam_ctlr_format_conv_config_t *config)
|
||||
@@ -784,6 +786,12 @@ esp_err_t esp_cam_ctlr_dvp_format_conversion(esp_cam_ctlr_handle_t cam_handle,
|
||||
|
||||
ESP_LOGD(TAG, "Configure format conversion: %d -> %d", config->src_format, config->dst_format);
|
||||
|
||||
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
|
||||
if (config->src_format == CAM_CTLR_COLOR_YUV420) {
|
||||
ESP_LOGE(TAG, "YUV420 is not allowed for source format");
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
#endif
|
||||
// Configure color format conversion
|
||||
cam_hal_color_format_convert(&ctlr->hal, config);
|
||||
|
||||
@@ -845,9 +853,17 @@ esp_err_t esp_cam_new_dvp_ctlr(const esp_cam_ctlr_dvp_config_t *config, esp_cam_
|
||||
|
||||
cam_hal_config_t cam_hal_config = {
|
||||
.port = config->ctlr_id,
|
||||
.cam_data_width = config->cam_data_width == 0 ? 8 : config->cam_data_width,
|
||||
.bit_swap_en = config->bit_swap_en,
|
||||
.byte_swap_en = config->byte_swap_en,
|
||||
};
|
||||
|
||||
ESP_RETURN_ON_FALSE(cam_hal_config.cam_data_width == 8 || cam_hal_config.cam_data_width == 16 || cam_hal_config.cam_data_width == 24, ESP_ERR_INVALID_ARG, TAG, "invalid argument: cam_data_width is not 8 or 16 or 24");
|
||||
|
||||
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
|
||||
ESP_RETURN_ON_FALSE(cam_hal_config.cam_data_width != 8 || cam_hal_config.byte_swap_en == 0, ESP_ERR_INVALID_ARG, TAG, "invalid argument: byte swap is not supported when cam_data_width is 8");
|
||||
#endif
|
||||
|
||||
if (!config->pin_dont_init) {
|
||||
// Initialzie DVP clock and GPIO internally
|
||||
ESP_GOTO_ON_ERROR(esp_cam_ctlr_dvp_init(config->ctlr_id, config->clk_src, config->pin),
|
||||
|
||||
@@ -563,6 +563,11 @@ uint32_t i2s_get_source_clk_freq(i2s_clock_src_t clk_src, uint32_t mclk_freq_hz)
|
||||
if (clk_src == I2S_CLK_SRC_APLL) {
|
||||
return i2s_set_get_apll_freq(mclk_freq_hz);
|
||||
}
|
||||
#endif
|
||||
#ifdef I2S_LL_DEFAULT_CLK_SRC
|
||||
if (clk_src == I2S_CLK_SRC_DEFAULT) {
|
||||
clk_src = I2S_LL_DEFAULT_CLK_SRC;
|
||||
}
|
||||
#endif
|
||||
esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_freq);
|
||||
return clk_freq;
|
||||
|
||||
@@ -742,7 +742,7 @@ TEST_CASE("I2S_loopback_test", "[i2s]")
|
||||
TEST_ESP_OK(i2s_del_channel(rx_handle));
|
||||
}
|
||||
|
||||
#if SOC_I2S_NUM > 1
|
||||
#if SOC_I2S_NUM > 1 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
|
||||
TEST_CASE("I2S_master_write_slave_read_test", "[i2s]")
|
||||
{
|
||||
i2s_chan_handle_t tx_handle;
|
||||
@@ -908,8 +908,8 @@ TEST_CASE("I2S_default_PLL_clock_test", "[i2s]")
|
||||
TEST_ESP_OK(i2s_new_channel(&chan_cfg, NULL, &rx_handle));
|
||||
TEST_ESP_OK(i2s_channel_init_std_mode(rx_handle, &std_cfg));
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP_REV_MIN_FULL >= 300
|
||||
std_cfg.clk_cfg.clk_src = I2S_CLK_SRC_PLL_160M;
|
||||
#ifdef I2S_LL_DEFAULT_CLK_SRC
|
||||
std_cfg.clk_cfg.clk_src = I2S_LL_DEFAULT_CLK_SRC;
|
||||
#endif
|
||||
i2s_test_common_sample_rate(rx_handle, &std_cfg.clk_cfg);
|
||||
#if SOC_I2S_SUPPORTS_XTAL
|
||||
|
||||
@@ -42,6 +42,10 @@ if(CONFIG_SOC_ISP_LSC_SUPPORTED)
|
||||
list(APPEND srcs "src/isp_lsc.c")
|
||||
endif()
|
||||
|
||||
if(CONFIG_SOC_ISP_WBG_SUPPORTED)
|
||||
list(APPEND srcs "src/isp_wbg.c")
|
||||
endif()
|
||||
|
||||
if(NOT ${target} STREQUAL "linux")
|
||||
list(APPEND requires esp_mm)
|
||||
endif()
|
||||
|
||||
@@ -24,3 +24,4 @@
|
||||
#include "driver/isp_hist.h"
|
||||
#include "driver/isp_lsc.h"
|
||||
#include "driver/isp_sharpen.h"
|
||||
#include "driver/isp_wbg.h"
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -39,14 +39,25 @@ typedef struct {
|
||||
int luminance[ISP_AF_WINDOW_NUM]; ///< Luminance, it refers how luminant an image is
|
||||
} isp_af_result_t;
|
||||
|
||||
/**
|
||||
* @brief ISP AWB subwindow result
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t white_patch_num[ISP_AWB_WINDOW_X_NUM][ISP_AWB_WINDOW_Y_NUM]; ///< white patch number that counted by AWB in the subwindow
|
||||
uint32_t sum_r[ISP_AWB_WINDOW_X_NUM][ISP_AWB_WINDOW_Y_NUM]; ///< The sum of R channel of these white patches
|
||||
uint32_t sum_g[ISP_AWB_WINDOW_X_NUM][ISP_AWB_WINDOW_Y_NUM]; ///< The sum of G channel of these white patches
|
||||
uint32_t sum_b[ISP_AWB_WINDOW_X_NUM][ISP_AWB_WINDOW_Y_NUM]; ///< The sum of B channel of these white patches
|
||||
} isp_awb_subwin_stat_result_t;
|
||||
|
||||
/**
|
||||
* @brief ISP AWB result
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t white_patch_num; ///< white patch number that counted by AWB in the window
|
||||
uint32_t sum_r; ///< The sum of R channel of these white patches
|
||||
uint32_t sum_g; ///< The sum of G channel of these white patches
|
||||
uint32_t sum_b; ///< The sum of B channel of these white patches
|
||||
uint32_t white_patch_num; ///< white patch number that counted by AWB in the window
|
||||
uint32_t sum_r; ///< The sum of R channel of these white patches
|
||||
uint32_t sum_g; ///< The sum of G channel of these white patches
|
||||
uint32_t sum_b; ///< The sum of B channel of these white patches
|
||||
isp_awb_subwin_stat_result_t subwin_result; ///< The AWB subwindow statistics result
|
||||
} isp_awb_stat_result_t;
|
||||
|
||||
/**
|
||||
|
||||
@@ -0,0 +1,81 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "esp_err.h"
|
||||
#include "driver/isp_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
WBG (White Balance Gain)
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief ISP BLC configurations
|
||||
*/
|
||||
typedef struct {
|
||||
//for future proof
|
||||
} esp_isp_wbg_config_t;
|
||||
|
||||
/**
|
||||
* @brief ISP WBG configuration
|
||||
*
|
||||
* @note After calling this API, WBG doesn't take into effect until `esp_isp_wbg_enable` is called
|
||||
*
|
||||
* @param[in] isp_proc Processor handle
|
||||
* @param[in] config WBG configurations
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK On success
|
||||
* - ESP_ERR_INVALID_STATE Not allowed to be called under current state
|
||||
* - ESP_ERR_INVALID_ARG If the combination of arguments is invalid
|
||||
* - ESP_ERR_NOT_SUPPORTED Not supported
|
||||
*/
|
||||
esp_err_t esp_isp_wbg_configure(isp_proc_handle_t isp_proc, const esp_isp_wbg_config_t *config);
|
||||
|
||||
/**
|
||||
* @brief Enable ISP WBG function
|
||||
*
|
||||
* @param[in] isp_proc Processor handle
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK On success
|
||||
* - ESP_ERR_INVALID_ARG If the combination of arguments is invalid.
|
||||
* - ESP_ERR_INVALID_STATE Driver state is invalid.
|
||||
*/
|
||||
esp_err_t esp_isp_wbg_enable(isp_proc_handle_t isp_proc);
|
||||
|
||||
/**
|
||||
* @brief Set AWB white balance gain
|
||||
*
|
||||
* @param[in] isp_proc Processor handle
|
||||
* @param[in] gain WBG white balance gain
|
||||
* @return
|
||||
* - ESP_OK On success
|
||||
* - ESP_ERR_INVALID_ARG Null pointer
|
||||
* - ESP_ERR_INVALID_STATE Driver state is invalid.
|
||||
*/
|
||||
esp_err_t esp_isp_wbg_set_wb_gain(isp_proc_handle_t isp_proc, isp_wbg_gain_t gain);
|
||||
|
||||
/**
|
||||
* @brief Disable ISP WBG function
|
||||
*
|
||||
* @param[in] isp_proc Processor handle
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK On success
|
||||
* - ESP_ERR_INVALID_ARG If the combination of arguments is invalid.
|
||||
* - ESP_ERR_INVALID_STATE Driver state is invalid.
|
||||
*/
|
||||
esp_err_t esp_isp_wbg_disable(isp_proc_handle_t isp_proc);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -9,6 +9,7 @@
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <esp_types.h>
|
||||
#include <stdatomic.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_attr.h"
|
||||
#include "esp_log.h"
|
||||
@@ -27,8 +28,12 @@
|
||||
#include "soc/isp_periph.h"
|
||||
#endif
|
||||
|
||||
// Helper macros for atomic operations to ensure Clang compatibility
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#include <atomic>
|
||||
#define ISP_ATOMIC_TYPE(T) std::atomic<T>
|
||||
#else
|
||||
#define ISP_ATOMIC_TYPE(T) _Atomic T
|
||||
#endif
|
||||
|
||||
#if CONFIG_ISP_ISR_IRAM_SAFE || CONFIG_ISP_CTRL_FUNC_IN_IRAM
|
||||
@@ -39,6 +44,10 @@ extern "C" {
|
||||
#define ISP_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
ISP_FSM_INIT, // Controller is initialized, but not enabled
|
||||
ISP_FSM_ENABLE, // Controller is enabled, but is not running
|
||||
@@ -59,7 +68,7 @@ typedef struct isp_processor_t {
|
||||
int csi_brg_id;
|
||||
void *csi_brg_hw;
|
||||
#endif
|
||||
isp_fsm_t isp_fsm;
|
||||
ISP_ATOMIC_TYPE(isp_fsm_t) isp_fsm;
|
||||
portMUX_TYPE spinlock;
|
||||
color_space_pixel_format_t in_color_format;
|
||||
color_space_pixel_format_t out_color_format;
|
||||
@@ -72,12 +81,15 @@ typedef struct isp_processor_t {
|
||||
isp_awb_ctlr_t awb_ctlr;
|
||||
isp_ae_ctlr_t ae_ctlr;
|
||||
isp_hist_ctlr_t hist_ctlr;
|
||||
isp_fsm_t bf_fsm;
|
||||
isp_fsm_t demosaic_fsm;
|
||||
isp_fsm_t sharpen_fsm;
|
||||
isp_fsm_t color_fsm;
|
||||
isp_fsm_t lsc_fsm;
|
||||
isp_fsm_t blc_fsm;
|
||||
ISP_ATOMIC_TYPE(isp_fsm_t) bf_fsm;
|
||||
ISP_ATOMIC_TYPE(isp_fsm_t) blc_fsm;
|
||||
ISP_ATOMIC_TYPE(isp_fsm_t) ccm_fsm;
|
||||
ISP_ATOMIC_TYPE(isp_fsm_t) color_fsm;
|
||||
ISP_ATOMIC_TYPE(isp_fsm_t) demosaic_fsm;
|
||||
ISP_ATOMIC_TYPE(isp_fsm_t) gamma_fsm;
|
||||
ISP_ATOMIC_TYPE(isp_fsm_t) lsc_fsm;
|
||||
ISP_ATOMIC_TYPE(isp_fsm_t) sharpen_fsm;
|
||||
ISP_ATOMIC_TYPE(isp_fsm_t) wbg_fsm;
|
||||
esp_isp_evt_cbs_t cbs;
|
||||
void *user_data;
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -239,6 +239,26 @@ bool IRAM_ATTR esp_isp_awb_isr(isp_proc_handle_t proc, uint32_t awb_events)
|
||||
.sum_b = isp_ll_awb_get_accumulated_b_value(proc->hal.hw),
|
||||
},
|
||||
};
|
||||
|
||||
// Get subwindow statistics
|
||||
for (int x = 0; x < ISP_AWB_WINDOW_X_NUM; x++) {
|
||||
for (int y = 0; y < ISP_AWB_WINDOW_Y_NUM; y++) {
|
||||
int subwindow_id = x * ISP_AWB_WINDOW_Y_NUM + y;
|
||||
|
||||
isp_ll_lut_awb_set_cmd(proc->hal.hw, ISP_LL_LUT_AWB_WHITE_PATCH_CNT, subwindow_id, ISP_LL_LUT_AWB);
|
||||
edata.awb_result.subwin_result.white_patch_num[x][y] = isp_ll_lut_awb_get_subwindow_white_patch_cnt(proc->hal.hw);
|
||||
|
||||
isp_ll_lut_awb_set_cmd(proc->hal.hw, ISP_LL_LUT_AWB_ACCUMULATED_R, subwindow_id, ISP_LL_LUT_AWB);
|
||||
edata.awb_result.subwin_result.sum_r[x][y] = isp_ll_lut_awb_get_subwindow_accumulated_r(proc->hal.hw);
|
||||
|
||||
isp_ll_lut_awb_set_cmd(proc->hal.hw, ISP_LL_LUT_AWB_ACCUMULATED_G, subwindow_id, ISP_LL_LUT_AWB);
|
||||
edata.awb_result.subwin_result.sum_g[x][y] = isp_ll_lut_awb_get_subwindow_accumulated_g(proc->hal.hw);
|
||||
|
||||
isp_ll_lut_awb_set_cmd(proc->hal.hw, ISP_LL_LUT_AWB_ACCUMULATED_B, subwindow_id, ISP_LL_LUT_AWB);
|
||||
edata.awb_result.subwin_result.sum_b[x][y] = isp_ll_lut_awb_get_subwindow_accumulated_b(proc->hal.hw);
|
||||
}
|
||||
}
|
||||
|
||||
// Invoke the callback if the callback is registered
|
||||
if (awb_ctlr->cbs.on_statistics_done) {
|
||||
need_yield |= awb_ctlr->cbs.on_statistics_done(awb_ctlr, &edata, awb_ctlr->user_data);
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -49,10 +49,10 @@ esp_err_t esp_isp_bf_configure(isp_proc_handle_t proc, const esp_isp_bf_config_t
|
||||
esp_err_t esp_isp_bf_enable(isp_proc_handle_t proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(proc->bf_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "bf is enabled already");
|
||||
isp_fsm_t expected_fsm = ISP_FSM_INIT;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->bf_fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "bf is enabled already");
|
||||
|
||||
isp_ll_bf_enable(proc->hal.hw, true);
|
||||
proc->bf_fsm = ISP_FSM_ENABLE;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
@@ -60,10 +60,10 @@ esp_err_t esp_isp_bf_enable(isp_proc_handle_t proc)
|
||||
esp_err_t esp_isp_bf_disable(isp_proc_handle_t proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(proc->bf_fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "bf isn't enabled yet");
|
||||
isp_fsm_t expected_fsm = ISP_FSM_ENABLE;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->bf_fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "bf isn't enabled yet");
|
||||
|
||||
isp_ll_bf_enable(proc->hal.hw, false);
|
||||
proc->bf_fsm = ISP_FSM_INIT;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
@@ -64,11 +64,11 @@ esp_err_t esp_isp_blc_configure(isp_proc_handle_t isp_proc, const esp_isp_blc_co
|
||||
esp_err_t esp_isp_blc_enable(isp_proc_handle_t isp_proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(isp_proc->blc_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "blc is enabled already");
|
||||
isp_fsm_t expected_fsm = ISP_FSM_INIT;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&isp_proc->blc_fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "blc is enabled already");
|
||||
|
||||
// Enable BLC module
|
||||
isp_ll_blc_enable(isp_proc->hal.hw, true);
|
||||
isp_proc->blc_fsm = ISP_FSM_ENABLE;
|
||||
|
||||
ESP_LOGD(TAG, "BLC enabled");
|
||||
return ESP_OK;
|
||||
@@ -77,7 +77,7 @@ esp_err_t esp_isp_blc_enable(isp_proc_handle_t isp_proc)
|
||||
esp_err_t esp_isp_blc_set_correction_offset(isp_proc_handle_t isp_proc, esp_isp_blc_offset_t *offset)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(isp_proc && offset, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(isp_proc->blc_fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "blc isn't enabled yet");
|
||||
ESP_RETURN_ON_FALSE(atomic_load(&isp_proc->blc_fsm) == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "blc isn't enabled yet");
|
||||
|
||||
// Set correction offset for each channel
|
||||
isp_ll_blc_set_correction_offset(isp_proc->hal.hw, offset->top_left_chan_offset, offset->top_right_chan_offset, offset->bottom_left_chan_offset, offset->bottom_right_chan_offset);
|
||||
@@ -92,11 +92,11 @@ esp_err_t esp_isp_blc_set_correction_offset(isp_proc_handle_t isp_proc, esp_isp_
|
||||
esp_err_t esp_isp_blc_disable(isp_proc_handle_t isp_proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(isp_proc->blc_fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "blc isn't enabled yet");
|
||||
isp_fsm_t expected_fsm = ISP_FSM_ENABLE;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&isp_proc->blc_fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "blc isn't enabled yet");
|
||||
|
||||
// Disable BLC module
|
||||
isp_ll_blc_enable(isp_proc->hal.hw, false);
|
||||
isp_proc->blc_fsm = ISP_FSM_INIT;
|
||||
|
||||
ESP_LOGD(TAG, "BLC disabled");
|
||||
return ESP_OK;
|
||||
|
||||
@@ -34,6 +34,8 @@ esp_err_t esp_isp_ccm_configure(isp_proc_handle_t proc, const esp_isp_ccm_config
|
||||
esp_err_t esp_isp_ccm_enable(isp_proc_handle_t proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
isp_fsm_t expected_fsm = ISP_FSM_INIT;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->ccm_fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "ccm is enabled already");
|
||||
|
||||
portENTER_CRITICAL(&proc->spinlock);
|
||||
isp_ll_ccm_enable(proc->hal.hw, true);
|
||||
@@ -45,6 +47,8 @@ esp_err_t esp_isp_ccm_enable(isp_proc_handle_t proc)
|
||||
esp_err_t esp_isp_ccm_disable(isp_proc_handle_t proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
isp_fsm_t expected_fsm = ISP_FSM_ENABLE;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->ccm_fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "ccm isn't enabled yet");
|
||||
|
||||
portENTER_CRITICAL(&proc->spinlock);
|
||||
isp_ll_ccm_enable(proc->hal.hw, false);
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -49,10 +49,10 @@ esp_err_t esp_isp_color_configure(isp_proc_handle_t proc, const esp_isp_color_co
|
||||
esp_err_t esp_isp_color_enable(isp_proc_handle_t proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(proc->color_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "color is enabled already");
|
||||
isp_fsm_t expected_fsm = ISP_FSM_INIT;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->color_fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "color is enabled already");
|
||||
|
||||
isp_ll_color_enable(proc->hal.hw, true);
|
||||
proc->color_fsm = ISP_FSM_ENABLE;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
@@ -60,10 +60,10 @@ esp_err_t esp_isp_color_enable(isp_proc_handle_t proc)
|
||||
esp_err_t esp_isp_color_disable(isp_proc_handle_t proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(proc->color_fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "color isn't enabled yet");
|
||||
isp_fsm_t expected_fsm = ISP_FSM_ENABLE;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->color_fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "color isn't enabled yet");
|
||||
|
||||
isp_ll_color_enable(proc->hal.hw, false);
|
||||
proc->color_fsm = ISP_FSM_INIT;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
@@ -119,7 +119,16 @@ esp_err_t esp_isp_new_processor(const esp_isp_processor_cfg_t *proc_config, isp_
|
||||
isp_ll_set_clock_div(proc->hal.hw, &clk_div);
|
||||
}
|
||||
proc->clk_src = clk_src;
|
||||
proc->isp_fsm = ISP_FSM_INIT;
|
||||
atomic_init(&proc->isp_fsm, ISP_FSM_INIT);
|
||||
atomic_init(&proc->bf_fsm, ISP_FSM_INIT);
|
||||
atomic_init(&proc->blc_fsm, ISP_FSM_INIT);
|
||||
atomic_init(&proc->ccm_fsm, ISP_FSM_INIT);
|
||||
atomic_init(&proc->color_fsm, ISP_FSM_INIT);
|
||||
atomic_init(&proc->demosaic_fsm, ISP_FSM_INIT);
|
||||
atomic_init(&proc->gamma_fsm, ISP_FSM_INIT);
|
||||
atomic_init(&proc->lsc_fsm, ISP_FSM_INIT);
|
||||
atomic_init(&proc->sharpen_fsm, ISP_FSM_INIT);
|
||||
atomic_init(&proc->wbg_fsm, ISP_FSM_INIT);
|
||||
proc->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
|
||||
|
||||
//Input & Output color format
|
||||
@@ -189,7 +198,7 @@ err:
|
||||
esp_err_t esp_isp_del_processor(isp_proc_handle_t proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(proc->isp_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "processor isn't in init state");
|
||||
ESP_RETURN_ON_FALSE(atomic_load(&proc->isp_fsm) == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "processor isn't in init state");
|
||||
|
||||
//declaim first, then do free
|
||||
ESP_RETURN_ON_ERROR(s_isp_declaim_processor(proc), TAG, "declaim processor fail");
|
||||
@@ -205,7 +214,7 @@ esp_err_t esp_isp_del_processor(isp_proc_handle_t proc)
|
||||
esp_err_t esp_isp_register_event_callbacks(isp_proc_handle_t proc, const esp_isp_evt_cbs_t *cbs, void *user_data)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(proc && cbs, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
|
||||
ESP_RETURN_ON_FALSE(proc->isp_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "processor isn't in the init state");
|
||||
ESP_RETURN_ON_FALSE(atomic_load(&proc->isp_fsm) == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "processor isn't in the init state");
|
||||
|
||||
#if CONFIG_ISP_ISR_IRAM_SAFE
|
||||
if (cbs->on_sharpen_frame_done) {
|
||||
@@ -230,11 +239,11 @@ esp_err_t esp_isp_register_event_callbacks(isp_proc_handle_t proc, const esp_isp
|
||||
esp_err_t esp_isp_enable(isp_proc_handle_t proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(proc->isp_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "processor isn't in init state");
|
||||
isp_fsm_t expected_fsm = ISP_FSM_INIT;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->isp_fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "processor isn't in init state");
|
||||
ESP_RETURN_ON_FALSE(proc->bypass_isp == false, ESP_ERR_INVALID_STATE, TAG, "processor is configured to be bypassed");
|
||||
|
||||
isp_ll_enable(proc->hal.hw, true);
|
||||
proc->isp_fsm = ISP_FSM_ENABLE;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
@@ -242,10 +251,10 @@ esp_err_t esp_isp_enable(isp_proc_handle_t proc)
|
||||
esp_err_t esp_isp_disable(isp_proc_handle_t proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(proc->isp_fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "processor isn't in enable state");
|
||||
isp_fsm_t expected_fsm = ISP_FSM_ENABLE;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->isp_fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "processor isn't in enable state");
|
||||
|
||||
isp_ll_enable(proc->hal.hw, false);
|
||||
proc->isp_fsm = ISP_FSM_INIT;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -46,10 +46,10 @@ esp_err_t esp_isp_demosaic_configure(isp_proc_handle_t proc, const esp_isp_demos
|
||||
esp_err_t esp_isp_demosaic_enable(isp_proc_handle_t proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(proc->demosaic_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "demosaic is enabled already");
|
||||
isp_fsm_t expected_fsm = ISP_FSM_INIT;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->demosaic_fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "demosaic is enabled already");
|
||||
|
||||
isp_ll_demosaic_enable(proc->hal.hw, true);
|
||||
proc->demosaic_fsm = ISP_FSM_ENABLE;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
@@ -57,13 +57,13 @@ esp_err_t esp_isp_demosaic_enable(isp_proc_handle_t proc)
|
||||
esp_err_t esp_isp_demosaic_disable(isp_proc_handle_t proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(proc->demosaic_fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "demosaic isn't enabled yet");
|
||||
isp_fsm_t expected_fsm = ISP_FSM_ENABLE;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->demosaic_fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "demosaic isn't enabled yet");
|
||||
|
||||
if (proc->out_color_format.color_space == (uint32_t)COLOR_SPACE_RAW) {
|
||||
// for other out_color_format, demosaic module is needed for rgb interpolation algorithm
|
||||
isp_ll_demosaic_enable(proc->hal.hw, false);
|
||||
}
|
||||
proc->demosaic_fsm = ISP_FSM_INIT;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
@@ -58,6 +58,8 @@ esp_err_t esp_isp_gamma_configure(isp_proc_handle_t proc, color_component_t comp
|
||||
esp_err_t esp_isp_gamma_enable(isp_proc_handle_t proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
isp_fsm_t expected_fsm = ISP_FSM_INIT;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->gamma_fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "gamma is enabled already");
|
||||
|
||||
portENTER_CRITICAL(&proc->spinlock);
|
||||
isp_ll_gamma_enable(proc->hal.hw, true);
|
||||
@@ -69,6 +71,8 @@ esp_err_t esp_isp_gamma_enable(isp_proc_handle_t proc)
|
||||
esp_err_t esp_isp_gamma_disable(isp_proc_handle_t proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
isp_fsm_t expected_fsm = ISP_FSM_ENABLE;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->gamma_fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "gamma is disabled already");
|
||||
|
||||
portENTER_CRITICAL(&proc->spinlock);
|
||||
isp_ll_gamma_enable(proc->hal.hw, false);
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -28,7 +28,7 @@ static const char *TAG = "ISP_LSC";
|
||||
esp_err_t esp_isp_lsc_allocate_gain_array(isp_proc_handle_t isp_proc, esp_isp_lsc_gain_array_t *gain_array, size_t *out_array_size_per_channel)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(isp_proc && gain_array && out_array_size_per_channel, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(isp_proc->lsc_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "lsc is enabled already");
|
||||
ESP_RETURN_ON_FALSE(atomic_load(&isp_proc->lsc_fsm) == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "lsc is enabled already");
|
||||
|
||||
int num_grids_x_max = ISP_LSC_GET_GRIDS(ISP_LL_HSIZE_MAX);
|
||||
int num_grids_y_max = ISP_LSC_GET_GRIDS(ISP_LL_VSIZE_MAX);
|
||||
@@ -76,10 +76,10 @@ esp_err_t esp_isp_lsc_configure(isp_proc_handle_t isp_proc, const esp_isp_lsc_co
|
||||
for (int y = 0; y < num_grids_y; y++) {
|
||||
for (int x = 0; x < num_grids_x; x++) {
|
||||
int i = y * num_grids_x + x;
|
||||
isp_ll_lut_set_wdata_r_gr(isp_proc->hal.hw, config->gain_array->gain_r[i], config->gain_array->gain_gr[i]);
|
||||
isp_ll_lut_set_cmd(isp_proc->hal.hw, true, false, i, ISP_LL_LUT_LSC);
|
||||
isp_ll_lut_set_wdata_gb_b(isp_proc->hal.hw, config->gain_array->gain_gb[i], config->gain_array->gain_b[i]);
|
||||
isp_ll_lut_set_cmd(isp_proc->hal.hw, true, true, i, ISP_LL_LUT_LSC);
|
||||
isp_ll_lut_lsc_set_wdata_r_gr(isp_proc->hal.hw, config->gain_array->gain_r[i], config->gain_array->gain_gr[i]);
|
||||
isp_ll_lut_lsc_set_cmd(isp_proc->hal.hw, true, false, i, ISP_LL_LUT_LSC);
|
||||
isp_ll_lut_lsc_set_wdata_gb_b(isp_proc->hal.hw, config->gain_array->gain_gb[i], config->gain_array->gain_b[i]);
|
||||
isp_ll_lut_lsc_set_cmd(isp_proc->hal.hw, true, true, i, ISP_LL_LUT_LSC);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -89,10 +89,10 @@ esp_err_t esp_isp_lsc_configure(isp_proc_handle_t isp_proc, const esp_isp_lsc_co
|
||||
esp_err_t esp_isp_lsc_enable(isp_proc_handle_t isp_proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(isp_proc->lsc_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "lsc is enabled already");
|
||||
isp_fsm_t expected_fsm = ISP_FSM_INIT;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&isp_proc->lsc_fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "lsc is enabled already");
|
||||
|
||||
isp_ll_lsc_enable(isp_proc->hal.hw, true);
|
||||
isp_proc->lsc_fsm = ISP_FSM_ENABLE;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
@@ -100,10 +100,10 @@ esp_err_t esp_isp_lsc_enable(isp_proc_handle_t isp_proc)
|
||||
esp_err_t esp_isp_lsc_disable(isp_proc_handle_t isp_proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(isp_proc->lsc_fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "lsc isn't enabled yet");
|
||||
isp_fsm_t expected_fsm = ISP_FSM_ENABLE;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&isp_proc->lsc_fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "lsc isn't enabled yet");
|
||||
|
||||
isp_ll_lsc_enable(isp_proc->hal.hw, false);
|
||||
isp_proc->lsc_fsm = ISP_FSM_INIT;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -51,11 +51,11 @@ esp_err_t esp_isp_sharpen_configure(isp_proc_handle_t proc, const esp_isp_sharpe
|
||||
esp_err_t esp_isp_sharpen_enable(isp_proc_handle_t proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(proc->sharpen_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "sharpen is enabled already");
|
||||
isp_fsm_t expected_fsm = ISP_FSM_INIT;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->sharpen_fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "sharpen is enabled already");
|
||||
|
||||
isp_ll_enable_intr(proc->hal.hw, ISP_LL_EVENT_SHARP_FRAME, true);
|
||||
isp_ll_sharp_enable(proc->hal.hw, true);
|
||||
proc->sharpen_fsm = ISP_FSM_ENABLE;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
@@ -63,11 +63,11 @@ esp_err_t esp_isp_sharpen_enable(isp_proc_handle_t proc)
|
||||
esp_err_t esp_isp_sharpen_disable(isp_proc_handle_t proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(proc->sharpen_fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "sharpen isn't enabled yet");
|
||||
isp_fsm_t expected_fsm = ISP_FSM_ENABLE;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->sharpen_fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "sharpen isn't enabled yet");
|
||||
|
||||
isp_ll_sharp_enable(proc->hal.hw, false);
|
||||
isp_ll_enable_intr(proc->hal.hw, ISP_LL_EVENT_SHARP_FRAME, false);
|
||||
proc->sharpen_fsm = ISP_FSM_INIT;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,78 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <stdatomic.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp_check.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "driver/isp_core.h"
|
||||
#include "driver/isp_wbg.h"
|
||||
#include "esp_private/isp_private.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
#include "soc/chip_revision.h"
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
WBG
|
||||
---------------------------------------------------------------*/
|
||||
|
||||
static const char *TAG = "ISP_WBG";
|
||||
|
||||
esp_err_t esp_isp_wbg_configure(isp_proc_handle_t isp_proc, const esp_isp_wbg_config_t *config)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32P4
|
||||
unsigned chip_version = efuse_hal_chip_revision();
|
||||
if (!ESP_CHIP_REV_ABOVE(chip_version, 300)) {
|
||||
ESP_RETURN_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, TAG, "WBG is not supported on ESP32P4 chips prior than v3.0");
|
||||
}
|
||||
#endif
|
||||
|
||||
ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
|
||||
// Configure clock control mode
|
||||
isp_ll_awb_set_wb_gain_clk_ctrl_mode(isp_proc->hal.hw, ISP_LL_PIPELINE_CLK_CTRL_AUTO);
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_isp_wbg_enable(isp_proc_handle_t isp_proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
isp_fsm_t expected_fsm = ISP_FSM_INIT;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&isp_proc->wbg_fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "wbg is enabled already");
|
||||
|
||||
// Enable WBG module
|
||||
isp_ll_awb_enable_wb_gain(isp_proc->hal.hw, true);
|
||||
|
||||
ESP_LOGD(TAG, "WBG enabled");
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_isp_wbg_set_wb_gain(isp_proc_handle_t isp_proc, isp_wbg_gain_t gain)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(atomic_load(&isp_proc->wbg_fsm) == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "wbg isn't enabled yet");
|
||||
|
||||
// Set WBG gain
|
||||
isp_ll_awb_set_wb_gain(isp_proc->hal.hw, gain);
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_isp_wbg_disable(isp_proc_handle_t isp_proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
isp_fsm_t expected_fsm = ISP_FSM_ENABLE;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&isp_proc->wbg_fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "wbg isn't enabled yet");
|
||||
|
||||
// Disable WBG module
|
||||
isp_ll_awb_enable_wb_gain(isp_proc->hal.hw, false);
|
||||
|
||||
ESP_LOGD(TAG, "WBG disabled");
|
||||
return ESP_OK;
|
||||
}
|
||||
@@ -226,15 +226,9 @@ esp_err_t rmt_select_periph_clock(rmt_channel_handle_t chan, rmt_clock_source_t
|
||||
// if the CPU frequency goes down, the transfer+encoding scheme could be unstable because CPU can't fill the data in time
|
||||
// so, choose ESP_PM_CPU_FREQ_MAX lock for non-dma mode
|
||||
// otherwise, chose lock type based on the clock source
|
||||
// note, even if the clock source is APB, we still use CPU_FREQ_MAX lock to ensure the stability of the RMT operation.
|
||||
esp_pm_lock_type_t pm_lock_type = chan->dma_chan ? ESP_PM_NO_LIGHT_SLEEP : ESP_PM_CPU_FREQ_MAX;
|
||||
|
||||
#if SOC_RMT_SUPPORT_APB
|
||||
if (clk_src == RMT_CLK_SRC_APB) {
|
||||
// APB clock frequency can be changed during DFS
|
||||
pm_lock_type = ESP_PM_APB_FREQ_MAX;
|
||||
}
|
||||
#endif // SOC_RMT_SUPPORT_APB
|
||||
|
||||
sprintf(chan->pm_lock_name, "rmt_%d_%d", group->group_id, chan->channel_id); // e.g. rmt_0_0
|
||||
ret = esp_pm_lock_create(pm_lock_type, 0, chan->pm_lock_name, &chan->pm_lock);
|
||||
ESP_RETURN_ON_ERROR(ret, TAG, "create pm lock failed");
|
||||
|
||||
@@ -1854,7 +1854,6 @@ TEST_CASE("test_spi_master_sleep_retention", "[spi]")
|
||||
spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
|
||||
buscfg.flags |= SPICOMMON_BUSFLAG_GPIO_PINS;
|
||||
buscfg.flags |= SPICOMMON_BUSFLAG_SLP_ALLOW_PD;
|
||||
buscfg.miso_io_num = buscfg.mosi_io_num; // set spi "self-loop"
|
||||
uint8_t send[16] = "hello spi x\n";
|
||||
uint8_t recv[16];
|
||||
spi_transaction_t trans_cfg = {
|
||||
@@ -1871,6 +1870,8 @@ TEST_CASE("test_spi_master_sleep_retention", "[spi]")
|
||||
#endif
|
||||
printf("Retention on GPSPI%d with dma: %d\n", periph + 1, use_dma);
|
||||
TEST_ESP_OK(spi_bus_initialize(periph, &buscfg, use_dma));
|
||||
// set spi "self-loop" after bus initialized
|
||||
spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_GPIO, spi_periph_signal[periph].spid_out);
|
||||
TEST_ESP_OK(spi_bus_add_device(periph, &devcfg, &dev_handle));
|
||||
|
||||
for (uint8_t cnt = 0; cnt < 3; cnt ++) {
|
||||
@@ -1925,8 +1926,9 @@ TEST_CASE("test_spi_master_auto_sleep_retention", "[spi]")
|
||||
spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
|
||||
buscfg.flags = (allow_pd) ? SPICOMMON_BUSFLAG_SLP_ALLOW_PD : 0;
|
||||
buscfg.flags |= SPICOMMON_BUSFLAG_GPIO_PINS;
|
||||
buscfg.miso_io_num = buscfg.mosi_io_num; // set spi "self-loop"
|
||||
TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_DISABLED));
|
||||
// set spi "self-loop" after bus initialized
|
||||
spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out);
|
||||
|
||||
spi_device_handle_t dev_handle;
|
||||
spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
|
||||
|
||||
@@ -50,6 +50,7 @@
|
||||
#define UART_BAUD_RATE (115200)
|
||||
#define BUF_SIZE (1024)
|
||||
#define TIMER_WAKEUP_TIME_US (1 * 100 * 1000)
|
||||
#define UART_READ_TOUT (pdMS_TO_TICKS(500))
|
||||
|
||||
static void force_stdout(void)
|
||||
{
|
||||
@@ -125,14 +126,15 @@ void send_and_verify_recived_data(const char* message, uint8_t length, bool shou
|
||||
uart_flush_input(MASTER_UART_NUM);
|
||||
uart_write_bytes(MASTER_UART_NUM, message, length);
|
||||
/* Wait for uart write finish */
|
||||
uart_wait_tx_idle_polling(MASTER_UART_NUM);
|
||||
uart_wait_tx_done(MASTER_UART_NUM, portMAX_DELAY);
|
||||
|
||||
bool wake_up_detected = false;
|
||||
const char *target = "Wakeup OK!";
|
||||
int target_len = 11;
|
||||
bool match = true;
|
||||
char *data = (char *) malloc(BUF_SIZE);
|
||||
int len = uart_read_bytes(MASTER_UART_NUM, data, target_len, 5000 / portTICK_PERIOD_MS);
|
||||
int len = uart_read_bytes(MASTER_UART_NUM, data, target_len, UART_READ_TOUT);
|
||||
*(data + len) = '\0';
|
||||
|
||||
if (len > 0) {
|
||||
if (len != target_len) {
|
||||
@@ -212,7 +214,10 @@ static void enter_sleep_and_send_respond(void)
|
||||
}
|
||||
|
||||
/* Wait for uart write finish */
|
||||
uart_wait_tx_idle_polling(SLAVE_UART_NUM);
|
||||
uart_wait_tx_done(MASTER_UART_NUM, portMAX_DELAY);
|
||||
|
||||
/* Wait for Master read data, otherwise the UART_INTR_TX_BRK_DONE intr will be triggered*/
|
||||
vTaskDelay(UART_READ_TOUT);
|
||||
}
|
||||
|
||||
// slave
|
||||
|
||||
@@ -198,6 +198,17 @@ if(CONFIG_IDF_TARGET_ESP32H4)
|
||||
)
|
||||
endif()
|
||||
|
||||
|
||||
if(CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
|
||||
if(CMAKE_C_COMPILER_ID MATCHES "GNU")
|
||||
idf_build_set_property(COMPILE_OPTIONS "-march=rv32imafc_zicsr_zifencei_xesppie" APPEND)
|
||||
endif()
|
||||
elseif(CONFIG_IDF_TARGET_ESP32P4)
|
||||
if(CMAKE_C_COMPILER_ID MATCHES "Clang") # TODO: LLVM-478
|
||||
message(FATAL_ERROR "ESP32-P4 rev. 3.0 or higher is not supported in Clang-based toolchain")
|
||||
endif()
|
||||
endif()
|
||||
|
||||
idf_component_register(SRCS ${srcs}
|
||||
INCLUDE_DIRS ${public_include_dirs}
|
||||
PRIV_INCLUDE_DIRS port/include include/esp_private
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -155,6 +155,29 @@ TEST(partition_api, test_partition_mmap)
|
||||
TEST_ASSERT_EQUAL(err, ESP_ERR_INVALID_SIZE);
|
||||
}
|
||||
|
||||
TEST(partition_api, test_partition_mmap_support_for_greater_than_4M)
|
||||
{
|
||||
// Scenario: Not specified flash size but provided partition table > 4M (default size supported)
|
||||
// esp_partition_mmap should calculate partition size from the binary, create mmap_flash_file and return ESP_OK
|
||||
|
||||
// unmap file to have correct initial conditions, regardless of result
|
||||
esp_partition_file_munmap();
|
||||
|
||||
// get and initialize the control structure for file mmap
|
||||
esp_partition_file_mmap_ctrl_t *p_file_mmap_ctrl = esp_partition_get_file_mmap_ctrl_input();
|
||||
TEST_ASSERT_NOT_NULL(p_file_mmap_ctrl);
|
||||
|
||||
memset(p_file_mmap_ctrl, 0, sizeof(*p_file_mmap_ctrl));
|
||||
strlcpy(p_file_mmap_ctrl->partition_file_name, BUILD_DIR"/partition_table/partition-table_8M.bin", sizeof(p_file_mmap_ctrl->partition_file_name));
|
||||
|
||||
// esp_partition_find_first calls the esp_partition_file_mmap in the background
|
||||
const esp_partition_t *partition_data = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, "storage");
|
||||
TEST_ASSERT_NOT_NULL(partition_data);
|
||||
|
||||
// cleanup after test
|
||||
esp_partition_file_munmap();
|
||||
}
|
||||
|
||||
TEST(partition_api, test_partition_mmap_diff_size)
|
||||
{
|
||||
// Scenario: default temporary flash file, explicitly specified size and file with partition table
|
||||
@@ -336,14 +359,10 @@ TEST(partition_api, test_partition_mmap_name_size)
|
||||
memset(p_file_mmap_ctrl_input, 0, sizeof(*p_file_mmap_ctrl_input));
|
||||
}
|
||||
|
||||
/* Negative TC to ensure mmap setup checks presence of partition file name (partition table binary file)
|
||||
* if flash size parameter was specified.
|
||||
* This test case specifies just flash file size but omits partition table binary file name.
|
||||
*/
|
||||
TEST(partition_api, test_partition_mmap_size_no_partition)
|
||||
{
|
||||
// Negative Scenario: conflicting settings - flash_file_name empty, flash_file_size set and partition_file_name not set
|
||||
// esp_partition_file_mmap should return ESP_ERR_INVALID_ARG
|
||||
// Scenario: flash_file_name empty, incorrect flash_file_size set and partition_file_name not set
|
||||
// esp_partition_file_mmap should calculate correct flash_file_size based on default partition table and return ESP_OK
|
||||
|
||||
// unmap file to have correct initial conditions, regardless of result
|
||||
esp_partition_file_munmap();
|
||||
@@ -357,22 +376,17 @@ TEST(partition_api, test_partition_mmap_size_no_partition)
|
||||
|
||||
const uint8_t *p_mem_block = NULL;
|
||||
esp_err_t err = esp_partition_file_mmap(&p_mem_block);
|
||||
|
||||
// expected result is invalid argument
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, err);
|
||||
TEST_ESP_OK(err);
|
||||
|
||||
// cleanup after test
|
||||
esp_partition_file_munmap();
|
||||
memset(p_file_mmap_ctrl_input, 0, sizeof(*p_file_mmap_ctrl_input));
|
||||
}
|
||||
|
||||
/* Negative TC to ensure mmap setup checks presence of flash size parameter if partition file name (partition table binary file) was specified.
|
||||
* This test case specifies just partition table binary file name but omits flash file size.
|
||||
*/
|
||||
TEST(partition_api, test_partition_mmap_no_size_partition)
|
||||
{
|
||||
// Negative Scenario: conflicting settings - flash_file_name empty, flash_file_size not set and partition_file_name set
|
||||
// esp_partition_file_mmap should return ESP_ERR_INVALID_ARG
|
||||
// Scenario: - flash_file_name empty, flash_file_size not set and partition_file_name set
|
||||
// esp_partition_file_mmap() will calculate flash_file_size based on given partition_table and return ESP_OK
|
||||
|
||||
// unmap file to have correct initial conditions, regardless of result
|
||||
esp_partition_file_munmap();
|
||||
@@ -382,14 +396,12 @@ TEST(partition_api, test_partition_mmap_no_size_partition)
|
||||
TEST_ASSERT_NOT_NULL(p_file_mmap_ctrl_input);
|
||||
|
||||
memset(p_file_mmap_ctrl_input, 0, sizeof(*p_file_mmap_ctrl_input));
|
||||
const char *partition_file_name = "/tmp/xyz.bin";
|
||||
const char *partition_file_name = BUILD_DIR"/partition_table/partition-table.bin";
|
||||
strlcpy(p_file_mmap_ctrl_input->partition_file_name, partition_file_name, sizeof(p_file_mmap_ctrl_input->partition_file_name));
|
||||
|
||||
const uint8_t *p_mem_block = NULL;
|
||||
esp_err_t err = esp_partition_file_mmap(&p_mem_block);
|
||||
|
||||
// expected result is invalid argument
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, err);
|
||||
TEST_ESP_OK(err);
|
||||
|
||||
// cleanup after test
|
||||
esp_partition_file_munmap();
|
||||
@@ -463,38 +475,6 @@ TEST(partition_api, test_partition_mmap_pfile_nf)
|
||||
memset(p_file_mmap_ctrl_input, 0, sizeof(*p_file_mmap_ctrl_input));
|
||||
}
|
||||
|
||||
/* Negative TC to check that requested size of emulated flash is at least so big to be able to load binary partition table.
|
||||
* Too small emulated flash size is introduced and respective error code is evaluated after mmap call.
|
||||
*/
|
||||
TEST(partition_api, test_partition_mmap_size_too_small)
|
||||
{
|
||||
// Negative Scenario: specified flash file size too small to hold at least partition table at default offset
|
||||
// esp_partition_file_mmap should return ESP_ERR_INVALID_SIZE
|
||||
|
||||
// unmap file to have correct initial conditions, regardless of result
|
||||
esp_partition_file_munmap();
|
||||
|
||||
// get and initialize the control structure for file mmap
|
||||
esp_partition_file_mmap_ctrl_t *p_file_mmap_ctrl_input = esp_partition_get_file_mmap_ctrl_input();
|
||||
TEST_ASSERT_NOT_NULL(p_file_mmap_ctrl_input);
|
||||
|
||||
memset(p_file_mmap_ctrl_input, 0, sizeof(*p_file_mmap_ctrl_input));
|
||||
|
||||
// set valid partition table name and very small flash size
|
||||
strlcpy(p_file_mmap_ctrl_input->partition_file_name, BUILD_DIR "/partition_table/partition-table.bin", sizeof(p_file_mmap_ctrl_input->partition_file_name));
|
||||
p_file_mmap_ctrl_input->flash_file_size = 1;
|
||||
|
||||
const uint8_t *p_mem_block = NULL;
|
||||
esp_err_t err = esp_partition_file_mmap(&p_mem_block);
|
||||
|
||||
// expected result is invalid argument
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_SIZE, err);
|
||||
|
||||
// cleanup after test
|
||||
esp_partition_file_munmap();
|
||||
memset(p_file_mmap_ctrl_input, 0, sizeof(*p_file_mmap_ctrl_input));
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
size_t read_ops;
|
||||
size_t write_ops;
|
||||
@@ -772,6 +752,7 @@ TEST_GROUP_RUNNER(partition_api)
|
||||
RUN_TEST_CASE(partition_api, test_partition_find_first);
|
||||
RUN_TEST_CASE(partition_api, test_partition_ops);
|
||||
RUN_TEST_CASE(partition_api, test_partition_mmap);
|
||||
RUN_TEST_CASE(partition_api, test_partition_mmap_support_for_greater_than_4M);
|
||||
RUN_TEST_CASE(partition_api, test_partition_mmap_diff_size);
|
||||
RUN_TEST_CASE(partition_api, test_partition_mmap_reopen);
|
||||
RUN_TEST_CASE(partition_api, test_partition_mmap_remove);
|
||||
@@ -780,7 +761,6 @@ TEST_GROUP_RUNNER(partition_api)
|
||||
RUN_TEST_CASE(partition_api, test_partition_mmap_no_size_partition);
|
||||
RUN_TEST_CASE(partition_api, test_partition_mmap_ffile_nf);
|
||||
RUN_TEST_CASE(partition_api, test_partition_mmap_pfile_nf);
|
||||
RUN_TEST_CASE(partition_api, test_partition_mmap_size_too_small);
|
||||
RUN_TEST_CASE(partition_api, test_partition_stats);
|
||||
RUN_TEST_CASE(partition_api, test_partition_power_off_emulation);
|
||||
RUN_TEST_CASE(partition_api, test_partition_copy);
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -8,6 +8,7 @@
|
||||
#include <assert.h>
|
||||
#include <string.h>
|
||||
#include <inttypes.h>
|
||||
#include <stdio.h>
|
||||
#include <sys/mman.h>
|
||||
#include <sys/stat.h>
|
||||
#include <fcntl.h>
|
||||
@@ -110,6 +111,64 @@ const char *esp_partition_subtype_to_str(const uint32_t type, const uint32_t sub
|
||||
}
|
||||
}
|
||||
|
||||
// Calculate required emulated flash size from a partition table binary.
|
||||
// Returns 0 on failure.
|
||||
static size_t esp_partition_calc_required_flash_size_from_file(const char *partition_file_path)
|
||||
{
|
||||
if (partition_file_path == NULL || partition_file_path[0] == '\0') {
|
||||
return 0;
|
||||
}
|
||||
|
||||
FILE *fp = fopen(partition_file_path, "rb");
|
||||
if (fp == NULL) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Determine file size as an additional lower bound
|
||||
if (fseek(fp, 0L, SEEK_END) != 0) {
|
||||
fclose(fp);
|
||||
return 0;
|
||||
}
|
||||
long file_size = ftell(fp);
|
||||
if (file_size < 0) {
|
||||
fclose(fp);
|
||||
return 0;
|
||||
}
|
||||
if (fseek(fp, 0L, SEEK_SET) != 0) {
|
||||
fclose(fp);
|
||||
return 0;
|
||||
}
|
||||
|
||||
size_t max_end = 0;
|
||||
size_t max_entries = file_size / sizeof(esp_partition_info_t);
|
||||
for (size_t i = 0; i < max_entries; i++) {
|
||||
esp_partition_info_t entry;
|
||||
size_t r = fread(&entry, 1, sizeof(entry), fp);
|
||||
if (r != sizeof(entry) || entry.magic != ESP_PARTITION_MAGIC) {
|
||||
break;
|
||||
}
|
||||
uint32_t end = entry.pos.offset + entry.pos.size;
|
||||
if (end > max_end) {
|
||||
max_end = end;
|
||||
}
|
||||
}
|
||||
|
||||
fclose(fp);
|
||||
|
||||
// Also ensure the flash holds the partition table itself at its offset
|
||||
size_t min_from_table_blob = (size_t)file_size + ESP_PARTITION_TABLE_OFFSET;
|
||||
size_t required = (max_end > min_from_table_blob) ? max_end : min_from_table_blob;
|
||||
|
||||
// Round up to emulated sector size
|
||||
size_t sector = ESP_PARTITION_EMULATED_SECTOR_SIZE;
|
||||
size_t rem = required % sector;
|
||||
if (rem != 0) {
|
||||
required += (sector - rem);
|
||||
}
|
||||
|
||||
return required;
|
||||
}
|
||||
|
||||
esp_err_t esp_partition_file_mmap(const uint8_t **part_desc_addr_start)
|
||||
{
|
||||
// temporary file is used only if control structure doesn't specify file name.
|
||||
@@ -136,21 +195,10 @@ esp_err_t esp_partition_file_mmap(const uint8_t **part_desc_addr_start)
|
||||
|
||||
open_existing_file = true;
|
||||
} else {
|
||||
// Open temporary file. If size was specified, also partition table has to be specified, otherwise raise error.
|
||||
// If none of size, partition table were specified, defaults are used.
|
||||
// Name of temporary file is available in s_esp_partition_file_mmap_ctrl.flash_file_name
|
||||
|
||||
// name of temporary file and its size is available in s_esp_partition_file_mmap_ctrl.flash_file_name and s_esp_partition_file_mmap_ctrl_input.flash_file_size respectively
|
||||
bool has_partfile = (strlen(s_esp_partition_file_mmap_ctrl_input.partition_file_name) > 0);
|
||||
bool has_len = (s_esp_partition_file_mmap_ctrl_input.flash_file_size > 0);
|
||||
|
||||
// conflicting input
|
||||
if (has_partfile != has_len) {
|
||||
ESP_LOGE(TAG, "Invalid combination of Partition file name: %s flash file size: %" PRIu32 " was specified. Use either both parameters or none.",
|
||||
s_esp_partition_file_mmap_ctrl_input.partition_file_name,
|
||||
(uint32_t) s_esp_partition_file_mmap_ctrl_input.flash_file_size);
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
// check if partition file is present, if not, use default
|
||||
if (!has_partfile) {
|
||||
strlcpy(s_esp_partition_file_mmap_ctrl_act.partition_file_name, BUILD_DIR "/partition_table/partition-table.bin", sizeof(s_esp_partition_file_mmap_ctrl_act.partition_file_name));
|
||||
@@ -158,10 +206,13 @@ esp_err_t esp_partition_file_mmap(const uint8_t **part_desc_addr_start)
|
||||
strlcpy(s_esp_partition_file_mmap_ctrl_act.partition_file_name, s_esp_partition_file_mmap_ctrl_input.partition_file_name, sizeof(s_esp_partition_file_mmap_ctrl_act.partition_file_name));
|
||||
}
|
||||
|
||||
// check if flash size is present, if not set to default
|
||||
if (!has_len) {
|
||||
s_esp_partition_file_mmap_ctrl_act.flash_file_size = ESP_PARTITION_DEFAULT_EMULATED_FLASH_SIZE;
|
||||
} else {
|
||||
// derive the partition size from the s_esp_partition_file_mmap_ctrl_act.partition_file_name
|
||||
size_t derived_size = esp_partition_calc_required_flash_size_from_file(s_esp_partition_file_mmap_ctrl_act.partition_file_name);
|
||||
// if derived size is zero, use default partition size
|
||||
s_esp_partition_file_mmap_ctrl_act.flash_file_size = (derived_size > 0) ? derived_size : ESP_PARTITION_DEFAULT_EMULATED_FLASH_SIZE;
|
||||
|
||||
// if the size of the temporary file is specified, check if the given partition size fits within it
|
||||
if (has_len && s_esp_partition_file_mmap_ctrl_input.flash_file_size > derived_size) {
|
||||
s_esp_partition_file_mmap_ctrl_act.flash_file_size = s_esp_partition_file_mmap_ctrl_input.flash_file_size;
|
||||
}
|
||||
|
||||
@@ -382,7 +433,7 @@ esp_err_t esp_partition_file_munmap(void)
|
||||
|
||||
esp_err_t esp_partition_write(const esp_partition_t *partition, size_t dst_offset, const void *src, size_t size)
|
||||
{
|
||||
assert(partition != NULL && s_spiflash_mem_file_buf != NULL);
|
||||
assert(partition != NULL && s_spiflash_mem_file_buf != NULL && src != NULL);
|
||||
|
||||
if (partition->readonly) {
|
||||
return ESP_ERR_NOT_ALLOWED;
|
||||
@@ -397,6 +448,15 @@ esp_err_t esp_partition_write(const esp_partition_t *partition, size_t dst_offse
|
||||
return ESP_ERR_INVALID_SIZE;
|
||||
}
|
||||
|
||||
// Ensure write stays within mapped flash file size
|
||||
if (s_esp_partition_file_mmap_ctrl_act.flash_file_size > 0) {
|
||||
size_t start = (size_t)partition->address + dst_offset;
|
||||
size_t max_len = s_esp_partition_file_mmap_ctrl_act.flash_file_size;
|
||||
if ((start > max_len) || ((size + start) > max_len)) {
|
||||
return ESP_ERR_INVALID_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
void *dst_addr = s_spiflash_mem_file_buf + partition->address + dst_offset;
|
||||
ESP_LOGV(TAG, "esp_partition_write(): partition=%s dst_offset=%" PRIu32 " src=%p size=%" PRIu32 " (real dst address: %p)", partition->label, (uint32_t) dst_offset, src, (uint32_t) size, dst_addr);
|
||||
|
||||
@@ -432,7 +492,7 @@ esp_err_t esp_partition_write(const esp_partition_t *partition, size_t dst_offse
|
||||
|
||||
esp_err_t esp_partition_read(const esp_partition_t *partition, size_t src_offset, void *dst, size_t size)
|
||||
{
|
||||
assert(partition != NULL && s_spiflash_mem_file_buf != NULL);
|
||||
assert(partition != NULL && s_spiflash_mem_file_buf != NULL && dst != NULL);
|
||||
|
||||
if (partition->encrypted) {
|
||||
return ESP_ERR_NOT_SUPPORTED;
|
||||
@@ -444,6 +504,15 @@ esp_err_t esp_partition_read(const esp_partition_t *partition, size_t src_offset
|
||||
return ESP_ERR_INVALID_SIZE;
|
||||
}
|
||||
|
||||
// Ensure read stays within mapped flash file size
|
||||
if (s_esp_partition_file_mmap_ctrl_act.flash_file_size > 0) {
|
||||
size_t start = (size_t)partition->address + src_offset;
|
||||
size_t max_len = s_esp_partition_file_mmap_ctrl_act.flash_file_size;
|
||||
if ((start > max_len) || ((size + start) > max_len)) {
|
||||
return ESP_ERR_INVALID_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
void *src_addr = s_spiflash_mem_file_buf + partition->address + src_offset;
|
||||
ESP_LOGV(TAG, "esp_partition_read(): partition=%s src_offset=%" PRIu32 " dst=%p size=%" PRIu32 " (real src address: %p)", partition->label, (uint32_t) src_offset, dst, (uint32_t) size, src_addr);
|
||||
|
||||
@@ -468,7 +537,7 @@ esp_err_t esp_partition_write_raw(const esp_partition_t *partition, size_t dst_o
|
||||
|
||||
esp_err_t esp_partition_erase_range(const esp_partition_t *partition, size_t offset, size_t size)
|
||||
{
|
||||
assert(partition != NULL);
|
||||
assert(partition != NULL && s_spiflash_mem_file_buf != NULL);
|
||||
|
||||
if (partition->readonly) {
|
||||
return ESP_ERR_NOT_ALLOWED;
|
||||
@@ -480,6 +549,15 @@ esp_err_t esp_partition_erase_range(const esp_partition_t *partition, size_t off
|
||||
return ESP_ERR_INVALID_SIZE;
|
||||
}
|
||||
|
||||
// Ensure erase stays within mapped flash file size
|
||||
if (s_esp_partition_file_mmap_ctrl_act.flash_file_size > 0) {
|
||||
size_t start = (size_t)partition->address + offset;
|
||||
size_t max_len = s_esp_partition_file_mmap_ctrl_act.flash_file_size;
|
||||
if ((start > max_len) || ((size + start) > max_len)) {
|
||||
return ESP_ERR_INVALID_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
void *target_addr = s_spiflash_mem_file_buf + partition->address + offset;
|
||||
ESP_LOGV(TAG, "esp_partition_erase_range(): partition=%s offset=%" PRIu32 " size=%" PRIu32 " (real target address: %p)", partition->label, (uint32_t) offset, (uint32_t) size, target_addr);
|
||||
|
||||
|
||||
+1
-1
Submodule components/esp_phy/lib updated: 45ce270340...218d3e79a3
@@ -69,7 +69,6 @@ choice SPIRAM_USE
|
||||
return SPI RAM pointers.
|
||||
|
||||
config SPIRAM_USE_MEMMAP
|
||||
depends on IDF_TARGET_ESP32
|
||||
bool "Integrate RAM into memory map"
|
||||
config SPIRAM_USE_CAPS_ALLOC
|
||||
bool "Make RAM allocatable using heap_caps_malloc(..., MALLOC_CAP_SPIRAM)"
|
||||
|
||||
@@ -156,7 +156,7 @@ systimer_hal_set_tick_rate_ops = 0x40002eac;
|
||||
/* Functions */
|
||||
sta_reset_beacon_timeout = 0x40003024;
|
||||
ieee80211_post_hmac_tx = 0x40003028;
|
||||
sta_rx_eapol = 0x4000302c;
|
||||
//sta_rx_eapol = 0x4000302c;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
len_dh_ie_ptr = 0x3fcdfa6c;
|
||||
g_authmode_threshold_failure_ptr = 0x3fcdfa68;
|
||||
|
||||
@@ -66,7 +66,7 @@ wifi_rf_phy_disable = 0x40000bc8;
|
||||
wifi_rf_phy_enable = 0x40000bcc;
|
||||
wifi_is_started = 0x40000bd0;
|
||||
/*sta_input = 0x40000bd4;*/
|
||||
sta_rx_eapol = 0x40000bd8;
|
||||
//sta_rx_eapol = 0x40000bd8;
|
||||
//sta_reset_beacon_timeout = 0x40000bdc;
|
||||
sta_get_beacon_timeout = 0x40000be0;
|
||||
ampdu_process_multicast_address_qos_frame = 0x40000be4;
|
||||
|
||||
@@ -62,7 +62,7 @@ wifi_rf_phy_disable = 0x40000b30;
|
||||
wifi_rf_phy_enable = 0x40000b34;
|
||||
wifi_is_started = 0x40000b38;
|
||||
/*sta_input = 0x40000b3c;*/
|
||||
sta_rx_eapol = 0x40000b40;
|
||||
//sta_rx_eapol = 0x40000b40;
|
||||
//sta_reset_beacon_timeout = 0x40000b44;
|
||||
sta_get_beacon_timeout = 0x40000b48;
|
||||
ampdu_process_multicast_address_qos_frame = 0x40000b4c;
|
||||
|
||||
@@ -90,7 +90,7 @@ ESP_SYSTEM_INIT_FN(esp_security_init, SECONDARY, BIT(0), 103)
|
||||
#if CONFIG_SECURE_BOOT_V2_ENABLED
|
||||
// H2, H21
|
||||
#if SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED
|
||||
// Also write protects the ECDSA_CURVE_MODE efuse bit.
|
||||
// Also write protects the ECC_FORCE_CONST_TIME efuse bit.
|
||||
if (ecdsa_ll_is_configurable_curve_supported()) {
|
||||
err = esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_ECDSA_CURVE_MODE);
|
||||
if (err != ESP_OK) {
|
||||
@@ -102,10 +102,13 @@ ESP_SYSTEM_INIT_FN(esp_security_init, SECONDARY, BIT(0), 103)
|
||||
|
||||
#if !CONFIG_SECURE_BOOT_SKIP_WRITE_PROTECTION_SCA
|
||||
// C5
|
||||
#if SOC_ECDSA_SUPPORT_CURVE_P384 && !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS
|
||||
#if SOC_ECDSA_SUPPORT_CURVE_P384 && !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS && !CONFIG_IDF_TARGET_ESP32P4
|
||||
// Since SECURE_BOOT_SHA384_EN, XTS_DPA_PSEUDO_LEVEL, and ECC_FORCE_CONST_TIME share the
|
||||
// same write-protection bit, these efuses should only be write-protected after all of
|
||||
// them have been programmed.
|
||||
// Note: ESP32-P4 lacks WR_DIS_SECURE_BOOT_SHA384_EN bit, so it relies on software protection
|
||||
// in the efuse write APIs (see esp_efuse_api.c) to prevent unauthorized programming of
|
||||
// SECURE_BOOT_SHA384_EN when Secure Boot using SHA-256 is enabled.
|
||||
err = esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_SECURE_BOOT_SHA384_EN);
|
||||
if (err != ESP_OK) {
|
||||
ESP_LOGE(TAG, "Failed to write protect the SECURE_BOOT_SHA384_EN efuse bit.");
|
||||
|
||||
@@ -643,11 +643,12 @@ esp_err_t esp_tee_sec_storage_ecdsa_sign_pbkdf2(const esp_tee_sec_storage_pbkdf2
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
hmac_key_id_t key_id = (hmac_key_id_t)(CONFIG_SECURE_TEE_PBKDF2_EFUSE_HMAC_KEY_ID);
|
||||
if (key_id < 0 || key_id >= HMAC_KEY_MAX) {
|
||||
int cfg_key_id = (int)CONFIG_SECURE_TEE_PBKDF2_EFUSE_HMAC_KEY_ID;
|
||||
if (cfg_key_id < 0 || cfg_key_id >= HMAC_KEY_MAX) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
hmac_key_id_t key_id = (hmac_key_id_t)cfg_key_id;
|
||||
esp_efuse_block_t blk = (esp_efuse_block_t)(EFUSE_BLK_KEY0 + key_id);
|
||||
if (esp_efuse_get_key_purpose(blk) != ESP_EFUSE_KEY_PURPOSE_HMAC_UP) {
|
||||
ESP_LOGE(TAG, "HMAC key is not burnt in the specified eFuse block ID");
|
||||
|
||||
@@ -48,12 +48,6 @@ __attribute__((unused)) static const uint32_t mmu_op_fail_seq[8] = {[0 ... 7] =
|
||||
} while (0)
|
||||
#endif
|
||||
|
||||
#if SOC_TEE_FLASH_OP_FAIL_FAULT
|
||||
#define CHECK_FLASH_OP_FAIL(err) TEST_ESP_ERR(ESP_FAIL, err)
|
||||
#else
|
||||
#define CHECK_FLASH_OP_FAIL(err) do { (void)(err); esp_restart(); } while (0)
|
||||
#endif
|
||||
|
||||
static const char *TAG = "test_esp_tee_flash_prot";
|
||||
|
||||
static void set_boot_count_in_nvs(uint8_t boot_count)
|
||||
@@ -146,8 +140,7 @@ static void test_esp_partition_api_r(const esp_partition_t *part)
|
||||
TEST_ASSERT_NOT_NULL(part);
|
||||
uint8_t buf_r[128];
|
||||
memset(buf_r, 0x00, sizeof(buf_r));
|
||||
esp_err_t err = esp_partition_read(part, 0x00, buf_r, sizeof(buf_r));
|
||||
CHECK_FLASH_OP_FAIL(err);
|
||||
esp_partition_read(part, 0x00, buf_r, sizeof(buf_r));
|
||||
}
|
||||
|
||||
static void test_esp_partition_api_w(const esp_partition_t *part)
|
||||
@@ -155,15 +148,13 @@ static void test_esp_partition_api_w(const esp_partition_t *part)
|
||||
TEST_ASSERT_NOT_NULL(part);
|
||||
uint8_t buf_w[128];
|
||||
memset(buf_w, 0xA5, sizeof(buf_w));
|
||||
esp_err_t err = esp_partition_write(part, 0x00, buf_w, sizeof(buf_w));
|
||||
CHECK_FLASH_OP_FAIL(err);
|
||||
esp_partition_write(part, 0x00, buf_w, sizeof(buf_w));
|
||||
}
|
||||
|
||||
static void test_esp_partition_api_e(const esp_partition_t *part)
|
||||
{
|
||||
TEST_ASSERT_NOT_NULL(part);
|
||||
esp_err_t err = esp_partition_erase_range(part, 0x00, SPI_FLASH_SEC_SIZE);
|
||||
CHECK_FLASH_OP_FAIL(err);
|
||||
esp_partition_erase_range(part, 0x00, SPI_FLASH_SEC_SIZE);
|
||||
}
|
||||
|
||||
static void test_esp_partition_api(void)
|
||||
@@ -267,22 +258,19 @@ static void test_esp_flash_api_r(uint32_t paddr)
|
||||
{
|
||||
uint8_t buf_r[128];
|
||||
memset(buf_r, 0x00, sizeof(buf_r));
|
||||
esp_err_t err = esp_flash_read(NULL, buf_r, paddr, sizeof(buf_r));
|
||||
CHECK_FLASH_OP_FAIL(err);
|
||||
esp_flash_read(NULL, buf_r, paddr, sizeof(buf_r));
|
||||
}
|
||||
|
||||
static void test_esp_flash_api_w(uint32_t paddr)
|
||||
{
|
||||
uint8_t buf_w[128];
|
||||
memset(buf_w, 0xA5, sizeof(buf_w));
|
||||
esp_err_t err = esp_flash_write(NULL, buf_w, paddr, sizeof(buf_w));
|
||||
CHECK_FLASH_OP_FAIL(err);
|
||||
esp_flash_write(NULL, buf_w, paddr, sizeof(buf_w));
|
||||
}
|
||||
|
||||
static void test_esp_flash_api_e(uint32_t paddr)
|
||||
{
|
||||
esp_err_t err = esp_flash_erase_region(NULL, paddr, SPI_FLASH_SEC_SIZE);
|
||||
CHECK_FLASH_OP_FAIL(err);
|
||||
esp_flash_erase_region(NULL, paddr, SPI_FLASH_SEC_SIZE);
|
||||
}
|
||||
|
||||
static void test_esp_flash_api(void)
|
||||
|
||||
+1
-1
Submodule components/esp_wifi/lib updated: f1df1ec287...3fa82c561a
@@ -140,6 +140,9 @@ TEST_CASE("Task on specific core works", "[freertos][psram]")
|
||||
TEST_ASSERT_EQUAL((size_t) corenum, corenum_info.recorded_core_num);
|
||||
|
||||
vTaskDelete(task_handle);
|
||||
|
||||
// Add a short delay to allow the idle task to free any remaining task memory
|
||||
vTaskDelay(10);
|
||||
}
|
||||
}
|
||||
#endif // !CONFIG_FREERTOS_UNICORE
|
||||
|
||||
+1
@@ -394,6 +394,7 @@ TEST_CASE("Test vTaskSuspendAll allows scheduling on other cores", "[freertos]")
|
||||
// Cleanup tasks
|
||||
vTaskDelete(a1_task_hdl);
|
||||
vTaskDelete(b1_task_hdl);
|
||||
vTaskDelay(10);
|
||||
}
|
||||
|
||||
vSemaphoreDelete(test_unblk_done_sem);
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -34,6 +34,9 @@ static volatile uint32_t count;
|
||||
// Lock variable to create a blocked task scenario
|
||||
static volatile SemaphoreHandle_t task_mutex;
|
||||
|
||||
// Semaphore to synchronize yield test tasks
|
||||
static SemaphoreHandle_t yield_sync_sem;
|
||||
|
||||
// This helper macro is used to store the task id atomically
|
||||
#define STORE_TASK_ID(task_id) ({ \
|
||||
portENTER_CRITICAL(&idx_lock); \
|
||||
@@ -56,10 +59,11 @@ static void yield_task1(void *arg)
|
||||
/* Store task_id in the sequence array */
|
||||
STORE_TASK_ID(task_id);
|
||||
|
||||
/* Notify the yield_task2 to run */
|
||||
task_sequence_ready = true;
|
||||
/* Give semaphore to unblock yield_task2, making it READY (not just setting a flag).
|
||||
* This ensures task2 is in the ready queue when we yield. */
|
||||
xSemaphoreGive(yield_sync_sem);
|
||||
|
||||
/* Yield */
|
||||
/* Yield - now task2 is guaranteed to be READY and should run next */
|
||||
taskYIELD();
|
||||
|
||||
/* Increment task count to notify unity task */
|
||||
@@ -73,10 +77,9 @@ static void yield_task2(void *arg)
|
||||
{
|
||||
uint32_t task_id = (uint32_t)arg;
|
||||
|
||||
/* Wait for the other task to run for the test to begin */
|
||||
while (!task_sequence_ready) {
|
||||
vTaskDelay(10);
|
||||
};
|
||||
/* Block on semaphore - this ensures task1 runs first and we don't poll.
|
||||
* When task1 gives the semaphore, we transition directly to READY state. */
|
||||
xSemaphoreTake(yield_sync_sem, portMAX_DELAY);
|
||||
|
||||
/* Store task_id in the sequence array */
|
||||
STORE_TASK_ID(task_id);
|
||||
@@ -108,9 +111,16 @@ TEST_CASE("Task yield must run the next ready task of the same priority", "[free
|
||||
/* Reset task sequence flag */
|
||||
task_sequence_ready = false;
|
||||
|
||||
/* Create test tasks */
|
||||
xTaskCreatePinnedToCore(yield_task1, "yield_task1", 2048, (void *)1, UNITY_FREERTOS_PRIORITY - 1, NULL, UNITY_FREERTOS_CPU);
|
||||
/* Create semaphore for synchronization - start empty so task2 blocks */
|
||||
yield_sync_sem = xSemaphoreCreateBinary();
|
||||
TEST_ASSERT_NOT_NULL(yield_sync_sem);
|
||||
|
||||
/* Create test tasks - order matters!
|
||||
* Task2 is created first and will immediately block on the semaphore.
|
||||
* Task1 is created second and will run first since task2 is blocked. */
|
||||
xTaskCreatePinnedToCore(yield_task2, "yield_task2", 2048, (void *)2, UNITY_FREERTOS_PRIORITY - 1, NULL, UNITY_FREERTOS_CPU);
|
||||
vTaskDelay(1); /* Ensure task2 has blocked on semaphore before creating task1 */
|
||||
xTaskCreatePinnedToCore(yield_task1, "yield_task1", 2048, (void *)1, UNITY_FREERTOS_PRIORITY - 1, NULL, UNITY_FREERTOS_CPU);
|
||||
|
||||
/* Wait for the tasks to finish up */
|
||||
while (count != 2) {
|
||||
@@ -122,6 +132,9 @@ TEST_CASE("Task yield must run the next ready task of the same priority", "[free
|
||||
/* Verify that the yield is successful and the next ready task is run */
|
||||
TEST_ASSERT_EQUAL(1, task_yield_sequence[idx++]);
|
||||
TEST_ASSERT_EQUAL(2, task_yield_sequence[idx++]);
|
||||
|
||||
/* Clean up semaphore */
|
||||
vSemaphoreDelete(yield_sync_sem);
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@@ -10,6 +10,7 @@
|
||||
#include "freertos/semphr.h"
|
||||
#include "esp_pm.h"
|
||||
#include "esp_private/esp_clk.h"
|
||||
#include "esp_clk_tree.h"
|
||||
|
||||
#include "sdkconfig.h"
|
||||
|
||||
@@ -66,9 +67,11 @@ static void consumer_task(void *arg)
|
||||
TEST_CASE("Test semaphore timeout during tickless idle", "[freertos]")
|
||||
{
|
||||
// Configure tickless idle
|
||||
uint32_t xtal_hz = 0;
|
||||
esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_XTAL, ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT, &xtal_hz);
|
||||
esp_pm_config_t pm_config = {
|
||||
.max_freq_mhz = esp_clk_cpu_freq() / MHZ,
|
||||
.min_freq_mhz = esp_clk_cpu_freq() / MHZ,
|
||||
.max_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ,
|
||||
.min_freq_mhz = xtal_hz / MHZ,
|
||||
.light_sleep_enable = true,
|
||||
};
|
||||
TEST_ESP_OK(esp_pm_configure(&pm_config));
|
||||
|
||||
@@ -74,7 +74,7 @@ void cam_hal_init(cam_hal_context_t *hal, const cam_hal_config_t *config)
|
||||
|
||||
cam_ll_enable_stop_signal(hal->hw, 0);
|
||||
cam_ll_swap_dma_data_byte_order(hal->hw, config->byte_swap_en);
|
||||
cam_ll_reverse_dma_data_bit_order(hal->hw, 0);
|
||||
cam_ll_reverse_dma_data_bit_order(hal->hw, config->bit_swap_en);
|
||||
cam_ll_enable_vsync_generate_eof(hal->hw, 1);
|
||||
|
||||
cam_hal_set_line_int_num(hal, 0);
|
||||
|
||||
@@ -26,6 +26,8 @@ extern "C" {
|
||||
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE (1 << 0)
|
||||
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE (1 << 1)
|
||||
|
||||
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Oneshot
|
||||
---------------------------------------------------------------*/
|
||||
|
||||
@@ -38,6 +38,8 @@ extern "C" {
|
||||
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_THRES0_HIGH_INT_ST_M : APB_SARADC_THRES1_HIGH_INT_ST_M)
|
||||
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_THRES1_LOW_INT_ST_M)
|
||||
|
||||
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Oneshot
|
||||
---------------------------------------------------------------*/
|
||||
|
||||
@@ -40,6 +40,8 @@ extern "C" {
|
||||
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
|
||||
|
||||
#define ADC_LL_ADC_FE_ON_MODEM_DOMAIN (1)
|
||||
|
||||
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
|
||||
/*---------------------------------------------------------------
|
||||
Oneshot
|
||||
---------------------------------------------------------------*/
|
||||
|
||||
@@ -39,6 +39,8 @@ extern "C" {
|
||||
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
|
||||
|
||||
#define ADC_LL_ADC_FE_ON_MODEM_DOMAIN (1)
|
||||
|
||||
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
|
||||
/*---------------------------------------------------------------
|
||||
Oneshot
|
||||
---------------------------------------------------------------*/
|
||||
|
||||
@@ -40,6 +40,8 @@ extern "C" {
|
||||
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? SARADC_THRES0_LOW_INT_ST_M : SARADC_THRES1_LOW_INT_ST_M)
|
||||
|
||||
#define ADC_LL_ADC_FE_ON_MODEM_DOMAIN (1)
|
||||
|
||||
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
|
||||
/*---------------------------------------------------------------
|
||||
Oneshot
|
||||
---------------------------------------------------------------*/
|
||||
|
||||
@@ -39,6 +39,8 @@ extern "C" {
|
||||
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
|
||||
|
||||
#define ADC_LL_ADC_FE_ON_MODEM_DOMAIN (1)
|
||||
|
||||
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
|
||||
/*---------------------------------------------------------------
|
||||
Oneshot
|
||||
---------------------------------------------------------------*/
|
||||
|
||||
@@ -34,6 +34,11 @@ extern "C" {
|
||||
#define LP_ADC_FORCE_XPD_SAR_PD 2 // Force power down
|
||||
#define LP_ADC_FORCE_XPD_SAR_PU 3 // Force power up
|
||||
|
||||
// ESP32P4 ADC2 channel is 2-7, so we need to subtract 2 to get the correct channel
|
||||
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 2
|
||||
|
||||
#define ADC_LL_NEED_APB_PERIPH_CLAIM(ADC_UNIT) (((ADC_UNIT) == ADC_UNIT_1) ? 0 : 1)
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Oneshot
|
||||
---------------------------------------------------------------*/
|
||||
@@ -352,13 +357,14 @@ static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t patt
|
||||
uint8_t offset = (pattern_index % 4) * 6;
|
||||
adc_ll_digi_pattern_table_t pattern = {0};
|
||||
|
||||
pattern.val = (table.atten & 0x3) | ((table.channel & 0xF) << 2);
|
||||
if (table.unit == ADC_UNIT_1){
|
||||
pattern.val = (table.atten & 0x3) | ((table.channel & 0xF) << 2);
|
||||
tab = ADC.sar1_patt_tab[index].sar1_patt_tab; //Read old register value
|
||||
tab &= (~(0xFC0000 >> offset)); //Clear old data
|
||||
tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; //Fill in the new data
|
||||
ADC.sar1_patt_tab[index].sar1_patt_tab = tab; //Write back
|
||||
} else {
|
||||
pattern.val = (table.atten & 0x3) | (((table.channel + 2) & 0xF) << 2);
|
||||
tab = ADC.sar2_patt_tab[index].sar2_patt_tab; //Read old register value
|
||||
tab &= (~(0xFC0000 >> offset)); //clear old data
|
||||
tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; //Fill in the new data
|
||||
|
||||
@@ -11,6 +11,8 @@
|
||||
#include "soc/ecdsa_reg.h"
|
||||
#include "soc/hp_sys_clkrst_struct.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "soc/efuse_reg.h"
|
||||
#include "soc/efuse_struct.h"
|
||||
#include "hal/ecdsa_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
@@ -440,6 +442,41 @@ static inline bool ecdsa_ll_is_deterministic_mode_supported(void)
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the ECDSA key block in eFuse
|
||||
*
|
||||
* @param curve ECDSA curve type
|
||||
* @param efuse_blk eFuse block number
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void ecdsa_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk)
|
||||
{
|
||||
#ifdef EFUSE_CFG_ECDSA_BLK
|
||||
(void) curve;
|
||||
EFUSE.conf.cfg_ecdsa_blk = efuse_blk;
|
||||
#else
|
||||
uint8_t efuse_blk_low = 0;
|
||||
uint8_t efuse_blk_high = 0;
|
||||
switch (curve) {
|
||||
case ECDSA_CURVE_SECP192R1:
|
||||
EFUSE.ecdsa.cfg_ecdsa_p192_blk = efuse_blk;
|
||||
break;
|
||||
case ECDSA_CURVE_SECP256R1:
|
||||
EFUSE.ecdsa.cfg_ecdsa_p256_blk = efuse_blk;
|
||||
break;
|
||||
case ECDSA_CURVE_SECP384R1:
|
||||
// ECDSA-p384 uses two efuse blocks to store the key. These two blocks are stored in a single integer
|
||||
// where the least significant 4 bits store the low key block number and the next 4 more significant bits store the high key block number.
|
||||
HAL_ECDSA_EXTRACT_KEY_BLOCKS(efuse_blk, efuse_blk_high, efuse_blk_low);
|
||||
EFUSE.ecdsa.cfg_ecdsa_p384_h_blk = efuse_blk_high;
|
||||
EFUSE.ecdsa.cfg_ecdsa_p384_l_blk = efuse_blk_low;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false && "Unsupported curve");
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the ECDSA peripheral uses MPI module's memory
|
||||
*/
|
||||
|
||||
@@ -12,6 +12,7 @@
|
||||
#include "hal/assert.h"
|
||||
#include "rom/efuse.h"
|
||||
#include "hal/ecdsa_types.h"
|
||||
#include "hal/ecdsa_ll.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@@ -94,8 +95,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(
|
||||
|
||||
__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk)
|
||||
{
|
||||
(void) curve;
|
||||
EFUSE.conf.cfg_ecdsa_blk = efuse_blk;
|
||||
ecdsa_ll_set_ecdsa_key_blk(curve, efuse_blk);
|
||||
}
|
||||
|
||||
/******************* eFuse control functions *************************/
|
||||
|
||||
@@ -42,7 +42,14 @@ extern "C" {
|
||||
#define I2S_LL_SLOT_FRAME_BIT_MAX 512 // Up-to 512 bits in one frame, determined by MAX(half_sample_bits) * 2
|
||||
|
||||
#define I2S_LL_XTAL_CLK_FREQ (40 * 1000000) // XTAL_CLK: 40MHz
|
||||
#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_XTAL_CLK_FREQ // No PLL clock source on P4, use XTAL as default
|
||||
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
|
||||
#define I2S_LL_DEFAULT_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz
|
||||
#define I2S_LL_DEFAULT_CLK_SRC I2S_CLK_SRC_PLL_160M
|
||||
#else
|
||||
#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_XTAL_CLK_FREQ // No PLL clock source before version 3, use XTAL as default
|
||||
#define I2S_LL_DEFAULT_CLK_SRC I2S_CLK_SRC_XTAL
|
||||
#endif
|
||||
|
||||
|
||||
#define I2S_LL_ETM_EVENT_TABLE(i2s_port, chan_dir, event) \
|
||||
(uint32_t[SOC_I2S_NUM][2][I2S_ETM_EVENT_MAX]){ \
|
||||
@@ -415,10 +422,14 @@ static inline uint32_t i2s_ll_get_clk_src(i2s_clock_src_t src)
|
||||
return 1;
|
||||
case I2S_CLK_SRC_EXTERNAL:
|
||||
return 2;
|
||||
case I2S_CLK_SRC_DEFAULT:
|
||||
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
|
||||
return 3;
|
||||
// Only support PLL_160M on P4 ver3 and later
|
||||
case I2S_CLK_SRC_PLL_160M:
|
||||
return 3;
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
default:
|
||||
HAL_ASSERT(false && "unsupported clock source");
|
||||
|
||||
@@ -13,6 +13,7 @@
|
||||
#include "hal/hal_utils.h"
|
||||
#include "hal/isp_types.h"
|
||||
#include "hal/color_types.h"
|
||||
#include "hal/config.h"
|
||||
#include "soc/isp_struct.h"
|
||||
#include "soc/hp_sys_clkrst_struct.h"
|
||||
#include "soc/clk_tree_defs.h"
|
||||
@@ -65,11 +66,14 @@ extern "C" {
|
||||
#define ISP_LL_EVENT_YUV2RGB_FRAME (1<<26)
|
||||
#define ISP_LL_EVENT_TAIL_IDI_FRAME (1<<27)
|
||||
#define ISP_LL_EVENT_HEADER_IDI_FRAME (1<<28)
|
||||
#define ISP_LL_EVENT_CROP_FRAME (1<<29)
|
||||
#define ISP_LL_EVENT_WBG_FRAME (1<<30)
|
||||
#define ISP_LL_EVENT_CROP_ERR (1<<31)
|
||||
|
||||
#define ISP_LL_EVENT_ALL_MASK (0x1FFFFFFF)
|
||||
#define ISP_LL_EVENT_AF_MASK (ISP_LL_EVENT_AF_FDONE | ISP_LL_EVENT_AF_ENV)
|
||||
#define ISP_LL_EVENT_AE_MASK (ISP_LL_EVENT_AE_FDONE | ISP_LL_EVENT_AE_ENV)
|
||||
#define ISP_LL_EVENT_AWB_MASK (ISP_LL_EVENT_AWB_FDONE)
|
||||
#define ISP_LL_EVENT_AWB_MASK (ISP_LL_EVENT_AWB_FDONE | ISP_LL_EVENT_WBG_FRAME)
|
||||
#define ISP_LL_EVENT_SHARP_MASK (ISP_LL_EVENT_SHARP_FRAME)
|
||||
#define ISP_LL_EVENT_HIST_MASK (ISP_LL_EVENT_HIST_FDONE)
|
||||
#define ISP_LL_EVENT_COLOR_MASK (ISP_LL_EVENT_COLOR_FRAME)
|
||||
@@ -165,8 +169,19 @@ typedef union {
|
||||
typedef enum {
|
||||
ISP_LL_LUT_LSC, ///< LUT for LSC
|
||||
ISP_LL_LUT_DPC, ///< LUT for DPC
|
||||
ISP_LL_LUT_AWB, ///< LUT for AWB
|
||||
} isp_ll_lut_t;
|
||||
|
||||
/**
|
||||
* @brief ISP LUT AWB type
|
||||
*/
|
||||
typedef enum {
|
||||
ISP_LL_LUT_AWB_WHITE_PATCH_CNT, ///< White patch count
|
||||
ISP_LL_LUT_AWB_ACCUMULATED_R, ///< Accumulated R
|
||||
ISP_LL_LUT_AWB_ACCUMULATED_G, ///< Accumulated G
|
||||
ISP_LL_LUT_AWB_ACCUMULATED_B, ///< Accumulated B
|
||||
} isp_ll_lut_awb_t;
|
||||
|
||||
/**
|
||||
* @brief ISP pipeline clock control mode
|
||||
*/
|
||||
@@ -1344,7 +1359,7 @@ static inline void isp_ll_lsc_set_xtablesize(isp_dev_t *hw, uint8_t xtablesize)
|
||||
LUT
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Select ISP LUT
|
||||
* @brief Select ISP LUT for LSC usage
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] is_write Is write or not
|
||||
@@ -1352,7 +1367,7 @@ static inline void isp_ll_lsc_set_xtablesize(isp_dev_t *hw, uint8_t xtablesize)
|
||||
* @param[in] addr LUT addr
|
||||
* @param[in] lut ISP LUT
|
||||
*/
|
||||
static inline void isp_ll_lut_set_cmd(isp_dev_t *hw, bool is_write, bool is_gb_b, uint32_t addr, isp_ll_lut_t lut)
|
||||
static inline void isp_ll_lut_lsc_set_cmd(isp_dev_t *hw, bool is_write, bool is_gb_b, uint32_t addr, isp_ll_lut_t lut)
|
||||
{
|
||||
uint32_t val = 0;
|
||||
val |= is_write ? (1 << 16) : 0;
|
||||
@@ -1369,7 +1384,7 @@ static inline void isp_ll_lut_set_cmd(isp_dev_t *hw, bool is_write, bool is_gb_b
|
||||
* @param[in] gb_gain gb gain
|
||||
* @param[in] b_gain b gain
|
||||
*/
|
||||
static inline void isp_ll_lut_set_wdata_gb_b(isp_dev_t *hw, isp_lsc_gain_t gb_gain, isp_lsc_gain_t b_gain)
|
||||
static inline void isp_ll_lut_lsc_set_wdata_gb_b(isp_dev_t *hw, isp_lsc_gain_t gb_gain, isp_lsc_gain_t b_gain)
|
||||
{
|
||||
hw->lut_wdata.lut_wdata = (gb_gain.val & 0x3ff) << 10 | (b_gain.val & 0x3ff);
|
||||
}
|
||||
@@ -1381,11 +1396,75 @@ static inline void isp_ll_lut_set_wdata_gb_b(isp_dev_t *hw, isp_lsc_gain_t gb_ga
|
||||
* @param[in] r_gain r gain
|
||||
* @param[in] gr_gain gr gain
|
||||
*/
|
||||
static inline void isp_ll_lut_set_wdata_r_gr(isp_dev_t *hw, isp_lsc_gain_t r_gain, isp_lsc_gain_t gr_gain)
|
||||
static inline void isp_ll_lut_lsc_set_wdata_r_gr(isp_dev_t *hw, isp_lsc_gain_t r_gain, isp_lsc_gain_t gr_gain)
|
||||
{
|
||||
hw->lut_wdata.lut_wdata = (r_gain.val & 0x3ff) << 10 | (gr_gain.val & 0x3ff);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set AWB LUT command
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] type ISP LUT AWB type
|
||||
* @param[in] addr AWB sub window ID
|
||||
*/
|
||||
static inline void isp_ll_lut_awb_set_cmd(isp_dev_t *hw, isp_ll_lut_awb_t type, uint32_t sub_window_id, isp_ll_lut_t lut)
|
||||
{
|
||||
HAL_ASSERT(sub_window_id <= 25);
|
||||
uint32_t val = 0;
|
||||
val |= 0x2000 + 4 * sub_window_id + type;
|
||||
val |= lut << 12;
|
||||
hw->lut_cmd.val = val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get AWB statistics of subwindow white patch count
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
*
|
||||
* @return White patch number
|
||||
*/
|
||||
static inline uint32_t isp_ll_lut_awb_get_subwindow_white_patch_cnt(isp_dev_t *hw)
|
||||
{
|
||||
return hw->lut_rdata.lut_rdata;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get AWB statistics of subwindow accumulated R
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
*
|
||||
* @return Accumulated R
|
||||
*/
|
||||
static inline uint32_t isp_ll_lut_awb_get_subwindow_accumulated_r(isp_dev_t *hw)
|
||||
{
|
||||
return hw->lut_rdata.lut_rdata;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get AWB statistics of subwindow accumulated G
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
*
|
||||
* @return Accumulated G
|
||||
*/
|
||||
static inline uint32_t isp_ll_lut_awb_get_subwindow_accumulated_g(isp_dev_t *hw)
|
||||
{
|
||||
return hw->lut_rdata.lut_rdata;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get AWB statistics of subwindow accumulated B
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
*
|
||||
* @return Accumulated B
|
||||
*/
|
||||
static inline uint32_t isp_ll_lut_awb_get_subwindow_accumulated_b(isp_dev_t *hw)
|
||||
{
|
||||
return hw->lut_rdata.lut_rdata;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
INTR
|
||||
---------------------------------------------------------------*/
|
||||
@@ -1614,6 +1693,58 @@ static inline uint32_t isp_ll_awb_get_accumulated_b_value(isp_dev_t *hw)
|
||||
return hw->awb0_acc_b.awb0_acc_b;
|
||||
}
|
||||
|
||||
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
|
||||
/**
|
||||
* @brief Enable AWB white balance gain
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] enable Enable / Disable
|
||||
*/
|
||||
static inline void isp_ll_awb_enable_wb_gain(isp_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->cntl.wbg_en = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set AWB white balance gain clock control mode
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] mode 'isp_ll_pipeline_clk_ctrl_t`
|
||||
*/
|
||||
static inline void isp_ll_awb_set_wb_gain_clk_ctrl_mode(isp_dev_t *hw, isp_ll_pipeline_clk_ctrl_t mode)
|
||||
{
|
||||
hw->clk_en.clk_wbg_force_on = mode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set AWB white balance gain
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] gain WBG white balance gain
|
||||
*/
|
||||
static inline void isp_ll_awb_set_wb_gain(isp_dev_t *hw, isp_wbg_gain_t gain)
|
||||
{
|
||||
hw->wbg_coef_r.wbg_r = gain.gain_r;
|
||||
hw->wbg_coef_g.wbg_g = gain.gain_g;
|
||||
hw->wbg_coef_b.wbg_b = gain.gain_b;
|
||||
}
|
||||
#else
|
||||
static inline void isp_ll_awb_enable_wb_gain(isp_dev_t *hw, bool enable)
|
||||
{
|
||||
//for compatibility
|
||||
}
|
||||
|
||||
static inline void isp_ll_awb_set_wb_gain_clk_ctrl_mode(isp_dev_t *hw, isp_ll_pipeline_clk_ctrl_t mode)
|
||||
{
|
||||
//for compatibility
|
||||
}
|
||||
|
||||
static inline void isp_ll_awb_set_wb_gain(isp_dev_t *hw, isp_wbg_gain_t gain)
|
||||
{
|
||||
//for compatibility
|
||||
}
|
||||
#endif //#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Demosaic
|
||||
---------------------------------------------------------------*/
|
||||
|
||||
@@ -25,6 +25,8 @@
|
||||
#include "soc/soc_caps.h"
|
||||
#include "soc/interrupts.h"
|
||||
#include "soc/soc_etm_source.h"
|
||||
#include "soc/efuse_reg.h"
|
||||
#include "soc/efuse_struct.h"
|
||||
#include "hal/temperature_sensor_types.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/misc.h"
|
||||
@@ -258,6 +260,23 @@ static inline void temperature_sensor_ll_set_sample_rate(uint16_t rate)
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_TSENS.sample_rate, sample_rate, rate);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Retrieve and calculate the temperature sensor calibration value.
|
||||
*
|
||||
* @return Temperature calibration value.
|
||||
*/
|
||||
static inline int temperature_sensor_ll_load_calib_param(void)
|
||||
{
|
||||
#ifdef EFUSE_TEMPERATURE_SENSOR
|
||||
uint32_t cal_temp = EFUSE.rd_sys_part2_data3.temperature_sensor;
|
||||
// BIT(8) stands for sign: 1: negative, 0: positive
|
||||
int tsens_cal = ((cal_temp & BIT(8)) != 0)? -(uint8_t)cal_temp: (uint8_t)cal_temp;
|
||||
return tsens_cal;
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -36,6 +36,8 @@ extern "C" {
|
||||
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_ADC1_THRES_INT_ST_M : APB_SARADC_ADC2_THRES_INT_ST_M)
|
||||
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_ADC1_THRES_INT_ST_M : APB_SARADC_ADC2_THRES_INT_ST_M)
|
||||
|
||||
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Oneshot
|
||||
---------------------------------------------------------------*/
|
||||
|
||||
@@ -38,6 +38,8 @@ extern "C" {
|
||||
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_THRES0_HIGH_INT_ST_M : APB_SARADC_THRES1_HIGH_INT_ST_M)
|
||||
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_THRES1_LOW_INT_ST_M)
|
||||
|
||||
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Oneshot
|
||||
---------------------------------------------------------------*/
|
||||
|
||||
@@ -28,6 +28,8 @@ typedef struct cam_hal_context {
|
||||
*/
|
||||
typedef struct cam_hal_config {
|
||||
int port; /*!< CAM port */
|
||||
uint32_t cam_data_width; /*!< CAM data width, 8 or 16 or 24 bit, default to 8 */
|
||||
bool bit_swap_en; /*!< CAM enable bit swap */
|
||||
bool byte_swap_en; /*!< CAM enable byte swap */
|
||||
} cam_hal_config_t;
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -125,6 +125,14 @@ typedef enum {
|
||||
AWB
|
||||
---------------------------------------------------------------*/
|
||||
|
||||
#if SOC_ISP_AWB_WINDOW_X_NUMS
|
||||
#define ISP_AWB_WINDOW_X_NUM SOC_ISP_AWB_WINDOW_X_NUMS // The AWB window number for sampling
|
||||
#define ISP_AWB_WINDOW_Y_NUM SOC_ISP_AWB_WINDOW_Y_NUMS // The AWB window number for sampling
|
||||
#else
|
||||
#define ISP_AWB_WINDOW_X_NUM 0
|
||||
#define ISP_AWB_WINDOW_Y_NUM 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ISP AWB sample point in the ISP pipeline
|
||||
*/
|
||||
@@ -133,12 +141,21 @@ typedef enum {
|
||||
ISP_AWB_SAMPLE_POINT_AFTER_CCM, ///< Sample AWB data after CCM (Color Correction Matrix)
|
||||
} isp_awb_sample_point_t;
|
||||
|
||||
/**
|
||||
* @brief ISP AWB gain
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t gain_r; ///< White balance gain for R channel
|
||||
uint32_t gain_g; ///< White balance gain for G channel
|
||||
uint32_t gain_b; ///< White balance gain for B channel
|
||||
} isp_awb_gain_t;
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
BF
|
||||
---------------------------------------------------------------*/
|
||||
#if SOC_ISP_BF_SUPPORTED
|
||||
#define ISP_BF_TEMPLATE_X_NUMS SOC_ISP_BF_TEMPLATE_X_NUMS // BF template x field nums
|
||||
#define ISP_BF_TEMPLATE_Y_NUMS SOC_ISP_BF_TEMPLATE_Y_NUMS // BF template y field nums
|
||||
#define ISP_BF_TEMPLATE_X_NUMS SOC_ISP_BF_TEMPLATE_X_NUMS ///< BF template x field nums
|
||||
#define ISP_BF_TEMPLATE_Y_NUMS SOC_ISP_BF_TEMPLATE_Y_NUMS ///< BF template y field nums
|
||||
#else
|
||||
#define ISP_BF_TEMPLATE_X_NUMS 0
|
||||
#define ISP_BF_TEMPLATE_Y_NUMS 0
|
||||
@@ -418,6 +435,18 @@ typedef union {
|
||||
uint32_t val; ///< 32-bit gradient ratio value
|
||||
} isp_lsc_gain_t;
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
WBG (White Balance Gain)
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief ISP White Balance Gain
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t gain_r; ///< White balance gain for R channel
|
||||
uint32_t gain_g; ///< White balance gain for G channel
|
||||
uint32_t gain_b; ///< White balance gain for B channel
|
||||
} isp_wbg_gain_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -22,11 +22,11 @@
|
||||
#define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB 4500
|
||||
|
||||
#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 19000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 450000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 750000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_3072KEY_PUBLIC_OP 33000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_3072KEY_PRIVATE_OP 950000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP 90000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 1900000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 3000000
|
||||
|
||||
// floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround)
|
||||
#define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70
|
||||
|
||||
@@ -17,11 +17,11 @@
|
||||
#define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB 900
|
||||
|
||||
#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 13500
|
||||
#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 420000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 650000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_3072KEY_PUBLIC_OP 36000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_3072KEY_PRIVATE_OP 960000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP 62000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 1850000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 2850000
|
||||
|
||||
#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_NO_FILTER 3
|
||||
#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_2 3
|
||||
|
||||
@@ -15,11 +15,11 @@
|
||||
#define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB 900
|
||||
|
||||
#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 18000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 490000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 700000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_3072KEY_PUBLIC_OP 45000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_3072KEY_PRIVATE_OP 1300000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP 80000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 2500000
|
||||
#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 3500000
|
||||
|
||||
// floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround)
|
||||
#define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70
|
||||
|
||||
@@ -210,8 +210,8 @@ void ieee802154_record_print(void)
|
||||
#if CONFIG_IEEE802154_RECORD_STATE
|
||||
ESP_EARLY_LOGW(IEEE802154_TAG, "Print the record state, current state index: %d", g_ieee802154_probe.state_index);
|
||||
for (uint8_t i = 0; i < IEEE802154_ASSERT_RECORD_STATE_SIZE; i++) {
|
||||
ESP_EARLY_LOGW(IEEE802154_TAG, "index %2d: line:%5s, state:%10s, timestamp: %lld",
|
||||
i, g_ieee802154_probe.state[i].line_str,
|
||||
ESP_EARLY_LOGW(IEEE802154_TAG, "index %2d: line:%5lu, state:%10s, timestamp: %lld",
|
||||
i, g_ieee802154_probe.state[i].line,
|
||||
ieee802154_state_string[g_ieee802154_probe.state[i].state],
|
||||
g_ieee802154_probe.state[i].timestamp);
|
||||
}
|
||||
@@ -221,8 +221,8 @@ void ieee802154_record_print(void)
|
||||
#if CONFIG_IEEE802154_RECORD_CMD
|
||||
ESP_EARLY_LOGW(IEEE802154_TAG, "Print the record cmd, current cmd index: %d", g_ieee802154_probe.cmd_index);
|
||||
for (uint8_t i = 0; i < IEEE802154_ASSERT_RECORD_CMD_SIZE; i++) {
|
||||
ESP_EARLY_LOGW(IEEE802154_TAG, "index %2d: line:%5s, cmd:%10s, timestamp: %lld",
|
||||
i, g_ieee802154_probe.cmd[i].line_str,
|
||||
ESP_EARLY_LOGW(IEEE802154_TAG, "index %2d: line:%5lu, cmd:%10s, timestamp: %lld",
|
||||
i, g_ieee802154_probe.cmd[i].line,
|
||||
ieee802154_get_cmd_string(g_ieee802154_probe.cmd[i].cmd),
|
||||
g_ieee802154_probe.cmd[i].timestamp);
|
||||
}
|
||||
|
||||
@@ -78,7 +78,7 @@ typedef struct {
|
||||
#if CONFIG_IEEE802154_RECORD_STATE
|
||||
#define IEEE802154_ASSERT_RECORD_STATE_SIZE CONFIG_IEEE802154_RECORD_STATE_SIZE
|
||||
#define ieee802154_set_state(a) do { s_ieee802154_state = a; \
|
||||
sprintf(g_ieee802154_probe.state[g_ieee802154_probe.state_index].line_str, "%d", __LINE__); \
|
||||
g_ieee802154_probe.state[g_ieee802154_probe.state_index].line = __LINE__; \
|
||||
g_ieee802154_probe.state[g_ieee802154_probe.state_index].timestamp = esp_timer_get_time(); \
|
||||
g_ieee802154_probe.state[g_ieee802154_probe.state_index++].state = a; \
|
||||
g_ieee802154_probe.state_index = \
|
||||
@@ -89,7 +89,7 @@ typedef struct {
|
||||
* @brief The table of recording IEEE802154 state command.
|
||||
*/
|
||||
typedef struct {
|
||||
char line_str[5]; /*!< record which line in esp_ieee802154_dev.c changes the state */
|
||||
uint32_t line; /*!< record which line in esp_ieee802154_dev.c changes the state */
|
||||
ieee802154_state_t state; /*!< record current radio state */
|
||||
uint64_t timestamp; /*!< record timestamp */
|
||||
} ieee802154_state_info_t;
|
||||
@@ -100,7 +100,7 @@ typedef struct {
|
||||
#if CONFIG_IEEE802154_RECORD_CMD
|
||||
#define IEEE802154_ASSERT_RECORD_CMD_SIZE CONFIG_IEEE802154_RECORD_CMD_SIZE
|
||||
#define ieee802154_set_cmd(a) do { ieee802154_ll_set_cmd(a); \
|
||||
sprintf(g_ieee802154_probe.cmd[g_ieee802154_probe.cmd_index].line_str, "%d", __LINE__); \
|
||||
g_ieee802154_probe.cmd[g_ieee802154_probe.cmd_index].line = __LINE__; \
|
||||
g_ieee802154_probe.cmd[g_ieee802154_probe.cmd_index].timestamp = esp_timer_get_time(); \
|
||||
g_ieee802154_probe.cmd[g_ieee802154_probe.cmd_index++].cmd = a; \
|
||||
g_ieee802154_probe.cmd_index = \
|
||||
@@ -111,7 +111,7 @@ typedef struct {
|
||||
* @brief The table of recording IEEE802154 radio command.
|
||||
*/
|
||||
typedef struct {
|
||||
char line_str[5]; /*!< record which line in esp_ieee802154_dev.c set the command */
|
||||
uint32_t line; /*!< record which line in esp_ieee802154_dev.c set the command */
|
||||
ieee802154_ll_cmd_t cmd; /*!< record current command */
|
||||
uint64_t timestamp; /*!< record timestamp */
|
||||
} ieee802154_cmd_info_t;
|
||||
|
||||
@@ -233,9 +233,6 @@ endif()
|
||||
if((SHA_PERIPHERAL_TYPE STREQUAL "core" AND CONFIG_SOC_SHA_SUPPORT_DMA) OR AES_PERIPHERAL_TYPE STREQUAL "dma")
|
||||
target_link_libraries(mbedcrypto PRIVATE idf::esp_mm)
|
||||
if(CONFIG_SOC_SHA_GDMA OR CONFIG_SOC_AES_GDMA)
|
||||
if(CONFIG_SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT)
|
||||
target_link_libraries(mbedcrypto PRIVATE idf::bootloader_support)
|
||||
endif()
|
||||
target_sources(mbedcrypto PRIVATE "${COMPONENT_DIR}/port/crypto_shared_gdma/esp_crypto_shared_gdma.c")
|
||||
endif()
|
||||
endif()
|
||||
|
||||
Submodule components/mbedtls/mbedtls updated: b5d87eaa67...ffb280bb63
@@ -41,9 +41,9 @@
|
||||
#include "aes/esp_aes_gcm.h"
|
||||
#endif
|
||||
|
||||
#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
|
||||
#include "esp_flash_encrypt.h"
|
||||
#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
|
||||
#ifdef SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
|
||||
#include "hal/efuse_hal.h"
|
||||
#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
|
||||
|
||||
/* Max size of each chunk to process when output buffer is in unaligned external ram
|
||||
must be a multiple of block size
|
||||
@@ -241,17 +241,17 @@ static int esp_aes_process_dma_ext_ram(esp_aes_context *ctx, const unsigned char
|
||||
|
||||
/* When AES-DMA operations are carried out using external memory with external memory encryption enabled,
|
||||
we need to make sure that the addresses and the sizes of the buffers on which the DMA operates are 16 byte-aligned. */
|
||||
#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
|
||||
if (esp_flash_encryption_enabled()) {
|
||||
#ifdef SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
|
||||
if (efuse_hal_flash_encryption_enabled()) {
|
||||
if (esp_ptr_external_ram(input) || esp_ptr_external_ram(output) || esp_ptr_in_drom(input) || esp_ptr_in_drom(output)) {
|
||||
input_alignment = MAX(get_cache_line_size(input), SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT);
|
||||
output_alignment = MAX(get_cache_line_size(output), SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT);
|
||||
input_alignment = MAX(get_cache_line_size(input), SOC_GDMA_EXT_MEM_ENC_ALIGNMENT);
|
||||
output_alignment = MAX(get_cache_line_size(output), SOC_GDMA_EXT_MEM_ENC_ALIGNMENT);
|
||||
|
||||
input_heap_caps = MALLOC_CAP_8BIT | (esp_ptr_external_ram(input) ? MALLOC_CAP_SPIRAM : MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
|
||||
output_heap_caps = MALLOC_CAP_8BIT | (esp_ptr_external_ram(output) ? MALLOC_CAP_SPIRAM : MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
|
||||
}
|
||||
}
|
||||
#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
|
||||
#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
|
||||
|
||||
if (realloc_input) {
|
||||
input_buf = heap_caps_aligned_alloc(input_alignment, chunk_len, input_heap_caps);
|
||||
@@ -537,19 +537,19 @@ int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsign
|
||||
return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH;
|
||||
}
|
||||
|
||||
#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
|
||||
if (esp_flash_encryption_enabled()) {
|
||||
#ifdef SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
|
||||
if (efuse_hal_flash_encryption_enabled()) {
|
||||
if (esp_ptr_external_ram(input) || esp_ptr_external_ram(output) || esp_ptr_in_drom(input) || esp_ptr_in_drom(output)) {
|
||||
if (((intptr_t)(input) & (SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
|
||||
if (((intptr_t)(input) & (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
|
||||
input_needs_realloc = true;
|
||||
}
|
||||
|
||||
if (((intptr_t)(output) & (SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
|
||||
if (((intptr_t)(output) & (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
|
||||
output_needs_realloc = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
|
||||
#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
|
||||
|
||||
/* DMA cannot access memory in the iCache range, copy input to internal ram */
|
||||
if (!s_check_dma_capable(input)) {
|
||||
@@ -1002,6 +1002,20 @@ int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsign
|
||||
if (block_bytes > 0) {
|
||||
/* Flush cache if input in external ram */
|
||||
#if (CONFIG_SPIRAM && SOC_PSRAM_DMA_CAPABLE)
|
||||
#ifdef SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
|
||||
if (efuse_hal_flash_encryption_enabled()) {
|
||||
if (esp_ptr_external_ram(input) || esp_ptr_external_ram(output) || esp_ptr_in_drom(input) || esp_ptr_in_drom(output)) {
|
||||
if (((intptr_t)(input) & (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
|
||||
input_needs_realloc = true;
|
||||
}
|
||||
|
||||
if (((intptr_t)(output) & (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
|
||||
output_needs_realloc = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
|
||||
|
||||
if (esp_ptr_external_ram(input)) {
|
||||
if (esp_cache_msync((void *)input, len, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED) != ESP_OK) {
|
||||
mbedtls_platform_zeroize(output, len);
|
||||
@@ -1049,12 +1063,18 @@ int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsign
|
||||
block_in_desc = block_desc;
|
||||
block_out_desc = block_desc + crypto_dma_desc_num;
|
||||
|
||||
#if SOC_AHB_GDMA_VERSION == 2
|
||||
// Limit max inlink descriptor length to be 16 byte aligned, as buffer sizes need to be 16 byte aligned
|
||||
// when Flash Encryption is enabled.
|
||||
dma_desc_setup_link(block_in_desc, input, block_bytes, DMA_DESCRIPTOR_BUFFER_MAX_SIZE_16B_ALIGNED, 0);
|
||||
#else
|
||||
// the size field has 12 bits, but 0 not for 4096.
|
||||
// to avoid possible problem when the size is not word-aligned, we only use 4096-4 per desc.
|
||||
// Maximum size of data in the buffer that a DMA descriptor can hold.
|
||||
dma_desc_setup_link(block_in_desc, input, block_bytes, DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED, 0);
|
||||
#endif
|
||||
|
||||
//Limit max inlink descriptor length to be 16 byte aligned, require for EDMA
|
||||
//Limit max outlink descriptor length to be 16 byte aligned, require for EDMA
|
||||
dma_desc_setup_link(block_out_desc, output, block_bytes, DMA_DESCRIPTOR_BUFFER_MAX_SIZE_16B_ALIGNED, 0);
|
||||
|
||||
/* Setup in/out start descriptors */
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -17,14 +17,16 @@
|
||||
#include "soc/soc_caps.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
|
||||
#include "esp_flash_encrypt.h"
|
||||
#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
|
||||
#ifdef SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
|
||||
#include "hal/efuse_hal.h"
|
||||
#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
|
||||
|
||||
#if SOC_AHB_GDMA_VERSION == 1
|
||||
#include "hal/gdma_ll.h"
|
||||
#elif SOC_AXI_GDMA_SUPPORTED
|
||||
#if SOC_AXI_GDMA_SUPPORTED
|
||||
#include "hal/axi_dma_ll.h"
|
||||
#elif SOC_AHB_GDMA_VERSION == 1
|
||||
#include "hal/gdma_ll.h"
|
||||
#elif SOC_AHB_GDMA_VERSION == 2
|
||||
#include "hal/ahb_dma_ll.h"
|
||||
#endif /* SOC_AHB_GDMA_VERSION */
|
||||
|
||||
#define NEW_CHANNEL_TIMEOUT_MS 1000
|
||||
@@ -89,7 +91,16 @@ static esp_err_t crypto_shared_gdma_init(void)
|
||||
.access_ext_mem = true, // crypto peripheral may want to access PSRAM
|
||||
};
|
||||
gdma_config_transfer(tx_channel, &transfer_cfg);
|
||||
|
||||
/* When using AHB-GDMA version 1, the max data burst size must be 0, otherwise buffers need to be aligned as well.
|
||||
* Whereas, in case of the other GDMA versions, the RX max burst size is default enabled, but with default burst size of 4,
|
||||
* but it case of Flash Encryption, the buffers can be allocated from the external memory, which requires 16 byte alignment.
|
||||
* Thus, we set the max data burst size to 16, similar to the TX channel.
|
||||
*/
|
||||
#if SOC_AHB_GDMA_VERSION == 1 || SOC_AXI_GDMA_SUPPORTED // IDF-14335: SOC_AXI_GDMA_SUPPORTED might not be needed here
|
||||
transfer_cfg.max_data_burst_size = 0;
|
||||
#endif
|
||||
|
||||
gdma_config_transfer(rx_channel, &transfer_cfg);
|
||||
|
||||
#ifdef SOC_AES_SUPPORTED
|
||||
@@ -156,7 +167,7 @@ esp_err_t esp_crypto_shared_gdma_start(const lldesc_t *input, const lldesc_t *ou
|
||||
|
||||
/* The external memory ecc-aes access must be enabled when there exists
|
||||
at least one buffer in the DMA descriptors that resides in external memory. */
|
||||
#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
|
||||
#if (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT && SOC_AXI_GDMA_SUPPORTED)
|
||||
static bool check_dma_descs_need_ext_mem_ecc_aes_access(const crypto_dma_desc_t *dmadesc)
|
||||
{
|
||||
crypto_dma_desc_t* desc = (crypto_dma_desc_t*) dmadesc;
|
||||
@@ -168,7 +179,7 @@ static bool check_dma_descs_need_ext_mem_ecc_aes_access(const crypto_dma_desc_t
|
||||
}
|
||||
return false;
|
||||
}
|
||||
#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
|
||||
#endif /* (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT && SOC_AXI_GDMA_SUPPORTED) */
|
||||
|
||||
esp_err_t esp_crypto_shared_gdma_start_axi_ahb(const crypto_dma_desc_t *input, const crypto_dma_desc_t *output, gdma_trigger_peripheral_t peripheral)
|
||||
{
|
||||
@@ -203,16 +214,19 @@ esp_err_t esp_crypto_shared_gdma_start_axi_ahb(const crypto_dma_desc_t *input, c
|
||||
/* tx channel is reset by gdma_connect(), also reset rx to ensure a known state */
|
||||
gdma_get_channel_id(rx_channel, &rx_ch_id);
|
||||
|
||||
#if SOC_AHB_GDMA_VERSION == 1
|
||||
gdma_ll_rx_reset_channel(&GDMA, rx_ch_id);
|
||||
#elif SOC_AXI_GDMA_SUPPORTED
|
||||
// IDF-14335: Use gdma_reset() instead
|
||||
#if SOC_AXI_GDMA_SUPPORTED
|
||||
axi_dma_ll_rx_reset_channel(&AXI_DMA, rx_ch_id);
|
||||
#endif /* SOC_AHB_GDMA_VERSION */
|
||||
#elif SOC_AHB_GDMA_VERSION == 1
|
||||
gdma_ll_rx_reset_channel(&GDMA, rx_ch_id);
|
||||
#elif SOC_AHB_GDMA_VERSION == 2
|
||||
ahb_dma_ll_rx_reset_channel(&AHB_DMA, rx_ch_id);
|
||||
#endif /* SOC_AXI_GDMA_SUPPORTED */
|
||||
|
||||
/* When GDMA operations are carried out using external memory with external memory encryption enabled,
|
||||
we need to enable AXI-DMA's AES-ECC mean access bit. */
|
||||
#if (SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT)
|
||||
if (esp_flash_encryption_enabled()) {
|
||||
#if (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT && SOC_AXI_GDMA_SUPPORTED)
|
||||
if (efuse_hal_flash_encryption_enabled()) {
|
||||
int tx_ch_id = 0;
|
||||
gdma_get_channel_id(tx_channel, &tx_ch_id);
|
||||
|
||||
@@ -224,7 +238,7 @@ esp_err_t esp_crypto_shared_gdma_start_axi_ahb(const crypto_dma_desc_t *input, c
|
||||
axi_dma_ll_tx_enable_ext_mem_ecc_aes_access(&AXI_DMA, tx_ch_id, false);
|
||||
}
|
||||
}
|
||||
#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
|
||||
#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
|
||||
|
||||
gdma_start(tx_channel, (intptr_t)input);
|
||||
gdma_start(rx_channel, (intptr_t)output);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user