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Chip/support esp32c61 v5.5

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This commit is contained in:
Jiang Jiang Jian
2025-07-22 12:21:36 +08:00
parent 7bed0d3937
commit 3c39b32195
375 changed files with 44801 additions and 39121 deletions
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components/bootloader_support/src/bootloader_init.c
+8 -2
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -19,6 +19,7 @@
#include "hal/wdt_hal.h"
#include "hal/efuse_hal.h"
#include "esp_bootloader_desc.h"
#include "esp_rom_sys.h"
static const char *TAG = "boot";
@@ -34,7 +35,12 @@ void bootloader_clear_bss_section(void)
esp_err_t bootloader_read_bootloader_header(void)
{
/* load bootloader image header */
if (bootloader_flash_read(ESP_BOOTLOADER_OFFSET, &bootloader_image_hdr, sizeof(esp_image_header_t), true) != ESP_OK) {
#if SOC_RECOVERY_BOOTLOADER_SUPPORTED
const uint32_t bootloader_flash_offset = esp_rom_get_bootloader_offset();
#else
const uint32_t bootloader_flash_offset = ESP_PRIMARY_BOOTLOADER_OFFSET;
#endif
if (bootloader_flash_read(bootloader_flash_offset, &bootloader_image_hdr, sizeof(esp_image_header_t), true) != ESP_OK) {
ESP_EARLY_LOGE(TAG, "failed to load bootloader image header!");
return ESP_FAIL;
}
components/bootloader_support/src/bootloader_mem.c
+7 -8
View File
@@ -25,20 +25,19 @@ void bootloader_init_mem(void)
* So, at boot disabling these filters. They will enable as per the
* use case by TEE initialization code.
*/
#ifdef SOC_APM_CTRL_FILTER_SUPPORTED
apm_hal_apm_ctrl_filter_enable_all(false);
/* [APM] On power-up, only the HP CPU starts in TEE mode; others default to REE2.
* APM blocks REE0–REE2 access by default. C5 ECO2 adds per-peripheral control
* (default REEx blocking), but config support is pending. As a workaround,
* all masters are set to TEE mode.
#if SOC_APM_CTRL_FILTER_SUPPORTED
apm_hal_enable_ctrl_filter_all(false);
/* [APM] On power-up, only the HP CPU starts in TEE mode; others
* default to REE2. APM blocks REE0–REE2 access by default.
* Thus, all masters are set to TEE mode.
*/
#if SOC_APM_SUPPORT_TEE_PERI_ACCESS_CTRL
apm_tee_hal_set_master_secure_mode_all(APM_LL_SECURE_MODE_TEE);
apm_hal_set_master_sec_mode_all(APM_SEC_MODE_TEE);
#endif // SOC_APM_SUPPORT_TEE_PERI_ACCESS_CTRL
#endif // SOC_APM_CTRL_FILTER_SUPPORTED
#endif
#ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
#if CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
// protect memory region
esp_cpu_configure_region_protection();
#endif
components/bootloader_support/src/esp32c5/flash_encryption_secure_features.c
+4 -7
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -71,12 +71,9 @@ esp_err_t esp_flash_encryption_enable_secure_features(void)
esp_err_t esp_flash_encryption_enable_key_mgr(void)
{
// Enable and reset key manager
// To suppress build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV
int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused));
key_mgr_ll_enable_bus_clock(true);
key_mgr_ll_enable_peripheral_clock(true);
key_mgr_ll_reset_register();
_key_mgr_ll_enable_bus_clock(true);
_key_mgr_ll_enable_peripheral_clock(true);
_key_mgr_ll_reset_register();
while (key_mgr_ll_get_state() != ESP_KEY_MGR_STATE_IDLE) {
};
components/bootloader_support/src/esp32p4/flash_encryption_secure_features.c
+4 -7
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -53,12 +53,9 @@ esp_err_t esp_flash_encryption_enable_secure_features(void)
esp_err_t esp_flash_encryption_enable_key_mgr(void)
{
// Enable and reset key manager
// To suppress build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV
int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused));
key_mgr_ll_enable_bus_clock(true);
key_mgr_ll_enable_peripheral_clock(true);
key_mgr_ll_reset_register();
_key_mgr_ll_enable_bus_clock(true);
_key_mgr_ll_enable_peripheral_clock(true);
_key_mgr_ll_reset_register();
while (key_mgr_ll_get_state() != ESP_KEY_MGR_STATE_IDLE) {
};
components/bootloader_support/src/esp_image_format.c
+17 -1
View File
@@ -23,6 +23,7 @@
#include "soc/soc_caps.h"
#include "hal/cache_ll.h"
#include "spi_flash_mmap.h"
#include "hal/efuse_hal.h"
#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
@@ -119,11 +120,26 @@ void esp_image_bootloader_offset_set(const uint32_t offset)
{
s_bootloader_partition_offset = offset;
ESP_LOGI(TAG, "Bootloader offsets for PRIMARY: 0x%x, Secondary: 0x%" PRIx32, ESP_PRIMARY_BOOTLOADER_OFFSET, s_bootloader_partition_offset);
#if SOC_RECOVERY_BOOTLOADER_SUPPORTED
uint32_t recovery_offset = efuse_hal_get_recovery_bootloader_address();
if (efuse_hal_recovery_bootloader_enabled()) {
ESP_LOGI(TAG, "Bootloader offset for RECOVERY: 0x%" PRIx32, recovery_offset);
} else if (recovery_offset == 0) {
ESP_LOGI(TAG, "Bootloader offset for RECOVERY: has not been set yet");
} else {
ESP_LOGI(TAG, "Bootloader offset for RECOVERY: is disabled");
}
#endif
}
static bool is_bootloader(uint32_t offset)
{
return ((offset == ESP_PRIMARY_BOOTLOADER_OFFSET) || (offset == s_bootloader_partition_offset));
return ((offset == ESP_PRIMARY_BOOTLOADER_OFFSET)
|| (offset == s_bootloader_partition_offset)
#if SOC_RECOVERY_BOOTLOADER_SUPPORTED
|| (efuse_hal_recovery_bootloader_enabled() ? offset == efuse_hal_get_recovery_bootloader_address() : false)
#endif
);
}
static esp_err_t image_load(esp_image_load_mode_t mode, const esp_partition_pos_t *part, esp_image_metadata_t *data)