pioduino/esp-idf
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'fix/aes-dma-psram-output-cache-coherency_v5.5' into 'release/v5.5'

Browse Source 
Ensure cache coherency when DMA writes to cacheable PSRAM buffers (AES) (v5.5)

See merge request espressif/esp-idf!44920
This commit is contained in:
Jiang Jiang Jian
2026-01-17 13:59:38 +08:00
parent c4dffdc79d 0742f3fce3
commit 3f10cdabc1
1 changed files with 15 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/mbedtls/port/aes/dma/esp_aes_dma_core.c
+15 -12
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -1040,6 +1040,7 @@ int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsign
return -1;
}
}
if (esp_ptr_external_ram(output)) {
size_t dcache_line_size;
ret = esp_cache_get_alignment(MALLOC_CAP_SPIRAM, &dcache_line_size);
@@ -1066,6 +1067,19 @@ int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsign
return esp_aes_process_dma_ext_ram(ctx, input, output, len, stream_out, input_needs_realloc, output_needs_realloc);
}
#if (CONFIG_SPIRAM && SOC_PSRAM_DMA_CAPABLE)
// When a DMA engine (AES-DMA operations) writes into a PSRAM destination buffer that previously contained dirty D-cache lines,
// later cache eviction can write back stale data and corrupt the DMA result.
// Fix this by cleaning the destination buffers before starting DMA transfers.
if (esp_ptr_external_ram(output)) {
if (esp_cache_msync((void *)output, block_bytes, ESP_CACHE_MSYNC_FLAG_DIR_M2C) != ESP_OK) {
mbedtls_platform_zeroize(output, len);
ESP_LOGE(TAG, "Cache sync failed for the output in external RAM");
return -1;
}
}
#endif
/* Set up dma descriptors for input and output considering the 16 byte alignment requirement for EDMA */
crypto_dma_desc_num = dma_desc_get_required_num(block_bytes, DMA_DESCRIPTOR_BUFFER_MAX_SIZE_16B_ALIGNED);
@@ -1155,17 +1169,6 @@ int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsign
goto cleanup;
}
#if (CONFIG_SPIRAM && SOC_PSRAM_DMA_CAPABLE)
if (block_bytes > 0) {
if (esp_ptr_external_ram(output)) {
if(esp_cache_msync((void*)output, block_bytes, ESP_CACHE_MSYNC_FLAG_DIR_M2C) != ESP_OK) {
mbedtls_platform_zeroize(output, len);
ESP_LOGE(TAG, "Cache sync failed for the output in external RAM");
return -1;
}
}
}
#endif
aes_hal_transform_dma_finish();
if (stream_bytes > 0) {