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feat(c6): fix pvt efuse print bug on c6 and adjust pvt prepare cost in sleep wakeup on c6/c5/c61

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This commit is contained in:
zlq
2026-01-19 20:05:17 +08:00
committed by chaijie@espressif.com
parent 1c37e7207f
commit cc91b64b05
2 changed files with 18 additions and 11 deletions
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components/esp_hw_support/port/esp32c6/pmu_pvt.c
+1 -9
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -106,8 +106,6 @@ void pvt_auto_dbias_init(void)
/*config lp offset for pvt func*/
uint8_t lp_hp_gap = get_lp_hp_gap();
set_pvt_hp_lp_gap(lp_hp_gap);
} else {
ESP_HW_LOGD(TAG, "blk_version is less than 3, pvt auto dbias init not supported in efuse.");
}
}
@@ -135,8 +133,6 @@ void IRAM_ATTR pvt_func_enable(bool enable)
CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
}
} else {
ESP_HW_LOGD(TAG, "blk_version is less than 3, pvt enable not supported in efuse.");
}
}
@@ -148,8 +144,6 @@ void charge_pump_init(void)
SET_PERI_REG_BITS(PVT_PMUP_CHANNEL_CFG_REG, PVT_PUMP_CHANNEL_CODE0, PVT_PUMP_CHANNEL_CODE, PVT_PUMP_CHANNEL_CODE0_S); //Set channel code
WRITE_PERI_REG(PVT_PMUP_BITMAP_LOW0_REG, (1 << PVT_PUMP_BITMAP)); // Select monitor cell for charge pump
SET_PERI_REG_BITS(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_DRV0, PVT_PUMP_DRV, PVT_PUMP_DRV0_S); //Configure the charging intensity
} else {
ESP_HW_LOGD(TAG, "blk_version is less than 3, pvt charge_pump init not supported in efuse.");
}
}
@@ -162,8 +156,6 @@ void IRAM_ATTR charge_pump_enable(bool enable)
} else {
CLEAR_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); //disable charge pump
}
} else {
ESP_HW_LOGD(TAG, "blk_version is less than 3, pvt charge_pump enable not supported in efuse.");
}
}
components/esp_hw_support/sleep_modes.c
+17 -2
View File
@@ -191,11 +191,14 @@
#elif CONFIG_IDF_TARGET_ESP32C6
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (318)
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (56)
#define PVT_REINIT_COST_US (60)
#elif CONFIG_IDF_TARGET_ESP32C5
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (318)
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (56)
#define PVT_REINIT_COST_US (25)
#elif CONFIG_IDF_TARGET_ESP32C61
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (230)
#define PVT_REINIT_COST_US (90)
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (70)
#elif CONFIG_IDF_TARGET_ESP32H2
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (118)
@@ -1477,9 +1480,9 @@ esp_err_t esp_light_sleep_start(void)
// Re-calibrate the RTC clock
sleep_low_power_clock_calibration(false);
uint32_t cur_cpu_freq = esp_clk_cpu_freq() / MHZ;
uint32_t xtal_freq = rtc_clk_xtal_freq_get();
if (s_config.overhead_out_need_remeasure) {
uint32_t cur_cpu_freq = esp_clk_cpu_freq() / MHZ;
uint32_t xtal_freq = rtc_clk_xtal_freq_get();
if (cur_cpu_freq < xtal_freq) {
s_config.sleep_time_overhead_out = DEFAULT_SLEEP_OUT_OVERHEAD_US * xtal_freq / cur_cpu_freq;
} else {
@@ -1496,6 +1499,18 @@ esp_err_t esp_light_sleep_start(void)
*/
#if SOC_PMU_SUPPORTED
int sleep_time_sw_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US + sleep_time_overhead_in + s_config.sleep_time_overhead_out;
#if CONFIG_ESP_ENABLE_PVT && !SOC_PVT_EN_WITH_SLEEP
/* PVT will only be enabled during the wake-up process if the CPU's clock source is PLL when the CPU goes to sleep. */
if ((cur_cpu_freq > xtal_freq)
#if CONFIG_IDF_TARGET_ESP32C5
/* On esp32c5, CPU 40m is divided from PLL160/240M */
|| (xtal_freq == SOC_XTAL_FREQ_48M && cur_cpu_freq == 40)
#endif
) {
sleep_time_sw_adjustment += PVT_REINIT_COST_US;
}
#endif
int sleep_time_hw_adjustment = pmu_sleep_calculate_hw_wait_time(sleep_flags, rtc_clk_slow_src_get(), s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period);
s_config.sleep_time_adjustment = sleep_time_sw_adjustment + sleep_time_hw_adjustment;
#else