feat(p4): changed to rev3.1 by default

components/esp_hw_support/lowpower/port/esp32p4/Kconfig.p4_rev3_mspi_workaround

@@ -1,7 +1,7 @@
 config P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
     bool
     depends on IDF_TARGET_ESP32P4
-    default y if !ESP32P4_SELECTS_REV_LESS_V3
+    default y if !ESP32P4_SELECTS_REV_LESS_V3  # Fixed since REV3.1
 
 config P4_REV3_MSPI_WORKAROUND_SIZE
     hex

components/esp_hw_support/port/esp32p4/Kconfig.hw_support

@@ -3,8 +3,7 @@ comment "Read the help text of the option below for explanation"
 
 config ESP32P4_SELECTS_REV_LESS_V3
     bool "Select ESP32-P4 revisions <3.0 (No >=3.x Support)"
-    default n if IDF_CI_BUILD
-    default y
+    default n
     help
         Select this option to support ESP32-P4 revisions 0.x and 1.x.
         Revisions higher than 3.0 (included) and revisions less than 3.0
@@ -13,7 +12,8 @@ config ESP32P4_SELECTS_REV_LESS_V3
 
 choice ESP32P4_REV_MIN
     prompt "Minimum Supported ESP32-P4 Revision"
-    default ESP32P4_REV_MIN_1
+    default ESP32P4_REV_MIN_300 if IDF_CI_BUILD
+    default ESP32P4_REV_MIN_301
     help
         Required minimum chip revision. ESP-IDF will check for it and
         reject to boot if the chip revision fails the check.

components/esp_hw_support/port/esp32p4/pmu_sleep.c

@@ -425,7 +425,9 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
         }
     } else {
 #if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
+    if (efuse_hal_chip_revision() == 300) {
         lp_clkrst_ll_boot_from_lp_ram(true);
+    }
 #endif
     }
 
@@ -456,8 +458,10 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
         ldo_ll_enable(LDO_ID2UNIT(CONFIG_ESP_LDO_CHAN_PSRAM_DOMAIN), true);
 #endif
 #if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
-        // Set reset vector back to HP ROM after deepsleep request rejected
-        lp_clkrst_ll_boot_from_lp_ram(false);
+        if (efuse_hal_chip_revision() == 300) {
+            // Set reset vector back to HP ROM after deepsleep request rejected
+            lp_clkrst_ll_boot_from_lp_ram(false);
+        }
 #endif
     }
 

components/esp_hw_support/port/esp32p4/rtc_clk_init.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -68,9 +68,10 @@ void rtc_clk_init(rtc_clk_config_t cfg)
         hp_dcmvset = pvt_hp_dcmvset;
     }
     // Switch to DCDC
-#if (CONFIG_ESP32P4_REV_MIN_FULL >= 301)
+#if (CONFIG_ESP32P4_REV_MIN_FULL >= 300)
     unsigned chip_version = efuse_hal_chip_revision();
-    if (ESP_CHIP_REV_ABOVE(chip_version, 301)) {
+    if (ESP_CHIP_REV_BETWEEN(chip_version, 300, 301)) {
+        // This workaround is only needed for P4 rev3.1
         SET_PERI_REG_MASK(PMU_DCM_CTRL_REG, PMU_DCDC_FB_RES_FORCE_PD);
     }
 #endif
@@ -79,8 +80,9 @@ void rtc_clk_init(rtc_clk_config_t cfg)
     pmu_ll_hp_set_dcm_vset(&PMU, PMU_MODE_HP_ACTIVE, hp_dcmvset);
     SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // Hand over control of dbias to pmu
     esp_rom_delay_us(1000);
-#if (CONFIG_ESP32P4_REV_MIN_FULL >= 301)
-    if (ESP_CHIP_REV_ABOVE(chip_version, 301)) {
+#if (CONFIG_ESP32P4_REV_MIN_FULL >= 300)
+    if (ESP_CHIP_REV_BETWEEN(chip_version, 300, 301)) {
+        // This workaround is only needed for P4 rev3.1
         REG_SET_FIELD(LP_SYSTEM_REG_SYS_CTRL_REG, LP_SYSTEM_REG_LP_FIB_SEL, 0xEF);// lp_fib_sel bit4 set to 0: select dig_fib_reg instead of ana_fib_reg
         CLEAR_PERI_REG_MASK(PMU_DCM_CTRL_REG, PMU_DCDC_FB_RES_FORCE_PD);
         esp_rom_delay_us(10);

components/soc/include/soc/chip_revision.h

@@ -29,12 +29,14 @@ extern "C" {
  */
 
 #define ESP_CHIP_REV_ABOVE(rev, min_rev) ((min_rev) <= (rev))
+#define ESP_CHIP_REV_BETWEEN(rev, min_rev, max_rev) (((min_rev) <= (rev)) && ((rev) <= (max_rev)))
 #define ESP_CHIP_REV_MAJOR_AND_ABOVE(rev, min_rev) (((rev) / 100 == (min_rev) / 100) && ((rev) >= (min_rev)))
 
 /**
  * eFuse block revision strategy is same as chip revision
  */
 #define ESP_EFUSE_BLK_REV_ABOVE(rev, min_rev) ESP_CHIP_REV_ABOVE(rev, min_rev)
+#define ESP_EFUSE_BLK_REV_BETWEEN(rev, min_rev, max_rev) ESP_CHIP_REV_BETWEEN(rev, min_rev, max_rev)
 #define ESP_EFUSE_BLK_REV_MAJOR_AND_ABOVE(rev, min_rev) ESP_CHIP_REV_MAJOR_AND_ABOVE(rev, min_rev)
 
 #ifdef __cplusplus