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fix(esp_hw_support): fix cpu restart failed due to rtc_clk in flash

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This commit is contained in:
hebinglin
2026-01-06 17:35:45 +08:00
parent ab213a9987
commit eec9c8843a
12 changed files with 63 additions and 53 deletions
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components/esp_hw_support/port/esp32/rtc_clk.c
+6 -5
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -31,6 +31,7 @@
#include "esp_private/systimer.h"
#include "hal/timer_ll.h"
#endif
#include "esp_attr.h"
#define XTAL_32K_BOOTSTRAP_TIME_US 7
@@ -369,7 +370,7 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
* Must satisfy: cpu_freq = XTAL_FREQ / div.
* Does not disable the PLL.
*/
void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
{
esp_rom_set_cpu_ticks_per_us(cpu_freq);
/* set divider from XTAL to APB clock */
@@ -461,7 +462,7 @@ void rtc_clk_cpu_freq_set_xtal(void)
rtc_clk_bbpll_disable();
}
void rtc_clk_cpu_set_to_default_config(void)
FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void)
{
int freq_mhz = (int)rtc_clk_xtal_freq_get();
@@ -607,7 +608,7 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t* config)
}
}
soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
FORCE_IRAM_ATTR soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
{
uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
if (xtal_freq_mhz == 0) {
@@ -621,7 +622,7 @@ void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq)
clk_ll_xtal_store_freq_mhz((uint32_t)xtal_freq);
}
void rtc_clk_apb_freq_update(uint32_t apb_freq)
FORCE_IRAM_ATTR void rtc_clk_apb_freq_update(uint32_t apb_freq)
{
clk_ll_apb_store_freq_hz(apb_freq);
}
components/esp_hw_support/port/esp32c2/rtc_clk.c
+6 -5
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -21,6 +21,7 @@
#include "esp_rom_sys.h"
#include "hal/clk_tree_ll.h"
#include "hal/regi2c_ctrl_ll.h"
#include "esp_attr.h"
static const char *TAG = "rtc_clk";
@@ -289,7 +290,7 @@ void rtc_clk_cpu_freq_set_xtal(void)
rtc_clk_bbpll_disable();
}
void rtc_clk_cpu_set_to_default_config(void)
FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void)
{
int freq_mhz = (int)rtc_clk_xtal_freq_get();
@@ -306,7 +307,7 @@ void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
* Must satisfy: cpu_freq = XTAL_FREQ / div.
* Does not disable the PLL.
*/
void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
{
esp_rom_set_cpu_ticks_per_us(cpu_freq);
/* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */
@@ -325,7 +326,7 @@ static void rtc_clk_cpu_freq_to_8m(void)
rtc_clk_apb_freq_update(SOC_CLK_RC_FAST_FREQ_APPROX);
}
soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
FORCE_IRAM_ATTR soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
{
uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
if (xtal_freq_mhz == 0) {
@@ -340,7 +341,7 @@ void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq)
clk_ll_xtal_store_freq_mhz(xtal_freq);
}
void rtc_clk_apb_freq_update(uint32_t apb_freq)
FORCE_IRAM_ATTR void rtc_clk_apb_freq_update(uint32_t apb_freq)
{
clk_ll_apb_store_freq_hz(apb_freq);
}
components/esp_hw_support/port/esp32c3/rtc_clk.c
+6 -5
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -19,6 +19,7 @@
#include "esp_rom_sys.h"
#include "hal/clk_tree_ll.h"
#include "hal/regi2c_ctrl_ll.h"
#include "esp_attr.h"
static const char *TAG = "rtc_clk";
@@ -318,7 +319,7 @@ void rtc_clk_cpu_freq_set_xtal(void)
rtc_clk_bbpll_disable();
}
void rtc_clk_cpu_set_to_default_config(void)
FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void)
{
int freq_mhz = (int)rtc_clk_xtal_freq_get();
@@ -335,7 +336,7 @@ void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
* Must satisfy: cpu_freq = XTAL_FREQ / div.
* Does not disable the PLL.
*/
static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
static FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
{
esp_rom_set_cpu_ticks_per_us(cpu_freq);
/* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */
@@ -354,7 +355,7 @@ static void rtc_clk_cpu_freq_to_8m(void)
rtc_clk_apb_freq_update(SOC_CLK_RC_FAST_FREQ_APPROX);
}
soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
FORCE_IRAM_ATTR soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
{
uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
if (xtal_freq_mhz == 0) {
@@ -369,7 +370,7 @@ void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq)
clk_ll_xtal_store_freq_mhz(xtal_freq);
}
void rtc_clk_apb_freq_update(uint32_t apb_freq)
FORCE_IRAM_ATTR void rtc_clk_apb_freq_update(uint32_t apb_freq)
{
clk_ll_apb_store_freq_hz(apb_freq);
}
components/esp_hw_support/port/esp32c5/rtc_clk.c
+3 -3
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@@ -172,7 +172,7 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
* Must satisfy: cpu_freq = XTAL_FREQ / div.
* Does not disable the PLL.
*/
static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
static FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
{
// let f_cpu = f_ahb
clk_ll_cpu_set_divider(div);
@@ -451,7 +451,7 @@ void rtc_clk_cpu_freq_set_xtal(void)
rtc_clk_bbpll_disable();
}
void rtc_clk_cpu_set_to_default_config(void)
FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void)
{
int freq_mhz = (int)rtc_clk_xtal_freq_get();
#ifndef BOOTLOADER_BUILD
@@ -497,7 +497,7 @@ void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
}
#endif
soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
FORCE_IRAM_ATTR soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
{
uint32_t xtal_freq_mhz = clk_ll_xtal_get_freq_mhz();
assert(xtal_freq_mhz == SOC_XTAL_FREQ_48M || xtal_freq_mhz == SOC_XTAL_FREQ_40M);
components/esp_hw_support/port/esp32c6/rtc_clk.c
+4 -3
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@@ -22,6 +22,7 @@
#include "soc/lp_aon_reg.h"
#include "esp_private/sleep_event.h"
#include "esp_private/regi2c_ctrl.h"
#include "esp_attr.h"
static const char *TAG = "rtc_clk";
@@ -184,7 +185,7 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
* Must satisfy: cpu_freq = XTAL_FREQ / div.
* Does not disable the PLL.
*/
static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
static FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
{
clk_ll_ahb_set_ls_divider(div);
clk_ll_cpu_set_ls_divider(div);
@@ -359,7 +360,7 @@ void rtc_clk_cpu_freq_set_xtal(void)
rtc_clk_bbpll_disable();
}
void rtc_clk_cpu_set_to_default_config(void)
FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void)
{
int freq_mhz = (int)rtc_clk_xtal_freq_get();
@@ -378,7 +379,7 @@ void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
clk_ll_cpu_clk_src_lock_release();
}
soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
FORCE_IRAM_ATTR soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
{
uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
if (xtal_freq_mhz == 0) {
components/esp_hw_support/port/esp32c61/rtc_clk.c
+3 -3
View File
@@ -170,7 +170,7 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
* Must satisfy: cpu_freq = XTAL_FREQ / div.
* Does not disable the PLL.
*/
static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
static FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
{
// let f_cpu = f_ahb
clk_ll_cpu_set_divider(div);
@@ -345,7 +345,7 @@ void rtc_clk_cpu_freq_set_xtal(void)
rtc_clk_bbpll_disable();
}
void rtc_clk_cpu_set_to_default_config(void)
FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void)
{
int freq_mhz = (int)rtc_clk_xtal_freq_get();
@@ -364,7 +364,7 @@ void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
clk_ll_cpu_clk_src_lock_release();
}
soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
FORCE_IRAM_ATTR soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
{
uint32_t xtal_freq_mhz = clk_ll_xtal_get_freq_mhz();
assert(xtal_freq_mhz == SOC_XTAL_FREQ_40M);
components/esp_hw_support/port/esp32h2/rtc_clk.c
+5 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -22,6 +22,7 @@
#include "soc/lp_aon_reg.h"
#include "esp_private/sleep_event.h"
#include "esp_private/regi2c_ctrl.h"
#include "esp_attr.h"
static const char *TAG = "rtc_clk";
@@ -195,7 +196,7 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
* Must satisfy: cpu_freq = XTAL_FREQ / div.
* Does not disable the PLL.
*/
static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
static FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
{
// let f_cpu = f_ahb
clk_ll_cpu_set_divider(div);
@@ -400,7 +401,7 @@ void rtc_clk_cpu_freq_set_xtal(void)
rtc_clk_bbpll_disable();
}
void rtc_clk_cpu_set_to_default_config(void)
FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void)
{
int freq_mhz = (int)rtc_clk_xtal_freq_get();
@@ -413,7 +414,7 @@ void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
rtc_clk_cpu_set_to_default_config();
}
soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
FORCE_IRAM_ATTR soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
{
uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
if (xtal_freq_mhz == 0) {
components/esp_hw_support/port/esp32h21/rtc_clk.c
+5 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -22,6 +22,7 @@
#include "soc/lp_aon_reg.h"
#include "esp_private/sleep_event.h"
#include "esp_private/regi2c_ctrl.h"
#include "esp_attr.h"
static const char *TAG = "rtc_clk";
@@ -195,7 +196,7 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
* Must satisfy: cpu_freq = XTAL_FREQ / div.
* Does not disable the PLL.
*/
static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
static FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
{
// let f_cpu = f_ahb
clk_ll_cpu_set_divider(div);
@@ -400,7 +401,7 @@ void rtc_clk_cpu_freq_set_xtal(void)
rtc_clk_bbpll_disable();
}
void rtc_clk_cpu_set_to_default_config(void)
FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void)
{
int freq_mhz = (int)rtc_clk_xtal_freq_get();
@@ -413,7 +414,7 @@ void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
rtc_clk_cpu_set_to_default_config();
}
soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
FORCE_IRAM_ATTR soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
{
uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
if (xtal_freq_mhz == 0) {
components/esp_hw_support/port/esp32h4/rtc_clk.c
+5 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -21,6 +21,7 @@
#include "soc/io_mux_reg.h"
#include "soc/lp_aon_reg.h"
#include "esp_private/sleep_event.h"
#include "esp_attr.h"
static const char *TAG = "rtc_clk";
@@ -175,7 +176,7 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
* Must satisfy: cpu_freq = XTAL_FREQ / div.
* Does not disable the PLL.
*/
static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
static FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
{
clk_ll_ahb_set_ls_divider(div);
clk_ll_cpu_set_ls_divider(div);
@@ -339,7 +340,7 @@ void rtc_clk_cpu_freq_set_xtal(void)
}
}
void rtc_clk_cpu_set_to_default_config(void)
FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void)
{
int freq_mhz = (int)rtc_clk_xtal_freq_get();
@@ -357,7 +358,7 @@ void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
clk_ll_cpu_clk_src_lock_release();
}
soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
FORCE_IRAM_ATTR soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
{
#if !CONFIG_IDF_ENV_FPGA
uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
components/esp_hw_support/port/esp32p4/rtc_clk.c
+5 -4
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -23,6 +23,7 @@
#include "soc/io_mux_reg.h"
#include "esp_private/sleep_event.h"
#include "esp_private/regi2c_ctrl.h"
#include "esp_attr.h"
static const char *TAG = "rtc_clk";
@@ -179,7 +180,7 @@ static void rtc_clk_cpll_configure(soc_xtal_freq_t xtal_freq, int cpll_freq)
* If to_default is set, then will configure CPU - MEM - SYS - APB frequencies back to power-on reset configuration (40 - 20 - 20 - 10)
* If to_default is not set, then will configure to 40 - 40 - 40 - 40
*/
static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div, bool to_default)
static FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div, bool to_default)
{
// let f_cpu = f_mem = f_sys = f_apb
uint32_t mem_divider = 1;
@@ -494,7 +495,7 @@ void rtc_clk_cpu_freq_set_xtal(void)
rtc_clk_cpll_disable();
}
void rtc_clk_cpu_set_to_default_config(void)
FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void)
{
int freq_mhz = (int)rtc_clk_xtal_freq_get();
@@ -509,7 +510,7 @@ void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
s_cur_cpll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep
}
soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
FORCE_IRAM_ATTR soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
{
uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
if (xtal_freq_mhz == 0) {
components/esp_hw_support/port/esp32s2/rtc_clk.c
+4 -3
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -25,6 +25,7 @@
#include "esp_private/systimer.h"
#include "hal/systimer_ll.h"
#endif
#include "esp_attr.h"
static const char *TAG = "rtc_clk";
@@ -445,7 +446,7 @@ void rtc_clk_cpu_freq_set_xtal(void)
/* BBPLL is kept enabled */
}
void rtc_clk_cpu_set_to_default_config(void)
FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void)
{
rtc_clk_cpu_freq_to_xtal(CLK_LL_XTAL_FREQ_MHZ, 1);
}
@@ -460,7 +461,7 @@ void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
* Must satisfy: cpu_freq = XTAL_FREQ / div.
* Does not disable the PLL.
*/
static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
static FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
{
rtc_cpu_freq_config_t cur_config;
rtc_clk_cpu_freq_get_config(&cur_config);
components/esp_hw_support/port/esp32s3/rtc_clk.c
+11 -10
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -25,6 +25,7 @@
#include "soc/regi2c_dig_reg.h"
#include "soc/sens_reg.h"
#include "sdkconfig.h"
#include "esp_attr.h"
static const char *TAG = "rtc_clk";
@@ -316,7 +317,7 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
}
}
void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
FORCE_IRAM_ATTR void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
{
soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
uint32_t source_freq_mhz;
@@ -339,8 +340,8 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
} else if (freq_mhz == CLK_LL_PLL_240M_FREQ_MHZ && source_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) {
div = 2;
} else {
ESP_HW_LOGE(TAG, "unsupported frequency configuration");
return;
// Unsupported frequency configuration
abort();
}
break;
}
@@ -350,8 +351,8 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
freq_mhz = source_freq_mhz;
break;
default:
ESP_HW_LOGE(TAG, "unsupported frequency configuration");
return;
// Unsupported frequency configuration
abort();
}
*out_config = (rtc_cpu_freq_config_t) {
.source = source,
@@ -380,7 +381,7 @@ void rtc_clk_cpu_freq_set_xtal(void)
rtc_clk_bbpll_disable();
}
void rtc_clk_cpu_set_to_default_config(void)
FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void)
{
int freq_mhz = (int)rtc_clk_xtal_freq_get();
@@ -399,7 +400,7 @@ void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
*
* Public function for testing only.
*/
void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
{
rtc_cpu_freq_config_t cur_config;
rtc_clk_cpu_freq_get_config(&cur_config);
@@ -433,7 +434,7 @@ static void rtc_clk_cpu_freq_to_8m(void)
REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, DEFAULT_LDO_SLAVE);
}
soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
FORCE_IRAM_ATTR soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
{
uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
if (xtal_freq_mhz == 0) {
@@ -448,7 +449,7 @@ void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq)
clk_ll_xtal_store_freq_mhz(xtal_freq);
}
void rtc_clk_apb_freq_update(uint32_t apb_freq)
FORCE_IRAM_ATTR void rtc_clk_apb_freq_update(uint32_t apb_freq)
{
s_apb_freq = apb_freq;
}