9b69adf1fa
Merge branch 'bugfix/esp_idf_h2_flash_cs_hold_v5.5' into 'release/v5.5'
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fix(esp_hw_support): fix flash cs unhold during sleep when pd top in esp32h2 (v5.5)
See merge request espressif/esp-idf!43558
2025-12-30 10:16:31 +08:00
1851470481
Merge branch 'feat/p4eco6_ldo2dcdc_support_v5.5' into 'release/v5.5'
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feat (p4eco6): open dcdc switch by software when dcdc stable (v5.5)
See merge request espressif/esp-idf!44578
2025-12-29 11:18:37 +08:00
fb7466c86b
Merge branch 'refactor/gdma_link_skip_null_buffer_v5.5' into 'release/v5.5'
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skip the NULL buffer in DMA mount pre-check (v5.5)
See merge request espressif/esp-idf!44459
2025-12-26 18:01:03 +08:00
9ea85ed080
Merge branch 'feat/add_c5_v102_config_v5.5' into 'release/v5.5'
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hw_support: add new config for c5 v1.2 and c61 v1.1 (v5.5)
See merge request espressif/esp-idf!43615
2025-12-26 09:51:18 +05:30
3fb705d852
feat (p4eco6): open dcdc switch by software when dcdc stable
2025-12-26 09:54:02 +08:00
e5b4993cd2
Merge branch 'backport/recent_backport_collection_v5.5' into 'release/v5.5'
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backport: backport recent i2s/parlio rx/touch related to v5.5
See merge request espressif/esp-idf!43785
2025-12-26 09:52:26 +08:00
08b3edc0a6
fix(esp_hw_support): fix flash cs unhold during sleep when pd top in esp32h2
2025-12-24 10:33:54 +08:00
b652c1a5e8
refactor(gdma): skip the null buffer in mount pre-check
2025-12-24 10:09:21 +08:00
5d5d15fbfc
fix(esp_hw_support): fix RNG to LP Peri domain dependency on C5
2025-12-23 23:43:13 +08:00
faf6cc4f84
feat(spi_flash): implement dynamic CPU frequency switching workaround for encrypted writes
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This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency
normally, while automatically reducing CPU frequency during encrypted flash writes to
ensure correct operation. The frequency limit is chip revision dependent:
- v1.2 and above: limited to 160MHz during encrypted writes
- v1.0 and below: limited to 80MHz during encrypted writes
Key implementation details:
- Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called
- Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer
- Works with both PM enabled and disabled configurations
- Frequency is automatically restored after encrypted write completes
- For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when
CPU frequency is reduced to 80MHz
- SPI1 timing registers are configured during frequency switching since encrypted writes
use SPI1 and must work correctly at reduced CPU frequencies
Code improvements:
- Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks
- Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of
hardcoded macros
- Add comprehensive test cases covering various PM configurations and edge cases
This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance
while maintaining reliable encrypted flash write functionality.
2025-12-17 03:33:29 +08:00
0f07ad18b6
fix: add mutex protection for software trigger RegDMA start to avoid data races
2025-12-11 20:32:53 +08:00
871ec2c1ef
Merge branch 'feat/enable_lowpower_tests_for_p4_v3_v5.5' into 'release/v5.5'
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feat: re-enable P4 pm/wakeup tests for rev3.0 (v5.5)
See merge request espressif/esp-idf!43760
2025-12-04 10:46:56 +08:00
ca8183d36a
fix(esp_hw_support): update DEFAULT_SLEEP_OUT_OVERHEAD_US for esp32c61
2025-12-02 14:59:04 +08:00
625c96675e
feat(hw_support): add config version for c61 v1.1
2025-11-30 19:40:47 +08:00
26b91fc262
feat(hw_support): add config version for c5 v1.2
2025-11-30 19:40:47 +08:00
047ea940bf
refactor(parlio_rx): refactor to support unaligned user payload buffer
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Closes https://github.com/espressif/esp-idf/issues/17581
2025-11-28 15:37:28 +08:00
ce84d734ef
feat(gdma_link): support to select final node link type
2025-11-27 11:36:58 +08:00
6a7659432b
Merge branch 'feat/esp_idf_feat_gpioworkaround_v5.5' into 'release/v5.5'
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feat(esp_hw_support): add gpio reset workaround except esp32 & esp32s2 (v5.5)
See merge request espressif/esp-idf!43469
2025-11-27 10:22:02 +08:00
2db91774f7
Merge branch 'fix/fix_bad_esp_clk_tree_initialize_v5.5' into 'release/v5.5'
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fix(esp_hw_support): fix esp32c5 clk seting broken after CPU reset (v5.5)
See merge request espressif/esp-idf!43453
2025-11-27 10:19:11 +08:00
ab1998e45b
feat(esp_hw_support): re-enable P4 sleep wakeup tests for rev3.0
2025-11-26 19:24:21 +08:00
d2ac65df80
Merge branch 'feat/make_p4_rev3_default_v5.5' into 'release/v5.5'
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p4: make v3 as default for CI (v5.5)
See merge request espressif/esp-idf!43441
2025-11-26 12:02:29 +08:00
d66ebb86d2
Merge branch 'feat/psram_250m_p4_v5.5' into 'release/v5.5'
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psram: support 250MHz in experimental (v5.5)
See merge request espressif/esp-idf!43348
2025-11-21 11:12:22 +08:00
4ef2005b80
change(ci): use p4 rev3 by default only when ci build
2025-11-20 11:33:36 +08:00
304ba1655b
fix check test scripts build issue
2025-11-20 11:33:36 +08:00
cdff2570c7
ci(p4): disable p4 rev3 invalid tests temporarily
2025-11-20 11:33:36 +08:00
e44a3603c4
refactor(sleep_cpu): suppress infinite loop warnings with compiler diagnostics
2025-11-20 11:33:36 +08:00
304ebc0c74
change(p4): make v3 as default
2025-11-20 11:33:36 +08:00
8e0f48798b
feat(esp_hw_support): add gpio reset workaround in esp32h21 & esp32h4
2025-11-18 14:19:17 +08:00
159418f638
fix(esp_hw_support): fix esp32c5 clk seting broken after CPU reset
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Closes https://github.com/espressif/esp-idf/issues/17780
2025-11-18 11:47:17 +08:00
34c9b4fc72
Merge branch 'fix/fix_c6_rtc_periph_depends_on_top_v5.5' into 'release/v5.5'
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fix(esp_hw_support): add dependency of the TOP domain to the RTC_PERIPH domain for esp32c6 (v5.5)
See merge request espressif/esp-idf!43383
2025-11-17 15:16:14 +08:00
8c77a3075a
fix(esp_hw_support): add dependency of the TOP domain to the RTC_PERIPH domain for esp32c6
2025-11-14 16:40:27 +08:00
b698ac758e
feat(psram): support 250MHz in experimental
2025-11-14 09:34:51 +08:00
9589ab5361
feat(gpio): add IO hold support for Deep-sleep for ESP32-P4 ECO5
2025-11-13 11:36:15 +08:00
4e525b6875
feat(tools): update toolchain version to esp-14.2.0_20251107
2025-11-08 11:15:14 +07:00
3b2a14f220
change(esp_hw_support): esp32p4 rev3.0 dummy read workaround refactor
2025-10-30 19:09:48 +08:00
3ee348fe52
fix(esp_hw_support): add p4 rev3.0 MSPI workaround for deepsleep
2025-10-30 19:09:44 +08:00
bb2052f2ef
fix(esp_hw_support): fix mie lost after pd_cpu sleep request reject
2025-10-29 17:22:19 +08:00
72ea3de736
change(esp_hw_support): set HP/LP mem in retention mode in sleep
2025-10-29 17:22:19 +08:00
8c3dab6bb1
Merge branch 'feat/esp_tee_mspi_tuning_v5.5' into 'release/v5.5'
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change(esp_tee): Fix TEE SPI flash API issues on ESP32-C5 (v5.5)
See merge request espressif/esp-idf!42907
2025-10-28 17:43:43 +05:30
a0de5f7387
Merge branch 'feature/esp32p4_eco5_support_v5.5' into 'release/v5.5'
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feat(gpio/ledc/uart/2ddma/ppa): ESP32P4 ECO5 related updates (v5.5)
See merge request espressif/esp-idf!42816
2025-10-27 15:50:42 +08:00
6cb1869480
Merge branch 'feat/support_esp32p4_eco5_pmu_v5.5' into 'release/v5.5'
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feat(esp_hw_support): update esp32p4 eco5 lowpower features support (v5.5)
See merge request espressif/esp-idf!42685
2025-10-27 14:47:33 +08:00
6bfea8fef8
feat(esp_tee): Enable MSPI tuning for Flash and PSRAM
2025-10-27 11:17:07 +05:30
e69eeb7355
feat(2ddma): ESP32P4 ECO5 2DDMA related updates
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Added one more pair of 2DDMA channels
Priority bit width increased corespondingly
Added three new CSC modes for RX channel 0
2025-10-22 20:05:59 +08:00
a9b2bd1b72
feat(interrupts): ESP32P4 ECO5 interrupt sources update
2025-10-22 20:05:59 +08:00
ffa4653a69
fix(flash): Modify the log safety in timing tuning
2025-10-22 19:31:16 +08:00
e054d168c1
Merge branch 'fix/c5_tee_sram_prot_v5.5' into 'release/v5.5'
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fix(esp_tee): Split TEE SRAM as I/DRAM for ESP32-C5 with PMA (v5.5)
See merge request espressif/esp-idf!42680
2025-10-21 17:25:15 +05:30
a6531fcd25
Merge branch 'feat/enable_esptool_stub_for_p4eco5_v5.5' into 'release/v5.5'
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feat(hw_support): enable esptool stub for p4eco5 (v5.5)
See merge request espressif/esp-idf!42688
2025-10-20 19:20:28 +08:00
5bcfa44e02
change(esp_hw_support): set HP/LP mem in retention mode in sleep
2025-10-20 17:18:58 +08:00
db95e8a7ad
fix(esp_hw_support): add PD_TOP lightsleep mspi failure workaround for p4 rev3
2025-10-20 17:18:57 +08:00
7950413b61
fix(esp_hw_support): fix P4 v3.0 USB leakage on PU_CNNT lightsleep
2025-10-20 17:18:56 +08:00
Jiang Jiang Jian