change(p4): make v3 as default
This commit is contained in:
armando
@@ -3,7 +3,7 @@ comment "Read the help text of the option below for explanation"
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config ESP32P4_SELECTS_REV_LESS_V3
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bool "Select ESP32-P4 revisions <3.0 (No >=3.x Support)"
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default y
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default n
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help
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Select this option to support ESP32-P4 revisions 0.x and 1.x.
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Revisions higher than 3.0 (included) and revisions less than 3.0
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File diff suppressed because it is too large
Load Diff
@@ -813,245 +813,19 @@ typedef union {
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} lp_spi_sleep_conf1_reg_t;
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/** Group: LP SPI W0 REG */
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/** Type of spi_w0 register
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/** Group: LP SPI Wn REG */
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/** Type of spi_wn register
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* SPI CPU-controlled buffer0
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*/
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typedef union {
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struct {
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/** reg_buf0 : R/W/SS; bitpos: [31:0]; default: 0;
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/** reg_buf : R/W/SS; bitpos: [31:0]; default: 0;
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* data buffer
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*/
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uint32_t reg_buf0:32;
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uint32_t reg_buf:32;
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};
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uint32_t val;
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} lp_spi_w0_reg_t;
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/** Group: LP SPI W1 REG */
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/** Type of spi_w1 register
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* SPI CPU-controlled buffer1
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*/
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typedef union {
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struct {
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/** reg_buf1 : R/W/SS; bitpos: [31:0]; default: 0;
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* data buffer
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*/
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uint32_t reg_buf1:32;
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};
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uint32_t val;
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} lp_spi_w1_reg_t;
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/** Group: LP SPI W2 REG */
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/** Type of spi_w2 register
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* SPI CPU-controlled buffer2
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*/
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typedef union {
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struct {
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/** reg_buf2 : R/W/SS; bitpos: [31:0]; default: 0;
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* data buffer
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*/
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uint32_t reg_buf2:32;
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};
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uint32_t val;
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} lp_spi_w2_reg_t;
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/** Group: LP SPI W3 REG */
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/** Type of spi_w3 register
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* SPI CPU-controlled buffer3
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*/
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typedef union {
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struct {
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/** reg_buf3 : R/W/SS; bitpos: [31:0]; default: 0;
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* data buffer
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*/
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uint32_t reg_buf3:32;
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};
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uint32_t val;
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} lp_spi_w3_reg_t;
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/** Group: LP SPI W4 REG */
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/** Type of spi_w4 register
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* SPI CPU-controlled buffer4
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*/
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typedef union {
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struct {
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/** reg_buf4 : R/W/SS; bitpos: [31:0]; default: 0;
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* data buffer
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*/
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uint32_t reg_buf4:32;
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};
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uint32_t val;
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} lp_spi_w4_reg_t;
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/** Group: LP SPI W5 REG */
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/** Type of spi_w5 register
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* SPI CPU-controlled buffer5
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*/
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typedef union {
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struct {
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/** reg_buf5 : R/W/SS; bitpos: [31:0]; default: 0;
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* data buffer
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*/
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uint32_t reg_buf5:32;
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};
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uint32_t val;
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} lp_spi_w5_reg_t;
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/** Group: LP SPI W6 REG */
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/** Type of spi_w6 register
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* SPI CPU-controlled buffer6
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*/
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typedef union {
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struct {
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/** reg_buf6 : R/W/SS; bitpos: [31:0]; default: 0;
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* data buffer
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*/
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uint32_t reg_buf6:32;
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};
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uint32_t val;
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} lp_spi_w6_reg_t;
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/** Group: LP SPI W7 REG */
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/** Type of spi_w7 register
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* SPI CPU-controlled buffer7
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*/
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typedef union {
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struct {
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/** reg_buf7 : R/W/SS; bitpos: [31:0]; default: 0;
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* data buffer
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*/
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uint32_t reg_buf7:32;
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};
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uint32_t val;
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} lp_spi_w7_reg_t;
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/** Group: LP SPI W8 REG */
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/** Type of spi_w8 register
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* SPI CPU-controlled buffer8
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*/
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typedef union {
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struct {
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/** reg_buf8 : R/W/SS; bitpos: [31:0]; default: 0;
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* data buffer
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*/
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uint32_t reg_buf8:32;
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};
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uint32_t val;
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} lp_spi_w8_reg_t;
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/** Group: LP SPI W9 REG */
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/** Type of spi_w9 register
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* SPI CPU-controlled buffer9
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*/
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typedef union {
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struct {
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/** reg_buf9 : R/W/SS; bitpos: [31:0]; default: 0;
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* data buffer
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*/
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uint32_t reg_buf9:32;
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};
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uint32_t val;
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} lp_spi_w9_reg_t;
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/** Group: LP SPI W10 REG */
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/** Type of spi_w10 register
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* SPI CPU-controlled buffer10
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*/
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typedef union {
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struct {
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/** reg_buf10 : R/W/SS; bitpos: [31:0]; default: 0;
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* data buffer
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*/
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uint32_t reg_buf10:32;
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};
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uint32_t val;
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} lp_spi_w10_reg_t;
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/** Group: LP SPI W11 REG */
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/** Type of spi_w11 register
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* SPI CPU-controlled buffer11
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*/
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typedef union {
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struct {
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/** reg_buf11 : R/W/SS; bitpos: [31:0]; default: 0;
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* data buffer
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*/
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uint32_t reg_buf11:32;
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};
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uint32_t val;
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} lp_spi_w11_reg_t;
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/** Group: LP SPI W12 REG */
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/** Type of spi_w12 register
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* SPI CPU-controlled buffer12
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*/
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typedef union {
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struct {
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/** reg_buf12 : R/W/SS; bitpos: [31:0]; default: 0;
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* data buffer
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*/
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uint32_t reg_buf12:32;
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};
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uint32_t val;
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} lp_spi_w12_reg_t;
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/** Group: LP SPI W13 REG */
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/** Type of spi_w13 register
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* SPI CPU-controlled buffer13
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*/
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typedef union {
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struct {
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/** reg_buf13 : R/W/SS; bitpos: [31:0]; default: 0;
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* data buffer
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*/
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uint32_t reg_buf13:32;
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};
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uint32_t val;
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} lp_spi_w13_reg_t;
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/** Group: LP SPI W14 REG */
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/** Type of spi_w14 register
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* SPI CPU-controlled buffer14
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*/
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typedef union {
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struct {
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/** reg_buf14 : R/W/SS; bitpos: [31:0]; default: 0;
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* data buffer
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*/
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uint32_t reg_buf14:32;
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};
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uint32_t val;
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} lp_spi_w14_reg_t;
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/** Group: LP SPI W15 REG */
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/** Type of spi_w15 register
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* SPI CPU-controlled buffer15
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*/
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typedef union {
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struct {
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/** reg_buf15 : R/W/SS; bitpos: [31:0]; default: 0;
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* data buffer
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*/
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uint32_t reg_buf15:32;
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};
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uint32_t val;
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} lp_spi_w15_reg_t;
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} lp_spi_wn_reg_t;
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/** Group: LP SPI SLAVE REG */
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/** Type of spi_slave register
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@@ -1238,22 +1012,7 @@ typedef struct {
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volatile lp_spi_sleep_conf1_reg_t spi_sleep_conf1;
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volatile lp_spi_dma_int_set_reg_t spi_dma_int_set;
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uint32_t reserved_050[18];
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volatile lp_spi_w0_reg_t spi_w0;
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volatile lp_spi_w1_reg_t spi_w1;
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volatile lp_spi_w2_reg_t spi_w2;
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volatile lp_spi_w3_reg_t spi_w3;
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volatile lp_spi_w4_reg_t spi_w4;
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volatile lp_spi_w5_reg_t spi_w5;
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volatile lp_spi_w6_reg_t spi_w6;
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volatile lp_spi_w7_reg_t spi_w7;
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volatile lp_spi_w8_reg_t spi_w8;
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volatile lp_spi_w9_reg_t spi_w9;
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volatile lp_spi_w10_reg_t spi_w10;
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volatile lp_spi_w11_reg_t spi_w11;
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volatile lp_spi_w12_reg_t spi_w12;
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volatile lp_spi_w13_reg_t spi_w13;
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volatile lp_spi_w14_reg_t spi_w14;
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volatile lp_spi_w15_reg_t spi_w15;
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volatile lp_spi_wn_reg_t data_buf[16];
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uint32_t reserved_0d8[2];
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volatile lp_spi_slave_reg_t spi_slave;
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volatile lp_spi_slave1_reg_t spi_slave1;
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@@ -1263,12 +1022,12 @@ typedef struct {
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volatile lp_rnd_eco_cs_reg_t rnd_eco_cs;
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volatile lp_rnd_eco_low_reg_t rnd_eco_low;
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volatile lp_rnd_eco_high_reg_t rnd_eco_high;
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} lp_dev_t;
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} lp_spi_dev_t;
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extern lp_dev_t LP_SPI;
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extern lp_spi_dev_t LP_SPI;
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#ifndef __cplusplus
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_Static_assert(sizeof(lp_dev_t) == 0x100, "Invalid size of lp_dev_t structure");
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_Static_assert(sizeof(lp_spi_dev_t) == 0x100, "Invalid size of lp_spi_dev_t structure");
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#endif
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#ifdef __cplusplus
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@@ -11,331 +11,331 @@
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extern "C" {
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#endif
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/** RTC_TIMER_TAR0_LOW_REG register
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/** LP_TIMER_TAR0_LOW_REG register
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* need_des
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*/
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#define RTC_TIMER_TAR0_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x0)
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/** RTC_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0;
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#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0)
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/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0;
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* need_des
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*/
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#define RTC_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU
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#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_M (RTC_TIMER_MAIN_TIMER_TAR_LOW0_V << RTC_TIMER_MAIN_TIMER_TAR_LOW0_S)
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#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU
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#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_S 0
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#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU
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#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S)
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#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU
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#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0
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/** RTC_TIMER_TAR0_HIGH_REG register
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/** LP_TIMER_TAR0_HIGH_REG register
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* need_des
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*/
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#define RTC_TIMER_TAR0_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x4)
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/** RTC_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0;
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#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4)
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/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0;
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* need_des
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*/
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#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU
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#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_M (RTC_TIMER_MAIN_TIMER_TAR_HIGH0_V << RTC_TIMER_MAIN_TIMER_TAR_HIGH0_S)
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#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU
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#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_S 0
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/** RTC_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0;
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#define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU
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#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S)
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#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU
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#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0
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/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0;
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* need_des
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*/
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#define RTC_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31))
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#define RTC_TIMER_MAIN_TIMER_TAR_EN0_M (RTC_TIMER_MAIN_TIMER_TAR_EN0_V << RTC_TIMER_MAIN_TIMER_TAR_EN0_S)
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#define RTC_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U
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#define RTC_TIMER_MAIN_TIMER_TAR_EN0_S 31
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#define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31))
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#define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S)
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#define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U
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#define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31
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/** RTC_TIMER_TAR1_LOW_REG register
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/** LP_TIMER_TAR1_LOW_REG register
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* need_des
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*/
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#define RTC_TIMER_TAR1_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x8)
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/** RTC_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0;
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#define LP_TIMER_TAR1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x8)
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/** LP_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0;
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* need_des
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*/
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#define RTC_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU
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#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_M (RTC_TIMER_MAIN_TIMER_TAR_LOW1_V << RTC_TIMER_MAIN_TIMER_TAR_LOW1_S)
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#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU
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#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_S 0
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#define LP_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU
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#define LP_TIMER_MAIN_TIMER_TAR_LOW1_M (LP_TIMER_MAIN_TIMER_TAR_LOW1_V << LP_TIMER_MAIN_TIMER_TAR_LOW1_S)
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#define LP_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU
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#define LP_TIMER_MAIN_TIMER_TAR_LOW1_S 0
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/** RTC_TIMER_TAR1_HIGH_REG register
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/** LP_TIMER_TAR1_HIGH_REG register
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* need_des
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*/
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#define RTC_TIMER_TAR1_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0xc)
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/** RTC_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0;
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#define LP_TIMER_TAR1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0xc)
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/** LP_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0;
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* need_des
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*/
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#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU
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#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_M (RTC_TIMER_MAIN_TIMER_TAR_HIGH1_V << RTC_TIMER_MAIN_TIMER_TAR_HIGH1_S)
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#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU
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#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_S 0
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/** RTC_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0;
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#define LP_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU
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#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_M (LP_TIMER_MAIN_TIMER_TAR_HIGH1_V << LP_TIMER_MAIN_TIMER_TAR_HIGH1_S)
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#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU
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#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_S 0
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/** LP_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0;
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* need_des
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*/
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#define RTC_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31))
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#define RTC_TIMER_MAIN_TIMER_TAR_EN1_M (RTC_TIMER_MAIN_TIMER_TAR_EN1_V << RTC_TIMER_MAIN_TIMER_TAR_EN1_S)
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#define RTC_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U
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#define RTC_TIMER_MAIN_TIMER_TAR_EN1_S 31
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#define LP_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31))
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#define LP_TIMER_MAIN_TIMER_TAR_EN1_M (LP_TIMER_MAIN_TIMER_TAR_EN1_V << LP_TIMER_MAIN_TIMER_TAR_EN1_S)
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#define LP_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U
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#define LP_TIMER_MAIN_TIMER_TAR_EN1_S 31
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/** RTC_TIMER_UPDATE_REG register
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/** LP_TIMER_UPDATE_REG register
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* need_des
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*/
|
||||
#define RTC_TIMER_UPDATE_REG (DR_REG_RTC_TIMER_BASE + 0x10)
|
||||
/** RTC_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0;
|
||||
#define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10)
|
||||
/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_TIMER_UPDATE (BIT(28))
|
||||
#define RTC_TIMER_MAIN_TIMER_UPDATE_M (RTC_TIMER_MAIN_TIMER_UPDATE_V << RTC_TIMER_MAIN_TIMER_UPDATE_S)
|
||||
#define RTC_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U
|
||||
#define RTC_TIMER_MAIN_TIMER_UPDATE_S 28
|
||||
/** RTC_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0;
|
||||
#define LP_TIMER_MAIN_TIMER_UPDATE (BIT(28))
|
||||
#define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S)
|
||||
#define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U
|
||||
#define LP_TIMER_MAIN_TIMER_UPDATE_S 28
|
||||
/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29))
|
||||
#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_M (RTC_TIMER_MAIN_TIMER_XTAL_OFF_V << RTC_TIMER_MAIN_TIMER_XTAL_OFF_S)
|
||||
#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U
|
||||
#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_S 29
|
||||
/** RTC_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0;
|
||||
#define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29))
|
||||
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S)
|
||||
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U
|
||||
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29
|
||||
/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_TIMER_SYS_STALL (BIT(30))
|
||||
#define RTC_TIMER_MAIN_TIMER_SYS_STALL_M (RTC_TIMER_MAIN_TIMER_SYS_STALL_V << RTC_TIMER_MAIN_TIMER_SYS_STALL_S)
|
||||
#define RTC_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U
|
||||
#define RTC_TIMER_MAIN_TIMER_SYS_STALL_S 30
|
||||
/** RTC_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0;
|
||||
#define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30))
|
||||
#define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S)
|
||||
#define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U
|
||||
#define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30
|
||||
/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_TIMER_SYS_RST (BIT(31))
|
||||
#define RTC_TIMER_MAIN_TIMER_SYS_RST_M (RTC_TIMER_MAIN_TIMER_SYS_RST_V << RTC_TIMER_MAIN_TIMER_SYS_RST_S)
|
||||
#define RTC_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U
|
||||
#define RTC_TIMER_MAIN_TIMER_SYS_RST_S 31
|
||||
#define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31))
|
||||
#define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S)
|
||||
#define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U
|
||||
#define LP_TIMER_MAIN_TIMER_SYS_RST_S 31
|
||||
|
||||
/** RTC_TIMER_MAIN_BUF0_LOW_REG register
|
||||
/** LP_TIMER_MAIN_BUF0_LOW_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_BUF0_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x14)
|
||||
/** RTC_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0;
|
||||
#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14)
|
||||
/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU
|
||||
#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_M (RTC_TIMER_MAIN_TIMER_BUF0_LOW_V << RTC_TIMER_MAIN_TIMER_BUF0_LOW_S)
|
||||
#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU
|
||||
#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_S 0
|
||||
#define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU
|
||||
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S)
|
||||
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU
|
||||
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0
|
||||
|
||||
/** RTC_TIMER_MAIN_BUF0_HIGH_REG register
|
||||
/** LP_TIMER_MAIN_BUF0_HIGH_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x18)
|
||||
/** RTC_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0;
|
||||
#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18)
|
||||
/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU
|
||||
#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_M (RTC_TIMER_MAIN_TIMER_BUF0_HIGH_V << RTC_TIMER_MAIN_TIMER_BUF0_HIGH_S)
|
||||
#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU
|
||||
#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_S 0
|
||||
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU
|
||||
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S)
|
||||
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU
|
||||
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0
|
||||
|
||||
/** RTC_TIMER_MAIN_BUF1_LOW_REG register
|
||||
/** LP_TIMER_MAIN_BUF1_LOW_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_BUF1_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x1c)
|
||||
/** RTC_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0;
|
||||
#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c)
|
||||
/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU
|
||||
#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_M (RTC_TIMER_MAIN_TIMER_BUF1_LOW_V << RTC_TIMER_MAIN_TIMER_BUF1_LOW_S)
|
||||
#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU
|
||||
#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_S 0
|
||||
#define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU
|
||||
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S)
|
||||
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU
|
||||
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0
|
||||
|
||||
/** RTC_TIMER_MAIN_BUF1_HIGH_REG register
|
||||
/** LP_TIMER_MAIN_BUF1_HIGH_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x20)
|
||||
/** RTC_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0;
|
||||
#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20)
|
||||
/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU
|
||||
#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_M (RTC_TIMER_MAIN_TIMER_BUF1_HIGH_V << RTC_TIMER_MAIN_TIMER_BUF1_HIGH_S)
|
||||
#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU
|
||||
#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_S 0
|
||||
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU
|
||||
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S)
|
||||
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU
|
||||
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0
|
||||
|
||||
/** RTC_TIMER_MAIN_OVERFLOW_REG register
|
||||
/** LP_TIMER_MAIN_OVERFLOW_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_OVERFLOW_REG (DR_REG_RTC_TIMER_BASE + 0x24)
|
||||
/** RTC_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0;
|
||||
#define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24)
|
||||
/** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31))
|
||||
#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_M (RTC_TIMER_MAIN_TIMER_ALARM_LOAD_V << RTC_TIMER_MAIN_TIMER_ALARM_LOAD_S)
|
||||
#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U
|
||||
#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_S 31
|
||||
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31))
|
||||
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S)
|
||||
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U
|
||||
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S 31
|
||||
|
||||
/** RTC_TIMER_INT_RAW_REG register
|
||||
/** LP_TIMER_INT_RAW_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_INT_RAW_REG (DR_REG_RTC_TIMER_BASE + 0x28)
|
||||
/** RTC_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0;
|
||||
#define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28)
|
||||
/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_OVERFLOW_RAW (BIT(30))
|
||||
#define RTC_TIMER_OVERFLOW_RAW_M (RTC_TIMER_OVERFLOW_RAW_V << RTC_TIMER_OVERFLOW_RAW_S)
|
||||
#define RTC_TIMER_OVERFLOW_RAW_V 0x00000001U
|
||||
#define RTC_TIMER_OVERFLOW_RAW_S 30
|
||||
/** RTC_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
|
||||
#define LP_TIMER_OVERFLOW_RAW (BIT(30))
|
||||
#define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S)
|
||||
#define LP_TIMER_OVERFLOW_RAW_V 0x00000001U
|
||||
#define LP_TIMER_OVERFLOW_RAW_S 30
|
||||
/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_SOC_WAKEUP_INT_RAW (BIT(31))
|
||||
#define RTC_TIMER_SOC_WAKEUP_INT_RAW_M (RTC_TIMER_SOC_WAKEUP_INT_RAW_V << RTC_TIMER_SOC_WAKEUP_INT_RAW_S)
|
||||
#define RTC_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U
|
||||
#define RTC_TIMER_SOC_WAKEUP_INT_RAW_S 31
|
||||
#define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31))
|
||||
#define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S)
|
||||
#define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U
|
||||
#define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31
|
||||
|
||||
/** RTC_TIMER_INT_ST_REG register
|
||||
/** LP_TIMER_INT_ST_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_INT_ST_REG (DR_REG_RTC_TIMER_BASE + 0x2c)
|
||||
/** RTC_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0;
|
||||
#define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c)
|
||||
/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_OVERFLOW_ST (BIT(30))
|
||||
#define RTC_TIMER_OVERFLOW_ST_M (RTC_TIMER_OVERFLOW_ST_V << RTC_TIMER_OVERFLOW_ST_S)
|
||||
#define RTC_TIMER_OVERFLOW_ST_V 0x00000001U
|
||||
#define RTC_TIMER_OVERFLOW_ST_S 30
|
||||
/** RTC_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0;
|
||||
#define LP_TIMER_OVERFLOW_ST (BIT(30))
|
||||
#define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S)
|
||||
#define LP_TIMER_OVERFLOW_ST_V 0x00000001U
|
||||
#define LP_TIMER_OVERFLOW_ST_S 30
|
||||
/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_SOC_WAKEUP_INT_ST (BIT(31))
|
||||
#define RTC_TIMER_SOC_WAKEUP_INT_ST_M (RTC_TIMER_SOC_WAKEUP_INT_ST_V << RTC_TIMER_SOC_WAKEUP_INT_ST_S)
|
||||
#define RTC_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U
|
||||
#define RTC_TIMER_SOC_WAKEUP_INT_ST_S 31
|
||||
#define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31))
|
||||
#define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S)
|
||||
#define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U
|
||||
#define LP_TIMER_SOC_WAKEUP_INT_ST_S 31
|
||||
|
||||
/** RTC_TIMER_INT_ENA_REG register
|
||||
/** LP_TIMER_INT_ENA_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_INT_ENA_REG (DR_REG_RTC_TIMER_BASE + 0x30)
|
||||
/** RTC_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0;
|
||||
#define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30)
|
||||
/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_OVERFLOW_ENA (BIT(30))
|
||||
#define RTC_TIMER_OVERFLOW_ENA_M (RTC_TIMER_OVERFLOW_ENA_V << RTC_TIMER_OVERFLOW_ENA_S)
|
||||
#define RTC_TIMER_OVERFLOW_ENA_V 0x00000001U
|
||||
#define RTC_TIMER_OVERFLOW_ENA_S 30
|
||||
/** RTC_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0;
|
||||
#define LP_TIMER_OVERFLOW_ENA (BIT(30))
|
||||
#define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S)
|
||||
#define LP_TIMER_OVERFLOW_ENA_V 0x00000001U
|
||||
#define LP_TIMER_OVERFLOW_ENA_S 30
|
||||
/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_SOC_WAKEUP_INT_ENA (BIT(31))
|
||||
#define RTC_TIMER_SOC_WAKEUP_INT_ENA_M (RTC_TIMER_SOC_WAKEUP_INT_ENA_V << RTC_TIMER_SOC_WAKEUP_INT_ENA_S)
|
||||
#define RTC_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U
|
||||
#define RTC_TIMER_SOC_WAKEUP_INT_ENA_S 31
|
||||
#define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31))
|
||||
#define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S)
|
||||
#define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U
|
||||
#define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31
|
||||
|
||||
/** RTC_TIMER_INT_CLR_REG register
|
||||
/** LP_TIMER_INT_CLR_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_INT_CLR_REG (DR_REG_RTC_TIMER_BASE + 0x34)
|
||||
/** RTC_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0;
|
||||
#define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34)
|
||||
/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_OVERFLOW_CLR (BIT(30))
|
||||
#define RTC_TIMER_OVERFLOW_CLR_M (RTC_TIMER_OVERFLOW_CLR_V << RTC_TIMER_OVERFLOW_CLR_S)
|
||||
#define RTC_TIMER_OVERFLOW_CLR_V 0x00000001U
|
||||
#define RTC_TIMER_OVERFLOW_CLR_S 30
|
||||
/** RTC_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0;
|
||||
#define LP_TIMER_OVERFLOW_CLR (BIT(30))
|
||||
#define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S)
|
||||
#define LP_TIMER_OVERFLOW_CLR_V 0x00000001U
|
||||
#define LP_TIMER_OVERFLOW_CLR_S 30
|
||||
/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_SOC_WAKEUP_INT_CLR (BIT(31))
|
||||
#define RTC_TIMER_SOC_WAKEUP_INT_CLR_M (RTC_TIMER_SOC_WAKEUP_INT_CLR_V << RTC_TIMER_SOC_WAKEUP_INT_CLR_S)
|
||||
#define RTC_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U
|
||||
#define RTC_TIMER_SOC_WAKEUP_INT_CLR_S 31
|
||||
#define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31))
|
||||
#define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S)
|
||||
#define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U
|
||||
#define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31
|
||||
|
||||
/** RTC_TIMER_LP_INT_RAW_REG register
|
||||
/** LP_TIMER_LP_INT_RAW_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_LP_INT_RAW_REG (DR_REG_RTC_TIMER_BASE + 0x38)
|
||||
/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
|
||||
#define LP_TIMER_LP_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x38)
|
||||
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30))
|
||||
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S)
|
||||
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U
|
||||
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30
|
||||
/** RTC_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
|
||||
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30))
|
||||
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S)
|
||||
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U
|
||||
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30
|
||||
/** LP_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31))
|
||||
#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_M (RTC_TIMER_MAIN_TIMER_LP_INT_RAW_V << RTC_TIMER_MAIN_TIMER_LP_INT_RAW_S)
|
||||
#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U
|
||||
#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_S 31
|
||||
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31))
|
||||
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_LP_INT_RAW_S)
|
||||
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U
|
||||
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_S 31
|
||||
|
||||
/** RTC_TIMER_LP_INT_ST_REG register
|
||||
/** LP_TIMER_LP_INT_ST_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_LP_INT_ST_REG (DR_REG_RTC_TIMER_BASE + 0x3c)
|
||||
/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0;
|
||||
#define LP_TIMER_LP_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x3c)
|
||||
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30))
|
||||
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S)
|
||||
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U
|
||||
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30
|
||||
/** RTC_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0;
|
||||
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30))
|
||||
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S)
|
||||
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U
|
||||
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30
|
||||
/** LP_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31))
|
||||
#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_M (RTC_TIMER_MAIN_TIMER_LP_INT_ST_V << RTC_TIMER_MAIN_TIMER_LP_INT_ST_S)
|
||||
#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U
|
||||
#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_S 31
|
||||
#define LP_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31))
|
||||
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_LP_INT_ST_S)
|
||||
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U
|
||||
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_S 31
|
||||
|
||||
/** RTC_TIMER_LP_INT_ENA_REG register
|
||||
/** LP_TIMER_LP_INT_ENA_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_LP_INT_ENA_REG (DR_REG_RTC_TIMER_BASE + 0x40)
|
||||
/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0;
|
||||
#define LP_TIMER_LP_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x40)
|
||||
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30))
|
||||
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S)
|
||||
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U
|
||||
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30
|
||||
/** RTC_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
|
||||
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30))
|
||||
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S)
|
||||
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U
|
||||
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30
|
||||
/** LP_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31))
|
||||
#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_M (RTC_TIMER_MAIN_TIMER_LP_INT_ENA_V << RTC_TIMER_MAIN_TIMER_LP_INT_ENA_S)
|
||||
#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U
|
||||
#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_S 31
|
||||
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31))
|
||||
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_LP_INT_ENA_S)
|
||||
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U
|
||||
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_S 31
|
||||
|
||||
/** RTC_TIMER_LP_INT_CLR_REG register
|
||||
/** LP_TIMER_LP_INT_CLR_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_LP_INT_CLR_REG (DR_REG_RTC_TIMER_BASE + 0x44)
|
||||
/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0;
|
||||
#define LP_TIMER_LP_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x44)
|
||||
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30))
|
||||
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S)
|
||||
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U
|
||||
#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30
|
||||
/** RTC_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0;
|
||||
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30))
|
||||
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S)
|
||||
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U
|
||||
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30
|
||||
/** LP_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31))
|
||||
#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_M (RTC_TIMER_MAIN_TIMER_LP_INT_CLR_V << RTC_TIMER_MAIN_TIMER_LP_INT_CLR_S)
|
||||
#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U
|
||||
#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_S 31
|
||||
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31))
|
||||
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_LP_INT_CLR_S)
|
||||
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U
|
||||
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_S 31
|
||||
|
||||
/** RTC_TIMER_DATE_REG register
|
||||
/** LP_TIMER_DATE_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_DATE_REG (DR_REG_RTC_TIMER_BASE + 0x3fc)
|
||||
/** RTC_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976;
|
||||
#define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc)
|
||||
/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_DATE 0x7FFFFFFFU
|
||||
#define RTC_TIMER_DATE_M (RTC_TIMER_DATE_V << RTC_TIMER_DATE_S)
|
||||
#define RTC_TIMER_DATE_V 0x7FFFFFFFU
|
||||
#define RTC_TIMER_DATE_S 0
|
||||
/** RTC_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
#define LP_TIMER_DATE 0x7FFFFFFFU
|
||||
#define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S)
|
||||
#define LP_TIMER_DATE_V 0x7FFFFFFFU
|
||||
#define LP_TIMER_DATE_S 0
|
||||
/** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_TIMER_CLK_EN (BIT(31))
|
||||
#define RTC_TIMER_CLK_EN_M (RTC_TIMER_CLK_EN_V << RTC_TIMER_CLK_EN_S)
|
||||
#define RTC_TIMER_CLK_EN_V 0x00000001U
|
||||
#define RTC_TIMER_CLK_EN_S 31
|
||||
#define LP_TIMER_CLK_EN (BIT(31))
|
||||
#define LP_TIMER_CLK_EN_M (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S)
|
||||
#define LP_TIMER_CLK_EN_V 0x00000001U
|
||||
#define LP_TIMER_CLK_EN_S 31
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -5,6 +5,7 @@
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include "pmu_reg.h"
|
||||
#ifdef __cplusplus
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user