2d344bc185
Merge branch 'fix/fix_mspi_reset_order_v5.5' into 'release/v5.5'
...
fix(esp_system): fix c61 mspi core/axi reset order (v5.5)
See merge request espressif/esp-idf!44097
2025-12-30 10:20:56 +08:00
08f5f0d66b
fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption
...
This reverts commit 7145fc9558752a6532072bb272e94389807eda51.
2025-12-24 02:31:57 +08:00
187f43a3bb
Revert "fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption"
...
This reverts commit 3c5d2e6b5843da853fb81067eb2bd287f7fbd735.
2025-12-17 03:33:30 +08:00
faf6cc4f84
feat(spi_flash): implement dynamic CPU frequency switching workaround for encrypted writes
...
This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency
normally, while automatically reducing CPU frequency during encrypted flash writes to
ensure correct operation. The frequency limit is chip revision dependent:
- v1.2 and above: limited to 160MHz during encrypted writes
- v1.0 and below: limited to 80MHz during encrypted writes
Key implementation details:
- Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called
- Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer
- Works with both PM enabled and disabled configurations
- Frequency is automatically restored after encrypted write completes
- For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when
CPU frequency is reduced to 80MHz
- SPI1 timing registers are configured during frequency switching since encrypted writes
use SPI1 and must work correctly at reduced CPU frequencies
Code improvements:
- Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks
- Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of
hardcoded macros
- Add comprehensive test cases covering various PM configurations and edge cases
This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance
while maintaining reliable encrypted flash write functionality.
2025-12-17 03:33:29 +08:00
3146ab33ab
fix(esp_system): fix c61 mspi core/axi reset order
2025-12-10 12:16:33 +08:00
83acb84d8a
bugfix: clear regdma status when restart
2025-12-02 13:34:21 +08:00
104145de7f
fix(esp_system): fix mspi write stuck after cpu/digital reset on c5/c61
2025-12-02 13:34:17 +08:00
3228998165
fix(uart): fix some wdt get triggered due to uart sclk not exist on C5
...
Interrupt wdt would get triggered on uart_driver_install if uart driver was deleted before
Closes https://github.com/espressif/esp-idf/issues/17779
RTC wdt would get triggered on esp_restart if uart driver was deleted before
2025-11-24 11:41:26 +08:00
fb20e147d5
fix(console): release default console UART pins if console is switched in bootloader
...
Also print out console UART pin number in app cpu_startup stage
Closes https://github.com/espressif/esp-idf/issues/16764
Closes https://github.com/espressif/esp-idf/issues/17459
2025-11-21 22:11:25 +08:00
29e9e7ebee
Merge branch 'feat/support_p4_unicore_auto_clock_gating_v5.5' into 'release/v5.5'
...
feat(esp_hw_support): support unicore auto clock gating for esp32p4 rev3+ (v5.5)
See merge request espressif/esp-idf!43370
2025-11-17 19:07:39 +08:00
376f396e20
Merge branch 'bugfix/esp32c5_encrypted_flash_write_v5.5' into 'release/v5.5'
...
fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption (v5.5)
See merge request espressif/esp-idf!43326
2025-11-17 15:02:40 +08:00
01b9a1dd18
Merge branch 'fix/fix_xtal32k_power_breaks_adc_v5.5' into 'release/v5.5'
...
fix(esp_system): fix XTAL32K power breaks ADC function on 32k XTAL clock pin (v5.5)
See merge request espressif/esp-idf!43297
2025-11-14 15:31:04 +08:00
9e06691c52
feat(esp_hw_support): support unicore auto clock gating for esp32p4 rev3+
2025-11-14 14:08:52 +08:00
3fd00b4d80
fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption
...
Encrypted flash write operation sometimes result in random corruption in
certain bytes. Root cause points to sudden current surge due to involvement of
encryption block overwhelming LDO supply. More details will be provided
in the ESP32-C5 SoC Errata document.
This fix limits the CPU clock to 160MHz for flash encryption enabled
case. Failing encrypted flash write tests could successfully pass in
this configuration. Going ahead, a dynamic clock adjustment in flash
driver will be considered to mitigate this issue.
2025-11-13 13:26:06 +05:30
7adb3a5a2e
fix(esp_system): fix XTAL32K power breaks ADC function on 32k XTAL clock pin
2025-11-13 14:17:34 +08:00
ea6ed237d2
fix(clk): 400MHz CPU should still be selectable on ESP32-P4 less than rev3
2025-11-13 11:36:22 +08:00
24a36e5c01
Merge branch 'fix/cdcacm-callback-placement_v5.5' into 'release/v5.5'
...
fix(esp_vfs_console): Update placement of cdcacm_xx_cb when ETS print enabled (v5.5)
See merge request espressif/esp-idf!41330
2025-10-31 07:10:47 +08:00
96aef65a2d
fix(esp_system): fix ext 32k io revoking breaks sleep io holding
2025-10-28 18:54:20 +08:00
2f63581f51
Merge branch 'bugfix/usb_dp_pin_unusable_after_cpu_reset_v5.5' into 'release/v5.5'
...
fix(gpio): fix USB DP pin unusable after CPU reset for S3/C3 (v5.5)
See merge request espressif/esp-idf!42800
2025-10-28 10:00:46 +08:00
a0de5f7387
Merge branch 'feature/esp32p4_eco5_support_v5.5' into 'release/v5.5'
...
feat(gpio/ledc/uart/2ddma/ppa): ESP32P4 ECO5 related updates (v5.5)
See merge request espressif/esp-idf!42816
2025-10-27 15:50:42 +08:00
5a4ff6bb6a
dma: fixed issue that DMA are not reset when CPU reset
...
When DMA keep writing the memory, some data may be corrupted after reset. For example, the stack of bootloader may be overwritten and failed to boot until a higher scope of reset (Core).
2025-10-23 21:39:09 +08:00
912c24eb09
fix(gpio): fix USB DP pin unusable after CPU reset for S3/C3
...
Closes https://github.com/espressif/esp-idf/issues/17488
2025-10-23 15:07:25 +08:00
e69eeb7355
feat(2ddma): ESP32P4 ECO5 2DDMA related updates
...
Added one more pair of 2DDMA channels
Priority bit width increased corespondingly
Added three new CSC modes for RX channel 0
2025-10-22 20:05:59 +08:00
e71732139a
fix(clk): allow P4 CPU clk freq can auto switch between 360/400MHz according to revision
2025-10-22 20:05:59 +08:00
438046d809
Merge branch 'fix/fix_esp32c5_xtal32k_clock_lost_in_sleep_v5.5' into 'release/v5.5'
...
fix(esp_system): manage slow clock sleep pd in select_rtc_slow_clk (v5.5)
See merge request espressif/esp-idf!42494
2025-10-20 14:36:47 +08:00
ea36c4f609
Merge branch 'feature/esp_tee_c5_v5.5' into 'release/v5.5'
...
feat(esp_tee): Initial support for ESP32-C5 and related changes (v5.5)
See merge request espressif/esp-idf!42357
2025-10-16 09:39:23 +05:30
508a659001
feat(esp_tee): Support for ESP32-C5 - the rest of the components
2025-10-14 10:12:11 +05:30
e6d4eec507
feat(p4): p4 rev3 real chip support
2025-10-13 15:25:23 +08:00
3d3b287672
fix(esp_system): manage slow clock sleep pd in select_rtc_slow_clk
2025-10-10 20:04:58 +08:00
69c31289ad
fix(clk): clear force_on reg for cache
2025-10-09 13:19:46 +08:00
175e885555
fix(esp_vfs_console): Update placement of cdcacm_xx_cb when ETS print enabled
2025-10-07 08:26:54 +02:00
dafdf1205d
Merge branch 'feat/secure_boot_ecdsa_p384_v5.5' into 'release/v5.5'
...
Support Secure Boot using ECDSA-P384 curve (v5.5)
See merge request espressif/esp-idf!40822
2025-07-31 21:24:55 +08:00
92a09ce7f0
Merge branch 'fix/fix_submode_assert_in_slowck_changed_ota_v5.5' into 'release/v5.5'
...
fix(esp_hw_support): fix assert when changing 8MD256 RTC slow clock source during OTA (v5.5)
See merge request espressif/esp-idf!40820
2025-07-30 10:46:31 +08:00
12393745c2
fix(esp_system): Remove redundant crypto clock source selection
2025-07-25 14:43:56 +05:30
ddbf8391d9
fix(esp_hw_support): enable ESP_SLEEP_RTC_FAST_USE_XTAL_MODE only once in RTC_FAST selection
2025-07-25 16:49:16 +08:00
e72ea712e7
feat(esp_system): Adds Kconfigs to place code in IRAM
2025-07-24 00:34:58 +08:00
0291ab0dfb
Merge branch 'feature/support_chip912_pvt_auto_dbias_360m_backport_v5.5' into 'release/v5.5'
...
feat(esp_hw_support): use pvt to auto control digital ldo and rtc ldo for esp32p4_backport_v5.5
See merge request espressif/esp-idf!40676
2025-07-22 17:36:09 +08:00
e2d5f85804
Merge branch 'feat/call_start_in_flash_v5.5' into 'release/v5.5'
...
esp_system: move call_start_cpu* into flash to save IRAM (v5.5)
See merge request espressif/esp-idf!39926
2025-07-22 14:38:14 +08:00
3c39b32195
Chip/support esp32c61 v5.5
2025-07-22 12:21:36 +08:00
3d3731965c
feat(esp_hw_support): use pvt to auto control digital ldo and rtc ldo for esp32p4
2025-07-18 09:54:31 +08:00
c844ba4f7f
fix(esp_system): force enable uart0 sclk in esp_restart
2025-07-03 19:13:41 +08:00
e1faf670b2
feat(hw_support): move call_start_cpu0 into flash to save IRAM
2025-06-17 15:11:36 +08:00
2e7a9174fc
Merge branch 'feature/esp_tee_h2_v5.5' into 'release/v5.5'
...
feat(esp_tee): Support for ESP32-H2 (v5.5)
See merge request espressif/esp-idf!39311
2025-06-16 12:04:22 +05:30
59496b4927
fix(system_internal): Avoid the sec clock reset caused due to resetting all crypto peripherals
2025-05-26 11:40:51 +05:30
27496e47f0
feat(esp_tee): Support for ESP32-H2 - the rest of the components
2025-05-21 10:06:17 +05:30
5e6ecd81b5
refactor: move_ocode_to_pmu_init_c6_c5_c61 (v5.5)
2025-05-20 21:14:56 +08:00
46225a4026
feat(esp_psram): Add a new API to just detect and enable the PSRAM
...
- esp_psram_chip_init() just detects and does basic initialisations of PSRAM
- esp_psram_init() initialises and maps/loads the PSRAM pages
2025-04-29 11:48:27 +05:30
112a955111
Merge branch 'feature/h21_reset_reason' into 'master'
...
feat(system): updated reset reasons for H21
Closes IDF-11542
See merge request espressif/esp-idf!38774
2025-04-28 17:35:30 +08:00
298da837fd
feat(system): updated reset reasons for H21
2025-04-27 16:11:24 +08:00
b9d055dfda
Merge branch 'fix/multi_core_race_cond_in_panic_handler' into 'master'
...
fix(panic_handler): Prevent race condition in panic handler
Closes IDFCI-2802, IDFCI-2867, and IDFCI-2869
See merge request espressif/esp-idf!37958
2025-04-23 18:52:16 +08:00
Jiang Jiang Jian