336 lines
10 KiB
C
336 lines
10 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "sdkconfig.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "freertos/task.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "soc/rtc.h"
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#if defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32C3)
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#include "soc/rtc_cntl_reg.h"
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#include "soc/syscon_reg.h"
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#endif
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#include "soc/efuse_reg.h"
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#include "esp32-hal.h"
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#include "esp32-hal-cpu.h"
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#include "hal/timer_ll.h"
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#include "esp_private/systimer.h"
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#include "esp_system.h"
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#ifdef ESP_IDF_VERSION_MAJOR // IDF 4+
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#if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4
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#include "xtensa_timer.h"
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#include "esp32/rom/rtc.h"
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static const char *clock_source_names[] = {"XTAL", "PLL", "8.5M", "APLL"};
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "xtensa_timer.h"
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#include "esp32s2/rom/rtc.h"
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static const char *clock_source_names[] = {"XTAL", "PLL", "8.5M", "APLL"};
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "xtensa_timer.h"
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#include "esp32s3/rom/rtc.h"
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static const char *clock_source_names[] = {"XTAL", "PLL", "17.5M"};
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#elif CONFIG_IDF_TARGET_ESP32C2
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#include "esp32c2/rom/rtc.h"
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static const char *clock_source_names[] = {"XTAL", "PLL", "17.5M"};
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rom/rtc.h"
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static const char *clock_source_names[] = {"XTAL", "PLL", "17.5M"};
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#elif CONFIG_IDF_TARGET_ESP32C6
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#include "esp32c6/rom/rtc.h"
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static const char *clock_source_names[] = {"XTAL", "PLL", "17.5M"};
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#elif CONFIG_IDF_TARGET_ESP32H2
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#include "esp32h2/rom/rtc.h"
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static const char *clock_source_names[] = {"XTAL", "PLL", "8.5M", "FLASH_PLL"};
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#elif CONFIG_IDF_TARGET_ESP32P4
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#include "esp32p4/rom/rtc.h"
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static const char *clock_source_names[] = {"XTAL", "CPLL", "17.5M"};
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#elif CONFIG_IDF_TARGET_ESP32C5
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#include "esp32c5/rom/rtc.h"
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static const char *clock_source_names[] = {"XTAL", "17.5M", "PLL_F160M", "PLL_F240M"};
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#elif CONFIG_IDF_TARGET_ESP32C61
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#include "esp32c61/rom/rtc.h"
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static const char *clock_source_names[] = {"XTAL", "17.5M", "PLL_F160M"};
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#else
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#error Target CONFIG_IDF_TARGET is not supported
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#endif
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#else // ESP32 Before IDF 4.0
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#include "rom/rtc.h"
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#endif
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typedef struct apb_change_cb_s {
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struct apb_change_cb_s *prev;
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struct apb_change_cb_s *next;
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void *arg;
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apb_change_cb_t cb;
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} apb_change_t;
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static apb_change_t *apb_change_callbacks = NULL;
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static SemaphoreHandle_t apb_change_lock = NULL;
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static void initApbChangeCallback() {
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static volatile bool initialized = false;
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if (!initialized) {
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initialized = true;
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apb_change_lock = xSemaphoreCreateMutex();
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if (!apb_change_lock) {
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initialized = false;
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}
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}
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}
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static void triggerApbChangeCallback(apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb) {
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initApbChangeCallback();
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xSemaphoreTake(apb_change_lock, portMAX_DELAY);
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apb_change_t *r = apb_change_callbacks;
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if (r != NULL) {
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if (ev_type == APB_BEFORE_CHANGE) {
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while (r != NULL) {
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r->cb(r->arg, ev_type, old_apb, new_apb);
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r = r->next;
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}
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} else { // run backwards through chain
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while (r->next != NULL) {
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r = r->next; // find first added
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}
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while (r != NULL) {
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r->cb(r->arg, ev_type, old_apb, new_apb);
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r = r->prev;
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}
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}
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}
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xSemaphoreGive(apb_change_lock);
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}
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bool addApbChangeCallback(void *arg, apb_change_cb_t cb) {
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initApbChangeCallback();
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apb_change_t *c = (apb_change_t *)malloc(sizeof(apb_change_t));
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if (!c) {
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log_e("Callback Object Malloc Failed");
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return false;
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}
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c->next = NULL;
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c->prev = NULL;
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c->arg = arg;
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c->cb = cb;
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xSemaphoreTake(apb_change_lock, portMAX_DELAY);
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if (apb_change_callbacks == NULL) {
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apb_change_callbacks = c;
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} else {
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apb_change_t *r = apb_change_callbacks;
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// look for duplicate callbacks
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while ((r != NULL) && !((r->cb == cb) && (r->arg == arg))) {
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r = r->next;
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}
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if (r) {
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log_e("duplicate func=%8p arg=%8p", c->cb, c->arg);
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free(c);
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xSemaphoreGive(apb_change_lock);
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return false;
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} else {
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c->next = apb_change_callbacks;
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apb_change_callbacks->prev = c;
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apb_change_callbacks = c;
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}
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}
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xSemaphoreGive(apb_change_lock);
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return true;
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}
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bool removeApbChangeCallback(void *arg, apb_change_cb_t cb) {
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initApbChangeCallback();
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xSemaphoreTake(apb_change_lock, portMAX_DELAY);
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apb_change_t *r = apb_change_callbacks;
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// look for matching callback
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while ((r != NULL) && !((r->cb == cb) && (r->arg == arg))) {
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r = r->next;
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}
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if (r == NULL) {
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log_e("not found func=%8p arg=%8p", cb, arg);
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xSemaphoreGive(apb_change_lock);
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return false;
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} else {
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// patch links
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if (r->prev) {
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r->prev->next = r->next;
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} else { // this is first link
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apb_change_callbacks = r->next;
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}
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if (r->next) {
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r->next->prev = r->prev;
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}
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free(r);
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}
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xSemaphoreGive(apb_change_lock);
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return true;
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}
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static uint32_t calculateApb(rtc_cpu_freq_config_t *conf) {
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
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if (conf->freq_mhz >= 80) {
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return 80 * MHZ;
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}
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return (conf->source_freq_mhz * MHZ) / conf->div;
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#else
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return APB_CLK_FREQ;
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#endif
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}
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#if defined(CONFIG_IDF_TARGET_ESP32) && !defined(LACT_MODULE) && !defined(LACT_TICKS_PER_US)
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void esp_timer_impl_update_apb_freq(uint32_t apb_ticks_per_us); //private in IDF
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#endif
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const char *getClockSourceName(uint8_t source) {
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if (source < SOC_CPU_CLK_SRC_INVALID) {
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return clock_source_names[source];
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}
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return "Invalid";
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}
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const char *getSupportedCpuFrequencyMhz(uint8_t xtal) {
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char *supported_frequencies = (char *)calloc(256, sizeof(char));
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int pos = 0;
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#if TARGET_CPU_FREQ_MAX_400
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#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_REV_MIN_FULL < 300
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pos += snprintf(supported_frequencies + pos, 256 - pos, "360");
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#else
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pos += snprintf(supported_frequencies + pos, 256 - pos, "400");
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#endif
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#elif TARGET_CPU_FREQ_MAX_240
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#if CONFIG_IDF_TARGET_ESP32
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if (!REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED) || !REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW)) {
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pos += snprintf(supported_frequencies + pos, 256 - pos, "160, 80");
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} else
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#endif
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{
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pos += snprintf(supported_frequencies + pos, 256 - pos, "240, 160, 80");
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}
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#elif TARGET_CPU_FREQ_MAX_160
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pos += snprintf(supported_frequencies + pos, 256 - pos, "160, 120, 80");
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#elif TARGET_CPU_FREQ_MAX_120
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pos += snprintf(supported_frequencies + pos, 256 - pos, "120, 80");
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#elif TARGET_CPU_FREQ_MAX_96
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pos += snprintf(supported_frequencies + pos, 256 - pos, "96, 64, 48");
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#else
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free(supported_frequencies);
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return "Unknown";
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#endif
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// Append xtal and its dividers only if xtal is nonzero
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if (xtal != 0) {
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// We'll show as: , <xtal>, <xtal/2>[, <xtal/4>] MHz
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pos += snprintf(supported_frequencies + pos, 256 - pos, ", %u, %u", xtal, xtal / 2);
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#if CONFIG_IDF_TARGET_ESP32
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// Only append xtal/4 if it's > 0 and meaningful for higher-frequency chips (e.g., ESP32 40MHz/4=10)
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if (xtal >= RTC_XTAL_FREQ_40M) {
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pos += snprintf(supported_frequencies + pos, 256 - pos, ", %u", xtal / 4);
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}
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#endif
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}
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pos += snprintf(supported_frequencies + pos, 256 - pos, " MHz");
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return supported_frequencies;
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}
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bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz) {
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rtc_cpu_freq_config_t conf, cconf;
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uint32_t capb, apb;
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[[maybe_unused]]
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uint8_t xtal = 0;
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// ===== Get XTAL Frequency and validate input =====
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#if TARGET_HAS_XTAL_FREQ
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xtal = (uint8_t)rtc_clk_xtal_freq_get();
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#endif
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// ===== Get current configuration and check if change is needed =====
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rtc_clk_cpu_freq_get_config(&cconf);
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if (cconf.freq_mhz == cpu_freq_mhz) {
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return true; // Frequency already set
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}
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// ===== Get configuration for new frequency =====
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if (!rtc_clk_cpu_freq_mhz_to_config(cpu_freq_mhz, &conf)) {
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log_e("CPU clock could not be set to %u MHz. Supported frequencies: %s", cpu_freq_mhz, getSupportedCpuFrequencyMhz(xtal));
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return false;
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}
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// ===== Calculate APB frequencies =====
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capb = calculateApb(&cconf);
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apb = calculateApb(&conf);
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// ===== Apply frequency change =====
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if (apb_change_callbacks) {
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triggerApbChangeCallback(APB_BEFORE_CHANGE, capb, apb);
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}
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rtc_clk_cpu_freq_set_config_fast(&conf);
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// Update APB frequency for targets with dynamic APB
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#if TARGET_HAS_DYNAMIC_APB
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if (capb != apb) {
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// Update REF_TICK (uncomment if REF_TICK is different than 1MHz)
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// if (conf.freq_mhz < 80) {
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// ESP_REG(APB_CTRL_XTAL_TICK_CONF_REG) = conf.freq_mhz / (REF_CLK_FREQ / MHZ) - 1;
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// }
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rtc_clk_apb_freq_update(apb);
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// ESP32-specific: Update esp_timer divisor
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#if CONFIG_IDF_TARGET_ESP32
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#if defined(LACT_MODULE) && defined(LACT_TICKS_PER_US)
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timer_ll_set_lact_clock_prescale(TIMER_LL_GET_HW(LACT_MODULE), apb / MHZ / LACT_TICKS_PER_US);
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#else
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esp_timer_impl_update_apb_freq(apb / MHZ);
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#endif
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#endif
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}
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#endif
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// Update FreeRTOS Tick Divisor for Xtensa targets
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#if TARGET_HAS_XTENSA_TICK
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uint32_t fcpu = (conf.freq_mhz >= 80) ? (conf.freq_mhz * MHZ) : (apb);
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_xt_tick_divisor = fcpu / XT_TICK_PER_SEC;
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#endif
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if (apb_change_callbacks) {
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triggerApbChangeCallback(APB_AFTER_CHANGE, capb, apb);
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}
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// ===== Debug logging =====
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log_d("%s: %u / %u = %u Mhz, APB: %u Hz", getClockSourceName(conf.source), conf.source_freq_mhz, conf.div, conf.freq_mhz, apb);
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return true;
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}
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uint32_t getCpuFrequencyMhz() {
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rtc_cpu_freq_config_t conf;
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rtc_clk_cpu_freq_get_config(&conf);
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return conf.freq_mhz;
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}
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uint32_t getXtalFrequencyMhz() {
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return rtc_clk_xtal_freq_get();
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}
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uint32_t getApbFrequency() {
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rtc_cpu_freq_config_t conf;
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rtc_clk_cpu_freq_get_config(&conf);
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return calculateApb(&conf);
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}
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