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fix(parlio_rx): fixed opposite sample edge issue

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Closes https://github.com/espressif/esp-idf/issues/18012
This commit is contained in:
laokaiyao
2025-12-30 13:21:40 +08:00
committed by Kevin (Lao Kaiyao)
parent c4df42abab
commit 37ee778e9a
4 changed files with 19 additions and 13 deletions
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components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c
+1 -1
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@@ -391,7 +391,7 @@ TEST_CASE("parallel_rx_unit_pulse_delimiter_test_via_i2s", "[parlio_rx]")
{
parlio_rx_pulse_delimiter_config_t pls_deli_cfg = {
.valid_sig_line_id = TEST_VALID_SIG,
.sample_edge = PARLIO_SAMPLE_EDGE_NEG,
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB,
.eof_data_len = TEST_EOF_DATA_LEN,
.timeout_ticks = 0,
components/hal/esp32c5/include/hal/parlio_ll.h
+6 -4
View File
@@ -255,8 +255,9 @@ static inline void parlio_ll_rx_start_soft_recv(parl_io_dev_t *dev, bool en)
__attribute__((always_inline))
static inline void parlio_ll_rx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
{
dev->rx_clk_cfg.rx_clk_i_inv = edge;
dev->rx_clk_cfg.rx_clk_o_inv = edge;
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->rx_clk_cfg.rx_clk_i_inv = invert;
dev->rx_clk_cfg.rx_clk_o_inv = invert;
}
/**
@@ -559,8 +560,9 @@ static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t sta
*/
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
{
dev->tx_clk_cfg.tx_clk_i_inv = edge;
dev->tx_clk_cfg.tx_clk_o_inv = edge;
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->tx_clk_cfg.tx_clk_i_inv = invert;
dev->tx_clk_cfg.tx_clk_o_inv = invert;
}
/**
components/hal/esp32h2/include/hal/parlio_ll.h
+6 -4
View File
@@ -258,8 +258,9 @@ static inline void parlio_ll_rx_start_soft_recv(parl_io_dev_t *dev, bool en)
__attribute__((always_inline))
static inline void parlio_ll_rx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
{
dev->rx_clk_cfg.rx_clk_i_inv = edge;
dev->rx_clk_cfg.rx_clk_o_inv = edge;
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->rx_clk_cfg.rx_clk_i_inv = invert;
dev->rx_clk_cfg.rx_clk_o_inv = invert;
}
/**
@@ -567,8 +568,9 @@ static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t sta
*/
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
{
dev->tx_clk_cfg.tx_clk_i_inv = edge;
dev->tx_clk_cfg.tx_clk_o_inv = edge;
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->tx_clk_cfg.tx_clk_i_inv = invert;
dev->tx_clk_cfg.tx_clk_o_inv = invert;
}
/**
components/hal/esp32p4/include/hal/parlio_ll.h
+6 -4
View File
@@ -295,8 +295,9 @@ static inline void parlio_ll_rx_start_soft_recv(parl_io_dev_t *dev, bool en)
__attribute__((always_inline))
static inline void parlio_ll_rx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
{
dev->rx_clk_cfg.rx_clk_i_inv = edge;
dev->rx_clk_cfg.rx_clk_o_inv = edge;
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->rx_clk_cfg.rx_clk_i_inv = invert;
dev->rx_clk_cfg.rx_clk_o_inv = invert;
}
/**
@@ -592,8 +593,9 @@ static inline void parlio_ll_tx_start(parl_io_dev_t *dev, bool en)
*/
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
{
dev->tx_clk_cfg.tx_clk_i_inv = edge;
dev->tx_clk_cfg.tx_clk_o_inv = edge;
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->tx_clk_cfg.tx_clk_i_inv = invert;
dev->tx_clk_cfg.tx_clk_o_inv = invert;
}
/**