fix: fix DCDC patch on P4 rev3.1

components/bootloader_support/src/flash_encrypt.c

@@ -210,7 +210,6 @@ void esp_flash_encryption_set_release_mode(void)
 #endif // CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED
 #endif // !CONFIG_IDF_TARGET_ESP32
 
-#if !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_REV_MIN_FULL < 300)
 #if SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
     if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) {
         uint8_t xts_pseudo_level = 0;
@@ -222,7 +221,6 @@ void esp_flash_encryption_set_release_mode(void)
         }
     }
 #endif
-#endif
 #ifdef CONFIG_IDF_TARGET_ESP32
     esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_DIS_CACHE);
 #else
@@ -484,7 +482,6 @@ bool esp_flash_encryption_cfg_verify_release_mode(void)
     }
     result &= secure;
 
-#if !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_REV_MIN_FULL < 300)
 #if SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
     if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) {
         uint8_t xts_pseudo_level = 0;
@@ -494,7 +491,6 @@ bool esp_flash_encryption_cfg_verify_release_mode(void)
             ESP_LOGW(TAG, "Not enabled XTS-AES pseudo rounds function (set XTS_DPA_PSEUDO_LEVEL->1 or more)");
         }
     }
-#endif
 #endif
     return result;
 }

components/esp_hw_support/lowpower/port/esp32p4/Kconfig.p4_rev3_mspi_workaround

@@ -1,10 +1,10 @@
 config P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
     bool
     depends on IDF_TARGET_ESP32P4
-    default y if !ESP32P4_SELECTS_REV_LESS_V3  # Fixed since REV3.1
+    default y if ESP32P4_REV_MIN_300  # Fixed since REV3.1
 
 config P4_REV3_MSPI_WORKAROUND_SIZE
     hex
     depends on IDF_TARGET_ESP32P4
-    default 0x100 if !ESP32P4_SELECTS_REV_LESS_V3
+    default 0x100 if ESP32P4_REV_MIN_300
     default 0

components/esp_hw_support/port/esp32p4/rtc_clk_init.c

@@ -68,10 +68,9 @@ void rtc_clk_init(rtc_clk_config_t cfg)
         hp_dcmvset = pvt_hp_dcmvset;
     }
     // Switch to DCDC
-#if (CONFIG_ESP32P4_REV_MIN_FULL >= 300)
+#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
     unsigned chip_version = efuse_hal_chip_revision();
-    if (ESP_CHIP_REV_BETWEEN(chip_version, 300, 301)) {
-        // This workaround is only needed for P4 rev3.1
+    if (ESP_CHIP_REV_ABOVE(chip_version, 301)) {
         SET_PERI_REG_MASK(PMU_DCM_CTRL_REG, PMU_DCDC_FB_RES_FORCE_PD);
     }
 #endif
@@ -80,9 +79,8 @@ void rtc_clk_init(rtc_clk_config_t cfg)
     pmu_ll_hp_set_dcm_vset(&PMU, PMU_MODE_HP_ACTIVE, hp_dcmvset);
     SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // Hand over control of dbias to pmu
     esp_rom_delay_us(1000);
-#if (CONFIG_ESP32P4_REV_MIN_FULL >= 300)
-    if (ESP_CHIP_REV_BETWEEN(chip_version, 300, 301)) {
-        // This workaround is only needed for P4 rev3.1
+#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
+    if (ESP_CHIP_REV_ABOVE(chip_version, 301)) {
         REG_SET_FIELD(LP_SYSTEM_REG_SYS_CTRL_REG, LP_SYSTEM_REG_LP_FIB_SEL, 0xEF);// lp_fib_sel bit4 set to 0: select dig_fib_reg instead of ana_fib_reg
         CLEAR_PERI_REG_MASK(PMU_DCM_CTRL_REG, PMU_DCDC_FB_RES_FORCE_PD);
         esp_rom_delay_us(10);