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Merge branch 'espressif:release/v5.5' into release/v5.5

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This commit is contained in:
Jason2866
2026-02-05 17:58:31 +01:00
committed by GitHub
parent 0b95311073 bc7a18fe63
commit 9d76f23148
146 changed files with 5863 additions and 451 deletions
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.gitlab/ci/docs.yml
+2 -2
View File
@@ -118,7 +118,7 @@ build_docs_html_full:
paths:
- docs/_build/*/*/*.txt
- docs/_build/*/*/html/*
expire_in: 12 hrs
expire_in: 4 days
variables:
DOC_BUILDERS: "html"
@@ -131,7 +131,7 @@ build_docs_html_partial:
paths:
- docs/_build/*/*/*.txt
- docs/_build/*/*/html/*
expire_in: 12 hrs
expire_in: 4 days
variables:
DOC_BUILDERS: "html"
parallel:
.pre-commit-config.yaml
+1 -1
View File
@@ -137,7 +137,7 @@ repos:
name: Check tools dir files patterns
entry: tools/ci/check_tools_files_patterns.py
language: python
files: '^tools/.+'
files: '^(tools/.+|.gitlab/ci/rules\.yml)'
additional_dependencies:
- PyYAML == 5.3.1
pass_filenames: false
components/bootloader/subproject/main/bootloader_start.c
+2
View File
@@ -4,8 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
#include "sdkconfig.h"
#include "esp_log.h"
#include "esp_rom_sys.h"
#include "esp_rom_caps.h"
#include "bootloader_init.h"
#include "bootloader_utility.h"
#include "bootloader_common.h"
components/bootloader_support/src/bootloader_common_loader.c
+9 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,6 +12,9 @@
#include "esp_rom_crc.h"
#include "esp_rom_gpio.h"
#include "esp_flash_partitions.h"
#if CONFIG_SECURE_BOOT
#include "esp_secure_boot.h"
#endif
#include "bootloader_flash.h"
#include "bootloader_common.h"
#include "soc/gpio_periph.h"
@@ -274,7 +277,12 @@ rtc_retain_mem_t* bootloader_common_get_rtc_retain_mem(void)
#define RETAIN_MEM_SIZE ALIGN_UP(sizeof(rtc_retain_mem_t), 8)
#define RTC_RETAIN_MEM_ADDR (SOC_RTC_DRAM_HIGH - RETAIN_MEM_SIZE)
#endif //ESP_ROM_HAS_LP_ROM
#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
static rtc_retain_mem_t *const s_bootloader_retain_mem = (rtc_retain_mem_t *)RTC_RETAIN_MEM_ADDR - ESP_SECURE_BOOT_DIGEST_LEN;
#else
static rtc_retain_mem_t *const s_bootloader_retain_mem = (rtc_retain_mem_t *)RTC_RETAIN_MEM_ADDR;
#endif
return s_bootloader_retain_mem;
#else
static __attribute__((section(".bootloader_data_rtc_mem"))) rtc_retain_mem_t s_bootloader_retain_mem;
components/bootloader_support/src/bootloader_random_esp32c5.c
+5 -4
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,6 +8,7 @@
#include "hal/regi2c_ctrl_ll.h"
#include "hal/adc_ll.h"
#include "hal/adc_types.h"
#include "hal/rng_ll.h"
#include "esp_private/regi2c_ctrl.h"
#include "soc/lpperi_reg.h"
@@ -51,9 +52,9 @@ void bootloader_random_enable(void)
adc_ll_digi_set_trigger_interval(200);
adc_ll_digi_trigger_enable();
SET_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_SAMPLE_ENABLE);
REG_SET_FIELD(LPPERI_RNG_CFG_REG, LPPERI_RTC_TIMER_EN, 0x3);
SET_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_TIMER_EN);
rng_ll_enable_sample(true);
rng_ll_enable_rtc_timer(true);
rng_ll_enable_rng_timer(true);
}
void bootloader_random_disable(void)
components/bootloader_support/src/flash_encrypt.c
+4 -2
View File
@@ -210,6 +210,7 @@ void esp_flash_encryption_set_release_mode(void)
#endif // CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED
#endif // !CONFIG_IDF_TARGET_ESP32
#if !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_REV_MIN_FULL < 300)
#ifdef SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND
if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) {
uint8_t xts_pseudo_level = 0;
@@ -221,7 +222,7 @@ void esp_flash_encryption_set_release_mode(void)
}
}
#endif
#endif
#ifdef CONFIG_IDF_TARGET_ESP32
esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_DIS_CACHE);
#else
@@ -483,6 +484,7 @@ bool esp_flash_encryption_cfg_verify_release_mode(void)
}
result &= secure;
#if !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_REV_MIN_FULL < 300)
#if SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND
if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) {
uint8_t xts_pseudo_level = 0;
@@ -493,7 +495,7 @@ bool esp_flash_encryption_cfg_verify_release_mode(void)
}
}
#endif
#endif
return result;
}
#endif // not CONFIG_IDF_TARGET_ESP32
components/bt/common/ble_log/Kconfig.in
+32 -8
View File
@@ -70,15 +70,39 @@ if BLE_LOG_ENABLED
help
Enable BLE Log for Link Layer
config BLE_LOG_LBM_LL_TRANS_SIZE
int "Buffer size for each peripheral transport of Link Layer LBM"
depends on BLE_LOG_LL_ENABLED
default 1024
if BLE_LOG_LL_ENABLED
config BLE_LOG_LBM_LL_TRANS_SIZE
int "Buffer size for each peripheral transport of Link Layer LBM"
default 1024
help
There're 2 Link Layer dedicated log buffer managers (LBMs) with
compare-and-swap (CAS) protection. Each LBM is managing 2 ping-
pong buffers, which means there will be additional 2 * 2 *
BLE_LOG_LBM_LL_TRANS_SIZE bytes buffer allocated
config BLE_LOG_LL_HCI_LOG_PAYLOAD_LEN_LIMIT_ENABLED
bool "Enable LL HCI Log Payload Length Limit"
default n
help
Enable length limit for LL HCI Log payload (addr_append).
When enabled, if len_append exceeds the configured limit,
it will be truncated to the maximum length.
config BLE_LOG_LL_HCI_LOG_PAYLOAD_LEN_LIMIT
int "LL HCI Log Payload Length Limit (bytes)"
depends on BLE_LOG_LL_HCI_LOG_PAYLOAD_LEN_LIMIT_ENABLED
default 32
help
Maximum length for LL HCI Log payload (len_append).
When the feature is enabled and len_append exceeds this value,
it will be truncated.
endif
config BLE_LOG_HOST_SIDE_HCI_LOG_ENABLED
bool "Enable BLE Host side HCI Logging"
default y
help
There're 2 Link Layer dedicated log buffer managers (LBMs) with
compare-and-swap (CAS) protection. Each LBM is managing 2 ping-
pong buffers, which means there will be additional 2 * 2 *
BLE_LOG_LBM_LL_TRANS_SIZE bytes buffer allocated
Enable BLE Host side HCI Logging
config BLE_LOG_PAYLOAD_CHECKSUM_ENABLED
bool "Enable payload checksum for BLE Log data integrity check"
components/bt/common/ble_log/src/ble_log_lbm.c
+28 -16
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -107,8 +107,7 @@ void ble_log_lbm_write_trans(ble_log_prph_trans_t **trans, ble_log_src_t src_cod
}
if (len_append) {
#if CONFIG_SOC_ESP_NIMBLE_CONTROLLER
if (omdata && !BLE_LOG_IN_ISR()) {
/* os_mbuf_copydata is in flash and not safe to call from ISR */
if (omdata) {
os_mbuf_copydata((struct os_mbuf *)addr_append, 0,
len_append, buf + BLE_LOG_FRAME_HEAD_LEN + len);
}
@@ -427,17 +426,17 @@ BLE_LOG_IRAM_ATTR
bool ble_log_write_hex(ble_log_src_t src_code, const uint8_t *addr, size_t len)
{
BLE_LOG_REF_COUNT_ACQUIRE(&lbm_ref_count);
size_t payload_len = len + sizeof(uint32_t);
if (!lbm_enabled) {
goto exit;
}
/* Get transport */
size_t payload_len = len + sizeof(uint32_t);
ble_log_lbm_t *lbm = ble_log_lbm_acquire();
ble_log_prph_trans_t **trans = ble_log_lbm_get_trans(lbm, payload_len);
if (!trans) {
ble_log_lbm_release(lbm);
goto exit;
goto failed;
}
/* Write transport */
@@ -452,12 +451,13 @@ bool ble_log_write_hex(ble_log_src_t src_code, const uint8_t *addr, size_t len)
BLE_LOG_REF_COUNT_RELEASE(&lbm_ref_count);
return true;
exit:
failed:
#if CONFIG_BLE_LOG_ENH_STAT_ENABLED
if (lbm_inited) {
ble_log_stat_mgr_update(src_code, payload_len, true);
}
#endif /* CONFIG_BLE_LOG_ENH_STAT_ENABLED */
exit:
BLE_LOG_REF_COUNT_RELEASE(&lbm_ref_count);
return false;
}
@@ -468,10 +468,12 @@ void ble_log_write_hex_ll(uint32_t len, const uint8_t *addr,
uint32_t len_append, const uint8_t *addr_append, uint32_t flag)
{
BLE_LOG_REF_COUNT_ACQUIRE(&lbm_ref_count);
size_t payload_len = len + len_append;
if (!lbm_enabled) {
goto exit;
}
/* Source code shall be determined before LBM enable status check */
ble_log_src_t src_code;
/* Source code shall be determined before LBM determination */
ble_log_src_t src_code = BLE_LOG_SRC_MAX;
bool use_ll_task = false;
if (flag & BIT(BLE_LOG_LL_FLAG_ISR)) {
src_code = BLE_LOG_SRC_LL_ISR;
@@ -485,24 +487,33 @@ void ble_log_write_hex_ll(uint32_t len, const uint8_t *addr,
}
bool omdata = flag & BIT(BLE_LOG_LL_FLAG_OMDATA);
if (!lbm_enabled) {
goto exit;
}
/* Determine LBM by flag */
ble_log_lbm_t *lbm;
if (BLE_LOG_IN_ISR()) {
/* Reuse common LBM acquire logic */
lbm = ble_log_lbm_acquire();
/* os_mbuf_copydata is in flash and not safe to call from ISR */
omdata = false;
} else {
lbm = (use_ll_task)? &(lbm_ctx->lbm_ll_task): &(lbm_ctx->lbm_ll_hci);
if (use_ll_task) {
lbm = &(lbm_ctx->lbm_ll_task);
} else {
lbm = &(lbm_ctx->lbm_ll_hci);
#if CONFIG_BLE_LOG_LL_HCI_LOG_PAYLOAD_LEN_LIMIT_ENABLED
if (len_append > CONFIG_BLE_LOG_LL_HCI_LOG_PAYLOAD_LEN_LIMIT) {
len_append = CONFIG_BLE_LOG_LL_HCI_LOG_PAYLOAD_LEN_LIMIT;
}
#endif /* CONFIG_BLE_LOG_LL_HCI_LOG_PAYLOAD_LEN_LIMIT_ENABLED */
}
}
/* Get transport */
size_t payload_len = len + len_append;
ble_log_prph_trans_t **trans = ble_log_lbm_get_trans(lbm, payload_len);
if (!trans) {
ble_log_lbm_release(lbm);
goto exit;
goto failed;
}
/* Write transport */
@@ -512,12 +523,13 @@ void ble_log_write_hex_ll(uint32_t len, const uint8_t *addr,
BLE_LOG_REF_COUNT_RELEASE(&lbm_ref_count);
return;
exit:
failed:
#if CONFIG_BLE_LOG_ENH_STAT_ENABLED
if (lbm_inited) {
ble_log_stat_mgr_update(src_code, payload_len, true);
}
#endif /* CONFIG_BLE_LOG_ENH_STAT_ENABLED */
exit:
BLE_LOG_REF_COUNT_RELEASE(&lbm_ref_count);
return;
}
components/bt/host/bluedroid/api/esp_bluedroid_hci.c
+6
View File
@@ -19,6 +19,9 @@
#if CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
#include "ble_log/ble_log_spi_out.h"
#endif // CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
#if CONFIG_BLE_LOG_ENABLED
#include "ble_log.h"
#endif /* CONFIG_BLE_LOG_ENABLED */
static esp_bluedroid_hci_driver_operations_t s_hci_driver_ops = { 0 };
@@ -70,6 +73,9 @@ void hci_host_send_packet(uint8_t *data, uint16_t len)
#if CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
ble_log_spi_out_hci_write(BLE_LOG_SPI_OUT_SOURCE_HCI_DOWNSTREAM, data, len);
#endif // CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
#if CONFIG_BLE_LOG_HOST_SIDE_HCI_LOG_ENABLED
ble_log_write_hex(BLE_LOG_SRC_HCI, data, len);
#endif /* CONFIG_BLE_LOG_HOST_SIDE_HCI_LOG_ENABLED */
#if (BT_CONTROLLER_INCLUDED == TRUE)
esp_vhci_host_send_packet(data, len);
#else /* BT_CONTROLLER_INCLUDED == TRUE */
components/bt/host/bluedroid/hci/hci_hal_h4.c
+6
View File
@@ -45,6 +45,9 @@
#if CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
#include "ble_log/ble_log_spi_out.h"
#endif // CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
#if CONFIG_BLE_LOG_ENABLED
#include "ble_log.h"
#endif /* CONFIG_BLE_LOG_ENABLED */
#define HCI_BLE_EVENT 0x3e
#define PACKET_TYPE_TO_INBOUND_INDEX(type) ((type) - 2)
@@ -605,6 +608,9 @@ static int host_recv_pkt_cb(uint8_t *data, uint16_t len)
#if CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
ble_log_spi_out_hci_write(BLE_LOG_SPI_OUT_SOURCE_HCI_UPSTREAM, data, len);
#endif // CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
#if CONFIG_BLE_LOG_HOST_SIDE_HCI_LOG_ENABLED
ble_log_write_hex(BLE_LOG_SRC_HCI, data, len);
#endif /* CONFIG_BLE_LOG_HOST_SIDE_HCI_LOG_ENABLED */
//Target has packet to host, malloc new buffer for packet
BT_HDR *pkt = NULL;
#if (BLE_42_SCAN_EN == TRUE)
components/bt/host/bluedroid/stack/gatt/att_protocol.c
+1 -2
View File
@@ -395,8 +395,7 @@ tGATT_STATUS attp_send_msg_to_l2cap(tGATT_TCB *p_tcb, BT_HDR *p_toL2CAP)
}
if (l2cap_ret == L2CAP_DW_FAILED) {
GATT_TRACE_DEBUG("ATT failed to pass msg:0x%0x to L2CAP",
*((UINT8 *)(p_toL2CAP + 1) + p_toL2CAP->offset));
GATT_TRACE_DEBUG("ATT failed to pass msg to L2CAP");
return GATT_INTERNAL_ERROR;
} else if (l2cap_ret == L2CAP_DW_CONGESTED) {
GATT_TRACE_DEBUG("ATT congested, message accepted");
components/bt/host/nimble/esp-hci/src/esp_nimble_hci.c
+10 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -27,6 +27,9 @@
#if CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
#include "ble_log/ble_log_spi_out.h"
#endif // CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
#if CONFIG_BLE_LOG_ENABLED
#include "ble_log.h"
#endif /* CONFIG_BLE_LOG_ENABLED */
#define NIMBLE_VHCI_TIMEOUT_MS 2000
#define BLE_HCI_EVENT_HDR_LEN (2)
@@ -80,6 +83,9 @@ void esp_vhci_host_send_packet_wrapper(uint8_t *data, uint16_t len)
#if CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
ble_log_spi_out_hci_write(BLE_LOG_SPI_OUT_SOURCE_HCI_DOWNSTREAM, data, len);
#endif // CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
#if CONFIG_BLE_LOG_HOST_SIDE_HCI_LOG_ENABLED
ble_log_write_hex(BLE_LOG_SRC_HCI, data, len);
#endif /* CONFIG_BLE_LOG_HOST_SIDE_HCI_LOG_ENABLED */
esp_vhci_host_send_packet(data, len);
}
@@ -260,6 +266,9 @@ static int host_rcv_pkt(uint8_t *data, uint16_t len)
#if CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
ble_log_spi_out_hci_write(BLE_LOG_SPI_OUT_SOURCE_HCI_UPSTREAM, data, len);
#endif // CONFIG_BT_BLE_LOG_SPI_OUT_HCI_ENABLED
#if CONFIG_BLE_LOG_HOST_SIDE_HCI_LOG_ENABLED
ble_log_write_hex(BLE_LOG_SRC_HCI, data, len);
#endif /* CONFIG_BLE_LOG_HOST_SIDE_HCI_LOG_ENABLED */
bt_record_hci_data(data, len);
components/bt/host/nimble/nimble
+1 -1
Submodule components/bt/host/nimble/nimble updated: 112925dfe7...d9a6fa8630
components/esp_adc/esp32/adc_dma.c
+7 -2
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -43,7 +43,12 @@ static IRAM_ATTR void adc_dma_intr_handler(void *arg)
esp_err_t adc_dma_intr_event_init(adc_continuous_ctx_t *adc_ctx)
{
return (esp_intr_alloc(i2s_periph_signal[ADC_DMA_I2S_HOST].irq, ESP_INTR_FLAG_IRAM, adc_dma_intr_handler,
int intr_flags = ESP_INTR_FLAG_LOWMED | ESP_INTR_FLAG_SHARED;
#if CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE
intr_flags |= ESP_INTR_FLAG_IRAM;
#endif
return (esp_intr_alloc(i2s_periph_signal[ADC_DMA_I2S_HOST].irq, intr_flags, adc_dma_intr_handler,
(void *)adc_ctx, &adc_ctx->adc_dma.dma_intr_hdl));
}
components/esp_adc/esp32s2/adc_dma.c
+7 -2
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -40,7 +40,12 @@ static IRAM_ATTR void adc_dma_intr_handler(void *arg)
esp_err_t adc_dma_intr_event_init(adc_continuous_ctx_t *adc_ctx)
{
return (esp_intr_alloc(spicommon_irqdma_source_for_host(ADC_DMA_SPI_HOST), ESP_INTR_FLAG_IRAM, adc_dma_intr_handler,
int intr_flags = ESP_INTR_FLAG_LOWMED | ESP_INTR_FLAG_SHARED;
#if CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE
intr_flags |= ESP_INTR_FLAG_IRAM;
#endif
return (esp_intr_alloc(spicommon_irqdma_source_for_host(ADC_DMA_SPI_HOST), intr_flags, adc_dma_intr_handler,
(void *)adc_ctx, &adc_ctx->adc_dma.dma_intr_hdl));
}
components/esp_driver_isp/include/driver/isp_ccm.h
+1 -1
View File
@@ -20,7 +20,7 @@ extern "C" {
*
*/
typedef struct {
float matrix[ISP_CCM_DIMENSION][ISP_CCM_DIMENSION]; /*!< The color correction matrix in float, range (-4.0, 4.0) */
float matrix[ISP_CCM_DIMENSION][ISP_CCM_DIMENSION]; /*!< The color correction matrix in float*/
bool saturation; /*!< Whether to use saturation when the float data in the matrix is out of the range,
* For example, if one of the matrix data is 5.0,
* When saturation is true, and final value will be limited to 4.0, and won't rise error
components/esp_driver_isp/src/isp_ccm.c
+12 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -21,6 +21,17 @@ esp_err_t esp_isp_ccm_configure(isp_proc_handle_t proc, const esp_isp_ccm_config
{
ESP_RETURN_ON_FALSE(proc && ccm_cfg, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
// Check matrix values are within valid range
float max_range = (1 << ISP_LL_CCM_MATRIX_INT_BITS);
float min_range = -(1 << ISP_LL_CCM_MATRIX_INT_BITS);
for (int i = 0; i < ISP_CCM_DIMENSION; i++) {
for (int j = 0; j < ISP_CCM_DIMENSION; j++) {
float value = ccm_cfg->matrix[i][j];
ESP_RETURN_ON_FALSE(value >= min_range && value <= max_range, ESP_ERR_INVALID_ARG, TAG,
"Matrix[%d][%d] value %f is out of range [%f, %f]", i, j, value, min_range, max_range);
}
}
bool ret = true;
bool valid = false;
portENTER_CRITICAL(&proc->spinlock);
components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c
+1 -1
View File
@@ -391,7 +391,7 @@ TEST_CASE("parallel_rx_unit_pulse_delimiter_test_via_i2s", "[parlio_rx]")
{
parlio_rx_pulse_delimiter_config_t pls_deli_cfg = {
.valid_sig_line_id = TEST_VALID_SIG,
.sample_edge = PARLIO_SAMPLE_EDGE_NEG,
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB,
.eof_data_len = TEST_EOF_DATA_LEN,
.timeout_ticks = 0,
components/esp_eth/include/esp_eth_mac_esp.h
+3
View File
@@ -182,6 +182,7 @@ typedef struct {
#if !SOC_EMAC_RMII_CLK_OUT_INTERNAL_LOOPBACK
eth_mac_clock_config_t clock_config_out_in; /*!< EMAC input clock configuration for internally generated output clock (when output clock is looped back externally) */
#endif //SOC_EMAC_RMII_CLK_OUT_INTERNAL_LOOPBACK
int32_t mdc_freq_hz; /*!< EMAC MDC frequency range limit, if set to 0 or a negative value, the driver will set the CSR clock range up to 2.5 MHz */
} eth_esp32_emac_config_t;
/**
@@ -257,6 +258,7 @@ typedef bool (*ts_target_exceed_cb_from_isr_t)(esp_eth_mediator_t *eth, void *us
}, \
.dma_burst_len = ETH_DMA_BURST_LEN_32, \
.intr_priority = 0, \
.mdc_freq_hz = 0, \
}
#elif CONFIG_IDF_TARGET_ESP32P4
#define ETH_ESP32_EMAC_DEFAULT_CONFIG() \
@@ -277,6 +279,7 @@ typedef bool (*ts_target_exceed_cb_from_isr_t)(esp_eth_mediator_t *eth, void *us
}, \
.dma_burst_len = ETH_DMA_BURST_LEN_32, \
.intr_priority = 0, \
.mdc_freq_hz = 0, \
.emac_dataif_gpio = \
{ \
.rmii = \
components/esp_eth/src/mac/esp_eth_mac_esp.c
+11 -1
View File
@@ -73,6 +73,7 @@ typedef struct {
bool do_flow_ctrl; // indicates whether we need to do software flow control
bool use_pll; // Only use (A/M)PLL in EMAC_DATA_INTERFACE_RMII && EMAC_CLK_OUT
SemaphoreHandle_t multi_reg_mutex; // lock for multiple register access
int32_t mdc_freq_hz;
#ifdef CONFIG_PM_ENABLE
esp_pm_lock_handle_t pm_lock;
#endif
@@ -547,7 +548,14 @@ static esp_err_t emac_esp32_init(esp_eth_mac_t *mac)
}
ESP_GOTO_ON_FALSE(to < emac->sw_reset_timeout_ms / 10, ESP_ERR_TIMEOUT, err, TAG, "reset timeout");
/* set smi clock */
emac_hal_set_csr_clock_range(&emac->hal, esp_clk_apb_freq());
uint32_t csr_freq_hz;
soc_module_clk_t csr_clk_src = emac_ll_get_csr_clk_src();
ESP_GOTO_ON_ERROR(esp_clk_tree_src_get_freq_hz(csr_clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &csr_freq_hz), err, TAG, "get CSR frequency failed");
if (emac->mdc_freq_hz <= 0) {
emac_hal_set_csr_clock_range(&emac->hal, csr_freq_hz);
} else {
emac_hal_find_set_closest_csr_clock_range(&emac->hal, emac->mdc_freq_hz, csr_freq_hz);
}
/* init mac registers by default */
emac_hal_init_mac_default(&emac->hal);
/* init dma registers with selected EMAC-DMA configuration */
@@ -843,6 +851,8 @@ esp_eth_mac_t *esp_eth_mac_new_esp32(const eth_esp32_emac_config_t *esp32_config
emac->dma_burst_len = esp32_config->dma_burst_len;
emac->sw_reset_timeout_ms = config->sw_reset_timeout_ms;
emac->mdc_freq_hz = esp32_config->mdc_freq_hz;
emac->flow_control_high_water_mark = FLOW_CONTROL_HIGH_WATER_MARK;
emac->flow_control_low_water_mark = FLOW_CONTROL_LOW_WATER_MARK;
emac->parent.set_mediator = emac_esp32_set_mediator;
components/esp_eth/test_apps/.build-test-rules.yml
+1 -1
View File
@@ -2,7 +2,7 @@
components/esp_eth/test_apps:
enable:
- if: IDF_TARGET in ["esp32"] # TODO: IDF-14365
- if: IDF_TARGET in ["esp32", "esp32p4"]
reason: ESP32 and ESP32P4 have internal EMAC. SPI Ethernet runners are based on ESP32.
depends_components:
- esp_eth
components/esp_eth/test_apps/README.md
+2 -2
View File
@@ -1,6 +1,6 @@
# EMAC Test
| Supported Targets | ESP32 |
| ----------------- | ----- |
| Supported Targets | ESP32 | ESP32-P4 |
| ----------------- | ----- | -------- |
This test app is used to test Ethernet MAC behavior with different chips.
components/esp_eth/test_apps/pytest_esp_eth.py
+12 -18
View File
@@ -288,48 +288,42 @@ def test_esp_eth_ip101(dut: IdfDut) -> None:
# ----------- IP101 ESP32P4 -----------
@pytest.mark.eth_ip101
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14365')
@pytest.mark.parametrize(
'config',
'config, target',
[
'default_ip101_esp32p4',
pytest.param('default_ip101_esp32p4', 'esp32p4', marks=[pytest.mark.eth_ip101]),
pytest.param('default_ip101_esp32p4v1', 'esp32p4', marks=[pytest.mark.eth_ip101, pytest.mark.esp32p4_eco4]),
],
indirect=True,
indirect=['target'],
)
@idf_parametrize('target', ['esp32p4'], indirect=['target'])
def test_esp32p4_ethernet(dut: IdfDut) -> None:
ethernet_test(dut)
dut.serial.hard_reset()
ethernet_l2_test(dut)
@pytest.mark.eth_ip101
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14365')
@pytest.mark.parametrize(
'config',
'config, target',
[
'default_ip101_esp32p4',
pytest.param('default_ip101_esp32p4', 'esp32p4', marks=[pytest.mark.eth_ip101]),
pytest.param('default_ip101_esp32p4v1', 'esp32p4', marks=[pytest.mark.eth_ip101, pytest.mark.esp32p4_eco4]),
],
indirect=True,
indirect=['target'],
)
@idf_parametrize('target', ['esp32p4'], indirect=['target'])
def test_esp32p4_emac(dut: IdfDut) -> None:
ethernet_int_emac_test(dut)
dut.serial.hard_reset()
ethernet_heap_alloc_test(dut)
@pytest.mark.eth_ip101
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14365')
@pytest.mark.parametrize(
'config',
'config, target',
[
'rmii_clko_esp32p4',
pytest.param('rmii_clko_esp32p4', 'esp32p4', marks=[pytest.mark.eth_ip101]),
pytest.param('rmii_clko_esp32p4v1', 'esp32p4', marks=[pytest.mark.eth_ip101, pytest.mark.esp32p4_eco4]),
],
indirect=True,
indirect=['target'],
)
@idf_parametrize('target', ['esp32p4'], indirect=['target'])
def test_esp32p4_emac_clko(dut: IdfDut) -> None:
dut.run_all_single_board_cases(group='esp_emac_clk_out')
components/esp_eth/test_apps/sdkconfig.ci.default_ip101_esp32p4v1
+12
View File
@@ -0,0 +1,12 @@
CONFIG_IDF_TARGET="esp32p4"
CONFIG_ESP32P4_SELECTS_REV_LESS_V3=y
CONFIG_UNITY_ENABLE_FIXTURE=y
CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y
CONFIG_ETH_USE_ESP32_EMAC=y
CONFIG_ESP_TASK_WDT_EN=n
CONFIG_TARGET_USE_INTERNAL_ETHERNET=y
CONFIG_TARGET_ETH_PHY_DEVICE_IP101=y
CONFIG_TARGET_USE_DEFAULT_EMAC_CONFIG=y
components/esp_eth/test_apps/sdkconfig.ci.rmii_clko_esp32p4v1
+18
View File
@@ -0,0 +1,18 @@
CONFIG_IDF_TARGET="esp32p4"
CONFIG_ESP32P4_SELECTS_REV_LESS_V3=y
CONFIG_UNITY_ENABLE_FIXTURE=y
CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y
CONFIG_ETH_USE_ESP32_EMAC=y
CONFIG_ESP_TASK_WDT_EN=n
CONFIG_TARGET_USE_INTERNAL_ETHERNET=y
CONFIG_TARGET_ETH_PHY_DEVICE_IP101=y
CONFIG_TARGET_USE_DEFAULT_EMAC_CONFIG=y
CONFIG_TARGET_RMII_CLK_OUT=y
# Test board needs to be modified!
# Connect GPIO23 to GPIO32 via wire.
CONFIG_TARGET_RMII_CLK_OUT_GPIO=23
CONFIG_TARGET_RMII_CLK_IN_GPIO=32
components/esp_event/test_apps/pytest_esp_event.py
+29
View File
@@ -7,6 +7,14 @@ from pytest_embedded_idf.utils import idf_parametrize
@pytest.mark.generic
@idf_parametrize('target', ['esp32', 'esp32s2', 'esp32c3'], indirect=['target'])
@pytest.mark.parametrize(
'config',
[
'defaults',
'no_isr_post',
],
indirect=True,
)
def test_esp_event(dut: Dut) -> None:
dut.run_all_single_board_cases()
@@ -14,6 +22,13 @@ def test_esp_event(dut: Dut) -> None:
@pytest.mark.host_test
@pytest.mark.qemu
@pytest.mark.xfail('config.getvalue("target") == "esp32c3"', reason='Unstable on QEMU, needs investigation')
@pytest.mark.parametrize(
'config',
[
'defaults',
],
indirect=True,
)
@idf_parametrize('target', ['esp32', 'esp32c3'], indirect=['target'])
def test_esp_event_qemu(dut: Dut) -> None:
for case in dut.test_menu:
@@ -23,6 +38,13 @@ def test_esp_event_qemu(dut: Dut) -> None:
@pytest.mark.host_test
@idf_parametrize('target', ['linux'], indirect=['target'])
@pytest.mark.parametrize(
'config',
[
'defaults',
],
indirect=True,
)
def test_esp_event_posix_simulator(dut: Dut) -> None:
dut.expect_exact('Press ENTER to see the list of tests.')
dut.write('*')
@@ -31,6 +53,13 @@ def test_esp_event_posix_simulator(dut: Dut) -> None:
@pytest.mark.generic
@idf_parametrize('target', ['esp32'], indirect=['target'])
@pytest.mark.parametrize(
'config',
[
'defaults',
],
indirect=True,
)
def test_esp_event_profiling(dut: Dut) -> None:
dut.expect_exact('Press ENTER to see the list of tests.')
dut.write('"profiling reports valid values"')
components/esp_event/test_apps/sdkconfig.ci.defaults
View File
components/esp_event/test_apps/sdkconfig.ci.no_isr_post
+1 -2
View File
@@ -1,3 +1,2 @@
# This configuration checks the event loop if posting from ISR is disabled
CONFIG_ESP_TASK_WDT_INIT=n
CONFIG_POST_EVENTS_FROM_ISR=n
CONFIG_ESP_EVENT_POST_FROM_ISR=n
components/esp_hw_support/Kconfig
+1
View File
@@ -319,6 +319,7 @@ menu "Hardware Settings"
config ESP_ENABLE_PVT
bool "Auto adjust hp & lp voltage using pvt function (MUST ENABLE FOR MP)"
depends on SOC_PMU_PVT_SUPPORTED
default n if IDF_TARGET_ESP32C6
default y
help
If enabled, hp & lp voltage can be auto adjust by PVT characteristic.
components/esp_hw_support/dma/esp_dma_utils.c
+13 -1
View File
@@ -20,6 +20,9 @@
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "esp_cache.h"
#if CONFIG_SPIRAM
#include "esp_private/esp_psram_mspi.h"
#endif
static const char *TAG = "dma_utils";
@@ -52,7 +55,7 @@ esp_err_t esp_dma_split_rx_buffer_to_cache_aligned(void *rx_buffer, size_t buffe
} else {
// If the stash buffer is offered by the caller, check if it is aligned
ESP_RETURN_ON_FALSE_ISR(split_line_size == 0 || (uintptr_t)(*ret_stash_buffer) % split_line_size == 0,
ESP_ERR_INVALID_ARG, TAG, "the offered stash buffer is not aligned");
ESP_ERR_INVALID_ARG, TAG, "the offered stash buffer is not aligned");
// If the stash buffer is offered by the caller, use it
stash_buffer = *ret_stash_buffer;
}
@@ -127,6 +130,15 @@ esp_err_t esp_dma_merge_aligned_rx_buffers(dma_buffer_split_array_t *align_array
{
ESP_RETURN_ON_FALSE_ISR(align_array, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
#if CONFIG_SPIRAM
// check if the original buffer is in external RAM, if so, add memory barrier
if (esp_ptr_external_ram(align_array->buf.head.recovery_address) ||
esp_ptr_external_ram(align_array->buf.body.recovery_address) ||
esp_ptr_external_ram(align_array->buf.tail.recovery_address)) {
esp_psram_mspi_mb();
}
#endif
// only need to copy the head and tail buffer
if (align_array->buf.head.length) {
memcpy(align_array->buf.head.recovery_address, align_array->buf.head.aligned_buffer, align_array->buf.head.length);
components/esp_hw_support/dma/gdma.c
+16 -13
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -28,7 +28,6 @@
#include "gdma_priv.h"
#include "esp_memory_utils.h"
#include "esp_flash_encrypt.h"
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
#include "esp_private/gdma_sleep_retention.h"
@@ -383,6 +382,21 @@ esp_err_t gdma_config_transfer(gdma_channel_handle_t dma_chan, const gdma_transf
// always enable descriptor burst as the descriptor is always word aligned and is in the internal SRAM
bool en_desc_burst = true;
bool en_data_burst = max_data_burst_size > 0;
#if SOC_PSRAM_DMA_CAPABLE || SOC_DMA_CAN_ACCESS_FLASH
// if MSPI encryption is enabled, and DMA wants to read/write external memory
if (efuse_hal_flash_encryption_enabled() && config->access_ext_mem) {
uint32_t enc_mem_alignment = GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT;
// when DMA access the encrypted external memory, extra alignment is needed for external memory
ext_mem_alignment = MAX(ext_mem_alignment, enc_mem_alignment);
if (max_data_burst_size < enc_mem_alignment) {
ESP_LOGW(TAG, "GDMA channel access encrypted external memory, adjust burst size to %d", enc_mem_alignment);
en_data_burst = true;
max_data_burst_size = enc_mem_alignment;
}
}
#endif // SOC_PSRAM_DMA_CAPABLE || SOC_DMA_CAN_ACCESS_FLASH
gdma_hal_enable_burst(hal, pair->pair_id, dma_chan->direction, en_data_burst, en_desc_burst);
if (en_data_burst) {
gdma_hal_set_burst_size(hal, pair->pair_id, dma_chan->direction, max_data_burst_size);
@@ -395,17 +409,6 @@ esp_err_t gdma_config_transfer(gdma_channel_handle_t dma_chan, const gdma_transf
}
#endif
// if MSPI encryption is enabled, and DMA wants to read/write external memory
if (esp_flash_encryption_enabled()) {
gdma_hal_enable_access_encrypt_mem(hal, pair->pair_id, dma_chan->direction, config->access_ext_mem);
// when DMA access the encrypted memory, extra alignment is needed for external memory
if (config->access_ext_mem) {
ext_mem_alignment = MAX(ext_mem_alignment, GDMA_ACCESS_ENCRYPTION_MEM_ALIGNMENT);
}
} else {
gdma_hal_enable_access_encrypt_mem(hal, pair->pair_id, dma_chan->direction, false);
}
// if the channel is not allowed to access external memory, set a super big (meaningless) alignment value
// so when the upper layer checks the alignment with an external buffer, the check should fail
if (!config->access_ext_mem) {
components/esp_hw_support/dma/gdma_link.c
+15 -3
View File
@@ -16,6 +16,7 @@
#include "esp_heap_caps.h"
#include "esp_private/gdma_link.h"
#include "hal/cache_hal.h"
#include "hal/efuse_hal.h"
#include "hal/cache_ll.h"
#include "esp_cache.h"
@@ -79,9 +80,16 @@ esp_err_t gdma_new_link_list(const gdma_link_list_config_t *config, gdma_link_li
// guard against overflow when calculating total bytes for descriptors
ESP_GOTO_ON_FALSE(num_items <= SIZE_MAX / item_size, ESP_ERR_INVALID_SIZE, err, TAG, "list too big");
bool items_in_ext_mem = config->flags.items_in_ext_mem;
uint32_t list_items_mem_caps = MALLOC_CAP_8BIT | MALLOC_CAP_DMA;
if (config->flags.items_in_ext_mem) {
list_items_mem_caps |= MALLOC_CAP_SPIRAM;
if (items_in_ext_mem) {
if (efuse_hal_flash_encryption_enabled()) {
items_in_ext_mem = false;
list_items_mem_caps |= MALLOC_CAP_INTERNAL;
ESP_LOGW(TAG, "DMA linked list items cannot be placed in PSRAM when external memory encryption is enabled, using internal memory instead");
} else {
list_items_mem_caps |= MALLOC_CAP_SPIRAM;
}
} else {
list_items_mem_caps |= MALLOC_CAP_INTERNAL;
}
@@ -90,7 +98,7 @@ esp_err_t gdma_new_link_list(const gdma_link_list_config_t *config, gdma_link_li
// do memory sync if the list items are in the cache
uint32_t data_cache_line_size = 0;
if (config->flags.items_in_ext_mem) {
if (items_in_ext_mem) {
data_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA);
} else {
data_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
@@ -178,6 +186,10 @@ esp_err_t gdma_link_mount_buffers(gdma_link_list_handle_t list, int start_item_i
size_t max_buffer_mount_length = ALIGN_DOWN(GDMA_MAX_BUFFER_SIZE_PER_LINK_ITEM, buffer_alignment);
if (!config->flags.bypass_buffer_align_check) {
ESP_RETURN_ON_FALSE_ISR(((uintptr_t)buf & (buffer_alignment - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "buf misalign idx=%"PRIu32" align=%"PRIu32, bi, buffer_alignment);
if (efuse_hal_flash_encryption_enabled()) {
// buffer size must be aligned to the encryption alignment which should be provided by the upper buffer_alignment
ESP_RETURN_ON_FALSE_ISR((len & (buffer_alignment - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "buf len misalign idx=%"PRIu32" len=%"PRIu32" align=%"PRIu32"", bi, len, buffer_alignment);
}
}
size_t num_items_need = (len + max_buffer_mount_length - 1) / max_buffer_mount_length;
ESP_RETURN_ON_FALSE_ISR(num_items_need <= remaining, ESP_ERR_INVALID_ARG, TAG,
components/esp_hw_support/dma/gdma_priv.h
+1 -2
View File
@@ -30,6 +30,7 @@
#include "hal/gdma_hal_ahb.h"
#include "hal/gdma_hal_axi.h"
#include "soc/gdma_periph.h"
#include "hal/efuse_hal.h"
#include "soc/periph_defs.h"
#include "esp_private/gdma.h"
#include "esp_private/periph_ctrl.h"
@@ -40,8 +41,6 @@
#define GDMA_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
#endif
#define GDMA_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 /*!< The alignment of the memory and size when DMA accesses the encryption memory */
///!< Logging settings
#define TAG "gdma"
components/esp_hw_support/hw_random.c
+7 -9
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2016-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2016-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -25,6 +25,9 @@
#if SOC_RNG_CLOCK_IS_INDEPENDENT
#include "hal/lp_clkrst_ll.h"
#if SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE || SOC_RNG_RTC_TIMER_ENTROPY_SOURCE
#include "hal/rng_ll.h"
#endif
#endif
#if defined CONFIG_IDF_TARGET_ESP32S3
@@ -106,15 +109,10 @@ void esp_fill_random(void *buf, size_t len)
#if SOC_RNG_CLOCK_IS_INDEPENDENT && !ESP_TEE_BUILD
ESP_SYSTEM_INIT_FN(init_rng, SECONDARY, BIT(0), 102)
{
#if SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE || SOC_RNG_RTC_TIMER_ENTROPY_SOURCE
rng_ll_enable();
#else
_lp_clkrst_ll_enable_rng_clock(true);
#if SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE
SET_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_SAMPLE_ENABLE);
#endif
#if SOC_RNG_RTC_TIMER_ENTROPY_SOURCE
// This would only be effective if the RTC clock is enabled
REG_SET_FIELD(LPPERI_RNG_CFG_REG, LPPERI_RTC_TIMER_EN, 0x3);
SET_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_TIMER_EN);
#endif
return ESP_OK;
}
components/esp_hw_support/linker.lf
+1 -1
View File
@@ -43,7 +43,7 @@ entries:
elif PM_SLP_IRAM_OPT = y && IDF_TARGET_ESP32P4 != y:
pmu_param:get_act_hp_dbias (noflash)
pmu_param:get_act_lp_dbias (noflash)
if SOC_PMU_PVT_SUPPORTED = y:
if SOC_PMU_PVT_SUPPORTED = y && ESP_ENABLE_PVT = y:
pmu_pvt (noflash)
if PM_SLP_IRAM_OPT = y && SOC_USB_SERIAL_JTAG_SUPPORTED = y:
sleep_console (noflash)
components/esp_hw_support/port/esp32c6/CMakeLists.txt
+4
View File
@@ -15,6 +15,10 @@ if(NOT non_os_build)
endif()
if(NOT BOOTLOADER_BUILD AND CONFIG_ESP_ENABLE_PVT)
list(APPEND srcs "pmu_pvt.c")
endif()
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
components/esp_hw_support/port/esp32c6/include/soc/rtc.h
+48
View File
@@ -96,6 +96,54 @@ set sleep_init default param
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
#if CONFIG_ESP_ENABLE_PVT
/*
set pvt default param
*/
#define PVT_CHANNEL0_SEL 34
#define PVT_CHANNEL1_SEL 38
#define PVT_CHANNEL0_CFG 0x1033e
#define PVT_CHANNEL1_CFG 0x1033e
#define PVT_CHANNEL2_CFG 0x10000
#define PVT_CMD0 0x24
#define PVT_CMD1 0x5
#define PVT_CMD2 0x427
#define PVT_TARGET 0xffff
#define PVT_CLK_DIV 1
#define PVT_EDG_MODE 1
#define PVT_DELAY_NUM_HIGH 108
#define PVT_DELAY_NUM_LOW 98
#define PVT_PUMP_CHANNEL_CODE 1
#define PVT_PUMP_BITMAP 21
#define PVT_PUMP_DRV 0
#define PVT_DELAY_NUM_PUMP 95
/**
* @brief Initialize PVT related parameters
*/
void pvt_auto_dbias_init(void);
/**
* @brief Enable or disable PVT functions
*
* @param enable true to enable, false to disable
*/
void pvt_func_enable(bool enable);
/**
* @brief Initialize charge pump related parameters
*/
void charge_pump_init(void);
/**
* @brief Enable or disable charge pump functions
*
* @param enable true to enable, false to disable
*/
void charge_pump_enable(bool enable);
#endif //#if CONFIG_ESP_ENABLE_PVT
/*
The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
storing in efuse (based on ATE 5k ECO3 chips)
components/esp_hw_support/port/esp32c6/pmu_init.c
+20
View File
@@ -19,6 +19,10 @@
#include "regi2c_ctrl.h"
#include "esp_private/ocode_init.h"
#include "esp_rom_sys.h"
#include "soc/rtc.h"
#include "hal/efuse_ll.h"
#include "hal/efuse_hal.h"
#include "esp_hw_log.h"
static __attribute__((unused)) const char *TAG = "pmu_init";
@@ -226,4 +230,20 @@ void pmu_init(void)
esp_ocode_calib_init();
}
#endif
#if CONFIG_ESP_ENABLE_PVT
/*setup pvt function*/
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 3) {
pvt_auto_dbias_init();
charge_pump_init();
pvt_func_enable(true);
charge_pump_enable(true);
esp_rom_delay_us(1000);
}
else {
ESP_HW_LOGW(TAG, "blk_version is less than 3, pvt function not supported in efuse.");
}
#endif
}
components/esp_hw_support/port/esp32c6/pmu_param.c
+1 -1
View File
@@ -351,7 +351,7 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
#define PMU_LP_SLEEP_POWER_CONFIG_DEFAULT() { \
.dig_power = { \
.mem_dslp = 1, \
.mem_dslp = 0, \
.peri_pd_en = 0, \
}, \
.clk_power = { \
components/esp_hw_support/port/esp32c6/pmu_pvt.c
+170
View File
@@ -0,0 +1,170 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <stdlib.h>
#include <esp_types.h>
#include "sdkconfig.h"
#include "esp_attr.h"
#include "soc/soc.h"
#include "soc/pmu_struct.h"
#include "soc/pvt_reg.h"
#include "soc/pmu_reg.h"
#include "soc/pcr_reg.h"
#include "hal/pmu_hal.h"
#include "pmu_param.h"
#include "esp_rom_sys.h"
#include "esp_private/esp_pmu.h"
#include "soc/regi2c_dig_reg.h"
#include "regi2c_ctrl.h"
#include "soc/rtc.h"
#include "hal/efuse_ll.h"
#include "hal/efuse_hal.h"
#include "esp_hw_log.h"
static __attribute__((unused)) const char *TAG = "pmu_pvt";
#if CONFIG_ESP_ENABLE_PVT
static uint8_t get_lp_hp_gap(void)
{
int8_t pvt_offset = 0;
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 3) {
uint8_t offset_read = efuse_ll_get_dbias_vol_gap();
bool offset_flag = offset_read >> 4;
uint8_t offset_value = offset_read & 0xf;
int8_t pvt_offset = 0;
if (offset_flag) {
pvt_offset = -1 * offset_value;
} else {
pvt_offset = offset_value;
}
pvt_offset = pvt_offset - 2;
assert((pvt_offset >= -15) && (pvt_offset <= 13));
if (pvt_offset < 0 ) {
pvt_offset = 16 - pvt_offset;
}
}
return pvt_offset;
}
static void set_pvt_hp_lp_gap(uint8_t value)
{
bool flag = value >> 4;
uint8_t abs_value = value & 0xf;
SET_PERI_REG_BITS(PVT_DBIAS_CMD0_REG, PVT_DBIAS_CMD0_OFFSET_FLAG, flag, PVT_DBIAS_CMD0_OFFSET_FLAG_S);
SET_PERI_REG_BITS(PVT_DBIAS_CMD0_REG, PVT_DBIAS_CMD0_OFFSET_VALUE, abs_value, PVT_DBIAS_CMD0_OFFSET_VALUE_S);
SET_PERI_REG_BITS(PVT_DBIAS_CMD1_REG, PVT_DBIAS_CMD1_OFFSET_FLAG, flag, PVT_DBIAS_CMD1_OFFSET_FLAG_S);
SET_PERI_REG_BITS(PVT_DBIAS_CMD1_REG, PVT_DBIAS_CMD1_OFFSET_VALUE, abs_value, PVT_DBIAS_CMD1_OFFSET_VALUE_S);
SET_PERI_REG_BITS(PVT_DBIAS_CMD2_REG, PVT_DBIAS_CMD2_OFFSET_FLAG, flag, PVT_DBIAS_CMD2_OFFSET_FLAG_S);
SET_PERI_REG_BITS(PVT_DBIAS_CMD2_REG, PVT_DBIAS_CMD2_OFFSET_VALUE, abs_value, PVT_DBIAS_CMD2_OFFSET_VALUE_S);
}
FORCE_INLINE_ATTR uint32_t get_pvt_hp_dbias(void)
{
return REG_GET_FIELD(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_DBIAS_VOL);
}
FORCE_INLINE_ATTR uint32_t get_pvt_lp_dbias(void)
{
return REG_GET_FIELD(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_LP_DBIAS_VOL);
}
void pvt_auto_dbias_init(void)
{
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 3) {
SET_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
/*config for dbias func*/
CLEAR_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN);
esp_rom_delay_us(1);
SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL_SEL0_REG, PVT_DBIAS_CHANNEL0_SEL, PVT_CHANNEL0_SEL, PVT_DBIAS_CHANNEL0_SEL_S);
SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL_SEL0_REG, PVT_DBIAS_CHANNEL1_SEL, PVT_CHANNEL1_SEL, PVT_DBIAS_CHANNEL1_SEL_S); // Select monitor cell ,which used to monitor PVT situation
SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL0_SEL_REG, PVT_DBIAS_CHANNEL0_CFG, PVT_CHANNEL0_CFG, PVT_DBIAS_CHANNEL0_CFG_S);
SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL1_SEL_REG, PVT_DBIAS_CHANNEL1_CFG, PVT_CHANNEL1_CFG, PVT_DBIAS_CHANNEL1_CFG_S);
SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL2_SEL_REG, PVT_DBIAS_CHANNEL2_CFG, PVT_CHANNEL2_CFG, PVT_DBIAS_CHANNEL2_CFG_S); // Configure filter threshold for avoiding auto-dbias overly sensitive regulation
SET_PERI_REG_BITS(PVT_DBIAS_CMD0_REG, PVT_DBIAS_CMD0_PVT, PVT_CMD0, PVT_DBIAS_CMD0_PVT_S);
SET_PERI_REG_BITS(PVT_DBIAS_CMD1_REG, PVT_DBIAS_CMD1_PVT, PVT_CMD1, PVT_DBIAS_CMD1_PVT_S);
SET_PERI_REG_BITS(PVT_DBIAS_CMD2_REG, PVT_DBIAS_CMD2_PVT, PVT_CMD2, PVT_DBIAS_CMD2_PVT_S); // Configure auto-dbias adjust property, such as adjusting step
SET_PERI_REG_BITS(PVT_DBIAS_TIMER_REG, PVT_TIMER_TARGET, PVT_TARGET, PVT_TIMER_TARGET_S); // Configure auto-dbias voltage regulation cycle
SET_PERI_REG_BITS(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM, PVT_CLK_DIV, PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S); //pvt function clock divider number
/*config for pvt cell: unit0; site2; vt2*/
SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_SEL); //pvt function clock source select
SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_REG, PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0, PVT_EDG_MODE, PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_S); // Select edge_mode
SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0, PVT_DELAY_NUM_HIGH, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_S); // The threshold for determining whether the voltage is too high
SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_REG, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1, PVT_DELAY_NUM_LOW, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_S); // The threshold for determining whether the voltage is too low
SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_REG, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2, PVT_DELAY_NUM_PUMP, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_S); // The threshold for chargepump
/*config lp offset for pvt func*/
uint8_t lp_hp_gap = get_lp_hp_gap();
set_pvt_hp_lp_gap(lp_hp_gap);
} else {
ESP_HW_LOGD(TAG, "blk_version is less than 3, pvt auto dbias init not supported in efuse.");
}
}
void IRAM_ATTR pvt_func_enable(bool enable)
{
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 3) {
if (enable) {
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); // start calibration @HP_CALI_DBIAS_DEFAUL
SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
SET_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
SET_PERI_REG_MASK(PVT_CLK_CFG_REG, PVT_MONITOR_CLK_PVT_EN);
SET_PERI_REG_MASK(PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG, PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0); // enable pvt clk
esp_rom_delay_us(10);
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pvt
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); // must clear @HP_CALI_DBIAS_DEFAULT
SET_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); // enable auto dbias
} else {
uint32_t pvt_hp_dbias = get_pvt_hp_dbias();
uint32_t pvt_lp_dbias = get_pvt_lp_dbias(); // update pvt_cali_dbias
SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, pvt_hp_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S);
SET_PERI_REG_BITS(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, pvt_lp_dbias, PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S);
CLEAR_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); //disable auto dbias
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pmu
CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
}
} else {
ESP_HW_LOGD(TAG, "blk_version is less than 3, pvt enable not supported in efuse.");
}
}
void charge_pump_init(void)
{
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 3) {
/*config for charge pump*/
SET_PERI_REG_BITS(PVT_PMUP_CHANNEL_CFG_REG, PVT_PUMP_CHANNEL_CODE0, PVT_PUMP_CHANNEL_CODE, PVT_PUMP_CHANNEL_CODE0_S); //Set channel code
WRITE_PERI_REG(PVT_PMUP_BITMAP_LOW0_REG, (1 << PVT_PUMP_BITMAP)); // Select monitor cell for charge pump
SET_PERI_REG_BITS(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_DRV0, PVT_PUMP_DRV, PVT_PUMP_DRV0_S); //Configure the charging intensity
} else {
ESP_HW_LOGD(TAG, "blk_version is less than 3, pvt charge_pump init not supported in efuse.");
}
}
void IRAM_ATTR charge_pump_enable(bool enable)
{
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 3) {
if (enable) {
SET_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); // enable charge pump
} else {
CLEAR_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); //disable charge pump
}
} else {
ESP_HW_LOGD(TAG, "blk_version is less than 3, pvt charge_pump enable not supported in efuse.");
}
}
#endif
components/esp_hw_support/port/esp32c6/pmu_sleep.c
+4
View File
@@ -314,6 +314,10 @@ static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_con
pmu_ll_hp_set_regulator_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd);
pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbias);
pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.drv_b);
#if CONFIG_ESP_ENABLE_PVT
uint32_t pvt_hp_dbias = GET_PERI_REG_BITS2(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_DBIAS_VOL_V, PMU_HP_DBIAS_VOL_S);
pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(MODEM), pvt_hp_dbias);
#endif
pmu_ll_lp_set_dbg_atten (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbg_atten);
pmu_ll_lp_set_current_power_off (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.pd_cur);
components/esp_hw_support/port/esp32c6/private_include/pmu_param.h
+1 -1
View File
@@ -305,7 +305,7 @@ typedef struct {
.lp_sys[PMU_MODE_LP_SLEEP] = { \
.dig_power = { \
.peri_pd_en = ((sleep_flags) & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \
.mem_dslp = 1 \
.mem_dslp = 0 \
}, \
.clk_power = { \
.xpd_xtal32k = ((sleep_flags) & PMU_SLEEP_PD_XTAL32K) ? 0 : 1,\
components/esp_hw_support/port/esp32c6/rtc_clk.c
+15 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -190,6 +190,10 @@ static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
clk_ll_cpu_set_ls_divider(div);
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
esp_rom_set_cpu_ticks_per_us(cpu_freq);
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
static void rtc_clk_cpu_freq_to_8m(void)
@@ -198,6 +202,10 @@ static void rtc_clk_cpu_freq_to_8m(void)
clk_ll_cpu_set_ls_divider(1);
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
esp_rom_set_cpu_ticks_per_us(20);
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
/**
@@ -207,6 +215,12 @@ static void rtc_clk_cpu_freq_to_8m(void)
*/
static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
{
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
pvt_auto_dbias_init();
charge_pump_init();
pvt_func_enable(true);
charge_pump_enable(true);
#endif
clk_ll_cpu_set_hs_divider(CLK_LL_PLL_480M_FREQ_MHZ / cpu_freq_mhz);
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
components/esp_hw_support/port/esp32c6/rtc_clk_init.c
+2
View File
@@ -80,6 +80,8 @@ void rtc_clk_init(rtc_clk_config_t cfg)
uint32_t hp_cali_dbias = get_act_hp_dbias();
uint32_t lp_cali_dbias = get_act_lp_dbias();
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // Hand over control of dbias to pmu
SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, hp_cali_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S);
SET_PERI_REG_BITS(PMU_HP_MODEM_HP_REGULATOR0_REG, PMU_HP_MODEM_HP_REGULATOR_DBIAS, hp_cali_dbias, PMU_HP_MODEM_HP_REGULATOR_DBIAS_S);
SET_PERI_REG_BITS(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, lp_cali_dbias, PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S);
components/esp_hw_support/port/esp32p4/Kconfig.hw_support
+4
View File
@@ -34,6 +34,9 @@ choice ESP32P4_REV_MIN
config ESP32P4_REV_MIN_300
bool "Rev v3.0"
depends on !ESP32P4_SELECTS_REV_LESS_V3
config ESP32P4_REV_MIN_301
bool "Rev v3.1"
depends on !ESP32P4_SELECTS_REV_LESS_V3
endchoice
config ESP32P4_REV_MIN_FULL
@@ -42,6 +45,7 @@ config ESP32P4_REV_MIN_FULL
default 1 if ESP32P4_REV_MIN_1
default 100 if ESP32P4_REV_MIN_100
default 300 if ESP32P4_REV_MIN_300
default 301 if ESP32P4_REV_MIN_301
config ESP_REV_MIN_FULL
int
components/esp_hw_support/port/esp32p4/esp_clk_tree.c
+7
View File
@@ -8,6 +8,7 @@
#include "esp_clk_tree.h"
#include "esp_err.h"
#include "esp_check.h"
#include "soc/clk_tree_defs.h"
#include "soc/rtc.h"
#include "hal/clk_gate_ll.h"
#include "hal/clk_tree_hal.h"
@@ -32,6 +33,12 @@ esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_sr
case SOC_MOD_CLK_XTAL:
clk_src_freq = clk_hal_xtal_get_freq_mhz() * MHZ;
break;
case SOC_MOD_CLK_SYS:
clk_src_freq = clk_hal_sys_get_freq_hz();
break;
case SOC_MOD_CLK_APB:
clk_src_freq = clk_hal_apb_get_freq_hz();
break;
case SOC_MOD_CLK_PLL_F20M:
clk_src_freq = CLK_LL_PLL_480M_FREQ_MHZ / clk_ll_pll_f20m_get_divider() * MHZ;
break;
components/esp_hw_support/port/esp32p4/pmu_sleep.c
+6 -3
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -221,11 +221,14 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
config->analog = analog_default;
}
if ((sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) || (sleep_flags & RTC_SLEEP_XTAL_AS_RTC_FAST)) {
config->analog.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
config->analog.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
}
if (sleep_flags & RTC_SLEEP_XTAL_AS_RTC_FAST) {
// Keep XTAL on in HP_SLEEP state if it is the clock source of RTC_FAST
power_default.hp_sys.xtal.xpd_xtal = 1;
config->analog.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
config->analog.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
config->analog.hp_sys.analog.dbg_atten = PMU_DBG_ATTEN_ACTIVE_DEFAULT;
config->analog.hp_sys.analog.dbias = HP_CALI_ACTIVE_DBIAS_DEFAULT;
}
components/esp_hw_support/port/esp32p4/rtc_clk_init.c
+10 -1
View File
@@ -68,15 +68,24 @@ void rtc_clk_init(rtc_clk_config_t cfg)
hp_dcmvset = pvt_hp_dcmvset;
}
// Switch to DCDC
#if CONFIG_ESP32P4_REV_MIN_301
unsigned chip_version = efuse_hal_chip_revision();
if (ESP_CHIP_REV_ABOVE(chip_version, 301)) {
SET_PERI_REG_MASK(PMU_DCM_CTRL_REG, PMU_DCDC_FB_RES_FORCE_PD);
}
#endif
pmu_ll_set_dcdc_en(&PMU, true);
pmu_ll_set_dcdc_switch_force_power_down(&PMU, false);
pmu_ll_hp_set_dcm_vset(&PMU, PMU_MODE_HP_ACTIVE, hp_dcmvset);
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // Hand over control of dbias to pmu
esp_rom_delay_us(1000);
unsigned chip_version = efuse_hal_chip_revision();
#if CONFIG_ESP32P4_REV_MIN_301
if (ESP_CHIP_REV_ABOVE(chip_version, 301)) {
REG_SET_FIELD(LP_SYSTEM_REG_SYS_CTRL_REG, LP_SYSTEM_REG_LP_FIB_SEL, 0xEF);// lp_fib_sel bit4 set to 0: select dig_fib_reg instead of ana_fib_reg
CLEAR_PERI_REG_MASK(PMU_DCM_CTRL_REG, PMU_DCDC_FB_RES_FORCE_PD);
esp_rom_delay_us(10);
}
#endif
pmu_ll_hp_set_regulator_xpd(&PMU, PMU_MODE_HP_ACTIVE, false);
soc_xtal_freq_t xtal_freq = cfg.xtal_freq;
components/esp_hw_support/sleep_modes.c
+15 -6
View File
@@ -40,6 +40,10 @@
#include "hal/rtc_io_hal.h"
#include "hal/clk_tree_hal.h"
#if __has_include("hal/rng_ll.h")
#include "hal/rng_ll.h"
#endif
#if SOC_SLEEP_SYSTIMER_STALL_WORKAROUND
#include "hal/systimer_ll.h"
#endif
@@ -751,7 +755,7 @@ static SLEEP_FN_ATTR void misc_modules_sleep_prepare(uint32_t sleep_flags, bool
regi2c_tsens_reg_read();
#endif
}
#if CONFIG_ESP_ENABLE_PVT
#if CONFIG_ESP_ENABLE_PVT && SOC_PVT_EN_WITH_SLEEP
pvt_func_enable(false);
#endif
@@ -766,7 +770,7 @@ static SLEEP_FN_ATTR void misc_modules_sleep_prepare(uint32_t sleep_flags, bool
*/
static SLEEP_FN_ATTR void misc_modules_wake_prepare(uint32_t sleep_flags)
{
#if CONFIG_ESP_ENABLE_PVT
#if CONFIG_ESP_ENABLE_PVT && SOC_PVT_EN_WITH_SLEEP
pvt_func_enable(true);
#endif
@@ -810,6 +814,13 @@ static SLEEP_FN_ATTR void misc_modules_wake_prepare(uint32_t sleep_flags)
#if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
regi2c_tsens_reg_write();
#endif
#if RNG_LL_DEPENDS_ON_LP_PERIPH
if (sleep_flags & PMU_SLEEP_PD_LP_PERIPH) {
// Re-enable the RNG module.
rng_ll_reset();
rng_ll_enable();
}
#endif
}
static SLEEP_FN_ATTR void sleep_low_power_clock_calibration(bool is_dslp)
@@ -2706,7 +2717,8 @@ static SLEEP_FN_ATTR uint32_t get_power_down_flags(void)
#endif
#if SOC_PM_SUPPORT_CNNT_PD
if (s_config.domain[ESP_PD_DOMAIN_CNNT].pd_option != ESP_PD_OPTION_ON && top_domain_pd_allowed()) {
// The TOP domain depends on the CNNT domain, only after the TOP power domain has been powered off is the CNNT power domain allowed to power down.
if (s_config.domain[ESP_PD_DOMAIN_CNNT].pd_option != ESP_PD_OPTION_ON && (pd_flags & PMU_SLEEP_PD_TOP)) {
pd_flags |= PMU_SLEEP_PD_CNNT;
}
#endif
@@ -2737,9 +2749,6 @@ static SLEEP_FN_ATTR uint32_t get_power_down_flags(void)
// TOP power domain depends on the RTC_PERIPH power domain on ESP32C6, RTC_PERIPH should only be disabled when the TOP domain is down.
pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
}
#elif CONFIG_IDF_TARGET_ESP32C5
// TODO: [ESP32C5] PM-642 RNG module depends on LP PERIPH domain, force it on temporary.
pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
#endif
return pd_flags;
}
components/esp_hw_support/sleep_system_peripheral.c
+1 -1
View File
@@ -164,7 +164,7 @@ static __attribute__((unused)) esp_err_t sleep_sys_periph_retention_init(void *a
err = sleep_pau_retention_init();
if(err) goto error;
#endif
#if CONFIG_ESP_ENABLE_PVT
#if CONFIG_ESP_ENABLE_PVT && SOC_PVT_RETENTION_BY_REGDMA
err = sleep_pvt_retention_init();
if(err) goto error;
#endif
components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c
+11 -4
View File
@@ -16,6 +16,8 @@
#include "freertos/semphr.h"
#include "ccomp_timer.h"
#include "esp_async_memcpy.h"
#include "hal/efuse_hal.h"
#if SOC_GDMA_SUPPORTED
#include "hal/gdma_ll.h"
#endif
@@ -148,17 +150,19 @@ static bool test_async_memcpy_cb_v1(async_memcpy_handle_t mcp_hdl, async_memcpy_
static void test_memory_copy_blocking(async_memcpy_handle_t driver)
{
SemaphoreHandle_t sem = xSemaphoreCreateBinary();
const uint32_t test_buffer_size[] = {256, 512, 1024, 2048, 4096, 5012};
const uint32_t test_buffer_size[] = {256, 512, 1024, 2048, 4096, 5008};
memcpy_testbench_context_t test_context = {
.align = 4,
.align = 16,
};
for (int i = 0; i < sizeof(test_buffer_size) / sizeof(test_buffer_size[0]); i++) {
// Test different align edge
for (int off = 0; off < 4; off++) {
test_context.buffer_size = test_buffer_size[i];
test_context.seed = i;
test_context.src_offset = off;
test_context.dst_offset = off;
if (!efuse_hal_flash_encryption_enabled()) {
test_context.src_offset = off;
test_context.dst_offset = off;
}
async_memcpy_setup_testbench(&test_context);
TEST_ESP_OK(esp_async_memcpy(driver, test_context.to_addr, test_context.from_addr, test_context.copy_size, test_async_memcpy_cb_v1, sem));
@@ -235,6 +239,9 @@ TEST_CASE("memory copy with dest address unaligned", "[async mcp]")
};
[[maybe_unused]] async_memcpy_handle_t driver = NULL;
if (efuse_hal_flash_encryption_enabled()) {
TEST_PASS_MESSAGE("Flash encryption is enabled, skip this test");
}
#if SOC_CP_DMA_SUPPORTED
printf("Testing memcpy by CP DMA\r\n");
components/esp_hw_support/test_apps/dma/main/test_dw_gdma.c
+4
View File
@@ -11,6 +11,7 @@
#include "unity.h"
#include "esp_private/dw_gdma.h"
#include "hal/dw_gdma_ll.h"
#include "hal/efuse_hal.h"
#include "esp_cache.h"
#include "esp_private/esp_cache_private.h"
@@ -540,6 +541,9 @@ TEST_CASE("DW_GDMA M2M Test: memory set with fixed address", "[DW_GDMA]")
size_t int_mem_alignment = 0;
TEST_ESP_OK(esp_cache_get_alignment(MALLOC_CAP_SPIRAM, &ext_mem_alignment));
TEST_ESP_OK(esp_cache_get_alignment(0, &int_mem_alignment));
if (efuse_hal_flash_encryption_enabled()) {
TEST_PASS_MESSAGE("Flash encryption is enabled, skip this test");
}
uint8_t *src_buf = heap_caps_aligned_calloc(ext_mem_alignment, 1, 256, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
uint8_t *dst_buf = heap_caps_aligned_calloc(int_mem_alignment, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
TEST_ASSERT_NOT_NULL(src_buf);
components/esp_hw_support/test_apps/dma/main/test_gdma.c
+38 -10
View File
@@ -20,6 +20,7 @@
#include "hal/gdma_ll.h"
#include "hal/cache_ll.h"
#include "hal/cache_hal.h"
#include "hal/efuse_hal.h"
#include "esp_cache.h"
#include "esp_memory_utils.h"
#include "gdma_test_utils.h"
@@ -173,7 +174,8 @@ TEST_CASE("GDMA channel allocation", "[GDMA]")
}
static void test_gdma_config_link_list(gdma_channel_handle_t tx_chan, gdma_channel_handle_t rx_chan,
gdma_link_list_handle_t *tx_link_list, gdma_link_list_handle_t *rx_link_list, bool dma_link_in_ext_mem)
gdma_link_list_handle_t *tx_link_list, gdma_link_list_handle_t *rx_link_list,
size_t burst_size, bool dma_link_in_ext_mem)
{
gdma_strategy_config_t strategy = {
@@ -183,6 +185,15 @@ static void test_gdma_config_link_list(gdma_channel_handle_t tx_chan, gdma_chann
TEST_ESP_OK(gdma_apply_strategy(tx_chan, &strategy));
TEST_ESP_OK(gdma_apply_strategy(rx_chan, &strategy));
gdma_transfer_config_t transfer_cfg = {
.max_data_burst_size = burst_size,
#if SOC_DMA_CAN_ACCESS_FLASH
.access_ext_mem = true,
#endif
};
TEST_ESP_OK(gdma_config_transfer(tx_chan, &transfer_cfg));
TEST_ESP_OK(gdma_config_transfer(rx_chan, &transfer_cfg));
gdma_trigger_t m2m_trigger = GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0);
// get a free DMA trigger ID for memory copy
uint32_t free_m2m_id_mask = 0;
@@ -231,16 +242,24 @@ static void test_gdma_m2m_transaction(gdma_channel_handle_t tx_chan, gdma_channe
TEST_ASSERT_NOT_NULL(done_sem);
TEST_ESP_OK(gdma_register_rx_event_callbacks(rx_chan, &rx_cbs, done_sem));
if (efuse_hal_flash_encryption_enabled()) {
dma_link_in_ext_mem = false;
}
gdma_link_list_handle_t tx_link_list = NULL;
gdma_link_list_handle_t rx_link_list = NULL;
test_gdma_config_link_list(tx_chan, rx_chan, &tx_link_list, &rx_link_list, dma_link_in_ext_mem);
test_gdma_config_link_list(tx_chan, rx_chan, &tx_link_list, &rx_link_list, 16, dma_link_in_ext_mem);
size_t int_mem_alignment = 0;
size_t ext_mem_alignment = 0;
TEST_ESP_OK(gdma_get_alignment_constraints(tx_chan, &int_mem_alignment, &ext_mem_alignment));
// allocate the source buffer from SRAM
uint8_t *src_data = heap_caps_calloc(1, 128, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
uint8_t *src_data = heap_caps_aligned_calloc(int_mem_alignment, 1, 128, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
TEST_ASSERT_NOT_NULL(src_data);
// allocate the destination buffer from SRAM
uint8_t *dst_data = heap_caps_calloc(1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
uint8_t *dst_data = heap_caps_aligned_calloc(int_mem_alignment, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
TEST_ASSERT_NOT_NULL(dst_data);
// prepare the source data
@@ -253,7 +272,7 @@ static void test_gdma_m2m_transaction(gdma_channel_handle_t tx_chan, gdma_channe
}
// test DMA can read data from main flash
#if SOC_DMA_CAN_ACCESS_FLASH
const char *src_string = "GDMA can read data from MSPI Flash";
static const char src_string[] __attribute__((aligned(GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT))) = "GDMA can read MSPI Flash data!!!";
size_t src_string_len = strlen(src_string);
TEST_ASSERT_TRUE(esp_ptr_in_drom(src_string));
@@ -268,12 +287,12 @@ static void test_gdma_m2m_transaction(gdma_channel_handle_t tx_chan, gdma_channe
gdma_buffer_mount_config_t tx_buf_mount_config[] = {
[0] = {
.buffer = src_data,
.buffer_alignment = 1,
.buffer_alignment = int_mem_alignment,
.length = 64,
},
[1] = {
.buffer = src_data + 64,
.buffer_alignment = 1,
.buffer_alignment = int_mem_alignment,
.length = 64,
#if !SOC_DMA_CAN_ACCESS_FLASH
.flags = {
@@ -285,7 +304,7 @@ static void test_gdma_m2m_transaction(gdma_channel_handle_t tx_chan, gdma_channe
#if SOC_DMA_CAN_ACCESS_FLASH
[2] = {
.buffer = (void *)src_string,
.buffer_alignment = 1,
.buffer_alignment = ext_mem_alignment,
.length = src_string_len,
.flags = {
.mark_eof = true,
@@ -412,6 +431,8 @@ static void test_gdma_m2m_unaligned_buffer_test(uint8_t *dst_data, uint8_t *src_
{
TEST_ASSERT_NOT_NULL(src_data);
TEST_ASSERT_NOT_NULL(dst_data);
memset(src_data, 0, data_length + offset_len);
memset(dst_data, 0, data_length + offset_len);
gdma_channel_handle_t tx_chan = NULL;
gdma_channel_handle_t rx_chan = NULL;
gdma_channel_alloc_config_t tx_chan_alloc_config = {};
@@ -430,7 +451,10 @@ static void test_gdma_m2m_unaligned_buffer_test(uint8_t *dst_data, uint8_t *src_
gdma_link_list_handle_t tx_link_list = NULL;
gdma_link_list_handle_t rx_link_list = NULL;
test_gdma_config_link_list(tx_chan, rx_chan, &tx_link_list, &rx_link_list, false);
test_gdma_config_link_list(tx_chan, rx_chan, &tx_link_list, &rx_link_list, 0, false);
size_t rx_mem_alignment = 0;
TEST_ESP_OK(gdma_get_alignment_constraints(rx_chan, &rx_mem_alignment, NULL));
// prepare the source data
for (int i = 0; i < data_length; i++) {
@@ -460,7 +484,7 @@ static void test_gdma_m2m_unaligned_buffer_test(uint8_t *dst_data, uint8_t *src_
TEST_ESP_OK(esp_dma_split_rx_buffer_to_cache_aligned(dst_data + offset_len, data_length, &align_array, &stash_buffer));
for (int i = 0; i < 3; i++) {
rx_aligned_buf_mount_config[i].buffer = align_array.aligned_buffer[i].aligned_buffer;
rx_aligned_buf_mount_config[i].buffer_alignment = sram_alignment;
rx_aligned_buf_mount_config[i].buffer_alignment = MAX(sram_alignment, rx_mem_alignment);
rx_aligned_buf_mount_config[i].length = align_array.aligned_buffer[i].length;
}
TEST_ESP_OK(gdma_link_mount_buffers(rx_link_list, 0, rx_aligned_buf_mount_config, 3, NULL));
@@ -496,6 +520,10 @@ static void test_gdma_m2m_unaligned_buffer_test(uint8_t *dst_data, uint8_t *src_
TEST_CASE("GDMA M2M Unaligned RX Buffer Test", "[GDMA][M2M]")
{
if (efuse_hal_flash_encryption_enabled()) {
TEST_PASS_MESSAGE("Flash encryption is enabled, skip this test");
}
uint8_t *sbuf = heap_caps_aligned_calloc(64, 1, 10240, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
uint8_t *dbuf = heap_caps_aligned_calloc(64, 1, 10240, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
components/esp_hw_support/test_apps/dma/main/test_gdma_crc.c
+17 -6
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -17,6 +17,7 @@
#include "soc/soc_caps.h"
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "hal/gdma_ll.h"
#include "esp_cache.h"
typedef struct {
@@ -32,37 +33,47 @@ static test_crc_case_t crc_test_cases[] = {
.crc_bit_width = 8,
.init_value = 0x00,
.poly_hex = 0x07,
.expected_result = 0xC6,
.expected_result = 0xB8,
},
[1] = {
.crc_bit_width = 8,
.init_value = 0x00,
.poly_hex = 0x07,
.reverse_data_mask = true, // refin = true
.expected_result = 0xDE,
.expected_result = 0xF0,
},
// CRC16, x^16+x^12+x^5+1
[2] = {
.crc_bit_width = 16,
.init_value = 0xFFFF,
.poly_hex = 0x1021,
.expected_result = 0x5289,
.expected_result = 0xA9B2,
},
// CRC32, x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
[3] = {
.crc_bit_width = 32,
.init_value = 0xFFFFFFFF,
.poly_hex = 0x04C11DB7,
.expected_result = 0x63B3E283,
.expected_result = 0x692F6C7E,
}
};
// CRC online: https://www.lddgo.net/en/encrypt/crc
static void test_gdma_crc_calculation(gdma_channel_handle_t tx_chan, int test_num_crc_algorithm)
{
// Note, burst size should be at least 16 when accessing encrypted external memory
gdma_transfer_config_t transfer_cfg = {
.max_data_burst_size = 16,
.access_ext_mem = true,
};
TEST_ESP_OK(gdma_config_transfer(tx_chan, &transfer_cfg));
uint32_t crc_result = 0;
const char *test_input_string = "Share::Connect::Innovate";
static const char test_input_string[] __attribute__((aligned(GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT))) = "GDMACRC Share::Connect::Innovate";
size_t input_data_size = strlen(test_input_string);
TEST_ASSERT_EQUAL((uintptr_t)test_input_string % GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT, 0);
// this test case also test the GDMA can fetch data from MSPI Flash
TEST_ASSERT_TRUE(esp_ptr_in_drom(test_input_string));
printf("Calculate CRC value for string: \"%s\"\r\n", test_input_string);
components/esp_hw_support/test_apps/dma/pytest_dma.py
+26
View File
@@ -33,3 +33,29 @@ def test_dma(dut: Dut) -> None:
@idf_parametrize('target', ['esp32s3'], indirect=['target'])
def test_dma_psram(dut: Dut) -> None:
dut.run_all_single_board_cases(reset=True)
@pytest.mark.flash_encryption
@pytest.mark.parametrize(
'config',
[
'ext_mem_encryption',
],
indirect=True,
)
@idf_parametrize('target', ['esp32p4', 'esp32c5'], indirect=['target'])
def test_dma_ext_mem_encryption(dut: Dut) -> None:
dut.run_all_single_board_cases(reset=True)
@pytest.mark.flash_encryption_f4r8
@pytest.mark.parametrize(
'config',
[
'ext_mem_encryption',
],
indirect=True,
)
@idf_parametrize('target', ['esp32s3'], indirect=['target'])
def test_dma_ext_mem_encryption_s3_f4r8(dut: Dut) -> None:
dut.run_all_single_board_cases(reset=True)
components/esp_hw_support/test_apps/dma/sdkconfig.ci.ext_mem_encryption
+9
View File
@@ -0,0 +1,9 @@
CONFIG_PARTITION_TABLE_OFFSET=0x9000
CONFIG_SECURE_FLASH_ENC_ENABLED=y
CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT=y
CONFIG_SECURE_BOOT_ALLOW_ROM_BASIC=y
CONFIG_SECURE_BOOT_ALLOW_JTAG=y
CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC=y
CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC=y
CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE=y
CONFIG_SECURE_FLASH_REQUIRE_ALREADY_ENABLED=y
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_random.c
+65
View File
@@ -5,9 +5,20 @@
*/
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <inttypes.h>
#include "sdkconfig.h"
#include "soc/soc_caps.h"
#include "unity.h"
#include "esp_random.h"
#if SOC_LIGHT_SLEEP_SUPPORTED
#include "esp_sleep.h"
#include "esp_private/esp_sleep_internal.h"
#include "esp_private/sleep_cpu.h"
#include "esp_private/esp_pmu.h"
#endif
/* Note: these are just sanity tests, not the same as
entropy tests
*/
@@ -69,3 +80,57 @@ TEST_CASE("call esp_fill_random()", "[random]")
TEST_ASSERT_EQUAL_HEX8(0xFF, one_buf[x]);
}
}
TEST_CASE("verify esp_random() bit balance 0/1 ratio", "[random]")
{
#if SOC_LIGHT_SLEEP_SUPPORTED
esp_sleep_context_t sleep_ctx;
esp_sleep_set_sleep_context(&sleep_ctx);
printf("go to light sleep for 1 seconds\r\n");
#if ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(true));
#endif
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
TEST_ESP_OK(esp_light_sleep_start());
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && !SOC_PM_TOP_PD_NOT_ALLOWED
// check if the power domain also is powered down
TEST_ASSERT_EQUAL(PMU_SLEEP_PD_TOP, (sleep_ctx.sleep_flags) & PMU_SLEEP_PD_TOP);
#endif
esp_sleep_set_sleep_context(NULL);
printf("Waked up! Let's see if esp_random can still work correctly...\r\n");
#if ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(false));
#endif
#endif
const size_t NUM_RANDOM = 50000; /* Need enough samples for statistical significance */
const float EXPECTED_RATIO = 0.5f; /* Expected ratio of 1s */
const float TOLERANCE = 0.01f; /* Allow 1% deviation (49%-51%) */
uint32_t bit_counts[32] = {0}; /* Count of 1s for each bit position */
/* Collect random numbers and count 1s in each bit position */
for (int i = 0; i < NUM_RANDOM; i++) {
uint32_t r = esp_random();
for (int bit = 0; bit < 32; bit++) {
if (r & (1U << bit)) {
bit_counts[bit]++;
}
}
}
/* Verify each bit position has approximately 50% ones */
printf("\nBit balance statistics (total samples: %zu):\n", NUM_RANDOM);
printf("Bit | 1s count | 0s count | 1s ratio | 0s ratio | Deviation\n");
printf("----|----------|----------|----------|----------|----------\n");
for (int bit = 0; bit < 32; bit++) {
uint32_t ones_count = bit_counts[bit];
uint32_t zeros_count = NUM_RANDOM - ones_count;
float ratio_ones = (float)ones_count / NUM_RANDOM;
float ratio_zeros = (float)zeros_count / NUM_RANDOM;
float deviation = fabs(ratio_ones - EXPECTED_RATIO);
printf("%3d | %8" PRIu32 " | %8" PRIu32 " | %8.4f | %8.4f | %9.4f\n",
bit, ones_count, zeros_count, ratio_ones, ratio_zeros, deviation);
/* Check if ratio is within tolerance */
TEST_ASSERT_LESS_THAN_FLOAT(TOLERANCE, deviation);
}
}
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.ci.release
+2
View File
@@ -4,3 +4,5 @@ CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
# we can silent the assertion to save the binary footprint
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.defaults
+3
View File
@@ -6,3 +6,6 @@ CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
# we can silent the assertion to save the binary footprint
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
# primitives for checking sleep internal state
CONFIG_ESP_SLEEP_DEBUG=y
components/esp_mm/heap_align_hw.c
+9 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,9 +9,11 @@
#include "sdkconfig.h"
#include "esp_heap_caps.h"
#include "esp_private/esp_cache_private.h"
#include "esp_private/gdma.h"
#include "soc/soc_caps.h"
#if SOC_GDMA_SUPPORTED
#include "hal/gdma_ll.h"
#include "hal/efuse_hal.h"
#endif
#if CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH
@@ -80,6 +82,12 @@ HEAP_IRAM_ATTR void esp_heap_adjust_alignment_to_hw(size_t *p_alignment, size_t
}
#endif
#if SOC_GDMA_SUPPORTED && (SOC_PSRAM_DMA_CAPABLE || SOC_DMA_CAN_ACCESS_FLASH)
if ((caps & MALLOC_CAP_DMA) && efuse_hal_flash_encryption_enabled()) {
alignment = (alignment > GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT) ? alignment : GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT;
}
#endif
// Align up `size` to resulting alignment as well.
size = (size + alignment - 1) & (~(alignment - 1));
components/esp_netif/test_apps/.build-test-rules.yml
+1 -1
View File
@@ -13,7 +13,7 @@ components/esp_netif/test_apps/test_app_esp_netif:
components/esp_netif/test_apps/test_app_vfs_l2tap:
disable:
- if: IDF_TARGET not in ["esp32"] # TODO: IDF-14365
- if: IDF_TARGET not in ["esp32", "esp32p4"]
temporary: true
reason: Not needed to test on all targets (chosen two, one for each architecture plus P4 tests time stamping)
depends_components:
components/esp_netif/test_apps/test_app_vfs_l2tap/README.md
+2 -2
View File
@@ -1,2 +1,2 @@
| Supported Targets | ESP32 |
| ----------------- | ----- |
| Supported Targets | ESP32 | ESP32-P4 |
| ----------------- | ----- | -------- |
components/esp_netif/test_apps/test_app_vfs_l2tap/pytest_esp_vfs_l2tap.py
+4 -20
View File
@@ -2,31 +2,15 @@
# SPDX-License-Identifier: CC0-1.0
import pytest
from pytest_embedded import Dut
from pytest_embedded_idf.utils import idf_parametrize
@pytest.mark.ethernet
@pytest.mark.parametrize(
'config',
'config, target',
[
'defaults',
pytest.param('default_esp32', 'esp32', marks=[pytest.mark.eth_ip101]),
pytest.param('default_esp32p4', 'esp32p4', marks=[pytest.mark.eth_ip101]),
],
indirect=True,
indirect=['target'],
)
@idf_parametrize('target', ['esp32'], indirect=['target'])
def test_esp_netif_vfs_l2tp(dut: Dut) -> None:
dut.run_all_single_board_cases()
@pytest.mark.eth_ip101
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14365')
@pytest.mark.parametrize(
'config',
[
'defaults',
],
indirect=True,
)
@idf_parametrize('target', ['esp32p4'], indirect=['target'])
def test_esp_netif_vfs_l2tp_p4(dut: Dut) -> None:
dut.run_all_single_board_cases()
components/esp_netif/test_apps/test_app_vfs_l2tap/sdkconfig.ci.default_esp32
+1
View File
@@ -0,0 +1 @@
CONFIG_IDF_TARGET="esp32"
components/esp_netif/test_apps/test_app_vfs_l2tap/sdkconfig.ci.default_esp32p4
+1
View File
@@ -0,0 +1 @@
CONFIG_IDF_TARGET="esp32p4"
components/esp_netif/test_apps/test_app_vfs_l2tap/sdkconfig.ci.defaults → components/esp_netif/test_apps/test_app_vfs_l2tap/sdkconfig.defaults
View File
components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld
+2 -2
View File
@@ -15,7 +15,7 @@ esf_buf_recycle = 0x40001ae8;
hal_mac_tx_set_ppdu = 0x40001af8;
ic_mac_deinit = 0x40001b00;
lmacAdjustTimestamp = 0x40001b10;
lmacDiscardMSDU = 0x40001b18;
/*lmacDiscardMSDU = 0x40001b18;*/
lmacEndFrameExchangeSequence = 0x40001b1c;
lmacMSDUAged = 0x40001b28;
//lmacSetTxFrame = 0x40001b4c;
@@ -30,7 +30,7 @@ pm_sleep = 0x40001bbc;
//pm_tbtt_process = 0x40001bc4;
ppAssembleAMPDU = 0x40001bcc;
ppCalTxAMPDULength = 0x40001bd8;
ppRxFragmentProc = 0x40001c28;
/*ppRxFragmentProc = 0x40001c28;*/
ppRxPkt = 0x40001c2c;
pp_coex_tx_request = 0x40001c54;
/* rcGetSched = 0x40001c88; */
components/esp_rom/esp32c2/ld/esp32c2.rom.ld
+1 -1
View File
@@ -711,7 +711,7 @@ wDev_Rxbuf_Deinit = 0x40001e5c;
ppCalTkipMic = 0x40001e60;
wDev_SnifferRxData = 0x40001e64;
hal_crypto_enable = 0x40001e68;
hal_crypto_disable = 0x40001e6c;
/*hal_crypto_disable = 0x40001e6c;*/
wDev_Insert_KeyEntry = 0x40001e70;
wDev_remove_KeyEntry = 0x40001e74;
rc_enable_trc = 0x40001e78;
components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld
+1 -1
View File
@@ -8,7 +8,7 @@ esf_buf_alloc_dynamic = 0x400015c0;
esf_buf_recycle = 0x400015c4;
/*hal_mac_tx_set_ppdu = 0x400015d4;*/
ic_mac_deinit = 0x400015dc;
lmacDiscardMSDU = 0x400015f4;
/*lmacDiscardMSDU = 0x400015f4;*/
/*lmacSetTxFrame = 0x40001628;*/
lmacTxDone = 0x4000162c;
/*lmacTxFrame = 0x40001630;*/
components/esp_rom/esp32c5/Kconfig.soc_caps.in
+4
View File
@@ -122,3 +122,7 @@ config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
config ESP_ROM_DELAY_US_PATCH
bool
default y
config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
bool
default y
components/esp_rom/esp32c5/esp_rom_caps.h
+1
View File
@@ -36,3 +36,4 @@
#define ESP_ROM_CLIC_INT_THRESH_PATCH (1) // ROM version of esprv_intc_int_set_threshold incorrectly assumes lowest MINTTHRESH is 0x1F, should be 0xF
#define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access.
#define ESP_ROM_DELAY_US_PATCH (1) // ROM ets_delay_us needs patch for U-mode operation
#define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP (1) // ROM supports the secure boot fast wakeup feature
components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld
+2 -2
View File
@@ -59,7 +59,7 @@ is_lmac_idle = 0x40000c84;
ic_get_he_rts_threshold_bytes = 0x40000c88;
lmacAdjustTimestamp = 0x40000c8c;
lmacDiscardAgedMSDU = 0x40000c90;
lmacDiscardMSDU = 0x40000c94;
/*lmacDiscardMSDU = 0x40000c94;*/
lmacEndFrameExchangeSequence = 0x40000c98;
lmacIsIdle = 0x40000c9c;
lmacIsLongFrame = 0x40000ca0;
@@ -184,7 +184,7 @@ ppRecycleAmpdu = 0x40000e78;
ppRecycleRxPkt = 0x40000e7c;
ppResortTxAMPDU = 0x40000e80;
ppResumeTxAMPDU = 0x40000e84;
ppRxFragmentProc = 0x40000e88;
/*ppRxFragmentProc = 0x40000e88;*/
/* ppRxPkt = 0x40000e8c; */
/* ppRxProtoProc = 0x40000e90; */
ppSearchTxQueue = 0x40000e94;
components/esp_rom/esp32c6/Kconfig.soc_caps.in
+4
View File
@@ -126,3 +126,7 @@ config ESP_ROM_NO_USB_SERIAL_OUTPUT_API
config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
bool
default y
config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
bool
default y
components/esp_rom/esp32c6/esp_rom_caps.h
+1
View File
@@ -37,3 +37,4 @@
#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
#define ESP_ROM_NO_USB_SERIAL_OUTPUT_API (1) // ROM does not export the usb-serial-jtag write char function
#define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access.
#define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP (1) // ROM supports the secure boot fast wakeup feature
components/esp_rom/esp32c61/ld/esp32c61.rom.eco4.ld
+1 -1
View File
@@ -36,7 +36,7 @@ pm_clear_wakeup_signal = 0x40000d78;
pm_mac_disable_tsf_tbtt_soc_wakeup = 0x40000d7c;
pm_mac_disable_tsf_tbtt_modem_wakeup = 0x40000d80;
pm_mac_enable_tsf_tbtt_soc_wakeup = 0x40000d84;
pm_mac_enable_tsf_tbtt_modem_wakeup = 0x40000d88;
//pm_mac_enable_tsf_tbtt_modem_wakeup = 0x40000d88;
//pm_mac_modem_params_rt_update = 0x40000d8c;
pm_coex_pwr_update = 0x40000d9c;
ppMapTxQueue = 0x40000ddc;
components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld
+2 -2
View File
@@ -57,7 +57,7 @@ is_lmac_idle = 0x40000bf4;
ic_get_he_rts_threshold_bytes = 0x40000bf8;
lmacAdjustTimestamp = 0x40000bfc;
lmacDiscardAgedMSDU = 0x40000c00;
lmacDiscardMSDU = 0x40000c04;
/*lmacDiscardMSDU = 0x40000c04;*/
lmacEndFrameExchangeSequence = 0x40000c08;
lmacIsIdle = 0x40000c0c;
lmacIsLongFrame = 0x40000c10;
@@ -184,7 +184,7 @@ ppRecycleAmpdu = 0x40000df0;
ppRecycleRxPkt = 0x40000df4;
ppResortTxAMPDU = 0x40000df8;
ppResumeTxAMPDU = 0x40000dfc;
ppRxFragmentProc = 0x40000e00;
/*ppRxFragmentProc = 0x40000e00;*/
/*ppRxPkt = 0x40000e04;*/
/*ppRxProtoProc = 0x40000e08;*/
ppSearchTxQueue = 0x40000e0c;
components/esp_rom/esp32h2/Kconfig.soc_caps.in
+4
View File
@@ -118,3 +118,7 @@ config ESP_ROM_NO_USB_SERIAL_OUTPUT_API
config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
bool
default y
config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
bool
default y
components/esp_rom/esp32h2/esp_rom_caps.h
+1
View File
@@ -35,3 +35,4 @@
#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
#define ESP_ROM_NO_USB_SERIAL_OUTPUT_API (1) // ROM does not export the usb-serial-jtag write char function
#define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access.
#define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP (1) // ROM supports the secure boot fast wakeup feature
components/esp_rom/esp32h21/Kconfig.soc_caps.in
+4
View File
@@ -98,3 +98,7 @@ config ESP_ROM_HAS_OUTPUT_PUTC_FUNC
config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
bool
default y
config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
bool
default y
components/esp_rom/esp32h21/esp_rom_caps.h
+1
View File
@@ -31,3 +31,4 @@
// #define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB (1) // ROM supports the HP core to jump to the RTC memory to execute stub code after waking up from deepsleep. //TODO: [ESP32H21] IDF-11515
#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
#define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access.
#define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP (1) // ROM supports the secure boot fast wakeup feature
components/esp_rom/esp32s3/ld/esp32s3.rom.ld
+1 -1
View File
@@ -955,7 +955,7 @@ lmacReachShortLimit = 0x40005394;
lmacRecycleMPDU = 0x400053a0;
lmacRxDone = 0x400053ac;
/*lmacSetTxFrame = 0x400053b8;*/
lmacTxDone = 0x400053c4;
/*lmacTxDone = 0x400053c4;*/
/*lmacTxFrame = 0x400053d0;*/
mac_tx_set_duration = 0x400053dc;
/* mac_tx_set_htsig = 0x400053e8;*/
components/esp_system/ld/ld.common
+9
View File
@@ -11,6 +11,13 @@
/* CPU instruction prefetch padding size for flash mmap scenario */
#define _esp_flash_mmap_prefetch_pad_size 16
/* Copy from esp_secure_boot.h */
#ifdef CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS
#define ESP_SECURE_BOOT_DIGEST_LEN 48
#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
#define ESP_SECURE_BOOT_DIGEST_LEN 32
#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
/*
* PMP region granularity size
* Software may determine the PMP granularity by writing zero to pmp0cfg, then writing all ones
@@ -70,6 +77,8 @@
has the required alignment */
#define ULP_ALIGNMENT_REQ_BYTES 256
#define RESERVE_RTC_MEM ALIGN_UP(ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC, ULP_ALIGNMENT_REQ_BYTES)
#elif CONFIG_SECURE_BOOT && CONFIG_ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
#define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC + ESP_SECURE_BOOT_DIGEST_LEN)
#else
#define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC)
#endif
components/esp_system/port/cpu_start.c
+21 -6
View File
@@ -547,7 +547,8 @@ MSPI_INIT_ATTR void sys_rtc_init(const soc_reset_reason_t *rst_reas)
esp_rtc_init();
}
NOINLINE_ATTR IRAM_ATTR void flash_init_state(void)
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
static NOINLINE_ATTR IRAM_ATTR void flash_init_state(void)
{
/**
* This function initialise the Flash chip to the user-defined settings.
@@ -564,7 +565,6 @@ NOINLINE_ATTR IRAM_ATTR void flash_init_state(void)
#endif
}
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
MSPI_INIT_ATTR void mspi_init(void)
{
#if CONFIG_ESPTOOLPY_OCT_FLASH && !CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT
@@ -612,6 +612,20 @@ MSPI_INIT_ATTR void mspi_init(void)
}
#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
#if CONFIG_IDF_TARGET_ESP32 && !CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_SPIRAM_BOOT_HW_INIT
/*
* Adjust flash configuration. This must be placed in IRAM because running from flash,
* while it is being reconfigured, will result in corrupt data being read.
*/
NOINLINE_ATTR IRAM_ATTR static void configure_flash(esp_image_header_t *fhdr)
{
bootloader_flash_gpio_config(fhdr);
bootloader_flash_dummy_config(fhdr);
bootloader_flash_clock_config(fhdr);
bootloader_flash_cs_timing_config();
}
#endif // CONFIG_IDF_TARGET_ESP32 && !CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_SPIRAM_BOOT_HW_INIT
/*
* Initialize other parts of the system, including other CPUs.
* As CPU0 needs to disable the cache in system_early_init function, the other cores are not allowed to run with the
@@ -643,6 +657,10 @@ NOINLINE_ATTR static void system_early_init(const soc_reset_reason_t *rst_reas)
#if SOC_CPU_CORES_NUM > 1 // there is no 'single-core mode' for natively single-core processors
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_REV_MIN_FULL >= 300
// Ensure autoclock gating mode for core1 is enabled, it gets disabled in single-core mode.
REG_SET_BIT(HP_SYS_CLKRST_CPU_WAITI_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN);
#endif
start_other_core();
#else
ESP_EARLY_LOGI(TAG, "Single core mode");
@@ -851,10 +869,7 @@ NOINLINE_ATTR static void system_early_init(const soc_reset_reason_t *rst_reas)
#if CONFIG_IDF_TARGET_ESP32
#if !CONFIG_SPIRAM_BOOT_HW_INIT
// If psram is uninitialized, we need to improve some flash configuration.
bootloader_flash_clock_config(&fhdr);
bootloader_flash_gpio_config(&fhdr);
bootloader_flash_dummy_config(&fhdr);
bootloader_flash_cs_timing_config();
configure_flash(&fhdr);
#endif //!CONFIG_SPIRAM_BOOT_HW_INIT
#endif //CONFIG_IDF_TARGET_ESP32
components/esp_system/port/soc/esp32c6/clk.c
+2
View File
@@ -316,8 +316,10 @@ __attribute__((weak)) void esp_perip_clk_init(void)
REG_CLR_BIT(PCR_TRACE_CONF_REG, PCR_TRACE_CLK_EN);
REG_CLR_BIT(PCR_RETENTION_CONF_REG, PCR_RETENTION_CLK_EN);
REG_CLR_BIT(PCR_MEM_MONITOR_CONF_REG, PCR_MEM_MONITOR_CLK_EN);
#if !CONFIG_ESP_ENABLE_PVT
REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
#endif
WRITE_PERI_REG(PCR_CTRL_CLK_OUT_EN_REG, 0);
#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
components/esp_wifi/include/esp_wifi.h
+3
View File
@@ -1092,6 +1092,9 @@ typedef void (*esp_vendor_ie_cb_t)(void *ctx, wifi_vendor_ie_type_t type, const
* @param vnd_ie Pointer to vendor specific element data. First 6 bytes should be a header with fields matching vendor_ie_data_t.
* If enable is false, this argument is ignored and can be NULL. Data does not need to remain valid after the function returns.
*
* @attention If user set the same vendor ie twice, the second set will fail and return ESP_ERR_INVALID_ARG.
* Please clear the vendor ie before setting again.
*
* @return
* - ESP_OK: succeed
* - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init()
components/esp_wifi/include/esp_wifi_types_generic.h
+2 -2
View File
@@ -536,7 +536,7 @@ typedef struct {
wifi_cipher_type_t pairwise_cipher; /**< Pairwise cipher of SoftAP, group cipher will be derived using this. Cipher values are valid starting from WIFI_CIPHER_TYPE_TKIP, enum values before that will be considered as invalid and default cipher suites(TKIP+CCMP) will be used. Valid cipher suites in softAP mode are WIFI_CIPHER_TYPE_TKIP, WIFI_CIPHER_TYPE_CCMP, WIFI_CIPHER_TYPE_TKIP_CCMP, WIFI_CIPHER_TYPE_GCMP and WIFI_CIPHER_TYPE_GCMP256. */
bool ftm_responder; /**< Enable FTM Responder mode */
wifi_pmf_config_t pmf_cfg; /**< Configuration for Protected Management Frame */
wifi_sae_pwe_method_t sae_pwe_h2e; /**< Configuration for SAE PWE derivation method */
wifi_sae_pwe_method_t sae_pwe_h2e; /**< Configuration for SAE PWE derivation method. Default value :2 (WPA3_SAE_PWE_BOTH) */
uint8_t transition_disable; /**< Whether to enable transition disable feature */
uint8_t sae_ext; /**< Enable SAE EXT feature. SOC_GCMP_SUPPORT is required for this feature. */
wifi_bss_max_idle_config_t bss_max_idle_cfg; /**< Configuration for bss max idle, effective if CONFIG_WIFI_BSS_MAX_IDLE_SUPPORT is enabled */
@@ -566,7 +566,7 @@ typedef struct {
uint32_t owe_enabled: 1; /**< Whether OWE is enabled for the connection */
uint32_t transition_disable: 1; /**< Whether to enable transition disable feature */
uint32_t reserved1: 26; /**< Reserved for future feature set */
wifi_sae_pwe_method_t sae_pwe_h2e; /**< Configuration for SAE PWE derivation method */
wifi_sae_pwe_method_t sae_pwe_h2e; /**< Configuration for SAE PWE derivation method. Default value :2 (WPA3_SAE_PWE_BOTH) */
wifi_sae_pk_mode_t sae_pk_mode; /**< Configuration for SAE-PK (Public Key) Authentication method */
uint8_t failure_retry_cnt; /**< Number of connection retries station will do before moving to next AP. scan_method should be set as WIFI_ALL_CHANNEL_SCAN to use this config.
Note: Enabling this may cause connection time to increase in case best AP doesn't behave properly. */
components/esp_wifi/lib
+1 -1
Submodule components/esp_wifi/lib updated: 156aed2cb6...8f933de0fd
components/hal/emac_hal.c
+26
View File
@@ -5,6 +5,8 @@
*/
#include <string.h>
#include "sdkconfig.h"
#include <stdlib.h>
#include "soc/soc_caps.h"
#include "esp_attr.h"
#include "hal/emac_hal.h"
#include "hal/emac_ll.h"
@@ -13,6 +15,15 @@
#define EMAC_PTP_INIT_TIMEOUT_US (10)
#endif // SOC_EMAC_IEEE1588V2_SUPPORTED
static uint8_t emac_crs_div_table[] = {
42,
62,
16,
26,
102,
124,
};
static esp_err_t emac_hal_flush_trans_fifo(emac_hal_context_t *hal)
{
emac_ll_flush_trans_fifo_enable(hal->dma_regs, true);
@@ -39,6 +50,21 @@ void emac_hal_init(emac_hal_context_t *hal)
#endif
}
void emac_hal_find_set_closest_csr_clock_range(emac_hal_context_t *hal, int mdc_freq_hz, int freq_hz)
{
int min_diff = abs(freq_hz / emac_crs_div_table[0] - mdc_freq_hz);
uint32_t best_div = 0;
for (int i = 1; i < sizeof(emac_crs_div_table) / sizeof(emac_crs_div_table[0]); i++) {
int cur_diff = abs(freq_hz / emac_crs_div_table[i] - mdc_freq_hz);
if (cur_diff < min_diff) {
min_diff = cur_diff;
best_div = i;
}
}
emac_ll_set_csr_clock_division(hal->mac_regs, best_div);
}
void emac_hal_set_csr_clock_range(emac_hal_context_t *hal, int freq)
{
/* Tell MAC system clock Frequency in MHz, which will determine the frequency range of MDC(1MHz~2.5MHz) */
components/hal/esp32/include/hal/emac_ll.h
+7
View File
@@ -22,6 +22,7 @@
#include "soc/emac_mac_struct.h"
#include "soc/emac_ext_struct.h"
#include "soc/dport_reg.h"
#include "soc/clk_tree_defs.h"
#ifdef __cplusplus
extern "C" {
@@ -694,6 +695,12 @@ static inline void emac_ll_pause_frame_enable(emac_ext_dev_t *ext_regs, bool ena
}
/*************** End of ext regs operation *********************/
static inline soc_module_clk_t emac_ll_get_csr_clk_src(void)
{
// Source of the ESP32 EMAC CRS clock is APB clock.
return SOC_MOD_CLK_APB;
}
#ifdef __cplusplus
}
#endif
components/hal/esp32c5/include/hal/gdma_ll.h
+1
View File
@@ -9,6 +9,7 @@
#include "hal/ahb_dma_ll.h"
#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
#define GDMA_LL_MAX_BURST_SIZE_PSRAM 32 // PSRAM controller doesn't support burst access with size > 32 bytes
#define GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 // The alignment of the memory and size when DMA accesses encrypted memory
#ifdef __cplusplus
extern "C" {
components/hal/esp32c5/include/hal/parlio_ll.h
+6 -4
View File
@@ -255,8 +255,9 @@ static inline void parlio_ll_rx_start_soft_recv(parl_io_dev_t *dev, bool en)
__attribute__((always_inline))
static inline void parlio_ll_rx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
{
dev->rx_clk_cfg.rx_clk_i_inv = edge;
dev->rx_clk_cfg.rx_clk_o_inv = edge;
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->rx_clk_cfg.rx_clk_i_inv = invert;
dev->rx_clk_cfg.rx_clk_o_inv = invert;
}
/**
@@ -559,8 +560,9 @@ static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t sta
*/
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
{
dev->tx_clk_cfg.tx_clk_i_inv = edge;
dev->tx_clk_cfg.tx_clk_o_inv = edge;
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->tx_clk_cfg.tx_clk_i_inv = invert;
dev->tx_clk_cfg.tx_clk_o_inv = invert;
}
/**
components/hal/esp32c5/include/hal/rng_ll.h
+88
View File
@@ -0,0 +1,88 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include <stdint.h>
#include "soc/lpperi_struct.h"
#include "hal/lp_clkrst_ll.h"
#define RNG_LL_DEPENDS_ON_LP_PERIPH 1
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enable or disable RNG sampling.
*
* @param enable True to enable, False to disable
*/
static inline void rng_ll_enable_sample(bool enable)
{
LPPERI.rng_cfg.rng_sample_enable = enable;
}
/**
* @brief Enable or disable rng xor rtc timer.
*
* @param enable True to enable, False to disable
*/
static inline void rng_ll_enable_rtc_timer(bool enable)
{
LPPERI.rng_cfg.rtc_timer_en = enable ? 0x3 : 0x0;
}
/**
* @brief Enable or disable rng xor async rng timer.
*
* @param enable True to enable, False to disable
*/
static inline void rng_ll_enable_rng_timer(bool enable)
{
LPPERI.rng_cfg.rng_timer_en = enable;
}
/**
* @brief Reset RNG.
*/
static inline void rng_ll_reset(void)
{
LPPERI.reset_en.lp_rng_reset_en = 1;
LPPERI.reset_en.lp_rng_reset_en = 0;
}
/**
* @brief Enable RNG module
*
* TODO: unify in rng_hal.c
*/
static inline void rng_ll_enable(void)
{
_lp_clkrst_ll_enable_rng_clock(true);
rng_ll_enable_sample(true);
rng_ll_enable_rtc_timer(true);
rng_ll_enable_rng_timer(true);
}
/**
* @brief Disable RNG module
*
* TODO: unify in rng_hal.c
*/
static inline void rng_ll_disable(void)
{
rng_ll_enable_sample(false);
rng_ll_enable_rtc_timer(false);
rng_ll_enable_rng_timer(false);
_lp_clkrst_ll_enable_rng_clock(false);
}
#ifdef __cplusplus
}
#endif
components/hal/esp32c61/include/hal/gdma_ll.h
+1
View File
@@ -9,6 +9,7 @@
#include "hal/ahb_dma_ll.h"
#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
#define GDMA_LL_MAX_BURST_SIZE_PSRAM 32 // PSRAM controller doesn't support burst access with size > 32 bytes
#define GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 // The alignment of the memory and size when DMA accesses encrypted memory
#ifdef __cplusplus
extern "C" {
components/hal/esp32h2/include/hal/parlio_ll.h
+6 -4
View File
@@ -258,8 +258,9 @@ static inline void parlio_ll_rx_start_soft_recv(parl_io_dev_t *dev, bool en)
__attribute__((always_inline))
static inline void parlio_ll_rx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
{
dev->rx_clk_cfg.rx_clk_i_inv = edge;
dev->rx_clk_cfg.rx_clk_o_inv = edge;
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->rx_clk_cfg.rx_clk_i_inv = invert;
dev->rx_clk_cfg.rx_clk_o_inv = invert;
}
/**
@@ -567,8 +568,9 @@ static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t sta
*/
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
{
dev->tx_clk_cfg.tx_clk_i_inv = edge;
dev->tx_clk_cfg.tx_clk_o_inv = edge;
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->tx_clk_cfg.tx_clk_i_inv = invert;
dev->tx_clk_cfg.tx_clk_o_inv = invert;
}
/**
components/hal/esp32h21/include/hal/gdma_ll.h
+1
View File
@@ -49,6 +49,7 @@ extern "C" {
#define GDMA_LL_AHB_DESC_ALIGNMENT 4
#define GDMA_LL_AHB_RX_BURST_NEEDS_ALIGNMENT 1
#define GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 // The alignment of the memory and size when DMA accesses encrypted memory
#define GDMA_LL_AHB_M2M_CAPABLE_PAIR_MASK 0x07 // pair 0,1,2 are M2M capable
components/hal/esp32h4/include/hal/gdma_ll.h
+1
View File
@@ -9,6 +9,7 @@
#include "hal/ahb_dma_ll.h"
#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
#define GDMA_LL_MAX_BURST_SIZE_PSRAM 64 // PSRAM support INCR16
#define GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 // The alignment of the memory and size when DMA accesses encrypted memory
#ifdef __cplusplus
extern "C" {
components/hal/esp32p4/clk_tree_hal.c
+1 -1
View File
@@ -45,7 +45,7 @@ static uint32_t clk_hal_mem_get_freq_hz(void)
return clk_hal_cpu_get_freq_hz() / clk_ll_mem_get_divider();
}
static uint32_t clk_hal_sys_get_freq_hz(void)
uint32_t clk_hal_sys_get_freq_hz(void)
{
return clk_hal_mem_get_freq_hz() / clk_ll_sys_get_divider();
}
components/hal/esp32p4/include/hal/aes_ll.h
+38
View File
@@ -11,6 +11,7 @@
#include "hal/aes_types.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/hwcrypto_reg.h"
#include "hal/config.h"
#ifdef __cplusplus
extern "C" {
@@ -250,6 +251,31 @@ static inline void aes_ll_interrupt_clear(void)
REG_WRITE(AES_INT_CLEAR_REG, 1);
}
/**
* @brief Enable the pseudo-round function during AES operations
*
* @param enable true to enable, false to disable
* @param base basic number of pseudo rounds, zero if disable
* @param increment increment number of pseudo rounds, zero if disable
* @param key_rng_cnt update frequency of the pseudo-key, zero if disable
*/
static inline void aes_ll_enable_pseudo_rounds(bool enable, uint8_t base, uint8_t increment, uint8_t key_rng_cnt)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_EN, enable);
if (enable) {
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_BASE, base);
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_INC, increment);
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_RNG_CNT, key_rng_cnt);
} else {
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_BASE, 0);
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_INC, 0);
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_RNG_CNT, 0);
}
#endif
}
/**
* @brief Continue a previous started transform
*
@@ -337,6 +363,18 @@ static inline void aes_ll_gcm_read_tag(uint8_t *tag)
}
}
/**
* @brief Check if the pseudo round function is supported
*/
static inline bool aes_ll_is_pseudo_rounds_function_supported(void)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
return true;
#else
return false;
#endif
}
#ifdef __cplusplus
}
#endif
components/hal/esp32p4/include/hal/axi_dma_ll.h
+7 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -294,6 +294,9 @@ static inline void axi_dma_ll_rx_enable_etm_task(axi_dma_dev_t *dev, uint32_t ch
/**
* @brief Whether to enable access to ecc or aes memory
*
* @note This function is not used for AXI-GDMA because it will affect the alignment requirement for internal memory.
* We have ensured that the AXI-GDMA can access the encrypted memory by 16-bytes alignment in software.
*/
static inline void axi_dma_ll_rx_enable_ext_mem_ecc_aes_access(axi_dma_dev_t *dev, uint32_t channel, bool enable)
{
@@ -528,6 +531,9 @@ static inline void axi_dma_ll_tx_enable_etm_task(axi_dma_dev_t *dev, uint32_t ch
/**
* @brief Whether to enable access to ecc or aes memory
*
* @note This function is not used for AXI-GDMA because it will affect the alignment requirement for internal memory.
* We have ensured that the AXI-GDMA can access the encrypted memory by 16-bytes alignment in software.
*/
static inline void axi_dma_ll_tx_enable_ext_mem_ecc_aes_access(axi_dma_dev_t *dev, uint32_t channel, bool enable)
{
components/hal/esp32p4/include/hal/emac_ll.h
+6
View File
@@ -816,6 +816,12 @@ static inline void emac_ll_ts_target_int_trig_enable(emac_ptp_dev_t *ptp_regs)
/************** End of ptp regs operation ********************/
static inline soc_module_clk_t emac_ll_get_csr_clk_src(void)
{
// Source of the ESP32P4 EMAC CRS clock is SYS clock.
return SOC_MOD_CLK_SYS;
}
/**
* @brief Enable the bus clock for the EMAC module
*

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