2ff54ff5c5
fix(soc): update breakpoint nums on c5 and h4
2025-12-29 10:31:32 +08:00
da5ff0c78c
Merge branch 'fix/add_soc_caps_for_pawr_feat_v5.5' into 'release/v5.5'
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fix(ble): add soc caps feat for PAwR (v5.5)
See merge request espressif/esp-idf!44150
2025-12-26 14:21:25 +08:00
faf6cc4f84
feat(spi_flash): implement dynamic CPU frequency switching workaround for encrypted writes
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This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency
normally, while automatically reducing CPU frequency during encrypted flash writes to
ensure correct operation. The frequency limit is chip revision dependent:
- v1.2 and above: limited to 160MHz during encrypted writes
- v1.0 and below: limited to 80MHz during encrypted writes
Key implementation details:
- Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called
- Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer
- Works with both PM enabled and disabled configurations
- Frequency is automatically restored after encrypted write completes
- For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when
CPU frequency is reduced to 80MHz
- SPI1 timing registers are configured during frequency switching since encrypted writes
use SPI1 and must work correctly at reduced CPU frequencies
Code improvements:
- Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks
- Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of
hardcoded macros
- Add comprehensive test cases covering various PM configurations and edge cases
This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance
while maintaining reliable encrypted flash write functionality.
2025-12-17 03:33:29 +08:00
0f07ad18b6
fix: add mutex protection for software trigger RegDMA start to avoid data races
2025-12-11 20:32:53 +08:00
0cce37f934
fix(ble): add soc caps config for pawr feat on ESP32C5
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(cherry picked from commit 19130df4f39b45a88d51baf9b7a0381bb73db063)
Co-authored-by: cjin <jinchen@espressif.com >
2025-12-11 16:23:09 +08:00
9589ab5361
feat(gpio): add IO hold support for Deep-sleep for ESP32-P4 ECO5
2025-11-13 11:36:15 +08:00
317a6f074d
fix(mbedtls/port): Align AES and SHA DMA buffers to 16 when SPIRAM encryption is enabled
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- Targets that support GDMA and MSPI encryption module need data and addresses aligned to 16
2025-11-11 17:45:11 +05:30
cf98517de1
feat: added test_cases for ECC P-384 curve operations
2025-10-31 10:38:52 +05:30
851602ed8e
feat: add ecdsa-p384 testcases and relative support for ESP32C5 ECO2
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This commit adds testcases in crypto/hal and mbedtls testapps.
2025-10-16 14:48:13 +08:00
6adb0e5fd4
Merge branch 'refactor/use_gdma_link_in_rmt_v5.5' into 'release/v5.5'
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refactor(rmt): use gdma link list driver to mount buffer (v5.5)
See merge request espressif/esp-idf!41233
2025-09-01 14:53:21 +08:00
d421c9963e
Merge branch 'feat/support_c5_c61_clkoutput_v5.5' into 'release/v5.5'
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feat(esp_hw_support): support clock output feature on esp32c5/esp32c61 (v5.5)
See merge request espressif/esp-idf!41108
2025-09-01 14:43:15 +08:00
ae2b5af875
Merge branch 'bugfix/add_phy_calibration_independent_support_v5.5' into 'release/v5.5'
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feat(phy): add phy calibration independent support(backport v5.5)
See merge request espressif/esp-idf!41416
2025-08-22 17:52:32 +08:00
5714153832
feat(phy): add phy calibration independent support
2025-08-22 10:49:23 +08:00
4213e41bbd
fix(soc): Disable XTS-AES-256 using efuse key for ESP32-C5
2025-08-19 21:59:34 +05:30
ba376fa81c
fix(rmt): deal with spurious RX done interrupts on ESP32
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Closes https://github.com/espressif/esp-idf/issues/15948
2025-08-14 11:22:49 +08:00
cafe454113
feat(esp_hw_support): support clock output feature on esp32c5/esp32c61
2025-08-08 11:36:28 +08:00
0be09bc38e
Merge branch 'feat/c5_flash_timing_tuning_v5.5' into 'release/v5.5'
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flash: flash timing tuning support on c5 (v5.5)
See merge request espressif/esp-idf!40879
2025-08-01 17:20:08 +08:00
c02e1edce4
Merge branch 'feat/support_rmt_on_h4_v5.5' into 'release/v5.5'
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fix(rmt): add pll and rcfast clock src on c5 (v5.5)
See merge request espressif/esp-idf!40915
2025-07-31 21:28:02 +08:00
b28bc7aeae
fix(rmt): add pll and rcfast clock src on c5
2025-07-30 17:26:58 +08:00
18ff6750cc
feat(flash): flash 80M timing tuning on c5
2025-07-29 14:10:28 +08:00
476f8f6f51
feat(bootloader_support): Support Secure Boot using ECDSA-P384 curve
2025-07-25 14:25:31 +05:30
3fa646e58a
Merge branch 'feat/add_cte_iq_report_example_v5.5' into 'release/v5.5'
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Add Bluetooth LE CTE connless example. (v5.5)
See merge request espressif/esp-idf!39783
2025-07-24 23:43:56 +08:00
8842c6577b
feat(esp32c5): Enable Bluetooth LE CTE feature
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(cherry picked from commit aa4489a8795412d347a68ce56f2054379bb0b118)
Co-authored-by: Geng Yuchao <gengyuchao@espressif.com >
2025-07-24 10:33:54 +08:00
a002a04332
feat(soc): Added soc capabilities related to RNG
2025-07-23 18:24:46 +05:30
3c39b32195
Chip/support esp32c61 v5.5
2025-07-22 12:21:36 +08:00
e7a76ff71e
feat(soc): Update ESP32-C5 ECO2 to support SHA512
2025-06-18 16:46:39 +05:30
d8fa0886b0
Merge branch 'feat/c5_eco2_psram_timing_tuning_v5.5' into 'release/v5.5'
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mspi: psram 80M timing tuning on C5 ECO2 (v5.5)
See merge request espressif/esp-idf!39345
2025-06-16 10:01:13 +08:00
23892d857a
change(esp_hw_support): force top domain power up during sleep
2025-06-05 22:07:30 +08:00
fafc25b8b9
feat(mspi): supported psram 80MHz timing tuning
2025-05-22 14:42:42 +08:00
63f72f659d
feat(power_glich): support power_glitch of esp32c5_eco1 and above, eco32c61 eco2 and above
2025-05-20 21:14:33 +08:00
0a17f79cc7
feat(esp_wifi): Add FTM support for ESP32C5 (ECO2)
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Closes https://github.com/espressif/esp-idf/issues/15909
2025-05-19 21:14:48 +08:00
929e14951b
Merge branch 'feat/add_parlio_bitscrambler_support' into 'master'
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feat(parlio_tx): add bitscrambler support
Closes IDF-12016
See merge request espressif/esp-idf!38368
2025-05-12 15:39:56 +08:00
3058e24af9
Merge branch 'feature/lp_core_c5_eco2' into 'master'
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feat(ulp): update ulp for c5 eco2
Closes IDF-8637
See merge request espressif/esp-idf!38431
2025-05-12 13:35:25 +08:00
39f6aeb536
feat(bitscrambler): add enable and disable function
2025-05-12 10:27:14 +08:00
2fbbcc6d36
feat(ulp): updated to reflect eco2 ulp changes
2025-05-12 10:22:20 +08:00
8a999ea19e
fix(security): Set all APM masters to operate in TEE mode by default
2025-05-11 10:01:11 +05:30
3a72305e50
feat(efuse): Support efuses for ESP32-C5 ECO2
2025-05-09 09:29:31 +03:00
0c76f6c556
Merge branch 'bugfix/idf-12651' into 'master'
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fix the issue of regdma update cache state before wait compare
Closes IDF-12651
See merge request espressif/esp-idf!38879
2025-05-01 12:03:55 +08:00
19874adb58
fix(soc_caps): fix the issue of regdma update cache state before wait compare
2025-04-30 18:14:52 +08:00
69164ed912
feat(sdio): supported sdio on esp32c5
2025-04-30 14:48:28 +08:00
35d17049e6
Merge branch 'support/esp32c5eco2_ble_15_4' into 'master'
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Resupport BLE and 15.4 for esp32c5eco2
Closes IDF-12822, IDF-12824, IDF-10559, IDF-10560, IDF-10561, IDF-10562, IDF-10563, IDF-10564, IDF-10565, IDF-10566, and IDF-10567
See merge request espressif/esp-idf!38804
2025-04-30 10:11:19 +08:00
0e554538f7
feat(802.15.4): supported IEEE802.15.4 on the C5ECO2
2025-04-29 16:45:47 +08:00
8344af1f09
Merge branch 'feat/support_length_eof' into 'master'
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feat(uhci): Add UHCI support on esp32c5, esp32h2.
See merge request espressif/esp-idf!38794
2025-04-29 14:34:58 +08:00
2e8d8beb9d
change(ble): supported ble for esp32c5-eco2
2025-04-29 14:24:47 +08:00
0be704f5dc
Merge branch 'doc/add_soc_support_coexistence_for_esp32c5' into 'master'
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docs(coex): add soc_support_coexistence for esp32c5
See merge request espressif/esp-idf!38378
2025-04-29 14:18:14 +08:00
f19e8e6970
fix: re-enabled ecdsa support for esp32c5-eco2
2025-04-28 20:58:09 +05:30
f566b500dd
feat(uhci): Add uhci (uart-dma) support on esp32c5, esp32h2
2025-04-28 16:24:42 +08:00
dd9f8bfcbc
feat(wifi): chip esp32c5 eco2 support wifi
2025-04-28 10:52:55 +08:00
ef619a4485
change(soc): update modem syscon and lpcon register and structure header files
2025-04-27 17:58:28 +08:00
6edf48d253
feat(parlio_tx): support cs signal on esp32c5 v1.0
2025-04-25 14:25:01 +08:00
Chen Jichang