pioduino/esp-idf
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3532 Commits

Author SHA1 Message Date
Jiang Jiang Jian c1e3d07c4b Merge branch 'bugfix/fix_esp32_phy_init_bb_clock_issue_v5.5' into 'release/v5.5' 
bugfix(wifi): fix incomplete phy initialization due to absence of bb clocks at...

See merge request espressif/esp-idf!45256
 2026-01-21 17:03:43 +08:00
Jiang Jiang Jian 187b0800ab Merge branch 'feat/support_esp32p4_lowpower_v5.5' into 'release/v5.5' 
feat(esp_hw_support): esp32p4 lowpower basic support (v5.5)

See merge request espressif/esp-idf!45188
 2026-01-21 02:17:47 +08:00
Michael (XIAO Xufeng) 3cf945bdbc Merge branch 'fix/p4_min_rev_usage_v5.5' into 'release/v5.5' 
P4: fix wrong rev_min usage in rom and other places (v5.5)

See merge request espressif/esp-idf!45224
 2026-01-21 00:47:30 +08:00
Jiang Jiang Jian 20107feb13 Merge branch 'feature/support_chip762_pvt_auto_dbias_backport_v5.5' into 'release/v5.5' 
feat(c61): support chip762 pvt auto dbias (v5.5)

See merge request espressif/esp-idf!45209
 2026-01-20 21:34:29 +08:00
Jiang Jiang Jian 18ce7a64d5 Merge branch 'feature/support_chip752_pvt_auto_dbias_backport_v5.5' into 'release/v5.5' 
feat(c5): support chip752 pvt auto dbias (v5.5)

See merge request espressif/esp-idf!45208
 2026-01-20 21:34:21 +08:00
liuning c65cf33dae bugfix(wifi): fix incomplete phy initialization due to absence of bb clocks at coexistence scenarios 2026-01-19 19:28:08 +08:00
armando e8814fc0f1 feat(p4): changed to rev3.1 by default 2026-01-19 17:53:52 +08:00
yanzihan@espressif.com 139d4d8952 feat(esp_hw_support): use pvt to auto control digital ldo and rtc ldo for esp32c61 v5.5 2026-01-19 15:59:47 +08:00
Jiang Jiang Jian 67025a23f7 Merge branch 'fix/fix_p4_lp_adc_unavailable_in_sleep_v5.5' into 'release/v5.5' 
feat(esp_hw_support): support ESP_SLEEP_USE_ADC_TSEN_MONITOR_MODE for esp32p4 (v5.5)

See merge request espressif/esp-idf!45195
 2026-01-19 14:59:22 +08:00
Jiang Jiang Jian a3ce1fc579 Merge branch 'feature/support_7.6.1_pvt_auto_dbias_v5.5' into 'release/v5.5' 
feat(esp32c6): auto adjust LDO voltage using pvt function (v5.5)

See merge request espressif/esp-idf!44102
 2026-01-19 14:57:11 +08:00
yanzihan@espressif.com 51adb83f39 feat(esp_hw_support): use pvt to auto control digital ldo and rtc ldo for esp32c5 v5.5 2026-01-19 14:25:25 +08:00
wuzhenghui 42ccf5d626 feat(esp_hw_support): esp32p4 rev3.1 no need MSPI workaround 2026-01-19 11:20:29 +08:00
Mahavir Jain e628865430 Merge branch 'feat/enable_pseudo_round_support_for_aes_v5.5' into 'release/v5.5' 
feat: enable pesudo round functionality for AES in ESP32P4 ECO5 (v5.5)

See merge request espressif/esp-idf!45175
 2026-01-18 18:19:06 +05:30
Mahavir Jain 79048b8aac Merge branch 'feat/enable_pseudo_round_support_for_xts_aes_esp32p4_eco5_v5.5' into 'release/v5.5' 
feat: added support for pseudo round xts aes in esp32p4 eco5 (v5.5)

See merge request espressif/esp-idf!45172
 2026-01-18 18:17:41 +05:30
wuzhenghui db9c08190e fix(soc): fix LP_UART clock source definitions to FOSC instead of LP_FAST 2026-01-16 17:23:50 +08:00
Jiang Jiang Jian c1a09f9cef Merge branch 'fix/p4_fixed_mdc_config_v5.5' into 'release/v5.5' 
fix(esp_eth): fixed ESP32P4 CSR clock range used to determine MDC (v5.5)

See merge request espressif/esp-idf!44225
 2026-01-16 14:33:02 +08:00
Jiang Jiang Jian 8a2f308a07 Merge branch 'bugfix/esp_idf_c5_eco3_cpu_lockup_v5.5' into 'release/v5.5' 
change: support top pd during sleep for esp32c5 eco3 and remove sleep mmu related flow (v5.5)

See merge request espressif/esp-idf!43570
 2026-01-16 14:21:02 +08:00
nilesh.kale c181032205 feat: enable pesudo round functionality for AES in ESP32P4 ECO5 2026-01-16 11:29:04 +05:30
nilesh.kale d8885101cd feat: added support for pseudo round xts aes in esp32p4 eco5 2026-01-16 11:18:38 +05:30
hebinglin 402558201c revert(esp_hw_support): force top domain power up during sleep 
This reverts commit 7912f9fafef4c90a2a644332c46af7fd5e91f148.
 2026-01-15 17:04:17 +08:00
zlq 873afefba8 feat(esp32c6): auto adjust LDO voltage using pvt function 2026-01-15 14:46:52 +08:00
muhaidong 76ab9e82c2 docs(wifi): update wifi fragment doc 2026-01-14 19:31:53 +08:00
Ondrej Kosta 2a5b04b0b4 fix(esp_eth): fixes EMAC MDC out of the range issue 
Closes https://github.com/espressif/esp-idf/issues/17984
 2026-01-06 22:18:37 +08:00
morris ded4814c8d Merge branch 'fix/update_breakpoint_nums_on_c5_h4_v5.5' into 'release/v5.5' 
fix(soc): update breakpoint nums on c5 and h4 (v5.5)

See merge request espressif/esp-idf!44356
 2025-12-30 12:19:23 +08:00
morris 1851470481 Merge branch 'feat/p4eco6_ldo2dcdc_support_v5.5' into 'release/v5.5' 
feat (p4eco6): open dcdc switch by software when dcdc stable (v5.5)

See merge request espressif/esp-idf!44578
 2025-12-29 11:18:37 +08:00
Chen Jichang 2ff54ff5c5 fix(soc): update breakpoint nums on c5 and h4 2025-12-29 10:31:32 +08:00
Island da5ff0c78c Merge branch 'fix/add_soc_caps_for_pawr_feat_v5.5' into 'release/v5.5' 
fix(ble): add soc caps feat for PAwR (v5.5)

See merge request espressif/esp-idf!44150
 2025-12-26 14:21:25 +08:00
chaijie@espressif.com 3fb705d852 feat (p4eco6): open dcdc switch by software when dcdc stable 2025-12-26 09:54:02 +08:00
morris 2a481f5bc7 Merge branch 'feat/isp_crop_driver_v5.5' into 'release/v5.5' 
feat(isp): support Crop driver on p4 rev3 (v5.5)

See merge request espressif/esp-idf!43446
 2025-12-26 09:51:13 +08:00
Chen Jichang 3678a25e4c fix(gdma): fix set dma burst size failure on p4 v3.0 2025-12-23 11:22:47 +08:00
Xiao Xufeng faf6cc4f84 feat(spi_flash): implement dynamic CPU frequency switching workaround for encrypted writes 
This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency
normally, while automatically reducing CPU frequency during encrypted flash writes to
ensure correct operation. The frequency limit is chip revision dependent:
- v1.2 and above: limited to 160MHz during encrypted writes
- v1.0 and below: limited to 80MHz during encrypted writes

Key implementation details:
- Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called
- Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer
- Works with both PM enabled and disabled configurations
- Frequency is automatically restored after encrypted write completes
- For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when
  CPU frequency is reduced to 80MHz
- SPI1 timing registers are configured during frequency switching since encrypted writes
  use SPI1 and must work correctly at reduced CPU frequencies

Code improvements:
- Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks
- Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of
  hardcoded macros
- Add comprehensive test cases covering various PM configurations and edge cases

This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance
while maintaining reliable encrypted flash write functionality.
 2025-12-17 03:33:29 +08:00
Chen Chen c9c25684ca feat(isp): support Crop driver on p4 rev3 
Add support for crop driver on p4eco5 and update example in
`isp/multi_pipelines`
 2025-12-15 15:11:45 +08:00
sibeibei 0f07ad18b6 fix: add mutex protection for software trigger RegDMA start to avoid data races 2025-12-11 20:32:53 +08:00
Jin Chen 7569042a61 fix(ble): add soc caps config for pawr feat on ESP32C61 
(cherry picked from commit d667a418261d00a0f5c8a9a359324f72d64447ff)

Co-authored-by: cjin <jinchen@espressif.com>
 2025-12-11 16:23:10 +08:00
Jin Chen 0cce37f934 fix(ble): add soc caps config for pawr feat on ESP32C5 
(cherry picked from commit 19130df4f39b45a88d51baf9b7a0381bb73db063)

Co-authored-by: cjin <jinchen@espressif.com>
 2025-12-11 16:23:09 +08:00
Jin Chen a6aa9bf7f5 fix(ble): add soc caps config for pawr feat on ESP32H2 
(cherry picked from commit 2eb79c71f10766c94176fe206024777183750d53)

Co-authored-by: cjin <jinchen@espressif.com>
 2025-12-11 16:23:08 +08:00
Jin Chen b0b2130475 fix(ble): add soc caps config for pawr feat on ESP32C6 
(cherry picked from commit 4e4b863299164bfb78fa2c4142e0a57a2894232f)

Co-authored-by: cjin <jinchen@espressif.com>
 2025-12-11 16:23:07 +08:00
Jiang Jiang Jian ddb9f5d9dc Merge branch 'fix/fix_mspi_write_stuck_after_reset_v5.5' into 'release/v5.5' 
fix(esp_system): fix mspi write stuck after cpu/digital reset on c5/c61 (v5.5)

See merge request espressif/esp-idf!43732
 2025-12-04 10:34:56 +08:00
wuzhenghui 104145de7f fix(esp_system): fix mspi write stuck after cpu/digital reset on c5/c61 2025-12-02 13:34:17 +08:00
gaoxu dfef29c007 feat(rng): support P4 ECO5 TRNG 2025-12-01 15:31:44 +08:00
morris 1d5fcc6d2e Merge branch 'bugfix/uart_related_backports_v5.5' into 'release/v5.5' 
fix(uart): some related uart backports (v5.5)

See merge request espressif/esp-idf!43617
 2025-11-27 10:52:38 +08:00
Song Ruo Jing 0c15b9f6a4 refactor(ppa): avoid the use of yuv422_pack_order field in PPA driver 2025-11-24 11:41:26 +08:00
armando 304ebc0c74 change(p4): make v3 as default 2025-11-20 11:33:36 +08:00
morris 7b2f4f2b88 Merge branch 'fix/mipi_dsi_phy_clk_type_v5.5' into 'release/v5.5' 
fix(lcd): fix mipi dsi phy type for p4 version below 3.0 (v5.5)

See merge request espressif/esp-idf!43354
 2025-11-14 18:21:55 +08:00
morris 1c4f1f47cc Merge branch 'feature/esp32p4_eco5_io_hold_v5.5' into 'release/v5.5' 
feat(gpio): add IO hold support for Deep-sleep for ESP32-P4 ECO5 (v5.5)

See merge request espressif/esp-idf!43308
 2025-11-14 15:22:50 +08:00
Chen Jichang f04318c605 fix(lcd): fix mipi dsi phy type for p4 version below 3.0 2025-11-14 11:07:26 +08:00
Michael (XIAO Xufeng) c51b5e955a Merge branch 'feature/support_efuses_esp32p4_eco5_v5.5' into 'release/v5.5' 
feat(efuse): Support efuses for ESP32-P4 ECO5 (v5.5)

See merge request espressif/esp-idf!42651
 2025-11-13 17:11:10 +08:00
Song Ruo Jing ea09a117ee feat(gpio): ESP32P4 ECO5 GPIO related update 2025-11-13 11:36:22 +08:00
Song Ruo Jing 9589ab5361 feat(gpio): add IO hold support for Deep-sleep for ESP32-P4 ECO5 2025-11-13 11:36:15 +08:00
harshal.patil 317a6f074d fix(mbedtls/port): Align AES and SHA DMA buffers to 16 when SPIRAM encryption is enabled 
- Targets that support GDMA and MSPI encryption module need data and addresses aligned to 16
 2025-11-11 17:45:11 +05:30